Instruction processing method, instruction processing circuit, processor and electronic device

Abstract

The present application provides an instruction processing method, an instruction processing circuit, a processor and an electronic device, and relates to the field of processor technology. The instruction processing method includes: selecting a target thread bundle from each thread bundle competing for a target resource, so that the target thread bundle uses the target resource to process the target type of instruction corresponding to the target resource; when the current instruction of the target thread bundle belongs to the target type of instruction, the target thread bundle is kept to continuously use the target resource; when the current instruction of the target thread bundle does not belong to the target type of instruction or there is no instruction to be executed in the target thread bundle, a new target thread bundle is selected from each thread bundle competing for the target resource. The solution of the embodiment of the present application can give each thread bundle the ability to continuously process instructions corresponding to the same type of resources, thereby meeting the soft-clause requirements of the kernel program.

Description

Technical Field

[0001] The present application relates to the field of processor technology, and in particular to an instruction processing method, an instruction processing circuit, a processor and an electronic device. Background Art

[0002] In many high-performance processors (such as GPU (Graphics Processing Unit), AI (Artificial Intelligence) processors, etc.), the software kernel program has a soft-clause requirement (for software programs, especially some user-written scenarios, in order to achieve the purpose of efficient kernel operation, some program segments will be deliberately written into the form of continuous instructions of the same type, which is called soft-clause. The requirement for continuous processing of continuous instructions of the same type is called soft-clause requirement), that is, for a thread bundle (warp) in the process of running its instruction program, it is required that the instruction segments of the same type can be processed continuously without being interrupted by other thread bundles. Here, the same type of instructions refers to instructions executed by threads such as memory load operation instructions (this instruction operation will request to operate on memory), ALU (Arithmetic And Logic Unit, Arithmetic And Logic Unit) calculation operation instructions. By continuously processing memory load operation instructions, it can be ensured that more memory requests are issued as soon as possible, and by continuously processing ALU calculation operation instructions, the ALU can be used for calculation continuously. In this way, different thread warps are coupled to each other to process different types of instructions, which can achieve a complementary effect. For example, thread warp 0 expects to process 8 memory instruction requests first and then 8 ALU instruction requests, while at the same time, thread warp 1 expects to process 8 ALU instruction requests first and then 8 memory instruction requests. In this way, thread warp 0 and thread warp 1 complement each other, and the probability of them competing for resources can be greatly reduced.

[0003] Currently, in high-performance processors, resources are usually allocated in a round-robin manner or in an age matrix manner (the age matrix method refers to allocating resources in the order in which thread bundles are born, with priority given to the first-born thread bundles). However, in the face of the soft-clause requirements of kernel programs, the above two methods cannot meet the requirements and cannot ensure that a thread bundle continuously processes the same type of instructions. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide an instruction processing method, an instruction processing circuit, a processor and an electronic device to meet the soft-clause requirements of kernel programs.

[0005] An embodiment of the present application provides an instruction processing method, comprising: selecting a target thread bundle from thread bundles competing for a target resource, so that the target thread bundle uses the target resource to process instructions of a target type corresponding to the target resource; when a current instruction of the target thread bundle belongs to an instruction of the target type, maintaining the target thread bundle to continuously use the target resource; when the current instruction of the target thread bundle does not belong to an instruction of the target type or there is no instruction to be executed in the target thread bundle, reselecting a new target thread bundle from the thread bundles competing for the target resource.

[0006] In the above implementation, after selecting a target thread bundle for a target resource, when the target thread bundle uses the target resource to process the current instruction, a new target thread bundle is no longer selected immediately in a polling manner or an age matrix manner, but the target thread bundle is waited for to continue to use the target resource to process the current instruction until the current instruction of the target thread bundle does not belong to the target type of instruction (i.e., does not belong to the instruction that needs to be processed by the target resource) or there is no instruction to be executed in the target thread bundle, and then a new target thread bundle is selected from the thread bundles competing for the target resource. On the contrary, when the current instruction of the target thread bundle belongs to the target type of instruction, the target thread bundle is kept to continuously use the target resource. In this way, for each thread bundle, it is given the ability to continuously process instructions corresponding to the same type of resources, thereby meeting the soft-clause requirements of the kernel program.

[0007] Furthermore, the method also includes: when selecting a target thread bundle, allocating a target token to the target thread bundle; wherein the target token is a token corresponding to an instruction of the target type; when a current instruction of the target thread bundle does not belong to an instruction of the target type or there is no instruction to be executed in the target thread bundle, canceling the target token allocated to the target thread bundle; correspondingly, when the current instruction of the target thread bundle does not belong to an instruction of the target type or there is no instruction to be executed in the target thread bundle, re-selecting a new target thread bundle from the thread bundles competing for the target resource, including: determining whether there is a thread bundle having the target token; when no thread bundle has the target token, re-selecting a new target thread bundle from the thread bundles competing for the target resource, and allocating the target token to the new target thread bundle.

[0008] In the above implementation, by allocating target tokens to thread warps, the occupation of target resources by thread warps is associated with the target tokens, so that whether a new target thread warp needs to be reselected from the thread warps competing for the target resources can be determined based on whether there are thread warps with target tokens, thereby ensuring that the solution can be executed correctly.

[0009] Furthermore, the method further includes: before allocating a target token to the target warp, determining whether a continuous processing function is enabled for the target warp.

[0010] Furthermore, the method further includes: if the target warp does not enable the continuous processing function, not allocating the target token to the target warp.

[0011] In the above implementation, by setting the continuous processing function, by judging whether the selected target thread bundle has the continuous processing function enabled, the target token is allocated to the target thread bundle only after the continuous processing function is enabled, so that the target thread bundle has the ability to continuously use the target resources. When the continuous processing function is not enabled for the target thread bundle, the target token is not allocated to the target thread bundle. In this way, the user or program can flexibly grant each thread bundle the right to continuously use the target resources as needed, so that the user or program can flexibly strengthen or weaken the instruction processing requirements of certain thread bundles (i.e., the requirement to use the target resources to process instructions), making the solution of the embodiment of the present application more flexible and universal.

[0012] An embodiment of the present application also provides an instruction processing circuit, comprising: an arbitrator connected to each thread bundle, and used to select a target thread bundle from each thread bundle competing for a target resource, so that the target thread bundle uses the target resource to process instructions of a target type corresponding to the target resource; wherein the target resource is a resource arbitrated by the arbitrator; the arbitrator is also used to be shut down when the current instruction of the target thread bundle belongs to an instruction of the target type, so as to keep the target thread bundle continuously using the target resource; a control circuit is respectively connected to each thread bundle and to the arbitrator, and is used to trigger the arbitrator to re-select a new target thread bundle from each thread bundle competing for the target resource when the current instruction of the target thread bundle does not belong to an instruction of the target type or there is no instruction to be executed in the target thread bundle.

[0013] In the above circuit, arbitration (i.e., selection) of the target thread bundle can be realized based on the arbitrator, and the instruction status in the target thread bundle can be determined through the control circuit, so that the work of the arbitrator can be effectively triggered, so that the target thread bundle can be selected for the target resource. After the target thread bundle uses the target resource to process the current instruction, it will no longer immediately select a new target thread bundle in a polling manner or an age matrix manner, but wait for the target thread bundle to continue to use the target resource to process the current instruction until the current instruction of the target thread bundle does not belong to the target type of instruction (i.e., does not belong to the instruction that needs to be processed using the target resource) or there is no instruction to be executed in the target thread bundle, and then the function of selecting a new target thread bundle from the thread bundles competing for the target resource is re-selected. In this way, the above instruction processing circuit can give each thread bundle the ability to continuously process instructions corresponding to the same type of resources, thereby meeting the soft-clause requirements of the kernel program.

[0014] Furthermore, there are multiple arbitrators, and different arbitrators are used to arbitrate different resources; the control circuit includes: multiple flag registers, each flag register is connected to one of the arbitrators and to one of the thread warps; the flag register is used to set the register value to a first target value when the connected thread warp is determined as a target thread warp by any of the arbitrators, and to set the register value to a second target value when the current instruction of the connected thread warp does not belong to the target type of instruction or there is no instruction to be executed in the target thread warp.

[0015] In the above implementation, the flag register is connected to the arbiter, so that based on the different register values ​​in the flag register, it can be effectively characterized whether the thread bundles competing for the arbiter are allocated with the target token (i.e., the first target value). When the target thread bundle with the token (first target value) flag register uses the target resource to process the current instruction, the new target thread bundle is no longer immediately selected in a polling manner or an age matrix manner, but the target thread bundle continues to use the target resource to process the target type of instruction until the current instruction of the target thread bundle does not belong to the target type of instruction (i.e., does not belong to the instruction that needs to be processed using the target resource) or there is no instruction to be executed in the target thread bundle, and then a new target thread bundle is selected from the thread bundles competing for the target resource in a polling manner or an age matrix manner, and the flag register of the new target thread bundle is set to the first target value, and the other thread bundles are set to the second target value, so as to ensure that the scheme can be executed correctly.

[0016] Furthermore, when any arbitrator determines the target thread warp, among the thread warps competing for the resources arbitrated by the arbitrator, the register value of the flag register connected to each of the thread warps except the target thread warp maintains the second target value; the arbitrator is specifically used to be closed when the current instruction of the target thread warp belongs to the instruction of the target type and the register value of the connected flag register is the first target value, so as to keep the target thread warp continuously using the target resources.

[0017] In the above implementation, the register values ​​of the flag registers corresponding to the thread warps except the target thread warp are maintained at the second target value, which can ensure that at most only one flag register value of a resource is the first target value at the same time, thereby effectively preventing the arbitrator of the resource from suspending work for a long time due to the erroneous existence of multiple flag register values ​​being the first target value, thereby preventing circuit failures.

[0018] Further, the control circuit includes: a plurality of status registers, which are respectively connected to the arbitrator, and each of the status registers is connected to one of the thread bundles; the arbitrator is specifically used for: when the value of any one of the status registers is a third target value, and the thread bundle connected to the status register is a target thread bundle, then: if the current instruction of the thread bundle belongs to the instruction of the target type, keep the target thread bundle continuously using the target resource; if the current instruction of the thread bundle does not belong to the instruction of the target type or there is no instruction to be executed in the target thread bundle, re-select a new target thread bundle from the thread bundles competing for the target resource; and, when the value of any one of the status registers is a fourth target value, and the thread bundle connected to the status register is the target thread bundle, after the current instruction of the target thread bundle is processed, re-select a new target thread bundle from the thread bundles competing for the target resource.

[0019] In the above implementation, by setting the status register, it is possible to configure the value of the status register corresponding to each thread bundle to control whether each thread bundle can continuously use the target resource after being selected as the target thread bundle, that is, it is possible to control whether each thread bundle is granted the right to continuously use the target resource, so that users or programs can flexibly strengthen or weaken the instruction processing requirements of certain thread bundles, making the solution of the embodiment of the present application more flexible and universal.

[0020] An embodiment of the present application also provides a processor, comprising any one of the aforementioned instruction processing circuits.

[0021] An embodiment of the present application also provides an electronic device, comprising the aforementioned processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope.

[0023] Figure 1 A basic structural diagram of an instruction processing circuit provided in an embodiment of the present application;

[0024] Figure 2 A basic structural diagram of a more specific instruction processing circuit provided in an embodiment of the present application;

[0025] Figure 3-1 A basic structural diagram of a specific instruction processing circuit provided in an embodiment of the present application;

[0026] Figure 3-2 For the embodiment of this application Figure 3-1 A more specific basic structural diagram of an instruction processing circuit is provided on the basis of FIG.

[0027] Figure 4 A basic structural diagram of an exemplary instruction processing circuit provided in an embodiment of the present application;

[0028] Figure 5 A schematic diagram of the basic structure of a second exemplary instruction processing circuit provided in an embodiment of the present application;

[0029] Figure 6 A schematic diagram of the basic structure of a third exemplary instruction processing circuit provided in an embodiment of the present application;

[0030] Figure 7 A flowchart of an instruction processing method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0032] In order to achieve the purpose of running the kernel efficiently, some program segments are written in the form of continuous instructions of the same type, and it is hoped that these instructions of the same type can be processed continuously without being interrupted by other thread bundles (called soft-clause requirements). In a processor, a kernel program is usually assigned to a thread bundle for processing. Therefore, when thread bundle arbitration is performed based on the traditional polling method or age matrix method, continuous instructions of the same type often cannot be executed coherently and will be interrupted by other thread bundles, thereby failing to meet the soft-clause requirements. In order to meet the soft-clause requirements, an instruction processing circuit and a matching instruction processing method are provided in an embodiment of the present application.

[0033] See also Figure 1 As shown, Figure 1 A basic structural diagram of an instruction processing circuit provided in an embodiment of the present application, including a thread warp, an arbiter and a control circuit.

[0034] It can be understood that in a processor, SP (Streaming Processor) is the most basic processing unit, and specific instructions are basically processed on SP. Multiple SPs plus some other resources (such as storage resources, shared memory, registers, etc.) form an SM (Streaming Multiprocessor). All SPs in an SM are divided into multiple warps (thread bundles), and the SPs in a warp can work simultaneously and execute the same instructions. That is, the thread bundle is used to execute instructions.

[0035] The arbiter is connected to each thread warp and is used to select a target thread warp from the thread warps competing for the target resource, so that the target thread warp uses the target resource to process instructions of a target type corresponding to the target resource.

[0036] It is understandable that different instructions require different resources, for example, a memory load operation instruction requires memory resources, while an ALU calculation operation instruction requires ALU resources. Different arbitrators may be used for arbitration of different resources. That is, in the embodiment of the present application, there may be multiple arbitrators, for example Figure 2 As shown, the arbitrators work in parallel to arbitrate different resources respectively.

[0037] It can be understood that since each thread warp processes instructions one by one, at the same time, a thread warp will not compete for more than two (including two) resources at the same time. Therefore, each arbitrator will arbitrate different thread warp sets at the same time, so that the target thread warps selected by each arbitrator will not conflict.

[0038] In an embodiment of the present application, the control circuit is respectively connected to each thread bundle and to the arbiter, and is used to trigger the arbiter to re-select a new target thread bundle from the thread bundles competing for the target resource when the current instruction of the target thread bundle does not belong to the target type of instruction or there is no instruction to be executed in the target thread bundle.

[0039] Optional, see Figure 2 As shown, the control circuit may include a plurality of flag registers, each flag register being connected to an arbiter and to a warp.

[0040] In an embodiment of the present application, the value of the flag register can be used to characterize the target token, thereby associating the occupation of the target resource by the thread bundle with the target token by allocating the target token. Therefore, based on whether there is a thread bundle with the target token, it can be determined whether it is necessary to reselect a new target thread bundle from the thread bundles competing for the target resource, thereby ensuring that the plan can be executed correctly.

[0041] The flag register sets the register value to a first target value when the connected thread warp is determined as a target thread warp by any arbitrator, and sets the register value to a second target value when the current instruction of the connected thread warp does not belong to an instruction of the target type or there is no instruction to be executed in the connected thread warp.

[0042] That is, when the register value of the tag register is the first target value, the allocation of the target token to the warp connected to the tag register is achieved.

[0043] In the embodiment of the present application, the register value of the flag register may be configured by the thread warp to which the flag register is connected, but this is not a limitation.

[0044] It can be understood that when any arbitrator determines the target thread warp, among the thread warps competing for the resources arbitrated by the arbitrator, the register values ​​of the flag registers connected to the thread warps other than the target thread warp should maintain the second target value. In this way, it can be ensured that at most one flag register of a resource has the first target value at the same time, thereby effectively preventing the arbitrator of the resource from suspending work for a long time due to the fact that there are multiple flag registers with the first target value by mistake, thereby preventing circuit failure.

[0045] In an embodiment of the present application, after determining the target thread warp, the arbitrator can reselect a new target thread warp from the thread warps competing for the resources arbitrated by the arbitrator after the target thread warp modifies the register value of the connected flag register from the first target value to the second target value.

[0046] For example, assuming that arbitrator A arbitrates the target thread bundle as thread bundle 1 from thread bundle 1, thread bundle 2, thread bundle 3, and thread bundle 4 in this round, thread bundle 1 starts to use the resources corresponding to arbitrator A to process instructions, and at the same time, thread bundle 1 sets the register value of the flag register connected to it from the second target value to the first target value, while thread bundle 2, thread bundle 3, and thread bundle 4 each maintain the register value of the flag register connected to it as the second target value. When thread bundle 1 has continuous instructions using the resources corresponding to arbitrator A, arbitrator A suspends arbitration at this time. Thread bundle 1 can continuously issue and process such instructions; on the contrary, when the current instruction of thread bundle 1 does not belong to the instructions processed using the resources corresponding to arbitrator A, or there is no instruction to be executed in thread bundle 1, thread bundle 1 sets the register value of the flag register connected to it from the first target value to the second target value, and arbitrator A resumes arbitration at this time.

[0047] It can be understood that in an optional implementation of the embodiment of the present application, the number of flag registers connected to each thread warp can be the same as the number of arbitrators. In the flag registers connected to each thread warp, different flag registers are connected to different arbitrators. For example, assuming that there are two arbitrators, namely arbitrator A and arbitrator B, and assuming that there are four thread warps, namely thread warp 1, thread warp 2, thread warp 3, and thread warp 4, then thread warp 1 is connected to flag register A1 and flag register B1, thread warp 2 is connected to flag register A2 and flag register B2, thread warp 3 is connected to flag register A3 and flag register B3, and thread warp 4 is connected to flag register A4 and flag register B4, wherein flag register A1, flag register A2, flag register A3, and flag register A4 are respectively connected to arbitrator A, and flag register B1, flag register B2, flag register B3, and flag register B4 are respectively connected to arbitrator B, so that each arbitrator only needs to determine whether it is necessary to re-select the target thread warp according to whether the register values ​​of the connected flag registers are all the second target values.

[0048] It can be understood that in the embodiment of the present application, the first target value can be 1, and the second target value can be 0, but it is not limited. When the first target value is 1 and the second target value is 0, each flag register can be connected to the enable end of the arbitrator through a NOR gate to enable the arbitrator to work. Still taking the above example as an example, assuming that the output ends of flag register A1, flag register A2, flag register A3, and flag register A4 are connected to the enable end of arbitrator A through a NOR gate A11, when any register value in flag register A1, flag register A2, flag register A3, and flag register A4 is 1, then the NOR gate A11 outputs 0, and arbitrator A suspends work. When the register values ​​of flag register A1, flag register A2, flag register A3, and flag register A4 are all 0, then the NOR gate A11 outputs 1, enabling arbitrator A to work. Similarly, the output ends of flag register B1, flag register B2, flag register B3, and flag register B4 are connected to the enable end of arbitrator B through NOR gate B11. When any register value among flag register B1, flag register B2, flag register B3, and flag register B4 is 1, the output of NOR gate B11 is 0, and arbitrator B suspends working. When the register values ​​of flag register B1, flag register B2, flag register B3, and flag register B4 are all 0, the output of NOR gate B11 is 1, enabling arbitrator B to work.

[0049] Optionally, in the embodiments of the present application, Figure 3-1 As shown, the control circuit may further include a plurality of status registers. The plurality of status registers are respectively connected to the arbitrator, and each status register is connected to a warp.

[0050] At this time, the arbiter is specifically used to: when the value of any state register is the third target value, the thread bundle connected to the state register is the target thread bundle, and the current instruction of the thread bundle does not belong to the target type of instruction or there is no instruction to be executed in the target thread bundle, reselect a new target thread bundle from the thread bundles competing for the target resource. And, when the value of any state register is the fourth target value, and the thread bundle connected to the state register is the target thread bundle, after the current instruction of the target thread bundle is processed, reselect a new target thread bundle from the thread bundles competing for the target resource.

[0051] In this way, by setting the status register, it is possible to configure the value of the status register corresponding to each thread bundle to achieve control over whether each thread bundle can continuously use the target resource after being selected as the target thread bundle, that is, to achieve the ability to control whether each thread bundle is granted the right to continuously use the target resource (for ease of description, in the embodiment of the present application, the situation where each thread bundle can continuously use the target resource is referred to as the situation where the continuous processing function is enabled, and the situation where the thread bundle cannot continuously use the target resource is referred to as the situation where the continuous processing function is not enabled, that is, the status register is equivalent to the enabling switch of the continuous processing function), so that users or programs can flexibly strengthen or weaken the instruction processing requirements of certain thread bundles, making the solution of the embodiment of the present application more flexible and universal.

[0052] It can be understood that in the embodiment of the present application, the status register and the flag register can be set at the same time, for example Figure 3-2 At this time, when the value of any state register is the third target value, the flag register of the thread warp is allowed to be set to the first target value (i.e., obtain the token); when the value of the state register of the thread warp is the fourth target value, the flag register of the thread warp is not allowed to be set to the first target value, but the flag register of the thread warp is required to always maintain the second target value, so as to realize the ability to set different thread warps to use the target resource continuously.

[0053] It can be understood that the so-called target resource refers to the resource arbitrated by the arbitrator. The target type refers to the type of instruction that needs to be processed using the target resource.

[0054] It can also be understood that in the embodiment of the present application, the first target value and the fourth target value can be 1, and the second target value and the third target value can be 0, but this is not a limitation.

[0055] When the first target value and the fourth target value are 1, and the second target value and the third target value are 0, the state register and the flag register connected to the same thread warp can be connected through an AND gate, for example Figure 4 When the register value of the status register is 0, the flag register is gated (disabled) and is not allowed to be set to the first target value (ie, token); conversely, when the status register is 0, the flag register is allowed to be configured to the first target value or the second target value.

[0056] It is understandable that in the embodiment of the present application, each arbitrator may only set one status register or all arbitrators may only set one status register, and control whether all thread warps simultaneously enable the continuous processing function or simultaneously disable the continuous processing function based on the register value of the status register.

[0057] Exemplarily, the status register can be connected to each flag register as a gate terminal, for example Figure 5 and Figure 6 shown.

[0058] It can also be understood that the above are only several optional control circuit implementation structures exemplified in the embodiments of the present application, but are not used as a display. In fact, as long as it can be realized that the arbitrator re-selects a new round of target thread bundles after the target token of the selected target thread bundle is cancelled (that is, after the register value of the flag register becomes the second target value), it can be adopted in the embodiments of the present application. For example, the flag register may not be set, but a record table may be maintained for each arbitrator, the record table records the ID number of each thread bundle, and the ID number of the selected target thread bundle is filled in the mark column representing the target token, or the ID number of the selected target thread bundle is marked in the record table, and when the current instruction of the target thread does not belong to the target type of instruction or there is no instruction to be executed in the target thread bundle, the ID number of the mark column representing the target token in the record table is cleared or the mark in the record table is removed, so that the arbitrator can realize work control based on the record table.

[0059] See below. Figure 7 As shown, Figure 7 The flowchart of the instruction processing method provided in the embodiment of the present application is shown. The instruction processing method can be implemented by, but is not limited to, the above instruction processing circuit. The instruction processing method includes:

[0060] S701: Select a target warp from the warps competing for the target resource, so that the target warp uses the target resource to process instructions of a target type corresponding to the target resource.

[0061] It can be understood that the instruction processing method in the embodiment of the present application can be executed by an arbitrator in the instruction processing circuit, but this is not a limitation.

[0062] It can also be understood that in the embodiment of the present application, the target warp may be selected based on a polling method or an age matrix method, but this is not a limitation.

[0063] S702: When the current instruction of the target thread bundle is an instruction of the target type, keep the target thread bundle continuously using the target resource; when the current instruction of the target thread bundle is not an instruction of the target type or there is no instruction to be executed in the target thread bundle, reselect a new target thread bundle from the thread bundles competing for the target resource.

[0064] It can be understood that after the target thread bundle is selected, the target thread bundle can use the target resources to continuously execute the instructions assigned to the target thread bundle by the kernel program. The current instruction refers to the instruction currently being executed by the target thread bundle or the instruction currently waiting to be executed after the previous instruction is executed. Since the entire execution process is dynamic, the current instruction of the target thread bundle will also change over time.

[0065] In the embodiment of the present application, the instruction processing method may further include:

[0066] When the target warp is selected, a target token is allocated to the target warp. When the current instruction of the target warp does not belong to the target type of instruction or there is no instruction to be executed in the target warp, the target token allocated to the target warp is cancelled.

[0067] Accordingly, step S702 includes: determining whether there is a thread warp with the target token; when there is no thread warp with the target token, selecting a new target thread warp from the thread warps competing for the target resource, and allocating the target token to the new target thread warp.

[0068] The target token is a token corresponding to the target type of instruction. It can be understood that for different resources, that is, for different arbitrators, their target tokens should be separate. Figure 4 For example, the flag registers connected to arbitrator A and arbitrator B are completely separated, thereby achieving the separation of the tokens corresponding to arbitrator A and arbitrator B, ensuring the executability of the scheme.

[0069] It can be understood that in the embodiment of the present application, the instruction processing method may further include:

[0070] Before allocating a target token to a target warp, it is first determined whether the target warp has a continuous processing function enabled.

[0071] A target token is allocated to a target warp only if the target warp has the continuous processing feature enabled.

[0072] If the target warp does not enable the continuous processing function, no target token is allocated to the target warp.

[0073] It can be understood that the scheme of the embodiment of the present application selects a target thread bundle for a target resource. After the target thread bundle uses the target resource to process the current instruction, it no longer immediately selects a new target thread bundle in a polling manner or an age matrix manner, but waits for the target thread bundle to continue to use the target resource to process the current instruction until the current instruction of the target thread bundle does not belong to the target type of instruction (that is, does not belong to the instruction that needs to be processed using the target resource) or there is no instruction to be executed in the target thread bundle, and then a new target thread bundle is selected from the thread bundles competing for the target resource. In this way, for each thread bundle, it is given the ability to continuously process instructions corresponding to the same type of resources, thereby meeting the soft-clause requirements of the kernel program.

[0074] Based on the same inventive concept, an embodiment of the present application also provides a processor, including the aforementioned instruction processing circuit.

[0075] In the embodiments of the present application, the processor may be, but is not limited to, a CPU (Central Processing Unit / Processor) with instruction processing capabilities, a GPU (Graphics Processing Unit), a GPGPU (General Purpose Computing on GPU) chip, an MCU (Microcontroller Unit), etc., but is not intended to be limiting.

[0076] Based on the same inventive concept, an embodiment of the present application also provides an electronic device, including the aforementioned processor.

[0077] It is understandable that the electronic device provided in the embodiment of the present application may also have more components. For example, the electronic device may also have a memory. The processor and the memory may be connected via, but not limited to, a communication bus.

[0078] In the embodiments of the present application, the memory may be a random access memory, a read-only memory, a programmable read-only memory, an erasable read-only memory, an electrically erasable read-only memory, etc., but is not limited thereto.

[0079] In the embodiments of the present application, the electronic device may be, but is not limited to, a desktop computer, a laptop computer, a smart phone, a smart wearable device, a smart vehicle-mounted device, a server, a console, and the like.

[0080] In the embodiments provided in this application, it should be understood that the disclosed circuits and methods can be implemented in other ways. The embodiments described above are merely illustrative.

[0081] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0082] As used herein, a plurality refers to two or more than two.

[0083] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A command processing method, characterized in that: include: Selecting a target warp from the warps competing for the target resource, so that the target warp uses the target resource to process instructions of a target type corresponding to the target resource; When the current instruction of the target warp is an instruction of the target type, keeping the target warp continuously using the target resource; When the current instruction of the target warp does not belong to the target type of instruction or there is no instruction to be executed in the target warp, a new target warp is selected from the warps competing for the target resource.

2. The instruction processing method according to claim 1, characterized in that: The method further comprises: When selecting a target warp, assigning a target token to the target warp; wherein the target token is a token corresponding to an instruction of the target type; When the current instruction of the target warp does not belong to the target type of instruction or there is no instruction to be executed in the target warp, canceling the target token allocated to the target warp; Correspondingly, when the current instruction of the target warp does not belong to the target type of instruction or there is no instruction to be executed in the target warp, a new target warp is selected from the warps competing for the target resource, including: Determine whether there is a thread warp with the target token; When no warp has the target token, a new target warp is selected from warps competing for the target resource, and the target token is allocated to the new target warp.

3. The instruction processing method according to claim 2, characterized in that: The method further comprises: Before allocating a target token to the target warp, it is determined that the target warp has a continuous processing function enabled.

4. The instruction processing method according to claim 3, characterized in that: The method further comprises: If the target warp does not enable the continuous processing function, the target token is not allocated to the target warp.

5. An instruction processing circuit, characterized in that: include: an arbitrator connected to each thread warp, and configured to select a target thread warp from each thread warp competing for a target resource, so that the target thread warp uses the target resource to process instructions of a target type corresponding to the target resource; wherein the target resource is a resource arbitrated by the arbitrator; The arbiter is further configured to be closed when the current instruction of the target warp belongs to the target type of instruction, so as to keep the target warp continuously using the target resource; The control circuit is connected to each of the thread bundles and the arbiter respectively, and is used to trigger the arbiter to re-select a new target thread bundle from the thread bundles competing for the target resource when the current instruction of the target thread bundle does not belong to the instruction of the target type or there is no instruction to be executed in the target thread bundle.

6. The instruction processing circuit according to claim 5, characterized in that: There are multiple arbitrators, and different arbitrators are used to arbitrate different resources; The control circuit comprises: a plurality of flag registers, each flag register being connected to one of the arbitrators and one of the thread warps; the flag register being used to set a register value to a first target value when the connected thread warp is determined as a target thread warp by any of the arbitrators, and to set a register value to a second target value when a current instruction of the connected thread warp does not belong to an instruction of the target type or there is no instruction to be executed in the target thread warp; The arbiter is specifically configured to be closed when the current instruction of the target warp is an instruction of the target type and the register value of the connected flag register is a first target value, so as to keep the target warp continuously using the target resource.

7. The instruction processing circuit according to claim 6, characterized in that: When any arbitrator determines the target warp, among the warps competing for the resources arbitrated by the arbitrator, the register value of the flag register connected to each of the warps except the target warp maintains the second target value.

8. The instruction processing circuit according to any one of claims 5 to 7, characterized in that: The control circuit comprises: A plurality of status registers, respectively connected to the arbitrators, and each of the status registers is connected to one of the warps; The arbiter is specifically used for: when the value of any one of the status registers is the third target value and the thread bundle connected to the status register is the target thread bundle, then: if the current instruction of the thread bundle belongs to the target type of instruction, keeping the target thread bundle continuously using the target resource; if the current instruction of the thread bundle does not belong to the target type of instruction or there is no instruction to be executed in the target thread bundle, reselecting a new target thread bundle from the thread bundles competing for the target resource; and, when the value of any one of the status registers is the fourth target value and the thread bundle connected to the status register is the target thread bundle, after the current instruction of the target thread bundle is processed, reselecting a new target thread bundle from the thread bundles competing for the target resource.

9. A processor, characterized in that: The method comprises the instruction processing circuit as claimed in any one of claims 5 to 8.

10. An electronic device, characterized in that: Comprising a processor as claimed in claim 9.

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