Chip fault control method, display driving circuit, display panel and medium

Abstract

The application provides a chip fault control method, a display driving circuit, a display panel and a medium, which are applied to the display driving circuit, the display driving circuit further comprises a plurality of other chips connected with a timing control chip, and the control method comprises the following steps: the timing control chip sends a fault detection signal to the plurality of other chips every interval of a preset frame number; if the fault detection pin level of at least one chip in the plurality of other chips is a preset level, the plurality of other chips are controlled to stop working. Since the timing control chip and each other chip are in real-time interaction through the fault detection signal and the fault recognition signal, the faulty chip can be located immediately. After the faulty chip is located, the timing control chip controls the plurality of other chips to stop working, so that the faulty chip, the other chips and peripheral devices can be prevented from being burned out, the detection efficiency of the faulty chip is improved, the repair rate of the driving board is improved, and the production cost of the driving board is reduced.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to a chip fault control method, a display driver circuit, a display panel, and a medium. Background Technology

[0002] With the continuous development of display technology, the demand for 8K TVs is growing explosively. Because the driving solution for 8K ultra-high-definition displays uses more IC chips (Integrated Circuit Chips) and components than the driving board for existing 4K resolution displays, the probability of driver board failure is greatly increased.

[0003] In existing technologies, when a driver board malfunctions, a significant amount of time is required to locate the fault before repairs can be made. Furthermore, when one IC chip fails, other IC chips continue to operate and output, which can cause the IC chips and surrounding passive components on the driver board to burn out, rendering the entire display panel unusable and potentially posing safety hazards.

[0004] Existing technologies have drawbacks: locating the fault point takes a lot of time, and the chip may burn itself and other components during a fault. Summary of the Invention

[0005] This application provides a chip fault control method, a display driver circuit, a display panel, and a storage medium, which can solve the problems that locating the fault point requires a lot of time and that the chip itself and other devices may burn out during the fault.

[0006] In a first aspect, embodiments of this application provide a chip fault control method applied to a timing control chip in a display driver circuit. The display driver circuit further includes a plurality of other chips connected to the timing control chip. The chip fault control method includes the following steps performed by the timing control chip:

[0007] At preset frame intervals, fault detection signals are sent to the multiple other chips respectively;

[0008] If the fault detection pin level of at least one of the other chips is at a preset level, then all the other chips will be controlled to stop working.

[0009] In one embodiment, after sending the fault detection signal to the plurality of other chips at preset frame intervals, the method further includes:

[0010] If the fault detection pin level of at least one of the other chips is a preset level, the chip with the fault detection pin level at the preset level is determined to be a faulty chip.

[0011] If a fault identification signal is received from the faulty chip, the location of the faulty chip can be located based on the fault identification signal.

[0012] In one embodiment, the fault identification signal is a preset fault identification character;

[0013] The step of locating the position of the faulty chip based on the faulty chip if a fault identification signal is received from the faulty chip includes:

[0014] If a preset fault identification character is received from the faulty chip during the frame interval, the location of the faulty chip is located based on the preset fault identification character.

[0015] In one embodiment, the fault identification signal is a level signal, which is a high-level signal or a low-level signal within a preset period;

[0016] The step of locating the position of the faulty chip based on the faulty chip if a fault identification signal is received from the faulty chip includes:

[0017] If a level signal with a preset period is received from the faulty chip, the location of the faulty chip is located based on the level signal.

[0018] In one embodiment, the step of controlling all the other chips to stop working if the fault detection pin level of at least one of the plurality of other chips is at a preset level includes:

[0019] If the fault detection pin level of at least one of the other chips is at a preset level, a preset stop-work character is sent to each of the other chips to control all of the other chips to stop working.

[0020] In one embodiment, the plurality of other chips include a boost chip, a power management chip, a correction amplitude chip, and a level conversion chip.

[0021] Secondly, embodiments of this application provide a display driving circuit, including a timing control chip and a plurality of other chips connected to the timing control chip, wherein the timing control chip is used to execute a chip fault control method as described in any one of the first aspects.

[0022] In one embodiment, the timing control chip is connected to the plurality of other chips via an integrated circuit bus, the integrated circuit bus including a first integrated circuit bus and a second integrated circuit bus;

[0023] The output port of the timing control chip is connected to the input ports of the plurality of other chips, and the input port of the timing control chip is connected to the output ports of the plurality of other chips.

[0024] The output port of the timing control chip sends fault detection signals to the other chips via the first integrated circuit bus at preset frame intervals.

[0025] The timing control chip is used to control the other chips to stop working via the first integrated circuit bus;

[0026] When the timing control chip executes the chip fault control method as described in any one of the first aspects, the input port of the timing control chip receives the fault identification signal sent by the faulty chip through the second integrated circuit bus.

[0027] Thirdly, embodiments of this application provide a display panel including a display area and a non-display area, the non-display area surrounding the display area, and also including a display driving circuit as described in the second aspect, the display driving circuit being disposed in the non-display area.

[0028] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the method as described in any of the first aspects.

[0029] It is understood that the beneficial effects of the second to fourth aspects mentioned above can be found in the relevant descriptions in the first aspect above, and will not be repeated here.

[0030] The beneficial effects of the embodiments in this application compared with the prior art are:

[0031] The chip fault control method of this application is applied to a display driver circuit, which also includes multiple other chips connected to a timing control chip. The timing control chip sends fault detection signals to the multiple other chips at preset frame intervals. If the fault detection pin level of at least one of the multiple other chips is at a preset level, the multiple other chips are controlled to stop working. Since the timing control chip and each of the other chips interact in real time through fault detection signals and fault identification signals, the faulty chip can be located immediately. After locating the faulty chip, the timing control chip then controls the multiple other chips to stop working, which can prevent the faulty chip, other chips and peripheral devices from being burned out, improve the detection efficiency of the faulty chip, and reduce the safety risks caused by the faulty chip. At the same time, by reducing the probability of devices on the driver board being burned out, the return rate of the driver board is increased, and the production cost of the driver board is also reduced. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic flowchart of a chip fault control method provided in an embodiment of this application;

[0034] Figure 2 This is a flowchart illustrating the process of sending fault detection signals to multiple other chips at preset frame intervals, according to another embodiment of this application.

[0035] Figure 3 This is a schematic diagram of the communication between the timing control chip and the boost chip, power management chip, calibration amplitude chip and level conversion chip provided in the embodiments of this application, showing the communication between each preset fault detection character and each preset stop working character;

[0036] Figure 4 This is a flowchart illustrating a chip fault control method according to another embodiment of this application;

[0037] Figure 5 This is a flowchart illustrating a chip fault control method according to another embodiment of this application;

[0038] Figure 6 This is a schematic diagram of the connection and transmission of the first display driving circuit provided in an embodiment of this application;

[0039] Figure 7 This is a schematic diagram of a timing control chip receiving a low-level fault identification signal, as provided in an embodiment of this application.

[0040] Figure 8 This is a schematic diagram of the connection and transmission of the second display driving circuit provided in an embodiment of this application;

[0041] Figure 9 This is another schematic diagram of the timing control chip receiving a low-level fault identification signal provided in this application embodiment. Detailed Implementation

[0042] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0043] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0044] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0045] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0046] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0047] With the continuous development of display technology, the demand for 8K TVs is growing explosively. Because the driving solution for 8K ultra-high-definition displays uses more IC chips (Integrated Circuit Chips) and components than the driving board for existing 4K resolution displays, the probability of driver board failure is greatly increased.

[0048] In existing technologies, when a driver board malfunctions, a significant amount of time is required to locate the fault before repairs can be carried out. Furthermore, when one IC chip fails, the other IC chips, which operate independently and whose operational statuses are not transparent to each other, continue to operate and output data. This can cause the IC chips and surrounding passive components on the driver board to burn out, rendering the entire display panel unusable and potentially posing safety hazards.

[0049] Existing technologies have drawbacks: locating the fault point takes a lot of time, and the chip may burn itself and other components during a fault.

[0050] The chip fault control method of this application is applied to a display driver circuit, which also includes multiple other chips connected to a timing control chip. The timing control chip sends fault detection signals to the multiple other chips at preset frame intervals. If the fault detection pin level of at least one of the multiple other chips is at a preset level, the multiple other chips are controlled to stop working. Since the timing control chip and each of the other chips interact in real time through fault detection signals and fault identification signals, the faulty chip can be located immediately. After locating the faulty chip, the timing control chip then controls the multiple other chips to stop working, which can prevent the faulty chip, other chips and peripheral devices from being burned out, improve the detection efficiency of the faulty chip, and reduce the safety risks caused by the faulty chip. At the same time, by reducing the probability of devices on the driver board being burned out, the return rate of the driver board is increased, and the production cost of the driver board is also reduced.

[0051] The technical solution of this application will be described below through specific embodiments.

[0052] In this embodiment, the display driving circuit includes a timing control chip and a plurality of other chips connected to the timing control chip.

[0053] Firstly, such as Figure 1 As shown, this embodiment provides a chip fault control method applied to a timing control chip in a display driver circuit. The chip fault control method includes the following steps performed by the timing control chip:

[0054] S100 sends fault detection signals to multiple other chips at preset frame intervals.

[0055] In one embodiment, a fault detection signal is sent to multiple other chips at preset frame intervals to detect the operating status of other chips in real time, so as to detect faults in other chips in a timely manner.

[0056] In one embodiment, the frame interval is greater than or equal to a preset number of frames. This facilitates the transmission of fault detection signals received by other chips when transmission conditions change, as excessively short frame intervals can cause distortion and reduce the decoding accuracy of other chips. Sending fault detection signals to multiple other chips when the frame interval is greater than or equal to the preset number of frames helps improve the integrity of fault detection signals received by other chips and improves their decoding accuracy.

[0057] In one embodiment, the preset frame number is greater than or equal to 4.

[0058] In one embodiment, the fault detection signal is a level signal. In another embodiment, the level signal is a square wave level signal. When other chips are in operation, the fault detection signal is a continuous square wave level signal, which facilitates fault detection directly through changes in level.

[0059] In one embodiment, if the fault detection signal is a square wave level signal, the timing control chip sends square wave level signals of the same frequency to other chips. Sending and receiving square wave level signals of the same frequency is beneficial to improving response speed, but it cannot identify other chips. In another embodiment, if the fault detection signal is a square wave level signal, the timing control chip sends square wave level signals of different frequencies to other chips. The received signal of each other chip is also a square wave level signal of the corresponding frequency. This allows the timing control chip to communicate with other chips individually and quickly identify other chips, improving the accuracy of subsequent control commands.

[0060] In another embodiment, the fault detection signal is a preset fault detection character, which facilitates the timing control chip to communicate independently with other chips and quickly identify other chips, thereby improving the accuracy of subsequent control commands and enhancing communication security.

[0061] In one embodiment, if the fault detection signal is a preset fault detection character, the timing control chip sends the same preset fault detection character to other chips. Since both sending and receiving the same preset fault detection character improves decoding speed and response speed, it cannot identify other chips. In another embodiment, if the fault detection signal is a preset fault detection character, the timing control chip sends different preset fault detection characters to other chips. The received signal of each other chip is also the corresponding preset fault detection character. This allows the timing control chip to communicate independently with other chips, quickly identify other chips, improve the accuracy of subsequent control commands, and further enhance communication security.

[0062] In one embodiment, the plurality of other chips include a boost converter chip, a power management chip, a calibration chip, and a level conversion chip.

[0063] In one embodiment, corresponding to multiple other chips, the preset fault detection characters include a first preset fault detection character, a second preset fault detection character, a third preset fault detection character, and a fourth preset fault detection character.

[0064] In one embodiment, to facilitate matching with other chip addresses, the preset fault detection character is set to a hexadecimal character. For example, the first preset fault detection character corresponding to the boost chip is 0x11, the second preset fault detection character corresponding to the power management chip is 0x22, the third preset fault detection character corresponding to the calibration amplitude chip is 0x33, and the fourth preset fault detection character corresponding to the level conversion chip is 0x44.

[0065] In one embodiment, such as Figure 2 As shown, after sending fault detection signals to multiple other chips at preset frame intervals, the process also includes:

[0066] S110, if the fault detection pin level of at least one of the multiple other chips is a preset level, the chip with the fault detection pin level at the preset level is determined to be the faulty chip.

[0067] In one embodiment, the preset level is high, and when multiple other chips are in normal working condition, the fault detection pin level is low; when at least one of the multiple other chips is in a faulty state, the fault detection pin level is high, and the chip with the high level on the fault detection pin is determined to be the faulty chip. In one embodiment, the high level is 3.3V.

[0068] In another embodiment, the preset level is low, and when multiple other chips are in normal working condition, the fault detection pin level is high; when at least one of the multiple other chips is in a faulty state, the fault detection pin level is low, and the chip with the low fault detection pin level is determined to be the faulty chip. In one embodiment, the low level is 0V.

[0069] S120: If a fault identification signal is received from a faulty chip, the location of the faulty chip is located based on the fault identification signal.

[0070] In one embodiment, if a fault identification signal is received from a faulty chip, the location of the faulty chip can be located based on the fault identification signal, which greatly reduces the time required to locate the faulty chip and improves maintenance efficiency.

[0071] In one embodiment, after identifying the faulty chip, the faulty chip sends a fault identification signal to the timing control chip. If the timing control chip receives the fault identification signal sent by the faulty chip, it locates the position of the faulty chip based on the fault identification signal.

[0072] In one embodiment, the fault identification signal is a level signal, which is either a high-level signal or a low-level signal within a preset period.

[0073] In one embodiment, if a fault identification signal is received from a faulty chip, the location of the faulty chip is located based on the fault identification signal, including:

[0074] If a preset periodic level signal is received from the faulty chip, the location of the faulty chip can be determined based on the level signal.

[0075] In one embodiment, if a level signal of a preset period is received from a faulty chip, the location of the faulty chip is located based on the level signal. Since at least one of the other chips is already a faulty chip, the level of the fault detection pin is different from the level of the normal working state, while the other normally working chips maintain the level of the normal working state. Therefore, the timing control chip can determine the location of the faulty chip based on the received level signal of the preset period.

[0076] In one embodiment, if the fault detection signal is a square wave level signal and the preset level is high, the fault identification signal is a high-level signal with a preset period; if the fault detection signal is a square wave level signal and the preset level is low, the fault identification signal is a low-level signal with a preset period. The preset period is greater than or equal to four square wave periods. It should be noted that the preset period is set according to the requirements of different display driving circuits, and is not specifically limited in this embodiment.

[0077] In another embodiment, the fault identification signal is a preset fault identification character.

[0078] In another embodiment, if a fault identification signal is received from a faulty chip, the location of the faulty chip is located based on the fault identification signal, including:

[0079] If a preset fault identification character is received from the faulty chip during the frame interval, the location of the faulty chip can be located based on the preset fault identification character.

[0080] In another embodiment, if a preset fault identification character is received from a faulty chip, the location of the faulty chip is located based on the preset fault identification character. Since at least one of the other chips is already a faulty chip, the fault detection pin level is different from the level of the normal working state and cannot continuously feed back the preset fault detection character, while the other normally working chips maintain the level of the normal working state and can continuously feed back the preset fault detection character. Therefore, the timing control chip can determine the location of the faulty chip based on the received preset fault identification character.

[0081] It should be noted that if the fault detection signal is a preset fault detection character, the preset fault identification character of the fault identification signal is a preset communication signal that cannot continuously feed back the preset fault detection character during the frame interval.

[0082] In one embodiment, if two or more chips malfunction simultaneously, only the malfunctioning chips can be identified; it is impossible to distinguish which two chips are specifically faulty. Since the preset fault identification characters have semantic meaning, they correspond to multiple other chips and also to preset fault detection characters. The preset fault identification characters include a first preset fault identification character, a second preset fault identification character, a third preset fault identification character, and a fourth preset fault identification character. The preset communication signals for the first, second, third, and fourth preset fault identification characters can be set to the same communication signal or to different communication signals.

[0083] S200: If the fault detection pin level of at least one of the other chips is at a preset level, then control all the other chips to stop working.

[0084] In one embodiment, if the fault detection pin level of at least one of the multiple other chips is at a preset level, then all the multiple other chips are controlled to stop working, so as to avoid the faulty chip and other normal chips continuing to output work, thereby causing other devices around the faulty chip and other normal chips to be burned out, thus improving the repair rate and reducing production costs.

[0085] In one embodiment, if the fault detection pin level of at least one of the other chips is at a preset level, then controlling all the other chips to stop working includes:

[0086] If the fault detection pin level of at least one of the other chips is at a preset level, a preset stop-work character is sent to each of the other chips to control all of the other chips to stop working.

[0087] In one embodiment, the preset stop characters include a first preset stop character, a second preset stop character, a third preset stop character, and a fourth preset stop character, which facilitates the separate control of different chips.

[0088] In one embodiment, to facilitate address matching with other chips and to correspond with preset fault detection characters, the preset stop-operation character is also set to a hexadecimal character. For example, the first preset stop-operation character corresponding to the boost chip is 0x10, the second preset stop-operation character corresponding to the power management chip is 0x20, the third preset stop-operation character corresponding to the calibration amplitude chip is 0x30, and the fourth preset stop-operation character corresponding to the level conversion chip is 0x40. Figure 3 The diagram illustrates the communication between the timing control chip and the boost chip, power management chip, amplitude correction chip, and level conversion chip, showing the preset fault detection characters and preset stop characters.

[0089] In yet another embodiment, such as Figure 4 As shown, a chip fault control method is applied to a timing control chip in a display driver circuit. The display driver circuit also includes multiple other chips connected to the timing control chip. The chip fault control method includes the following steps performed by the timing control chip:

[0090] S101 sends fault detection signals of the same frequency to multiple other chips at preset frame intervals.

[0091] S102, if a fault identification signal is received from the faulty chip, the location range of the faulty chip is determined based on the fault identification signal. If the fault detection pin level of at least one of the multiple other chips is a preset level, the chip with the fault detection pin level at the preset level is determined to be the faulty chip.

[0092] S103, multiple other chips include a preset first frequency fault chip. If the fault detection signal is a preset fault detection character, the preset fault detection character is sent to the preset first frequency fault chip respectively. The preset first frequency fault chip is the chip that has historically experienced a first frequency fault.

[0093] S104, if the fault identification signal is a preset fault identification character, and the preset fault identification character sent by the fault chip is received during the frame interval, the position of the fault chip in the preset first frequency fault chip is determined based on the preset fault identification character and the position range of the fault chip.

[0094] S105, multiple other chips also include a preset second frequency fault chip. If the fault detection signal is a preset fault detection character, the preset fault detection character is sent to the preset second frequency fault chip respectively. The preset second frequency fault chip is a chip that has historically experienced a second frequency fault, and the value of the first frequency is greater than the value of the second frequency.

[0095] S106, if the fault identification signal is a preset fault identification character, and the preset fault identification character sent by the fault chip is received during the frame interval, the position of the fault chip in the preset second frequency fault chip is determined based on the preset fault identification character and the position range of the fault chip.

[0096] S107, if at least one of the other chips is a faulty chip, send a preset stop working character to the other chips respectively to control all the other chips to stop working.

[0097] In another embodiment, the timing control chip sends a square wave of the same frequency to multiple other chips at preset frame intervals. When the other chips are working normally, after receiving the square wave from the timing control chip, they also send a square wave of the same frequency to the timing control chip at preset frame intervals. If the fault detection pin level of at least one of the multiple other chips is set to a low level, the chip with the low level of the fault detection pin is determined to be the faulty chip. Therefore, if the timing control chip receives a fault identification signal of low level from the faulty chip (i.e., the faulty chip no longer sends a square wave of the same frequency), since the fault identification signal is a continuous low level signal, the timing control chip cannot confirm the specific faulty chip. It's not possible to precisely pinpoint the faulty chip; only its location range can be determined. For example, if there's a continuous low-level signal every preset frame interval, there's one faulty chip; if there are two continuous low-level signals every preset frame interval, there are two faulty chips. Since multiple other chips are pre-classified into preset first-frequency and preset second-frequency faulty chips (the first frequency value is greater than the second frequency value), after determining the location range of the faulty chip, the timing control chip simultaneously sends preset fault detection characters to both the preset first-frequency and preset second-frequency faulty chips. For example, the boost chip and power management chip are designated as preset first-frequency faulty chips. The amplitude correction chip and the level conversion chip are preset second-frequency fault chips. They send 0x11 to the boost chip, 0x22 to the power management chip, 0x33 to the amplitude correction chip, and 0x44 to the level conversion chip, respectively. Based on the preset fault identification characters received from the fault chip, the specific location of the faulty chip can be accurately determined. That is, a normally functioning chip will return the same preset fault identification character to the timing control chip; a chip that does not return the corresponding character is a faulty chip. Therefore, the faulty chip can be accurately located by the absence of a corresponding preset fault identification character. For example, the boost chip may not normally return the preset fault identification character 0x11 to the timing control chip. If the other three chips all return the corresponding characters, then the boost chip is the faulty chip, and the other chips are normal chips. If at least one of the other chips is a faulty chip, a preset stop-work character is sent to each of the other chips to control them to stop working. Since the timing control chip only needs to use a fault identification signal with the same frequency as the fault detection signal when the other chips are working normally, it avoids the reduction of the decoding efficiency of the integrated circuit bus caused by using a preset fault detection character to respond to the timing control chip when the other chips are working normally. This improves the data processing efficiency of the timing control chip, improves the display effect and response speed of the display panel, and can also accurately locate the position of the faulty chip.Furthermore, when all other chips are operating normally, only a fault detection signal of the same frequency needs to be sent to multiple other chips at preset frame intervals. This means that during the time periods when no fault detection signal or preset fault detection character is sent, other tasks between the timing control chip and other chips are not occupied, improving the efficiency of the connection channel between the timing control chip and other chips. Simultaneously, compared to the requirement of four input ports for the timing control chip to locate faulty chips based solely on preset levels, this embodiment only requires one input port, significantly reducing port usage and the number of ports required for the timing control chip.

[0098] In another embodiment, such as Figure 5 As shown, a chip fault control method is applied to a timing control chip in a display driver circuit. The display driver circuit also includes multiple other chips connected to the timing control chip. The chip fault control method includes the following steps performed by the timing control chip:

[0099] S201 sends fault detection signals of the same frequency to multiple other chips at preset frame intervals.

[0100] S202, if a fault identification signal is received from a faulty chip, the location range of the faulty chip and the number of first faulty chips are determined based on the fault identification signal. If the fault detection pin level of at least one chip among multiple other chips is a preset level, the chip with the fault detection pin level at the preset level is determined to be a faulty chip, and the number of first faulty chips is the total number of faulty chips among the other chips.

[0101] S203, multiple other chips include a preset first frequency fault chip. If the fault detection signal is a preset fault detection character, the preset fault detection character is first sent to the preset first frequency fault chip respectively. The preset first frequency fault chip is the chip that has historically experienced a first frequency fault.

[0102] S204, if the fault identification signal is a preset fault identification character, and the preset fault identification character sent by the fault chip is received during the frame interval, the position of the fault chip and the number of the second fault chip in the preset first frequency fault chips are determined based on the preset fault identification character and the position range of the fault chip, and the number of the second fault chip is the number of the fault chips in the preset first frequency fault chips.

[0103] S205, if the number of second faulty chips is equal to the number of first faulty chips, send a preset stop working character to multiple other chips respectively to control multiple other chips to stop working.

[0104] S206, if the number of second faulty chips is less than the number of first faulty chips, and the fault detection signal is a preset fault detection character, and multiple other chips also include preset second frequency faulty chips, then the preset fault detection characters are sent to the preset second frequency faulty chips respectively, wherein the preset second frequency faulty chips are chips that have historically experienced second frequency faults, and the value of the first frequency is greater than the value of the second frequency.

[0105] S207, if the fault identification signal is a preset fault identification character, and the preset fault identification character sent by the fault chip is received during the frame interval, the position of the fault chip in the preset second frequency fault chip and the number of the third fault chip are determined based on the preset fault identification character and the position range of the fault chip. The number of the third fault chip is the number of fault chips in the preset second frequency fault chip, and the sum of the number of the second fault chip and the number of the third fault chip is equal to the number of the first fault chip.

[0106] S208, if the sum of the number of second faulty chips and the number of third faulty chips is equal to the number of first faulty chips, a preset stop working character is sent to multiple other chips to control multiple other chips to stop working.

[0107] In another embodiment, differing from yet another embodiment, after determining the location range of the faulty chip and the number of first faulty chips, since multiple other chips are pre-classified into preset first-frequency faulty chips and preset second-frequency faulty chips, with the first-frequency value being greater than the second-frequency value (i.e., the chip with a higher probability of failure is the preset first-frequency faulty chip), the timing control chip first sends preset fault detection characters to the preset first-frequency faulty chips respectively. For example, if the boost chip and power management chip are set as preset first-frequency faulty chips, 0x11 is sent to the boost chip and 0x22 is sent to the power management chip respectively. Then, based on the preset fault identification characters received from the faulty chips, the specific location of the faulty chip and the number of second faulty chips are precisely located. That is, normally functioning chips will return the same preset fault identification character to the timing control chip, while those that do not return the corresponding character... The chip is a faulty chip, so it can be accurately located by not returning the corresponding preset fault identification character. For example, if the boost chip does not return the preset fault identification character 0x11 to the timing control chip, but the power management chip returns the corresponding character 0x22 to the timing control chip, then the boost chip is a faulty chip, and the other chips are normal chips. If the number of second faulty chips is equal to the number of first faulty chips, that is, all faulty chips are in the preset first frequency of faulty chips, then the accurate location of all faulty chips has been completed. Therefore, there is no need to perform fault detection and location on the chips in the preset second frequency of faulty chips. The timing control chip sends preset stop working characters to multiple other chips to control multiple other chips to stop working, thereby reducing the detection time of faulty chips, improving the detection efficiency of faulty chips, and completing the accurate location of all faulty chips.

[0108] In another embodiment, if the number of second faulty chips is less than the number of first faulty chips, the timing control chip sends preset fault detection characters to preset second-frequency faulty chips respectively. For example, the amplitude correction chip and the level conversion chip are preset second-frequency faulty chips, so 0x33 is sent to the amplitude correction chip and 0x44 is sent to the level conversion chip. Then, based on the preset fault identification characters sent by the received faulty chips, the specific location of the faulty chip and the number of third faulty chips can be accurately located. That is, normally functioning chips will return the same preset fault identification character to the timing control chip, and chips that do not return the corresponding character are faulty chips. Therefore, it is possible to accurately locate which chip is faulty by not returning the corresponding preset fault identification character. For example, if the amplitude correction chip does not normally return the preset fault identification character 0x33 to the timing control chip, but the level conversion chip returns the corresponding character 0x44 to the timing control chip, then the amplitude correction chip is a faulty chip, and the level conversion chip is a normal chip. If the sum of the number of second faulty chips and the number of third faulty chips is equal to the number of first faulty chips, that is, all faulty chips have been accurately located, the timing control chip can accurately locate the faulty chip. The timing control chip sends preset stop characters to multiple other chips to control them to stop working. Since the timing control chip only needs to respond with a fault identification signal at the same frequency as the fault detection signal when other chips are working normally, this avoids reducing the decoding efficiency of the integrated circuit bus by using preset fault detection characters to respond to the timing control chip when other chips are working normally. This improves the data processing efficiency of the timing control chip, enhances the display effect and response speed of the display panel, and allows for precise location of the faulty chip. Furthermore, when all other chips are working normally, only a fault detection signal at the same frequency needs to be sent to multiple other chips at preset frame intervals. During the time periods when no fault detection signal or preset fault detection character is sent, other tasks between the timing control chip and other chips are not occupied, improving the efficiency of the connection channel between the timing control chip and other chips. Also, compared to the four input ports required for locating the faulty chip based solely on preset levels, this embodiment only requires one input port, significantly reducing port usage and the number of ports required for the timing control chip.

[0109] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0110] The advantages of this embodiment compared to the prior art are:

[0111] The chip fault control method of this embodiment is applied to a display driver circuit, which also includes multiple other chips connected to a timing control chip. The timing control chip sends fault detection signals to the multiple other chips at preset frame intervals. If the fault detection pin level of at least one of the multiple other chips is at a preset level, the multiple other chips are controlled to stop working. Since the timing control chip and each of the other chips interact in real time through fault detection signals and fault identification signals, the faulty chip can be located immediately. After locating the faulty chip, the timing control chip then controls the multiple other chips to stop working, which can prevent the faulty chip, other chips and peripheral devices from being burned out, improve the detection efficiency of the faulty chip, and reduce the safety risks caused by the faulty chip. At the same time, by reducing the probability of devices on the driver board being burned out, the return rate of the driver board is increased, and the production cost of the driver board is also reduced.

[0112] Secondly, this embodiment provides a display driving circuit, including a timing control chip and a plurality of other chips connected to the timing control chip. The timing control chip is used to execute a chip fault control method as described in any of the contents of the first aspect.

[0113] In one embodiment, the timing control chip is connected to multiple other chips via an integrated circuit bus, which includes a first integrated circuit bus and a second integrated circuit bus. The output port of the timing control chip is connected to the input ports of the multiple other chips, and the input ports of the timing control chip are connected to the output ports of the multiple other chips. The output port of the timing control chip sends fault detection signals to the multiple other chips via the first integrated circuit bus at preset frame intervals. The timing control chip is used to control the multiple other chips to stop working via the first integrated circuit bus. When the timing control chip executes the chip fault control method as described in any of the first aspects, the input port of the timing control chip receives the fault identification signal sent by the faulty chip via the second integrated circuit bus.

[0114] In one embodiment, the plurality of other chips include a boost converter chip, a power management chip, a calibration amplitude chip, and a level conversion chip. The display driver circuit of this embodiment includes a timing control chip, a boost converter chip, a power management chip, a calibration amplitude chip, and a level conversion chip, wherein the timing control chip is connected to the boost converter chip, the power management chip, the calibration amplitude chip, and the level conversion chip respectively via an integrated circuit bus.

[0115] In one embodiment, such as Figure 6As shown, the display driving circuit includes a first display driving circuit. The output port of the timing control chip of the first display driving circuit is connected to the input ports of the boost chip, the power management chip, the calibration amplitude chip, and the level conversion chip via a first integrated circuit bus. The output port of the timing control chip sends fault detection signals to the boost chip, the power management chip, the calibration amplitude chip, and the level conversion chip via the first integrated circuit bus every preset frame interval. The timing control chip is also used to control multiple other chips to stop working via the first integrated circuit bus. The input port of the timing control chip is connected to the output ports of the boost chip, the power management chip, the calibration amplitude chip, and the level conversion chip via a second integrated circuit bus. The input port of the timing control chip receives fault identification signals sent by the faulty chip via the second integrated circuit bus every preset frame interval.

[0116] In one embodiment, in the first display driving circuit, since the input port of the timing control chip only receives signals from the boost chip, power management chip, calibration amplitude chip and level conversion chip through the second integrated circuit bus, if a level signal of a preset period sent by the faulty chip is received, the position of the faulty chip is located based on the level signal. Since at least one of the other chips is already a faulty chip, the level of the fault detection pin is different from the level of the normal working state, while the other normally working chips maintain the level of the normal working state. Therefore, the timing control chip can determine the position of the faulty chip according to the received level signal of the preset period.

[0117] In one embodiment, in the first display driving circuit, if the fault detection signal is a square wave level signal and the preset level is high, the fault identification signal is a high-level signal with a preset period; if the fault detection signal is a square wave level signal and the preset level is low, the fault identification signal is a low-level signal with a preset period. The preset period is greater than or equal to four square wave periods. Figure 7 This is a schematic diagram of a timing control chip receiving a low-level fault identification signal. It should be noted that the preset period is set according to the requirements of different display driver circuits, and is not specifically limited in this embodiment.

[0118] In another embodiment, in the first display driving circuit, the output port of the timing control chip is connected to the input ports of the boost chip, the power management chip, the amplitude correction chip, and the level conversion chip via a first integrated circuit bus. Every preset frame interval, the output port of the timing control chip sends fault detection signals of the same frequency to the boost chip, the power management chip, the amplitude correction chip, and the level conversion chip via the first integrated circuit bus. If the fault detection pin level of at least one of the boost chip, the power management chip, the amplitude correction chip, and the level conversion chip is at a preset level, the input port of the timing control chip receives the feedback signals from the boost chip, the power management chip, the amplitude correction chip, and the level conversion chip only via the second integrated circuit bus, determining that the chip with the fault detection pin level at the preset level is the faulty chip. Every preset frame interval, the timing control chip sends fault detection signals via the first integrated circuit bus to the boost chip, the power management chip, the amplitude correction chip, and the level conversion chip. The timing control chip sends a square wave of the same frequency to multiple other chips. When these other chips are working normally, after receiving the square wave from the timing control chip, they will also send a square wave of the same frequency to the timing control chip through the second integrated circuit bus at preset intervals. If the fault detection pin level of at least one of the multiple other chips is set to a low level, the chip with the low level of the fault detection pin is identified as the faulty chip. Therefore, if the timing control chip receives a fault identification signal of a low level from the faulty chip (i.e., the faulty chip no longer sends a square wave of the same frequency), the timing control chip cannot identify which other chip is the faulty chip because the fault identification signal is a continuous low level signal. It cannot accurately locate the faulty chip, but can only determine the location range of the faulty chip. For example, if there is a continuous low level signal at preset intervals, there is 1 faulty chip; if there are 2 continuous low level signals at preset intervals, there are 2 faulty chips.Because multiple other chips are pre-classified into preset first-frequency fault chips and preset second-frequency fault chips, with the first-frequency value being greater than the second-frequency value, after determining the location range of the faulty chip, the timing control chip simultaneously sends preset fault detection characters to the preset first-frequency fault chips and preset second-frequency fault chips respectively. For example, if the boost chip and power management chip are set as preset first-frequency fault chips, and the calibration amplitude chip and level conversion chip are set as preset second-frequency fault chips, then 0x11 is sent to the boost chip, 0x22 to the power management chip, and 0x33 to the calibration amplitude chip, respectively. The timing control chip sends 0x44 to the level conversion chip and then pinpoints the location of the faulty chip based on the preset fault identification character sent by the faulty chip. That is, a normally functioning chip will return the same preset fault identification character to the timing control chip via the second integrated circuit bus. Chips that do not return the corresponding character are faulty chips. Therefore, the faulty chip can be accurately located by the absence of the corresponding preset fault identification character. For example, if the boost chip does not return the preset fault identification character 0x11 to the timing control chip, but the other three chips all return the corresponding character, then the boost chip is the faulty chip. Other chips are normal chips; if at least one of the other chips is faulty, a preset stop-work character is sent to each of the other chips to control them to stop working. Since the timing control chip only needs to respond with a fault identification signal at the same frequency as the fault detection signal when the other chips are working normally, this avoids reducing the decoding efficiency of the integrated circuit bus by using a preset fault detection character to respond to the timing control chip when the other chips are working normally. This improves the data processing efficiency of the timing control chip, enhances the display effect and response speed of the display panel, and also allows for precise location of the faulty chip. Furthermore, when all other chips are working normally, only a fault detection signal at the same frequency needs to be sent to the other chips at preset frame intervals. During the time period when no fault detection signal or preset fault detection character is sent, other tasks between the timing control chip and other chips are not occupied, improving the utilization efficiency of the integrated circuit bus between the timing control chip and other chips. Also, compared to the four input ports required for locating the faulty chip based solely on a preset level, this embodiment only requires one input port, significantly reducing port usage and the number of ports on the timing control chip.

[0119] In the design of large-size display panels, it has been found that level conversion chips and power management chips have a higher probability of failure. Therefore, level conversion chips and power management chips are listed as the first frequency failure chips. Boost chips and amplitude correction chips have a lower probability of failure. Therefore, level conversion chips and power management chips are listed as the second frequency failure chips.

[0120] In another embodiment, in the first display driving circuit, unlike the previous embodiment, after determining the location range and number of first faulty chips, since multiple other chips are pre-classified into preset first-frequency faulty chips and preset second-frequency faulty chips, and the value of the first frequency is greater than the value of the second frequency (i.e., the chip with a higher probability of failure is the preset first-frequency faulty chip), the timing control chip first sends preset fault detection characters to the preset first-frequency faulty chips respectively. For example, if the boost chip and the power management chip are set as preset first-frequency faulty chips, 0x11 is sent to the boost chip and 0x22 is sent to the power management chip respectively. Then, based on the preset fault identification characters received from the faulty chips, the specific location of the faulty chip and the number of second faulty chips are accurately located. That is, normally functioning chips will return the same preset fault identification characters to the timing control chip. Chips that return corresponding characters are faulty chips. Therefore, the faulty chip can be accurately located by not returning the corresponding preset fault identification character. For example, if the boost chip does not return the preset fault identification character 0x11 to the timing control chip, but the power management chip returns the corresponding character 0x22 to the timing control chip, then the boost chip is the faulty chip, and the other chips are normal chips. If the number of second faulty chips is equal to the number of first faulty chips, that is, all faulty chips are among the preset first frequency faulty chips, then the accurate location of all faulty chips has been completed. Therefore, there is no need to perform fault detection and location on the preset second frequency faulty chips. The timing control chip sends preset stop working characters to multiple other chips to control multiple other chips to stop working, thereby reducing the detection time of faulty chips, improving the detection efficiency of faulty chips, and completing the accurate location of all faulty chips.

[0121] In another embodiment, if the number of second faulty chips is less than the number of first faulty chips, the timing control chip sends preset fault detection characters to preset second-frequency faulty chips respectively. For example, the amplitude correction chip and the level conversion chip are preset second-frequency faulty chips, so 0x33 is sent to the amplitude correction chip and 0x44 is sent to the level conversion chip. Then, based on the preset fault identification characters sent by the received faulty chips, the specific location of the faulty chip and the number of third faulty chips can be accurately located. That is, normally functioning chips will return the same preset fault identification character to the timing control chip, and chips that do not return the corresponding character are faulty chips. Therefore, it is possible to accurately locate which chip is faulty by not returning the corresponding preset fault identification character. For example, if the amplitude correction chip does not normally return the preset fault identification character 0x33 to the timing control chip, but the level conversion chip returns the corresponding character 0x44 to the timing control chip, then the amplitude correction chip is a faulty chip, and the level conversion chip is a normal chip. If the sum of the number of second faulty chips and the number of third faulty chips is equal to the number of first faulty chips, that is, all faulty chips have been accurately located, the timing control chip can accurately locate the faulty chip. The timing control chip sends preset stop characters to multiple other chips to control them to stop working. Since the timing control chip only needs to respond with a fault identification signal at the same frequency as the fault detection signal when other chips are working normally, this avoids reducing the decoding efficiency of the integrated circuit bus by using preset fault detection characters to respond to the timing control chip when other chips are working normally. This improves the data processing efficiency of the timing control chip, enhances the display effect and response speed of the display panel, and allows for precise location of the faulty chip. Furthermore, when all other chips are working normally, only a fault detection signal at the same frequency needs to be sent to multiple other chips at preset frame intervals. During the time periods when no fault detection signal or preset fault detection character is sent, other tasks between the timing control chip and other chips are not occupied, improving the efficiency of the connection channel between the timing control chip and other chips. Also, compared to the four input ports required for locating the faulty chip based solely on preset levels, this embodiment only requires one input port, significantly reducing port usage and the number of ports required for the timing control chip.

[0122] In one embodiment, such as Figure 8As shown, the display driving circuit includes a second display driving circuit, and the integrated circuit bus also includes a third integrated circuit bus, a fourth integrated circuit bus, a fifth integrated circuit bus, a sixth integrated circuit bus, and a seventh integrated circuit bus. The output port of the timing control chip of the second display driving circuit is connected to the input ports of the boost chip, the power management chip, the amplitude correction chip, and the level conversion chip via the first integrated circuit bus. The first input port of the timing control chip is connected to the output port of the boost chip via the fourth integrated circuit bus, the second input port of the timing control chip is connected to the output port of the power management chip via the fifth integrated circuit bus, the third input port of the timing control chip is connected to the output port of the amplitude correction chip via the sixth integrated circuit bus, and the fourth input port of the timing control chip is connected to the output port of the level conversion chip via the seventh integrated circuit bus. The output port of the timing control chip sends a fault detection signal to the boost chip, the power management chip, the amplitude correction chip, and the level conversion chip via the third integrated circuit bus every preset frame interval, and controls the boost chip, the power management chip, the amplitude correction chip, and the level conversion chip to stop working via the first integrated circuit bus.

[0123] In one embodiment, in the second display driving circuit, if the fault detection signal is a square wave level signal and the preset level is high, the fault identification signal is a high-level signal with a preset period; if the fault detection signal is a square wave level signal and the preset level is low, the fault identification signal is a low-level signal with a preset period. The preset period is greater than or equal to four square wave periods. Figure 9 This diagram illustrates the timing control chip receiving a low-level fault identification signal. It should be noted that the preset period is set according to the requirements of different display driver circuits, and is not specifically limited in this embodiment.

[0124] Thirdly, embodiments of this application provide a display panel including a display area and a non-display area, the non-display area surrounding the display area, and further including a display driving circuit as described in the second aspect, the display driving circuit being used to execute the control method as described in any one of the first aspects, the display driving circuit being disposed in the non-display area.

[0125] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the method as described in any of the first aspects.

[0126] It is understood that the beneficial effects of the second to fourth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here.

[0127] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0128] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0129] In the embodiments provided in this application, it should be understood that the disclosed apparatus / network devices and methods can be implemented in other ways. For example, the apparatus / network device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0130] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0131] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for controlling chip faults, characterized in that, A timing control chip is used in a display driving circuit, the display driving circuit further including a plurality of other chips connected to the timing control chip, the control method including the following steps performed by the timing control chip: At preset frame intervals, a fault detection signal is sent to the other chips; wherein, the fault detection signal is a square wave level signal, and the timing control chip sends square wave level signals of different frequencies to the other chips, and the received signal of each other chip is a square wave level signal of the corresponding frequency; If the fault detection pin level of at least one of the other chips is at a preset level, then all the other chips are controlled to stop working. After sending fault detection signals to the plurality of other chips at preset frame intervals, the method further includes: If the fault detection pin level of at least one of the other chips is a preset level, the chip with the fault detection pin level at the preset level is determined to be a faulty chip. If a fault identification signal is received from the faulty chip, the location of the faulty chip is located based on the fault identification signal. The fault identification signal is a preset fault identification character; the step of locating the position of the fault chip based on the fault identification signal if the fault identification signal sent by the fault chip is received includes: if the preset fault identification character sent by the fault chip is received during the frame interval, the position of the fault chip is located based on the preset fault identification character; wherein, the frame interval is greater than or equal to the preset number of frames; Alternatively, the fault identification signal is a level signal, which is a high-level signal or a low-level signal within a preset period; the step of locating the position of the fault chip based on the fault identification signal if the fault chip is received includes: locating the position of the fault chip based on the level signal if the level signal of the preset period is received.

2. The control method as described in claim 1, characterized in that, The step of controlling all other chips to stop working if the fault detection pin level of at least one of the other chips is at a preset level includes: If the fault detection pin level of at least one of the other chips is at a preset level, a preset stop-work character is sent to each of the other chips to control all of the other chips to stop working.

3. The chip fault control method according to any one of claims 1 to 2, characterized in that, The other chips include boost converter chips, power management chips, amplitude correction chips, and level conversion chips.

4. A display driving circuit, characterized in that, It includes a timing control chip and a plurality of other chips connected to the timing control chip, the timing control chip being used to perform a chip fault control method as described in any one of claims 1 to 3.

5. The display driving circuit as described in claim 4, characterized in that, The timing control chip is connected to the plurality of other chips via an integrated circuit bus, which includes a first integrated circuit bus and a second integrated circuit bus. The output port of the timing control chip is connected to the input ports of the plurality of other chips, and the input port of the timing control chip is connected to the output ports of the plurality of other chips. The output port of the timing control chip sends fault detection signals to the other chips via the first integrated circuit bus at preset frame intervals. The timing control chip is used to control the other chips to stop working via the first integrated circuit bus; When the timing control chip executes the chip fault control method as described in any one of claims 1 to 3, the input port of the timing control chip receives the fault identification signal sent by the faulty chip through the second integrated circuit bus.

6. A display panel, comprising a display area and a non-display area, wherein the non-display area surrounds the display area, characterized in that, The display panel further includes a display driving circuit as described in any one of claims 4 or 5, wherein the display driving circuit is disposed in the non-display area.

7. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1 to 3.

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