Millimeter-wave phase shifters

Abstract

The millimeter-wave phase shifter provided by the present disclosure includes: a power distribution network; two matching baluns connected to the output end of the power distribution network, each of which converts a single-ended signal provided by the power distribution network into a corresponding differential signal; two inter-stage matching baluns, each for synthesizing the differential signal into a corresponding single-ended output signal; two variable gain amplifiers with redundant bits, each of which is connected between the matching balun and the inter-stage matching balun of the corresponding path, and is used to control the amplitude of the single-ended output signal of the corresponding path by adding a redundant bit with a weight of 1; and an orthogonal signal generation network connected to the output end of the two inter-stage matching baluns, for orthogonally synthesizing the two single-ended output signals to obtain a radio frequency output signal. The present disclosure improves the amplitude and phase error of the millimeter-wave phase shifter by rationally controlling the redundant bit state and fine-tuning the amplitude of the I / Q two-path signal.

Description

Technical Field

[0001] The present disclosure relates to the technical field of radio frequency integrated circuits, and in particular to a millimeter wave phase shifter. Background Art

[0002] With the increasing demand for bandwidth and data rates in wireless communications and other fields, millimeter-wave (30GHz-300GHz) technology is considered a viable solution to current microwave communication challenges, such as limited bandwidth and low transmission rates. The millimeter-wave frequency band offers abundant spectrum resources, enabling high-data-rate transmission in communication systems and high-resolution imaging in radar systems. Phased array technology, defined as "electronically controlled radiation electromagnetics," offers a promising solution for achieving high data rates and bandwidth. It employs multiple antennas arranged at fixed distances, generating signals at different times. When these waves overlap and interfere with each other, they create a constructive signal in one direction and a destructive signal in another, thus achieving beam shaping, increasing signal output power and extending the beam's reach. Phase shifters are essential components in phased array systems.

[0003] Among the many circuit structures that can achieve phase shifting, vector interpolation phase shifters are an excellent choice, offering wide phase shift accuracy and range. A classic vector interpolation phase shifter consists of a quadrature signal generation network, I and Q variable gain amplifiers, and a power combiner network. Adjusting the gain of the variable gain amplifiers adjusts the phase shifter's accuracy, resulting in a more compact chip.

[0004] Traditional digital variable-gain amplifiers directly calculate the gain level based on the required phase-shift accuracy. This results in large amplitude and phase errors near the critical points (0°, 90°, 180°, and 270°) of the four quadrants of the rectangular coordinate system caused by insufficient adjustment capability in the vector interpolation phase shifter they construct.

[0005] Traditional phase shifter architectures often utilize a quadrature signal generation network composed of unbalanced transformers. This creates a natural asymmetry between the I and Q paths, leading to significant phase and amplitude errors. Traditional phase shifter connections also typically utilize a sequential connection sequence of a quadrature signal generation network, a variable gain amplifier, and a power combiner network, resulting in significant phase errors. Summary of the Invention

[0006] The present disclosure aims to solve at least one of the technical problems existing in the prior art.

[0007] To this end, the present disclosure provides a millimeter-wave phase shifter based on a redundant bit design to overcome the problem of large amplitude and phase errors introduced in specific intervals by vector interpolation phase shifters composed of existing digital variable-gain amplifiers. By adding redundant bit groups with the same weight as the 1-bit MOS transistor group to the digital variable-gain amplifier, the present disclosure increases the gain adjustment range of the variable-gain amplifier, thereby reducing the amplitude and phase errors of the phase shifter. The millimeter-wave phase shifter provided by the present disclosure includes:

[0008] A power distribution network is used to split the RF input signal into two single-ended signals with the same phase;

[0009] an I-way matching balun and a Q-way matching balun connected to the output end of the power distribution network, wherein the I-way matching balun is used to convert one single-ended signal provided by the power distribution network into an I-way differential signal, and the Q-way matching balun is used to convert another single-ended signal provided by the power distribution network into a Q-way differential signal;

[0010] an I-channel inter-stage matching balun and a Q-channel inter-stage matching balun, wherein the I-channel inter-stage matching balun is used to combine the I-channel differential signal into an I-channel single-ended output signal, and the Q-channel inter-stage matching balun is used to combine the Q-channel differential signal into a Q-channel single-ended output signal;

[0011] an I-channel variable gain amplifier and a Q-channel variable gain amplifier with redundant bits, the I-channel variable gain amplifier being connected between the I-channel matching balun and the I-channel inter-stage matching balun, and being used to control the amplitude of the I-channel single-ended output signal by adding redundant bits with a weight of 1; and the Q-channel variable gain amplifier being connected between the Q-channel matching balun and the Q-channel inter-stage matching balun, and being used to control the amplitude of the Q-channel single-ended output signal by adding redundant bits with a weight of 1; and

[0012] The orthogonal signal generating network connected to the output ends of the I-path inter-stage matching balun and the Q-path inter-stage matching balun is used to perform orthogonal synthesis on the I-path and Q-path single-ended output signals to obtain a radio frequency output signal.

[0013] In some embodiments, each variable gain amplifier is respectively composed of a half-bit weight unit, a redundant bit weight unit and N n-bit weight units connected to provide a total of N+2 positive phase control bits and N+2 negative phase control bits, N=log2(360 / x), x is the required phase shift step, wherein the weights of the positive and negative phase control bits provided by the half-bit weight unit are 1 and 0 respectively, the weights of the positive and negative phase control bits provided by the redundant bit weight unit are ±1 respectively, and the weights of the positive and negative phase control bits provided by the remaining n-bit weight units are x n The relationship between its digit n is x n =±2n-1 , n∈[1,N].

[0014] In some embodiments, the redundant bit weight unit and each n-bit weight unit are respectively composed of a differential cascode amplifier with a tail current tube and an inverter; the differential cascode amplifier includes 7 transistors, transistors M1 and M2 constitute a group of switch tubes, transistors M3 and M4 constitute another group of switch tubes, transistors M5 and M6 constitute a differential pair tube, and transistor M7 serves as a tail current tube; wherein the source end of transistor M7 is grounded, the drain end of transistor M7 is connected to the source end of transistor M5 and transistor M6, and the gate end of transistor M7 is connected to the bias voltage V Bias The gate terminals of transistor M5 and transistor M6 are respectively connected to the differential output terminals of the corresponding matching balun; the source terminals of transistor M1 and transistor M2 are connected to the drain terminal of transistor M5, the source terminals of transistor M3 and transistor M4 are connected to the drain terminal of transistor M6, the drain terminals of transistor M1, transistor M2, transistor M3 and transistor M4 are differentially connected to the differential input terminals of the corresponding inter-stage matching balun, the gate terminals of transistor M1 and transistor M4 are connected to the output terminal of the inverter, and the gate terminals of transistor M2 and transistor M3 are connected to the input terminal of the inverter.

[0015] In some embodiments, the transistors are all MOS transistors.

[0016] In some embodiments, the half-bit weight unit is composed of a differential cascode amplifier with a tail current tube and an inverter; the differential cascode amplifier includes 7 transistors, transistors M1 and M2 constitute a group of switch tubes, transistors M3 and M4 constitute another group of switch tubes, transistors M5 and M6 constitute a differential pair tube, and transistor M7 serves as a tail current tube; wherein the source terminal of transistor M7 is grounded, the drain terminal of transistor M7 is connected to the source terminals of transistors M5 and transistor M6, and the gate terminal of transistor M7 is connected to the bias voltage V Bias The gate terminals of transistor M5 and transistor M6 are respectively connected to the differential output terminals of the corresponding matching balun; the source terminals of transistor M1 and transistor M2 are connected to the drain terminal of transistor M5, the source terminals of transistor M3 and transistor M4 are connected to the drain terminal of transistor M6, the drain terminals of transistor M1 and crystal transistor M4 are differentially connected to the differential input terminals of the corresponding inter-stage matching balun, the drain terminals of transistors M2 and M3 are connected to the power supply voltage VDD, the gate terminals of transistor M1 and transistor M4 are connected to the output terminal of the inverter, and the gate terminals of transistor M2 and transistor M3 are connected to the input terminal of the inverter.

[0017] In some embodiments, the transistors are all MOS transistors.

[0018] In some embodiments, the orthogonal signal generating network includes a transformer, wherein the primary coil and the secondary coil of the transformer are formed by metal stacking, and the paths through which the metals forming the primary coil and the secondary coil of the transformer pass are the same.

[0019] In some embodiments, the orthogonal signal generating network further includes an isolation resistor and two adjustment capacitors. The input end of the primary coil of the transformer is respectively connected to the output ends of the I and Q inter-stage matching baluns, one end of the secondary coil of the transformer is connected to the isolation resistor, and the other end of the secondary coil of the transformer is used to output the RF output signal. The two adjustment capacitors are connected across the primary coil and the secondary coil.

[0020] In some embodiments, the primary coil and secondary coil of the transformer are respectively composed of two layers of stacked square metal coils, and the paths passed by each layer of metal of the primary coil and secondary coil of the transformer are completely consistent. The first metal constitutes the 1 / 2 circumference outer circle and the 1 / 2 circumference inner circle of the first layer of metal coil in the primary coil, and the second metal constitutes the 1 / 2 circumference outer circle and the 1 / 2 circumference inner circle of the second layer of metal coil in the primary coil; the first metal constitutes the 1 / 2 circumference outer circle and the 1 / 2 circumference inner circle of the first layer of metal coil in the secondary coil, and the second metal constitutes the 1 / 2 circumference outer circle and the 1 / 2 circumference inner circle of the second layer of metal coil in the secondary coil.

[0021] In some embodiments, the first metal uses a metal layer M9 provided by a 65 nm CMOS process, and the second metal uses a metal layer M8 provided by a 65 nm CMOS process.

[0022] The technical features and beneficial effects of the present disclosure are as follows:

[0023] 1. Improve amplitude and phase errors. By adding redundant bits with the same weight as the 1-bit MOS transistor group to the digital variable gain amplifier, the gain adjustment range of the variable gain amplifier is increased, thereby reducing the amplitude and phase errors of the phase shifter. By adjusting the layout of the unbalanced transformer to a balanced transformer, the phase and amplitude errors are improved. By changing the connection sequence within the phase shifter, the phase error is improved.

[0024] 2. No additional power consumption or chip area is added. The added redundant bit has a weight of 1 in the digital variable gain amplifier and has no significant impact on the overall power consumption. The area of ​​the MOS tube is almost negligible compared to the passive components required for matching. Replacing the connection order and adding a redundant bit will not increase the layout area. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1A schematic diagram of the circuit structure of a millimeter-wave phase shifter based on redundant bit design provided in an embodiment of the present disclosure;

[0026] FIG2( a ) is a schematic diagram of the circuit structure of the n-th weight unit in the millimeter-wave phase shifter provided by an embodiment of the present disclosure;

[0027] FIG2( b ) is a schematic diagram of the circuit structure of a half-bit weight unit in a millimeter-wave phase shifter provided by an embodiment of the present disclosure;

[0028] Figure 3 A schematic structural diagram of a balanced transformer in a millimeter-wave phase shifter provided in an embodiment of the present disclosure;

[0029] Figure 4 1 is a comparison of the amplitude and phase errors of the vector interpolation phase shifter according to the embodiment of the present disclosure and the RMS values ​​of the amplitude and phase errors of a conventional phase shifter using the same 65 nm CMOS process. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solutions and advantages of this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0031] On the contrary, this application covers any alternatives, modifications, equivalents, and solutions made within the spirit and scope of this application as defined by the claims. Furthermore, to facilitate a better understanding of this application, certain specific details are described in detail below in the detailed description of this application. Those skilled in the art will be able to fully understand this application without these details.

[0032] See also Figure 1 , an embodiment of the present disclosure provides a millimeter wave phase shifter, comprising:

[0033] Power distribution network, used to divide the RF input signal RF IN Split into two single-ended signals with the same phase;

[0034] An I-channel matching balun and a Q-channel matching balun connected to the output end of the power distribution network, the I-channel matching balun is used to convert one single-ended signal provided by the power distribution network into an I-channel differential signal, and the Q-channel matching balun is used to convert another single-ended signal provided by the power distribution network into a Q-channel differential signal;

[0035] The I-channel inter-stage matching balun and the Q-channel inter-stage matching balun are used to combine the I-channel differential signal into an I-channel single-ended output signal, and the Q-channel inter-stage matching balun is used to combine the Q-channel differential signal into a Q-channel single-ended output signal;

[0036] an I-channel variable gain amplifier and a Q-channel variable gain amplifier with redundant bits, the I-channel variable gain amplifier being connected between the I-channel matching balun and the I-channel interstage matching balun and being used to control the amplitude of the I-channel single-ended output signal by adding redundant bits with a weight of 1, and the Q-channel variable gain amplifier being connected between the Q-channel matching balun and the Q-channel interstage matching balun and being used to control the amplitude of the Q-channel single-ended output signal by adding redundant bits with a weight of 1; and

[0037] The orthogonal signal generating network connected to the output of the I-way inter-stage matching balun and the Q-way inter-stage matching balun is used to perform orthogonal synthesis on the I-way and Q-way single-ended output signals to obtain the RF output signal RF OUT .

[0038] In some embodiments, the power distribution network is composed of a 0° power splitter, which divides the RF input signal RF IN It is divided into two paths with the same phase. The input end of the 0° power divider is connected to the RF input signal, the first output end is connected to the I-path matching balun, and the second output end is connected to the Q-path matching balun.

[0039] In some embodiments, each of the I / Q paths has a matching balun, and each matching balun has a primary coil (L1, L3) and a secondary coil (L2, L4). One end of the primary coil is connected to the output end of the power distribution network, and the other end of the primary coil is grounded. The two ends of the secondary coil are differentially connected to the non-inverting input and inverting input ends of a corresponding variable gain amplifier. The center tap of the secondary coil is connected to the bias voltage (VB_I, VB_Q) to provide a determined static operating point for the corresponding variable gain amplifier.

[0040] In some embodiments, each of the I / Q channels has a variable gain amplifier, and the variable gain amplifiers of the I / Q channels have the same structure. Here, one of the variable gain amplifiers is used as an example for explanation. The variable gain amplifier consists of a half-bit weight unit (in Figure 1 In the figure, the half-bit weight unit is represented by an upper triangle symbol with 1 / 0 inside), a redundant bit weight unit (in Figure 1 In the figure, the redundancy bit weight unit is represented by an upper triangle symbol with ±1 inside and a bold outer frame) and N n-bit weight units (in Figure 1 In the figure, the remaining triangles (except the half-bit weight unit and the redundant bit weight unit) are connected in parallel to provide N+2 positive phase control bits and N+2 negative phase control bits, N=log2(360 / x), z is the required phase shift step, among which the weights of the positive and negative phase control bits provided by the half-bit weight unit are 1 and 0 respectively, the weights of the positive and negative phase control bits provided by the redundant bit weight unit are ±1 respectively (0° corresponds to positive phase, which is positive output, 180° corresponds to negative phase, which is negative output), and the weights of the positive and negative phase control bits provided by the remaining n-bit weight units are xn The relationship between its digit n is x n =±2 n-1 , n∈[1,N].

[0041] Furthermore, each weight unit is respectively composed of a differential cascode amplifier with a tail current tube and an inverter. The redundant bit weight unit and the N n-bit weight units have the same structure and connection method. The n-th bit weight unit in the I path is now taken as an example for explanation. Referring to Figure 2(a), the n-th bit weight unit contains a differential cascode amplifier composed of 7 MOS transistors and an inverter INV. Among the 7 MOS transistors, transistor M7 serves as a tail current tube, transistors M5 and M6 form a differential pair tube, and transistors M1 to M4 are grouped in pairs to form two groups of switch tubes. The source terminal of transistor M7 is grounded, the drain terminal of transistor M7 is connected to the source terminals of transistors M5 and M6, and the gate terminal of transistor M7 is connected to the bias voltage V Bias ; The source terminals of transistors M5 and M6 are connected to the drain terminal of transistor M7, and the gate terminals of transistors M5 and M6 are respectively connected to the positive and negative phases of the differential output terminals of the secondary coil (L2 or L4) of the matching balun, that is, the secondary coil of the matching balun provides a bias voltage VB_I for the gate terminals of transistors M5 and M6, and the drain terminals of transistors M5 and M6 are connected to the source terminals of two groups of switch tubes. Specifically, the drain terminal of transistor M5 is connected to the source terminals of transistors M1 and M2, and the drain terminal of transistor M6 is connected to the source terminals of transistors M3 and M4; transistors M1 and M2 serve as a group of switch tubes, and transistors M3 and M4 serve as a group of switch tubes. The source terminals of transistors M1 and M2 are connected to the drain terminal of transistor M5, the source terminals of transistors M3 and M4 are connected to the drain terminal of transistor M6, and the drain terminals of transistors M1 to M4 are differentially connected to the differential input terminals of the corresponding inter-stage matching balun. Specifically, the drain terminals of transistors M1 and M3 are connected to the inverting terminals of the differential input terminals of the corresponding inter-stage matching balun, the drain terminals of transistors M2 and M4 are connected to the non-inverting terminals of the differential input terminals of the corresponding inter-stage matching balun, the gate terminals of transistors M1 and M4 are connected to the output terminal of inverter INV, and the gate terminals of transistors M2 and M3 are connected to the input terminal of inverter INV. The structure of the half-bit weight unit is similar to that of the redundant bit weight unit, but the connection method of the transistors of the two is slightly different. See Figure 2(b). In the half-bit weight unit, the source terminal of transistor M7 is grounded, the drain terminal of transistor M7 is connected to the source terminals of transistors M5 and M6, and the gate terminal of transistor M7 is connected to the bias voltage V BiasThe source terminals of transistors M5 and M6 are connected to the drain terminal of transistor M7, and the gate terminals of transistors M5 and M6 are connected to the positive and negative phases of the differential output terminals of the secondary coil (L2 or L4) of the corresponding matching balun, that is, the secondary coil of the matching balun provides a bias voltage VB_I for the gate terminals of transistors M5 and M6, and the drain terminals of transistors M5 and M6 are connected to the source terminals of the two groups of switch tubes. Specifically, the drain terminal of transistor M5 is connected to the source terminals of transistors M1 and M2, and the drain terminal of transistor M6 is connected to the source terminals of transistors M3 and M4; transistor M1 and M2 serve as a group of switching tubes, and transistors M3 and M4 serve as a group of switching tubes. The source terminals of transistors M1 and M2 are connected to the drain terminal of transistor M5, and the source terminals of transistors M3 and M4 are connected to the drain terminal of transistor M6. The drain terminals of transistors M1 and M4 are differentially connected to the differential input terminals of the corresponding inter-stage matching balun. The drain terminals of transistors M2 and M3 are connected to the power supply voltage VDD. The gate terminals of transistors M1 and M4 are connected to the output terminal of the inverter INV, and the gate terminals of transistors M2 and M3 are connected to the input terminal of the inverter INV.

[0042] In some embodiments, each of the I / Q paths has an interstage matching balun, and each interstage matching balun has a primary coil (L5, L7) and a secondary coil (L6, L8). The input end of the primary coil is connected to the differential output end of the corresponding variable gain amplifier, the center tap of the primary coil is connected to the power supply voltage VDD to power the variable gain amplifier, one end of the secondary coil (serving as the output end of the secondary coil) is connected to the input end of the orthogonal signal generating network, and the other end of the secondary coil is grounded.

[0043] In some embodiments, the orthogonal signal generation network is composed of a transformer, two adjustment capacitors C1 and C2, and an isolation resistor Res. The two input ends of the primary coil L10 of the transformer are respectively connected to the output ends of the secondary coils L6 and L8 of the I and Q interstage matching baluns. One end of the secondary coil L9 of the transformer is connected to the isolation resistor Res, and the other end of the secondary coil L9 is used to output the RF output signal RF OUT , two adjustment capacitors C1 and C2 are connected between the primary coil L10 and the secondary coil L9.

[0044] Furthermore, in order to improve the problem of deterioration of amplitude and phase performance due to different resistance losses in the traditional structure, the primary coil L10 and the secondary coil L9 of the transformer in this embodiment adopt a balanced connection. Specifically, the primary coil and the secondary coil of the transformer are formed by metal stacking, and the metal forming the primary coil and the secondary coil of the transformer pass through the same path. Figure 3As shown in the figure, taking the quadrilateral transformer as an example, the solid line represents the primary coil L10, the dotted line represents the secondary coil L9, the bold part uses the M9 layer metal that comes with the 65nm CMOS process, and the thin line part uses the M8 layer metal that comes with the 65nm CMOS process. The primary coil L10 and the secondary coil L9 pass through exactly the same metal path.

[0045] The following describes the embodiments of the present disclosure in conjunction with the accompanying drawings:

[0046] The present disclosure provides a millimeter wave phase shifter, the circuit structure of which is as follows: Figure 1 As shown, it includes a power distribution network, two matching baluns, two variable gain amplifiers with redundant bits, two inter-stage matching baluns and an orthogonal signal generation network connected in sequence; wherein:

[0047] In this embodiment, the power distribution network uses a 0° power divider composed of the metal layer M9 of the 65nm CMOS process. The input end of the power distribution network is connected to the RF input signal RF IN The differential output ends of the power distribution network are connected to the signal input ends of the matching baluns of the I and Q paths respectively.

[0048] Matching baluns are provided, one each for the I / Q paths. In this embodiment, both are octagonal in shape. The primary coils (L1, L3) of the matching baluns are constructed from the metal layer M9 native to the 65nm CMOS process, while the secondary coils (L2, L4) of the matching baluns are constructed from the metal layer M8 native to the 65nm CMOS process. The primary coils (L1, L3) have no center tap; one end is connected to the power distribution network and the other end is grounded. The secondary coils (L2, L4) are connected to the non-inverting and inverting inputs of the I / Q variable gain amplifiers, respectively. The center taps of the secondary coils (L2, L4) provide the bias voltages VB_I and VB_Q for the variable gain amplifiers.

[0049] Variable gain amplifier, in this embodiment, there is one each for I / Q paths, and each path is composed of 7*[log2(360 / x)+2] MOS transistors and their control signals. Every 7 transistors constitute a weight unit, with a total of seven groups and a total of 7 pairs of control signals. Among them, the seven positive phase control signals are given by the positive phase control bit S+, and the corresponding seven negative phase bias S- are implemented by the inverter INV inside each weight unit to achieve the inversion operation. Taking the seven transistors in the nth position (n∈[1,5]) as an example, M1, M2, M3, M4, M5, M6, and M7 are all NMOS tubes, all biased in the saturation region, among which transistors M1, M2, M3, and M4 are used as switching tubes, transistors M5 and M6 form a differential pair tube, transistor M7 is used as a tail current tube, and the 7 transistors share an RF protection ring. The source end of transistor M7 is grounded, the drain end is connected to the source end of the differential pair tubes M5 and M6 using the M4 layer metal, and the gate end is connected to the external bias V using the M4 layer metal. Bias, used for gain adjustment. The source terminals of transistors M5 and M6 are connected to the drain terminal of transistor M7 using the M4 layer metal. The drain terminal of transistor M5 is connected to the source terminals of transistors M1 and M2 using the M4 layer metal. The gate terminal of transistor M5 is connected to the positive input terminal of the variable gain amplifier of the I / Q path using the M8 layer metal. The drain terminal of transistor M6 is connected to the source terminals of transistors M3 and M4 using the M4 layer metal. The gate terminal of transistor M6 is connected to the negative input terminal of the variable gain amplifier of the I / Q path using the M9 layer metal. The source terminals of switch tubes M1 and M2 are connected to the M4 layer metal. The gate terminals of the switches M1 and M4 are connected to the drain of transistor M5 using the M4 metal layer. The drain terminals of the switches M1 and M3 are connected to the inverting output terminal of the I / Q circuit using the M8 metal layer. The drain terminals of the switches M2 and M4 are connected to the non-inverting output terminal of the I / Q circuit using the M9 metal layer. The gate terminals of the switches M1 and M4 are connected to the output terminal of the inverter INV using the M2 metal layer. The gate terminals of the switches M2 and M3 are connected to the input terminal of the inverter INV using the M3 metal layer. The input terminal of the inverter INV is connected to the n-th bit control signal Bitn_I or Bitn_Q. The structure of the other six groups of MOS transistors in each path is the same as that of the fifth-bit weight unit. The binary weights of the MOS tube sizes are: 0 control bit: 1 (provided by the half-bit weight unit), redundant bit: 1 (provided by the redundant bit weight unit), 1 control bit: 1 (provided by the 1st bit weight unit), 2 control bits: 2 (provided by the 2nd bit weight unit), 3 control bits: 4 (provided by the 3rd bit weight unit), 4 control bits: 8 (provided by the 4th bit weight unit), 5 control bits: 16 (provided by the 5th bit weight unit). The size of the MOS transistor with a weight of 1 is as follows: M1, M2, M3, M4: 4μm / 1μm, M5, M6: 2μm / 1μm, M7: 1μm / 1μm; the size of the MOS transistor with a weight of 2 is as follows: M1, M2, M3, M4: 8μm / 1μm, M5, M6: 4μm / 1μm, M7: 2μm / 1μm; the size of the MOS transistor with a weight of 4 is as follows: M1, M2, M3, M4: 16μm m / 1μm, M5, M6: 8μm / 1μm, M7: 4μm / 1μm; for the MOS transistor with a weight of 8, the size values ​​are as follows: M1, M2, M3, M4: 32μm / 1μm, M5, M6: 16μm / 1μm, M7: 8μm / 1μm; for the MOS transistor with a weight of 16, the size values ​​are as follows: M1, M2, M3, M4: 64μm / 1μm, M5, M6: 32μm / 1μm, M7: 16μm / 1μm. All tail current tubes are isolated from the signal lines by the ground plane formed by the metal layers M5 and M6 and the through holes between them. The gate ends of all tail current tubes are connected together by the M4 layer metal; the gate ends of all differential pair tubes M5 are connected by the M8 layer metal, and the gate ends of all M6 are connected by the M9 layer metal. The output ends of all M1 and M4 switch tubes are connected together by the M8 layer metal, and the output ends of all M2 and M3 switch tubes are connected together by the M9 layer metal.

[0050] The interstage matching balun, one for each I / Q path, is octagonal in shape in this embodiment. The primary coils (L5, L7) are constructed from an M9 metal layer, and the secondary coils (L6, L8) are constructed from an M8 metal layer. The primary coil's two ends are connected to the positive and negative outputs of the variable gain amplifier, respectively. Its center tap is connected to the power supply voltage VDD to power the variable gain amplifier. One end of the secondary coil is connected to the input of the quadrature signal generation network, and the other end is grounded. The secondary coil has no center tap.

[0051] Orthogonal signal generation network. In this embodiment, the primary coil L9 and the secondary coil L10 in the orthogonal signal generation network are each composed of two layers of stacked regular quadrilateral metal coils. The paths through which the metal layers of the primary coil L9 and the secondary coil L10 pass are completely consistent. Figure 3 In order to clearly illustrate the specific structure of the primary coil L9 and the secondary coil L10, Figure 3 The figure shows the metal coils of each layer in the primary coil L9 and the secondary coil L10 in an exploded form. In actual use, the primary coil L9 and the secondary coil L10 are stacked. The metal layer M9 of the 65nm CMOS process forms the outer circle of the upper metal coil (or lower metal coil) of the primary coil L9, which is 1 / 2 of the circumference (see Figure 3 The thick solid line in the figure) and the inner circle of 1 / 2 circumference (see Figure 3 The thin solid line in the figure) is used to form the 1 / 2 outer circle and 1 / 2 inner circle of the lower metal coil (or upper metal coil) in the primary coil L9 by the metal layer M8 of the 65nm CMOS process. The two ends of the primary coil L9 are connected to the output ends of the I and Q inter-stage matching baluns. The 1 / 2 outer circle of the upper metal coil (or lower metal coil) in the secondary coil L10 is formed by the metal layer M9 of the 65nm CMOS process (see Figure 3 The thick dashed line in the figure) and the inner circle of 1 / 2 circumference (see Figure 3 The thin dashed line segment in the figure) is used. The metal layer M8 of the 65nm CMOS process forms the 1 / 2 circumference outer circle and the 1 / 2 circumference inner circle of the lower metal coil (or upper metal coil) in the secondary coil L10. One end of the secondary coil L10 is connected to a matching resistor, and the other end is connected to the output RF output signal RF OUT .

[0052] In the millimeter-wave phase shifter based on redundant bit design provided in the embodiment of the present disclosure, the tail current tube of each bias voltage is biased at 0.5V, the bias of the differential pair tube is at 1V, the control signal provided when the switch tube is turned on is 1.2V, and the control signal provided when it is turned off is 0V.

[0053] The working principle of the millimeter wave phase shifter based on redundant bit design provided in the embodiment of the present disclosure is as follows:

[0054] After the signal is divided into two equal-amplitude and in-phase signals through the 0° power distribution network, it is converted into a differential signal through two self-matching baluns. The differential signal passes through a digital variable gain amplifier and adjusts the amplitude of the I and Q signals by adjusting the control bit. The relationship between the initial value of the I control bit and the required phase shift angle θ and the phase shift number n is: the I control bit is 2 n The relationship between the initial value of the Q-path control bit and the required phase shift angle θ and the phase shift number n is: n The binary representation of the integer sinθ-1) is obtained. At this time, the redundant bits do not output signals. Due to the influence of parasitic parameters in the layout, only using the initial control bits cannot achieve good gain and phase performance. At this time, it can be improved by fine-tuning the control bits. However, near the four quadrant transitions of 0°, 90°, 180°, and 270°, the output of the I or Q path often reaches 2 n -1, the adjustment capability is limited. Depending on the needs, the redundant bits can output signals with a weight of -2, 0, or 2 to assist in optimizing circuit performance. When the redundant bits in both the I and Q paths simultaneously output +1 and -1 signals, the resulting signal amplitude is 0. Simultaneously outputting +1 or -1 signals results in an overall output of +2 or -2. These adjusted signals are fed into the 0° and 90° inputs of the quadrature signal generation network for quadrature synthesis, producing a phase shift effect.

[0055] To minimize resistive losses, passive component designs often utilize thicker top metal layers. In traditional transformer models, the primary coil is drawn using the M9 metal layer, and the secondary coil is drawn using the M8 metal layer. In TSMC's 65nm CMOS process, the M9 metal layer is 3.4μm thick, while the M8 metal layer is only 0.9μm. This results in smaller resistive losses in the primary coil than in the secondary coil, leading to inherent symmetry issues in the I and Q paths, which degrades the network's amplitude and phase characteristics. In this design, a balanced transformer utilizes short-distance bridges between the AP and M7 metal layers, ensuring that each current path contains a loop of M9 metal in series with a loop of M8 metal of equal length. This improved balanced transformer physically maintains the same path losses for the primary and secondary coils, mitigating the degraded amplitude and phase performance associated with unequal resistive losses in traditional structures.

[0056] In the phase shifter layout design, since the balun, phase shifter, and variable gain amplifier are not completely ideal, some phase offset will be introduced. In addition, the variable gain amplifier has a limited adjustment range, which will cause the phase error of the phase shifter to be relatively large when switching between the four quadrants, resulting in a deterioration of the phase performance of the phase shifter. Therefore, a redundant bit with a weight of 1 is added to the variable gain amplifier. The drain terminal of the switch pair is differentially connected to the output terminal of the amplifier, which increases the adjustment range of the amplifier from -31 to +31 to -32 to +32. This optimizes the performance of the phase shifter without significantly increasing the circuit power consumption.

[0057] This embodiment uses 65nm CMOS technology (a conventional manufacturing technology in this field) to prepare a millimeter wave phase shifter based on redundant bit design, and the simulation results are shown in FIG. Figure 4 given. Figure 4 A comparison of the RMS values ​​of amplitude error and phase error of the phase shifter before and after using redundant bit design and balanced quadrature signal generation network design is given.

[0058] In summary, the present disclosure can improve the amplitude error and phase error of the phase shifter.

[0059] The above embodiments verify the correctness and effectiveness of the present disclosure. The above description is only a millimeter wave vector interpolation phase shifter circuit based on redundant bit design in a specific CMOS process and a specific frequency band, and is not intended to limit the scope of protection of the present disclosure.

Claims

1. A millimeter wave phase shifter, characterized in that: include: A power distribution network is used to split the RF input signal into two single-ended signals with the same phase; an I-way matching balun and a Q-way matching balun connected to the output end of the power distribution network, wherein the I-way matching balun is used to convert one single-ended signal provided by the power distribution network into an I-way differential signal, and the Q-way matching balun is used to convert another single-ended signal provided by the power distribution network into a Q-way differential signal; an I-channel inter-stage matching balun and a Q-channel inter-stage matching balun, wherein the I-channel inter-stage matching balun is used to combine the I-channel differential signal into an I-channel single-ended output signal, and the Q-channel inter-stage matching balun is used to combine the Q-channel differential signal into a Q-channel single-ended output signal; An I-channel variable gain amplifier and a Q-channel variable gain amplifier with redundant bits, the I-channel variable gain amplifier being connected between the I-channel matching balun and the I-channel inter-stage matching balun, and being used to control the amplitude of the I-channel single-ended output signal by adding redundant bits with a weight of 1; the Q-channel variable gain amplifier being connected between the Q-channel matching balun and the Q-channel inter-stage matching balun, and being used to control the amplitude of the Q-channel single-ended output signal by adding redundant bits with a weight of 1; as well as an orthogonal signal generating network connected to the output ends of the I-path inter-stage matching balun and the Q-path inter-stage matching balun, for performing orthogonal synthesis on the I-path and Q-path single-ended output signals to obtain a radio frequency output signal; Each variable gain amplifier is composed of a half-bit weight unit, a redundant bit weight unit and N n-bit weight units, providing a total of N+2 positive phase control bits and N+2 negative phase control bits, N=log2(360 / x), x is the required phase shift step, wherein the weights of the positive and negative phase control bits provided by the half-bit weight unit are 1 and 0 respectively, the weights of the positive and negative phase control bits provided by the redundant bit weight unit are ±1 respectively, and the weights of the positive and negative phase control bits provided by the remaining n-bit weight units are x n The relationship between its digit n is x n =±2 n-1 , n∈[1,N].

2. The millimeter wave phase shifter according to claim 1, wherein: The redundant bit weight unit and each n-bit weight unit are respectively composed of a differential cascode amplifier with a tail current tube and an inverter; the differential cascode amplifier includes 7 transistors, transistors M1 and M2 constitute a group of switch tubes, transistors M3 and M4 constitute another group of switch tubes, transistors M5 and M6 constitute a differential pair tube, and transistor M7 serves as a tail current tube; wherein the source end of transistor M7 is grounded, the drain end of transistor M7 is connected to the source end of transistor M5 and transistor M6, and the gate end of transistor M7 is connected to the bias voltage V Bias The gate terminals of transistor M5 and transistor M6 are respectively connected to the differential output terminals of the corresponding matching balun; the source terminals of transistor M1 and transistor M2 are connected to the drain terminal of transistor M5, the source terminals of transistor M3 and transistor M4 are connected to the drain terminal of transistor M6, the drain terminals of transistor M1, transistor M2, transistor M3 and transistor M4 are differentially connected to the differential input terminals of the corresponding inter-stage matching balun, the gate terminals of transistor M1 and transistor M4 are connected to the output terminal of the inverter, and the gate terminals of transistor M2 and transistor M3 are connected to the input terminal of the inverter.

3. The millimeter wave phase shifter according to claim 2, wherein: The transistors are all MOS transistors.

4. The millimeter wave phase shifter according to claim 1, wherein: The half-bit weight unit is composed of a differential cascode amplifier with a tail current tube and an inverter; the differential cascode amplifier includes 7 transistors, transistors M1 and M2 constitute a group of switch tubes, transistors M3 and M4 constitute another group of switch tubes, transistors M5 and M6 constitute a differential pair tube, and transistor M7 serves as a tail current tube; wherein the source end of transistor M7 is grounded, the drain end of transistor M7 is connected to the source end of transistor M5 and transistor M6, and the gate end of transistor M7 is connected to the bias voltage V Bias The gate terminals of transistor M5 and transistor M6 are respectively connected to the differential output terminals of the corresponding matching balun; the source terminals of transistor M1 and transistor M2 are connected to the drain terminal of transistor M5, the source terminals of transistor M3 and transistor M4 are connected to the drain terminal of transistor M6, the drain terminals of transistor M1 and crystal transistor M4 are differentially connected to the differential input terminals of the corresponding inter-stage matching balun, the drain terminals of transistors M2 and M3 are connected to the power supply voltage VDD, the gate terminals of transistor M1 and transistor M4 are connected to the output terminal of the inverter, and the gate terminals of transistor M2 and transistor M3 are connected to the input terminal of the inverter.

5. The millimeter wave phase shifter according to claim 4, wherein: The transistors are all MOS transistors.

6. The millimeter wave phase shifter according to any one of claims 1 to 5, characterized in that: The orthogonal signal generating network includes a transformer, wherein the primary coil and the secondary coil of the transformer are formed by metal stacking, and the paths through which the metals forming the primary coil and the secondary coil of the transformer pass are the same.

7. The millimeter wave phase shifter according to claim 6, wherein: The orthogonal signal generating network also includes an isolation resistor and two adjustment capacitors. The input end of the primary coil of the transformer is respectively connected to the output ends of the I and Q inter-stage matching baluns. One end of the secondary coil of the transformer is connected to the isolation resistor, and the other end of the secondary coil of the transformer is used to output the RF output signal. The two adjustment capacitors are connected across the primary coil and the secondary coil.

8. The millimeter wave phase shifter according to claim 6, wherein: The primary coil and secondary coil of the transformer are respectively composed of two layers of stacked square metal coils, and the paths passed by the various layers of metal in the primary coil and secondary coil of the transformer are completely consistent. The first metal constitutes the 1 / 2 circumference outer circle and the 1 / 2 circumference inner circle of the first layer of metal coil in the primary coil, and the second metal constitutes the 1 / 2 circumference outer circle and the 1 / 2 circumference inner circle of the second layer of metal coil in the primary coil; the first metal constitutes the 1 / 2 circumference outer circle and the 1 / 2 circumference inner circle of the first layer of metal coil in the secondary coil, and the second metal constitutes the 1 / 2 circumference outer circle and the 1 / 2 circumference inner circle of the second layer of metal coil in the secondary coil.

9. The millimeter wave phase shifter according to claim 8, wherein: The first metal uses the metal layer M9 provided by the 65nm CMOS process, and the second metal uses the metal layer M8 provided by the 65nm CMOS process.

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