Voltage regulator comprising a charge pump circuit

Abstract

The present disclosure relates to voltage regulators including charge pump circuits. In embodiments, a voltage regulator has an input node to receive an input voltage and an output node. The voltage regulator has a charge pump circuit to receive a boost control signal to boost the input voltage based on the boost control signal. The voltage regulator also has a feedback regulation circuit configured to receive the output voltage to provide a first operating control signal and a second operating control signal as a function of the output voltage; a stage control circuit configured to receive the first operating control signal and to control the boost control signal as a function of the first operating control signal; and a filter coupled to the output node configured to receive the second operating control signal and configured to inject charge to or sink charge from the output node as a function of the second operating control signal.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Italian Application No. 102022000002786 filed February 15, 2022, which is hereby incorporated by reference in its entirety. TECHNICAL FIELD

[0003] The present invention relates generally to voltage regulators, and in particular embodiments, to a voltage regulator having a charge pump circuit. BACKGROUND

[0004] Generally, voltage regulators having a charge pump circuit are used to generate an output voltage higher than a corresponding input voltage by exploiting clock-controlled charge transfer between capacitors acting as charge accumulation elements (i.e., operating as DC-DC step-up converters).

[0005] In particular, in SoC (System on Chip) applications, it is often required to generate a high internal voltage to drive specific circuit blocks.

[0006] For example, charge pump circuits are used in non-volatile memories of the flash, EEPROM or PCM type, where programming and erasing operations are performed by applying to the memory cells a voltage higher than the internal supply voltage available within the memory.

[0007] Figure 1 A block diagram of a known voltage regulator 1 is shown, comprising a charge pump circuit 5 coupled between an input node 6 at an input voltage V IN and an output node 7 at an output voltage V OUT . A capacitive load 9 having a capacitance C L is coupled between the output node 7 and ground. The charge pump circuit 5 comprises one or more charge pump stages, e.g., voltage doublers, not shown here, cascaded (or in series) between the input node 6 and the output node 7.

[0008] The voltage regulator 1 provides on-off regulation of the charge pump circuit 5 (i.e., it has a control loop circuit configured to control the activation of the charge pump circuit 5) so that the output voltage V OUT is maintained at a reference desired voltage V REF .

[0009] The voltage regulator 1 comprises a comparator 11 receiving the output voltage V OUT and the reference voltage V REF and providing a stop signal STOP; an oscillator 13 coupled to the output of the comparator 11 and providing a clock signal CLK; and a logic circuit 15 receiving the clock signal CLK and the input voltage V INIt also provides stage or boost signals PHASES to charge pump circuit 5.

[0010] The stage signal PHASES is a square wave signal that has the frequency of the clock signal CLK and controls the stage of charge pump circuit 5.

[0011] like Figure 2 As shown in the timing diagram, during use, voltage regulator 1 has an on-phase and an off-phase. During the on-phase, the output voltage V... OUT Less than the reference voltage V REF During the disconnection phase, the output voltage V OUT Higher than the reference voltage V REF .

[0012] During the turn-on phase, comparator 11 holds the stop signal STOP at a low value, and logic circuit 15 switches the phase signal PHASES between low and high values ​​to activate charge pump circuit 5 and increase the output voltage V. OUT The value of .

[0013] During the disconnection phase, comparator 11 holds the stop signal STOP at a high value, and logic circuit 15 freezes the commutation of the phase signal PHASES, thereby stopping the operation of charge pump circuit 5.

[0014] However, each of the voltage regulator 1, comparator 11, oscillator 13 and logic circuit 15 has a response time that introduces a delay during the effective moment, and the effective moment of switching between effective moment phases introduces a delay.

[0015] like Figure 2 As shown, due to the delay of comparator 11, comparator 11 switches the stop signal STOP to a high value at time t2, regarding the output voltage V. OUT Effectively overcome the reference voltage V REF To delay the switch about time t1.

[0016] Furthermore, the switching time t3 of the PHASES signal during the freeze phase of logic circuit 15 is delayed with respect to time t2 due to the delay of logic circuit 15.

[0017] In fact, between the time t1 when charge pump circuit 5 should stop working and the time t2 when charge pump circuit 5 stops working, the output voltage V OUT Maintain the increase to the reference voltage V REF Above.

[0018] During the turn-off phase, the output voltage V OUT The voltage is reduced due to the discharge current flowing through the load 9 and other circuits (not shown here) connected to the output node 7 of the voltage regulator 1.

[0019] At the output voltage V OUT After the voltage drops below the reference voltage (time t4), comparator 11 switches the stop signal STOP to a low value (time t5), and logic circuit 15 begins the phase signal commutation (time t6).

[0020] However, similar to what was discussed above, between the time t4 when charge pump circuit 5 should start operating and the time t6 when charge pump circuit 5 starts operating, the output voltage continues to decrease to the reference voltage V. REF the following.

[0021] In practice, in voltage regulator 1, the output voltage V OUT At reference voltage V REF The surrounding oscillations thus form a peak-to-peak amplitude V with a peak value, for example, up to several hundred mV (e.g., 160 mV). R The ripples.

[0022] Output voltage V OUT The ripple reduces the performance of voltage regulator 1. For example, if voltage regulator 1 is used in a non-volatile memory, the output voltage V OUT High ripple can cause changes in the programming current of memory cells, which can lead to errors or failures in non-volatile memory.

[0023] Reduce the amplitude V of the ripple R One approach is to couple a large filter capacitor in parallel to load 9 (i.e., between output node 7 and ground). The filter capacitor has a capacitance C equal to or greater than that of load 9. L The capacitance value. However, this method requires a high occupancy rate in the small circuit area where the voltage regulator 1 is formed or where the electronic device with the voltage regulator 1 is incorporated.

[0024] Reduce the amplitude V of the ripple R Another approach is to design a faster regulation loop (i.e., design comparator 11, oscillator 13, and logic circuit 15) to respond to the output voltage V. OUT Above and below reference voltage V REF The voltage regulator 1 can react more quickly to changes in voltage. However, this method increases the manufacturing cost and design complexity of the voltage regulator 1. Furthermore, even with this method, the comparator 11, oscillator 13, and logic circuit 15 will still have unavoidable response delays. Summary of the Invention

[0025] The purpose of this invention is to overcome the shortcomings of the prior art.

[0026] According to the present invention, a voltage regulator and a method for operating the voltage regulator are provided.

[0027] This voltage regulator has an input node and an output node for receiving an input voltage. The voltage regulator includes a charge pump circuit configured to provide an output voltage at the output node with a boost value relative to the input voltage, wherein boosting of the input voltage is performed based on a boost control signal. The voltage regulator further includes a feedback regulation circuit configured to provide a first operation control signal and a second operation control signal based on the output voltage; a stage control circuit configured to receive the first operation control signal and provide a boost control signal based on the first operation control signal; and a filter coupled to the output node, configured to receive the second operation control signal and configured to inject charge into or absorb charge from the output node, the charge being based on the second operation control signal.

[0028] According to one embodiment, the feedback regulation circuit has an inverter configured to receive a first operation control signal and provide a second operation control signal.

[0029] According to an embodiment, the inverter has a response time for providing a second operation control signal in response to a switch of a first operation control signal, and the stage control circuit has a response time for providing a stage control signal in response to a switch of the first operation control signal. The response time of the inverter is shorter than the response time of the stage control circuit. Attached Figure Description

[0030] To better understand the present invention, non-limiting embodiments are now described with reference to the accompanying drawings, in which:

[0031] Figure 1 A block diagram of a known voltage regulator including a charge pump circuit is shown;

[0032] Figure 2 It shows Figure 1 The time-varying waveform of the voltage regulator during use;

[0033] Figure 3 A block diagram of an embodiment of this voltage regulator, including a charge pump circuit, is shown;

[0034] Figure 4 It shows Figure 3 A circuit diagram of an exemplary embodiment of a charge pump circuit;

[0035] Figure 5 It shows Figure 4 Timing diagram of the waveform of the charge pump circuit in use;

[0036] Figure 6 Block diagrams of different embodiments of this voltage regulator are shown;

[0037] Figure 7A block diagram of the non-volatile memory incorporated in this voltage regulator is shown; and

[0038] Figure 8 A circuit diagram of an embodiment of the comparator of this voltage regulator is shown. Detailed Implementation

[0039] Figure 3 A voltage regulation circuit or voltage regulator 50 is shown, including a circuit connected to receive the input voltage V. IN The input node 53 and provides the output voltage V OUT The charge pump circuit 52 between the output nodes 54.

[0040] Voltage regulator 50 will output voltage V OUT Provided to the load (here with capacitance C) coupled between output node 54 and reference potential line (ground) 57. L The capacitor load is 55.

[0041] Input voltage V IN It is a low voltage, for example, between 1V and 4V, particularly around 2.8V, which can be the internal power supply voltage coupled to the voltage regulator 50 (i.e., the logic power supply voltage V of the voltage regulator 50). DD Or different voltages generated by other circuit components, not shown here).

[0042] The charge pump circuit 52 may include a boost stage connected between the input node 53 and the output node 54, or multiple boost stages connected in series or in parallel between the input node 53 and the output node 54.

[0043] The boost stage is of a known type; for example, depending on the specific application, the boost stage can be a voltage multiplier circuit or a different type of circuit.

[0044] The circuit pump circuit 52 receives one or more stage signals PHASES (hereinafter also referred to as boost control signals), which control the selective activation and deactivation of the boost stages to enable the selective and alternating transfer of charge accumulated in each boost stage from one boost stage to the next boost stage.

[0045] An exemplary embodiment of the charge pump circuit 52 is in Figure 4 It is shown in the figure and described in detail below.

[0046] Voltage regulator 50 provides switching regulation for charge pump circuit 52 to maintain output voltage V. OUT Equal to the desired output voltage, for example, between 4V and 6V, denoted here as the reference voltage V. REF .

[0047] In one embodiment, the voltage regulator 50 includes a comparator 58 and a stage control circuit 60, the comparator 58 receiving the output voltage V. OUT and reference voltage V REF It provides an operation control signal, here represented as the stop signal STOP. The stage control circuit 60 receives the stop signal STOP and provides the stage signal PHASES. Comparator 58 responds to the comparison output voltage V OUT and reference voltage V REF A stop signal STOP is provided. In this embodiment, the stop signal STOP is a signal with a high logic value (here, the logic supply voltage V). DD A square wave signal with a low logic value (0V in this case) and a low logic value (0V in this case). When the output voltage V OUT It becomes higher than the reference voltage V REF When the output voltage V is high, comparator 58 switches the stop signal STOP to a high logic value. OUT It becomes lower than the reference voltage V REF When this occurs, comparator 58 switches the stop signal STOP to a low logic value. In this embodiment, comparator 58 is powered by the logic supply voltage V. DD Bias.

[0048] The stage control circuit 60 includes an oscillator 63 and a logic control circuit 65. The oscillator 63 receives a stop signal STOP and provides a clock signal CLK. The logic control circuit 65 receives the clock signal CLK and provides a stage signal PHASES to the charge pump circuit 52.

[0049] When the stop signal STOP has a low logic value, the clock signal CLK is at a low logic value (e.g., 0V) and a high logic value (e.g., logic supply voltage V). DD Switching between them at high frequencies, such as megahertz (e.g., 150 MHz).

[0050] When the stop signal STOP has a high logic value, the oscillator 63 stops switching the clock signal CLK between the corresponding high and low logic values. For example, when the stop signal STOP switches from the corresponding low logic value to the corresponding high logic value (i.e., on the rising edge of the stop signal STOP), the oscillator 63 freezes the clock signal CLK to its current (or actual) value.

[0051] Logic control circuit 65 provides stage signals PHASES to charge pump circuit 52. The number of stage signals PHASES depends on the specific implementation of charge pump circuit 52, for example, on the number, specific configuration, and type of stages in charge pump circuit 52. This is described by way of example only and is further illustrated below. Figure 5 exhibit Figure 4 An example of the stage signal PHASES in an exemplary embodiment of a charge pump circuit.

[0052] According to one embodiment, the logic control circuit 65 may include one or more level shifter circuits configured to adjust the high and low logic voltage values ​​of the stage signal PHASES starting from the clock signal CLK. For example, if the input voltage V IN Unlike logic power supply voltage V DD In this case, a level shifter circuit can be used. For example, Figure 3 As shown by the dashed arrow, the logic control circuit 65 receives the input voltage V. IN .

[0053] The voltage regulator 50 further includes a regulating capacitor 70, which has a capacitance C B It also has a first terminal 70A coupled to the output node 54 and a second terminal 70B for receiving the inverted stop signal STOP_N.

[0054] Adjust the capacitance C of capacitor 70 B Less than the load capacitance, for example, including capacitor C at a load of 55. L Between 1 / 30 and 1 / 10, especially 1 / 20. In the embodiment, the capacitance C of the adjusting capacitor 70 is... B With a load of 55, capacitor C L The ratio between them can be determined by ΔV and the logic power supply voltage V. DD The ratio between them is used to select, where ΔV is the output voltage V during use. OUT The desired voltage reduction of the ripple is discussed in detail below.

[0055] In one embodiment, the voltage regulator 50 further includes an inverter 75 that receives a stop signal STOP and provides an inverted stop signal STOP_N. In this embodiment, the inverter 75 is biased to the logic supply voltage V. DD However, inverter 75 can be biased to different voltages (e.g., input voltage V). IN ).

[0056] The inverter 75 has a low response time of, for example, several nanoseconds (e.g., between 1 ns and 6 ns) relative to the stop signal STOP.

[0057] In an embodiment, in response to the stop signal STOP switching from the corresponding low logic value to the corresponding high logic value, the inverter 75 switches the inverted stop signal STOP_N from the corresponding high logic value to the corresponding low logic value within a short time interval of, for example, several nanoseconds, particularly between 1ns and 6ns.

[0058] Similarly, in response to the stop signal STOP switching from the corresponding high logic value to the corresponding low logic value, inverter 75 switches the inverted stop signal STOP_N from the corresponding low logic value to the corresponding high logic value within a short time interval (e.g., a few nanoseconds, specifically between 1ns and 6ns).

[0059] In fact, the response time of inverter 75 is less than the time it takes for stage control circuit 60 to react to the switch of stop signal STOP (i.e., to start or stop the operation of charge pump circuit 52).

[0060] In fact, inverter 75 and comparator 58 form a feedback adjustment circuit 77, in Figure 3 The dashed line indicates that it is configured to provide output voltage V. OUT The stop signal STOP and the inverted stop signal STOP_N, especially based on the output voltage V OUT and reference voltage V REF The comparison between the two signals provides the stop signal STOP and the inverted stop signal STOP_N.

[0061] For example only, Figure 4 A detailed embodiment of the charge pump circuit 52 is shown, having two boost stages 80A and 80B coupled to each other at an intermediate node 82. Boost stage 80A receives an input voltage V. IN The input node 83 is directly connected to the intermediate node 82, and the output node is directly connected to the intermediate node 82. The boost stage 80B has an input node directly connected to the intermediate node 82 and provides an output voltage V. OUT Output node 84.

[0062] The boost stages 80A and 80B (equal to each other here) are each voltage doublers, and each is formed by a first part 85A coupled between the corresponding input node 83 and intermediate node 82 and the corresponding stage intermediate node 86, and a second part 85B coupled between the corresponding stage intermediate node 86 and the corresponding intermediate node 82 and the corresponding output node 84.

[0063] The first portion 85A of the boost stages 80A and 80B is formed by two pump capacitors 87A and 87B, which have first terminals coupled to the input node 83 and intermediate node 82 of the respective boost stages 80A and 80B via corresponding switches (here, two MOSFET transistors 88). The first terminals of the pump capacitors 87A and 87B are also coupled to the gate terminal of the corresponding MOSFET transistor 89, whose conductive terminals (source and drain) are connected to the input node 83, intermediate node 82, and intermediate node 86 of the respective boost stages 80A and 80B.

[0064] The second portion 85B of the boost stages 80A and 80B is formed by two pump capacitors 90A and 90B, which have first terminals coupled to the intermediate node 82 and output node 84 of the respective boost stages 80A and 80B via corresponding switches (here, two MOSFET transistors 91). The first terminals of the pump capacitors 90A and 90B are also coupled to the gate terminals of the corresponding MOSFET transistors 92, whose conductive terminals (source and drain) are connected to the intermediate node 82, output node 84, and intermediate node 86 of the respective boost stages 80A and 80B.

[0065] The boost stages 80A and 80B each have two channel capacitors 93, the first terminal of which is coupled to the intermediate node 86 of the corresponding boost stages 80A and 80B.

[0066] according to Figure 4 For example, logic control circuit 65 provides multiple stage signals PHASES, including stage signals P1, P2, P1_N, P2_N, CKA, and CKB provided to boost stage 80A (examples are shown in...). Figure 5 (as shown in the diagram) and the stage signals P12, P22, P1_N2, P2_N2, CKA2 and CKB2 provided to the boost stage 80B.

[0067] In this embodiment, stage signals P1 and P2 are provided to the second terminals of pump capacitor 87A and pump capacitor 87B, respectively. Stage signals P1_N and P2_N are complementary (inverted) to stage signals P1 and P2, respectively, and are provided to the second terminals of pump capacitor 90A and pump capacitor 90B, respectively. One of stage signals CKA and CKB is inverted relative to the other and is provided to the pass capacitors 87A and 87B, respectively. In this embodiment, stage signals P12, P22, P1_N2, P2_N2, CKA2, and CKB2 are equal to stage signals P1, P2, P1_N, P2_N, CKA, and CKB, respectively, and have a phase shift of 90° with them.

[0068] In operation, the voltage regulator 50 has an on-phase and an off-phase. During the on-phase, the charge pump circuit 52 is activated, enabling charge accumulation and transfer between the input node 53 and the output node 54. During the off-phase, the charge pump circuit 52 is deactivated, and charge accumulation and transfer between the input node 53 and the output node 54 ceases. During the on-phase, the output voltage V... OUT Increase over time.

[0069] For example, refer to Figure 4 An exemplary embodiment of the charge pump circuit 52,Figure 5 The possible temporal behavior of stage signals P1, P2, P1_N, P2_N, CKA, and CKB during the turn-on phase of voltage regulator 50 is illustrated. In an embodiment, stage signals P1, P2, P1_N, P2_N, CKA, and CKB oscillate between corresponding high logic values ​​and corresponding low logic values ​​during the turn-on phase, enabling sequential accumulation and transfer of charge between input node 53 and output node 54 via boost stages 80A and 80B of circuit pump circuit 52.

[0070] During the turn-off phase, the phase signal PHASES has a constant value (i.e., does not oscillate), thereby disabling the accumulation and transfer of charge through the charge pump circuit 52. During the turn-off phase, the output voltage V OUT The current decreases over time due to the current flowing through load 55 (i.e., from output node 54 to ground 57).

[0071] In the voltage regulator 50, during the turn-on phase, when the output voltage V OUT It becomes higher than the reference voltage V REF When this happens, comparator 58 will switch the stop signal STOP to the corresponding high value (i.e., the logic power supply voltage V). DD ).

[0072] Therefore, inverter 75 switches the inverted stop signal STOP_N to the corresponding low value. When the inverted stop signal STOP_N is switched from a high value (i.e., the power supply logic voltage V), the inverter switches the signal to a low value. DD When switched to a low value (i.e., 0V), an event equal to the high value and the low value (i.e., equal to V) occurs at the second terminal 70B of the regulating capacitor 70. DD The voltage change between ( ) is the difference between ( ). Therefore, regulating capacitor 70 absorbs an amount equal to C from output node 54. B ∙V DD The charge, thereby reducing the output voltage V. OUT The value of .

[0073] Therefore, even if the stage control circuit 60 has a time delay before the stop stage signal PHASES and the charge pump circuit 52 is deactivated, the output voltage V that will occur during this time delay will be... OUT The increase is at least partly due to the charge C absorbed by the regulating capacitor 70. B ∙V DD To compensate.

[0074] During the turn-off phase of the voltage regulator 50, when the output voltage V OUT Reduced to reference voltage V REFWhen this occurs, comparator 58 switches the stop signal STOP to the corresponding low value (i.e., 0V). Therefore, inverter 75 switches the inverted stop signal STOP_N to the corresponding high value (i.e., logic supply voltage V). DD ).

[0075] When the inverting stop signal STOP_N switches from a low value (i.e., 0V) to a low value (i.e., the power supply logic voltage V), DD When the value is equal to both the low and high values ​​(i.e., equal to V) at the second terminal 70B of the adjusting capacitor 70, a value equal to V is generated. DD The voltage change between ( ) is the difference between them. Therefore, adjusting capacitor 70 injects an amount equal to C into output node 54. B ∙V DD The charge, thereby increasing the output voltage V. OUT The value of .

[0076] Therefore, even if the stage control circuit 60 has a time delay before activating the charge pump circuit 52, the output voltage V that will occur during the time delay period... OUT The reduction is at least partially due to the charge C injected into the output node 54 by the regulating capacitor 70. B ·V DD To compensate.

[0077] In practice, the regulating capacitor 70 acts as a filter to inject or absorb charge from the output node 54, the amount of charge depending on the inverted stop signal STOP_N.

[0078] For example, considering V DD =1V and adjust the capacitance C of capacitor 70. B It is 1 / 20 of the load capacitor 55. The high-low (or low-high) switch of the stop signal STOP can change the output voltage V. OUT The change is tens of millivolts.

[0079] The applicant has confirmed that, relative to the reference Figure 1 and 2 The output voltage V of the known voltage regulator 1 is described. OUT The peak-to-peak amplitude V of the ripple R The output voltage V of voltage regulator 50 OUT The peak amplitude of the ripple can be reduced, for example, by about 40%.

[0080] For example, during the design phase or in use, the absolute value of the high-low voltage difference of the inverted stop signal STOP_N and the capacitance C of capacitor 70 can be adjusted. B The value of can adjust the charge injected into and absorbed from output node 54, thereby adjusting the output voltage V. OUT The peak-to-peak amplitude correction of the ripple.

[0081] By maintaining the capacitance C of the regulating capacitor 70 B The capacitance C is much smaller than that of the capacitive load of 55. L This can reduce the output voltage V. OUT The ripple reduces the size of the voltage regulator 50, which allows for a smaller die area and thus lower manufacturing costs.

[0082] Figure 6 Different embodiments of this voltage regulator, represented by 150, are shown. Voltage regulator 150 has a similar... Figure 2 The general structure of the voltage regulator 50; therefore, common components are indicated by the same reference numerals and will not be described further.

[0083] In one embodiment, the voltage regulator 150 includes a charge pump circuit 52 coupled between the input node 53 and the output node 54; the comparator 58 receives the output voltage V. OUT A stop signal STOP is provided; the stage control circuit 60 receives the stop signal STOP and provides a stage signal PHASES. The voltage regulator 150 also includes an adjusting capacitor 70, denoted as a first adjusting capacitor 70, and an inverter 75, denoted as a first inverter 75. The voltage regulator 150 also includes a second adjusting capacitor 153 and a second inverter 155. The second adjusting capacitor 153 has a capacitance C less than that of the capacitive load 55. L Capacitor C B2 For example, including in capacitor C L Between 1 / 30 and 1 / 10, especially capacitor C L Approximately 1 / 20.

[0084] The second regulator capacitor 153 has a first terminal 153A coupled to the output node 54 and a second terminal 153B coupled to the output of the second inverter 155. The second inverter 155 receives the inversion stop signal STOP_N from the first inverter 75 and provides a second inversion stop signal STOP_NN at its output.

[0085] In fact, the first inverter 75, comparator 58, and second inverter 175 form a feedback regulation circuit, represented here by 177 and indicated by a dashed line. This feedback regulation circuit is configured to provide a stop signal STOP, and the first inverted stop signal STOP_N and the second inverted stop signal STOP_NN are based on the output voltage V. OUT Especially based on the output voltage V OUT and reference voltage V REF A comparison between them.

[0086] The second inverter 155 is powered by logic power supply voltage V.DD Bias. In this embodiment, the high logic value of the second inverting stop signal STOP_NN is the logic supply voltage V. DD Furthermore, the low logic value of the second inverted stop signal STOP_NN is 0V.

[0087] The response time of the second inverter 155 is higher than that of the first inverter 75, for example, at least ten times higher, for example, tens of nanoseconds higher, especially including the range of 20 ns and 100 ns.

[0088] The response time of the second inverter 155 can be equal to or greater than the time taken for the stage control circuit 60 to react to the switch of the stop signal STOP (i.e., to start or stop the operation of the charge pump circuit 52).

[0089] In an embodiment, in response to the first inverter stop signal STOP_N switching from the corresponding low logic value to the corresponding high logic value, the second inverter 155 switches the second inverter stop signal STOP_NN from the corresponding high logic value to the corresponding low logic value over a time interval of, for example, tens of nanoseconds, particularly between 20ns and 100ns.

[0090] In response to the switching of the first inverted stop signal STOP_N from the corresponding high logic value to the corresponding low logic value, the second inverter 155 switches the second inverted stop signal STOP_NN from the corresponding low logic value to the corresponding high logic value within a time interval of, for example, tens of nanoseconds, particularly between 20ns and 100ns.

[0091] In fact, the second inverter 155 has a low drive capability, which allows the second terminal 153B of the second regulating capacitor 153 to be driven from a low logic value to a high logic value and from a high logic value to a low logic value, with a slope that can last for tens of nanoseconds (i.e., slower than the response time of the first inverter 75).

[0092] In use, it is similar to a reference. Figure 3 For the first regulating capacitor 70 described, the switch in the stop signal STOP and therefore the switch in the second inverted stop signal STOP_NN make equal to C. B2 ·V DD The charge is slowly absorbed or injected from the output node 54 of the voltage regulator 150 into the output node 54 of the voltage regulator 150.

[0093] In this embodiment, when the stop signal STOP switches from the corresponding high logic value to the corresponding low logic value, the second stop inverting signal STOP_NN also switches from the corresponding high logic value to the corresponding low logic value, thereby absorbing charge C from the output node 54. B2 ·V DDThis limits the voltage rise. On the other hand, when the stop signal STOP switches from the corresponding low logic value to the corresponding high logic value, the second stop inverting signal STOP_NN also switches from the corresponding low logic value to the corresponding high logic value, thereby injecting charge C into the output node 54. B2 ·V DD Therefore, it helps to maintain the power consumption from external loads (e.g., load 55). In fact, the second inverter 155 has a longer response time than the first inverter 75, which allows for a further reduction in the output voltage V. OUT The ripple, especially if the voltage regulator 150 is coupled to a low-current load at the output.

[0094] This voltage regulator can be integrated into electronic devices to provide a stable voltage source within the devices.

[0095] For example, Figure 7 It shows examples including Figure 3 A block diagram of the voltage regulator 50 and the memory 200. However, the memory 200 may include... Figure 6 Voltage regulator 150.

[0096] The memory 200 is a known type of non-volatile memory, particularly a phase-change type memory (PCM), which can be integrated into electronic devices (e.g., smartphones, laptops, cameras, wearable devices, etc., not shown here) and coupled to them via a multiplexed bus 201.

[0097] The memory 200 includes a PCM memory array 202 having multiple memory cells arranged in multiple rows and columns; a row decoder 204 and a column decoder 206 configured to select memory cells of the PCM memory array 202 from an addressing signal ADDRESS during use, and to perform operations (e.g., read or write) on the addressing signal ADDRESS; a voltage regulator 208 coupled to the row decoder 204; an internal clock 210; a finite state machine (FSM) 211; a digital-to-analog converter (DAC) 212; several internal registers 214; and a sensing circuit 216 configured to read the state of the addressed memory cells.

[0098] The FSM211 controls the internal operations of the memory 200 (e.g., booting, writing, reading, etc.) and manages data reception and transmission via the multiplexed bus 201.

[0099] The memory 200 further includes programming circuitry 220, which is coupled to the column decoder 206, FSM 211, and DAC 212. Programming circuitry 220 is also coupled to and receives the output voltage V from the output node 54 of the voltage regulator 50. OUT .

[0100] Programming circuit 220 is configured to change the state of the addressed memory cells of PCM memory array 202 (i.e., write operation). In an embodiment, to change the state of the memory cells, programming circuit 220 uses a high voltage (i.e., the output voltage V of voltage regulator 50). OUT To generate high programming current.

[0101] Voltage regulators 50, 150 relative to known voltage regulators (e.g., Figure 1 The known voltage regulator 1) generates a more stable output voltage, thereby allowing the programming circuit 220 to generate a stable programming current. Therefore, write errors in the memory 200 can be avoided. Thus, the memory 200 has high reliability.

[0102] Obviously, modifications and variations can be made to the voltage regulators 50, 150 without departing from the scope of the invention as defined by the appended claims. For example, the regulating capacitors 70, 153 can be formed by any electronic device that functions as a capacitive element, such as a transistor (e.g., an NMOS transistor whose gate is connected to the output node 54, and whose source, drain, and body are interconnected to each other and to the output of the inverters 75, 155). Furthermore, depending on the specific application, the capacitors 70, 153 can form a filter that includes other electrical components (not shown here), which can be passive or active, such as resistors.

[0103] For example, Figure 8 Different embodiments of the comparator (represented herein as 258) of voltage regulators 50 and 150 are shown. Comparator 258 includes a voltage divider 260 and a comparator amplifier 263, the voltage divider 260 being coupled to the output voltage V. OUT Between ground 57 and having a voltage divider node 261, comparator amplifier 263 has a reference voltage V REF The first input is coupled to the voltage divider node 261 and the second input provides the stop signal STOP at the output.

[0104] Voltage divider 260 is formed by a first branch 260A and a second branch 260B. The first branch 260A includes an RC parallel circuit and is coupled between the output node 54 and the voltage divider node 261. The second branch 260B includes an RC parallel circuit and is coupled between the voltage divider node 261 and ground 57.

[0105] In practice, depending on the specific application, the reference voltage V REF It can be equal to the output voltage V OUT Or it depends on the output function V OUT .

[0106] Based on the functional indications given above, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art.

[0107] Although this specification has been described in detail, it should be understood that various changes, substitutions, and alterations can be made without departing from the spirit and scope of this disclosure as defined by the appended claims. In the various drawings, the same elements are designated by the same reference numerals. Furthermore, the scope of this disclosure is not intended to be limited to the specific embodiments described herein, as it will be readily understood by one of ordinary skill in the art from this disclosure that existing or future processes, machines, manufactures, compositions of matter, means, methods, or steps may perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein. Therefore, the appended claims are intended to include such processes, machines, manufactures, compositions of matter, means, methods, or steps within their scope.

[0108] Therefore, the specification and drawings are to be considered merely as a description of this disclosure as defined by the appended claims, and are to be considered to cover any and all modifications, variations, combinations or equivalents falling within the scope of this disclosure.

Claims

1. A voltage regulator, comprising: A charge pump circuit is coupled between the input node and the output node of the voltage regulator, the charge pump circuit being configured to generate an output voltage at the output node based on a corresponding boost control signal, the output voltage having a boost value relative to the input voltage received at the input node; The feedback regulation circuit is configured to generate a first operation control signal and a second operation control signal based on the output voltage. A stage control circuit is configured to generate a boost control signal based on the first operation control signal; as well as The filter is configured to inject charge into or absorb charge from the output node, the charge being based on the second operation control signal.

2. The voltage regulator of claim 1, wherein the filter includes a capacitor element having a first terminal and a second terminal, the first terminal being coupled to the output node, and the second terminal being configured to receive the second operation control signal.

3. The voltage regulator of claim 1, wherein the feedback regulation circuit includes an inverter configured to receive the first operation control signal and generate the second operation control signal.

4. The voltage regulator of claim 3, wherein the inverter is a first inverter, the feedback regulation circuit further includes a second inverter configured to receive the second operation control signal and generate a third operation control signal, the filter includes a capacitive element having a first terminal and a second terminal, the first terminal being coupled to the output node, and the second terminal being configured to receive the third operation control signal.

5. The voltage regulator of claim 4, wherein the first inverter has a first response time when generating the second operation control signal in response to switching of the first operation control signal, and wherein the second inverter has a second response time when generating the third operation control signal in response to switching of the second operation control signal, the second response time being greater than the first response time.

6. The voltage regulator of claim 1, wherein the feedback regulation circuit includes a comparator, the comparator being configured to: The output voltage is compared with the reference voltage; In response to the output voltage being greater than the reference voltage, the first operation control signal is switched to a first value; and In response to the output voltage being less than the reference voltage, the first operation control signal is switched to a second value.

7. The voltage regulator of claim 6, wherein the stage control circuit is configured to: In response to the first operation control signal switching to the first value, the boosting of the input voltage by the charge pump circuit is disabled; and The charge pump circuit is enabled to boost the input voltage in response to the first operation control signal switching to the second value.

8. The voltage regulator of claim 1, wherein the voltage regulator is a voltage regulator for a non-volatile memory.

9. The voltage regulator according to claim 8, wherein the non-volatile memory is a phase-change memory.

10. A method for operating a voltage regulator, comprising: The charge pump circuit of the voltage regulator generates an output voltage at the output node of the voltage regulator. The output voltage is a boosted value relative to the input voltage received at the input node of the voltage regulator. The output voltage is based on a corresponding boost control signal. The charge pump circuit is coupled between the input node and the output node. The feedback regulation circuit of the voltage regulator generates a first operation control signal and a second operation control signal based on the output voltage; The voltage regulator's stage control circuit generates a boost control signal based on the first operation control signal; as well as The voltage regulator's filter injects charge into or absorbs charge from the output node, the charge being based on the second operation control signal.

11. The method of claim 10, wherein generating the second operation control signal comprises inverting the first operation control signal to generate the second operation control signal.

12. The method of claim 10, wherein the filter includes a first capacitor element, a first terminal of the first capacitor element being coupled to the output node, the method further comprising receiving the second operation control signal at a second terminal of the first capacitor element.

13. The method of claim 12, wherein the filter includes a second capacitor element, a first terminal of the second capacitor element being coupled to the output node, the method further comprising: The feedback adjustment circuit generates a third operation control signal; as well as The third operation control signal is received by the second terminal of the second capacitor element, and the third operation control signal is an inverted signal relative to the second operation control signal.

14. The method of claim 10, further comprising: The output voltage is compared with the reference voltage; In response to the output voltage being greater than the reference voltage, the first operation control signal is switched to a first value; as well as In response to the output voltage being less than the reference voltage, the first operation control signal is switched to a second value.

15. The method of claim 10, wherein the step of injecting into or absorbing from the output node is performed faster than the step of the stage control circuit providing the corresponding boost control signal to the charge pump circuit.

16. A device including a non-volatile memory with a voltage regulator, the voltage regulator comprising: A charge pump circuit, coupled between the input node and the output node of the voltage regulator, is configured to generate an output voltage at the output node based on a corresponding boost control signal, the output voltage having a boost value relative to the input voltage received at the input node; The feedback regulation circuit is configured to generate a first operation control signal and a second operation control signal based on the output voltage. A stage control circuit is configured to generate a boost control signal based on the first operation control signal; as well as The filter is configured to inject charge into or absorb charge from the output node, the charge being based on the second operation control signal.

17. The device of claim 16, wherein the filter includes a capacitive element having a first terminal and a second terminal, the first terminal being coupled to the output node and the second terminal being configured to receive the second operation control signal, and wherein the feedback adjustment circuit includes an inverter configured to receive the first operation control signal and generate the second operation control signal.

18. The device of claim 17, wherein the inverter is a first inverter, the feedback adjustment circuit further includes a second inverter configured to receive the second operation control signal and generate a third operation control signal, the filter includes a capacitive element having a first terminal and a second terminal, the first terminal being coupled to the output node, and the second terminal being configured to receive the third operation control signal.

19. The apparatus of claim 18, wherein the first inverter has a first response time when generating the second operation control signal in response to switching of the first operation control signal, and wherein the second inverter has a second response time when generating the third operation control signal in response to switching of the second operation control signal, the second response time being greater than the first response time.

20. The device of claim 16, wherein the feedback adjustment circuit includes a comparator configured to: The output voltage is compared with the reference voltage; In response to the output voltage being greater than the reference voltage, the first operation control signal is switched to a first value; and In response to the output voltage being less than the reference voltage, the first operation control signal is switched to a second value, and The stage control circuit is configured as follows: In response to the first operation control signal switching to the first value, the boosting of the input voltage by the charge pump circuit is disabled, and The charge pump circuit is enabled to boost the input voltage in response to the first operation control signal switching to the second value.

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