A high slew rate voltage buffer based on a differential structure of a flip-flop voltage follower

Abstract

This invention provides a high slew rate voltage buffer based on a differential structure of a flip-flop voltage follower, comprising an output stage and two complementary bias DFVF pairs of different types. Each complementary bias DFVF pair is connected at one end to the input voltage and at the other end to the output stage. The output stage includes two different types of output transistors connected to the output voltage. The two complementary bias DFVF pairs provide complementary bias voltages to the two different types of output transistors, ensuring that at least one DFVF is always active. This ensures that during large signal conversion, the dynamic current of the output stage is always greater than the static current. This invention guarantees a high slew rate for the buffer under various large signal inputs, reducing input-to-output delay.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit design, and more particularly to a high slew rate voltage buffer based on a flip-flop voltage follower differential structure. Background Technology

[0002] Voltage buffers enable output voltage to follow input voltage and are widely used in various integrated circuit applications. For example, in the column driver design of active matrix liquid crystal displays (LCDs), high slew rate, Class AB voltage buffers are typically required to quickly drive large capacitive loads, thereby accelerating the circuit response speed with low power consumption, reducing the delay from input voltage to output voltage, and achieving rapid output voltage following of input voltage.

[0003] A flip-flop voltage follower (FVF) is a simple buffer, as shown in Figures 1(a) and 1(b), where the input transistor is enclosed in a dashed box. Because the output current is very small in the static state but can become very large under certain dynamic conditions, it is a "class-AB" buffer. Although this buffer can achieve output voltage following the input voltage, there is always a significant voltage difference between the output and input voltages, therefore it is not an ideal buffer.

[0004] By adding two MOSFETs to the FVF, one MOSFET forms a differential input pair with the original input transistor, and the other MOSFET acts as a current mirror to reflect larger dynamic currents. This creates a differential structure (DFVF) for a flip-flop voltage follower, as shown in Figures 2(a) and 2(b). In Figure 2(a), the upper dashed box contains the current mirror, and the lower dashed box contains the differential input transistor M1. In Figure 2(b), the upper dashed box contains the differential input transistor M6, and the lower dashed box contains the current mirror. Because the current mirror transistor can replicate the larger dynamic current generated by the FVF to other MOSFETs, it facilitates functional expansion and offers greater design flexibility. By using a complementary approach of nMOS-DFVF (DFVF with nMOS as the differential input pair) and pMOS-DFVF (DFVF with pMOS as the differential input pair), combined with adaptive bias MOSFETs M3 and M10, and output transistors M7 and M14, a buffer with an output voltage equal to the input voltage can be designed, such as... Figure 3 As shown, this buffer is designed based on two different types of DFVFs: nMOS and pMOS. It can not only eliminate the voltage difference between the output and input voltages, but also achieve rail-to-rail functionality and provide a high slew rate under certain conditions.

[0005] The specific implementation principle of the rail-to-rail function is as follows:

[0006] As long as the input voltage V in GND+V GS,N +V DS,N (where GND is 0, V) GS,N V is the gate-source voltage of the nMOS transistor. DS,N If the drain-source voltage of the nMOS transistor is V, then the nMOS-DFVF can operate normally. At this point, assuming the output voltage V... out >V in Since the nMOS differential input pair transistors M1 and M2 are source-coupled, the drain current of M2 is larger than that of M1 and also larger than that of M6. Because the drain current of M6 is equal to that of M7, and the drain current of M7 is equal to that of M3, the drain current of M2 should be larger than that of M3. However, in reality, M2 and M3 are source-coupled and have equal gate voltages, so their drain currents should be equal, which contradicts the previous conclusion. Therefore, V out >V in This is not true. Similarly, we can prove that V... out <V in That also doesn't hold true. Therefore, V out =V in That is, at this time Figure 3 The upper part of the circuit (within the red dashed box in the diagram), consisting of M1 to M7 and two current sources, can perform voltage buffering. Similarly, as long as the input voltage V... in <VDD-V GS,P -V DS,P (Where VDD is the power supply voltage, which is 3V in this circuit, V...) GS,P V is the gate-source voltage of the pMOS transistor. DS,P (where is the drain-source voltage of the pMOS transistor) Figure 3 The lower half of the circuit (within the blue dashed box in the diagram), consisting of M8 to M14 and two current sources, can function as a voltage buffer. Because when VDD is large (e.g., 3V), V... GS,N +V DS,N <VDD-V GS,P -V DS,P The condition is always met, therefore regardless of the input voltage V in Within what range? Figure 3 The circuits shown can all function as buffers. The difference lies in whether V... in <V GS,N +V DS,N If the upper half of the buffer circuit is not working, then only the lower half of the buffer circuit acts as the buffer; if V in >VDD-V GS,P -V DS,PIf the lower half of the buffer circuit is not working, then only the upper half of the buffer circuit acts as the buffer; if V GS,N +V DS,N <V in <VDD-V GS,P -V DS,P Then the entire buffer can work normally.

[0007] The specific principle behind achieving a high slew rate is as follows:

[0008] In the static state, ignoring the effect of MOSFET mismatch, due to the voltage follower function of the buffer, V out =V in In dynamic cases, when V in When the voltage suddenly increases from 0 to VDD, the circuit changes from V... in To V out There is a delay t in the process delay In other words, V out This cannot be changed immediately, therefore the operating states of transistors M1 and M2 in the differential pair are no longer consistent. At this time, transistor M2 is off, and the gate voltage of transistor M4 is close to VDD. Since transistor M4 and the current source connected in series with it form a source follower, which can perform level shifting, the gate voltage of transistor M5 is also very high at this time. Because VDD... in The sudden increase in voltage causes a sudden increase in the source voltage of M1, which is also the drain voltage of M5. Therefore, the current flowing through M5 will suddenly increase. Since the current injected into M5 can only be provided by M6, the current in M6 will increase significantly. This rapidly increasing dynamic current is mirrored to the output transistor M7 through M6, which acts as a current mirror, allowing for rapid charging of the load capacitor and a rapid rise in the output voltage until it equals the input voltage. The current change in the buffer when the input voltage suddenly drops from VDD to 0 is similar. Since the slew rate is defined as the ratio of the charging current across the load capacitor to the load capacitance value, the large dynamic output current of this buffer ensures its high slew rate. The dynamic waveform of the input voltage jumping between VDD and 0 is as follows: Figure 4 As shown. It can be seen that when V in After the transition occurs, V out Change to V in The short time taken indicates that the buffer has a small delay from input to output.

[0009] However, Figure 3 The buffer structure shown has a significant drawback: if the input voltage transition range is narrow, resulting in only the upper (lower) half of the circuit working during the entire dynamic process, the slew rate of the buffer will be severely limited. Figure 3 The specific analysis of the limited buffer slew rate is as follows:

[0010] When V in From VDD to VDD-V GS,P -V DS,P (or more than VDD-V) GS,P -V DS,P At higher voltages, only the upper half of the buffer circuitry operates during large-signal conversions. Because V out The situation cannot be changed immediately. At this point, the source voltage of transistor M2 remains high, causing transistor M1 to be cut off. Therefore, transistors M6 and the pMOS output transistor M7 are both cut off; simultaneously, since the lower half of the buffer circuit is not operating, the nMOS output transistor M14 is also cut off. The output capacitor can only discharge through the adaptive bias transistor M3. Because the gate-source voltages of transistors M2 and M3 are the same, and the bias current of transistor M2 is constant, the discharge current of the output capacitor is fixed and equal to the quiescent current of transistor M2. For low power consumption, the quiescent current of the buffer is usually required to be small; therefore, the slew rate of the buffer is very small, and the dynamic response speed of the buffer becomes very slow, i.e., the delay t from the input voltage to the output voltage. delay2 This increases significantly. The corresponding waveform is shown in Figure 5(a). Similarly, when V... in From GND (which is 0) instantly rising to V GS,N +V DS,N (or V) GS,N +V DS,N At lower voltages, the buffer's slew rate is also very small, and its dynamic response speed is extremely slow, with a delay t from the input voltage to the output voltage. delay1 This will also increase significantly. The corresponding waveform is shown in Figure 5(b).

[0011] However, many analog circuits—such as low-dropout linear regulators (LDOs) that employ off-chip capacitor compensation—require the buffer's input voltage to jump across any range (e.g., from 0 to V). GS,N +V DS,N Or from VDD to VDD-V instantly GS,P -V DS,P The slew rate can be maintained at a high level to reduce the delay from input to output and achieve a fast response, which existing solutions cannot meet. Summary of the Invention

[0012] To address the problems existing in the prior art, this invention provides a high slew rate voltage buffer based on a differential structure of a flip-flop voltage follower, which can ensure that the buffer has a high slew rate under various large signal inputs.

[0013] To achieve the above objectives, the present invention adopts the following solution:

[0014] A high slew rate voltage buffer based on a flip-flop voltage follower differential structure includes an output stage and two different types of bias complementary DFVF pairs, wherein one end of each bias complementary DFVF pair is connected to the input voltage and the other end is connected to the output stage, and the output stage includes two different types of output transistors connected to the output voltage.

[0015] The two complementary bias DFVF pairs can provide complementary bias voltages for the two different types of output transistors, ensuring that there is always a DFVF in operation, so that the dynamic current of the output stage is always greater than the static current when performing large signal conversion.

[0016] In some embodiments, the present invention further includes the following technical features:

[0017] The two different types of output transistors are a pMOS output transistor and an nMOS output transistor.

[0018] The bias-complementary DFVF pair includes two sequentially connected first DFVF and second DFVF, and a phase converter connected to the second DFVF, wherein the first DFVF and the second DFVF are completely symmetrical, and the phase converter is used to convert the bias voltage of one type of output transistor to the bias voltage of another type of output transistor.

[0019] The two bias-complementary DFVF pairs are a bias-complementary nMOS-DFVF pair and a bias-complementary pMOS-DFVF pair, respectively.

[0020] The bias-complementary nMOS-DFVF pair includes two sequentially connected and completely symmetrical first nMOS-DFVF and second nMOS-DFVF, and an nMOS-phase converter connected to the second nMOS-DFVF. The first nMOS-DFVF provides a bias voltage to the pMOS output transistor; the second nMOS-DFVF provides a bias voltage to the nMOS output transistor through the nMOS-phase converter.

[0021] The first nMOS-DFVF includes five nMOS transistors, namely MA1, MA2, MA3, MA4 and an nMOS current source, and two pMOS transistors, namely MA5 and a pMOS current source. The gates of MA1 and MA2 are connected to the input voltage and the output voltage, respectively, and their sources are connected to the drain of MA4. The drain of MA1 is connected to the drain and gate of MA5. The drain of MA2 is connected to both the gate of MA3 and one end of the pMOS current source, and the other end of the pMOS current source is connected to VDD. The drain of MA3 is directly connected to VDD, and its source is connected to both the gate of MA4 and one end of the nMOS current source, and the other end of the nMOS current source is connected to GND. The source of MA4 is connected to GND, and the source of MA5 is connected to VDD.

[0022] The second nMOS-DFVF includes five nMOS transistors, namely MB1, MB2, MB3, MB4, and an nMOS current source for the nMOS-DFVF, and two pMOS transistors, namely MB5 and a pMOS current source for the nMOS-DFVF. The gates of MB1 and MB2 are connected to the output voltage and the input voltage, respectively, and their sources are connected to the drain of MB4. The drain of MB1 is connected to the drain and gate of MB5. The drain of MB2 is connected to both the gate of MB3 and one end of the pMOS current source, and the other end of the pMOS current source is connected to VDD. The drain of MB3 is directly connected to VDD, and its source is connected to both the gate of MB4 and one end of the nMOS current source, and the other end of the nMOS current source is connected to GND. The source of MB4 is connected to GND, and the source of MB5 is connected to VDD. Here, VDD is the power supply voltage, and GND is ground.

[0023] The bias-complementary pMOS-DFVF pair includes two sequentially connected and completely symmetrical first pMOS-DFVF and second pMOS-DFVF, and a pMOS-phase converter connected to the second pMOS-DFVF. The first pMOS-DFVF provides a bias voltage to the nMOS output transistor; the second pMOS-DFVF provides a bias voltage to the pMOS output transistor through the pMOS-phase converter.

[0024] The first pMOS-DFVF includes five pMOS transistors, namely MA6, MA7, MA8, MA9, and a pMOS current source for the pMOS-DFVF, and two nMOS transistors, namely MA10 and an nMOS current source for the pMOS-DFVF. The gates of MA6 and MA7 are connected to the input voltage and the output voltage, respectively, and their sources are connected to the drain of MA9. The drain of MA6 is connected to the drain and gate of MA10. The drain of MA7 is connected to both the gate of MA8 and one end of the nMOS current source, and the other end of the nMOS current source is connected to GND. The drain of MA8 is directly connected to GND, and its source is connected to both the gate of MA9 and one end of the pMOS current source, and the other end of the pMOS current source is connected to VDD. The source of MA9 is connected to VDD, and the source of MA10 is connected to GND.

[0025] The second pMOS-DFVF includes five pMOS transistors, namely MB6, MB7, MB8, MB9, and a pMOS current source for the pMOS-DFVF, and two nMOS transistors, namely MB10 and an nMOS current source for the pMOS-DFVF. The gates of MB6 and MB7 are connected to the output voltage and the input voltage, respectively, and their sources are connected to the drain of MB9. The drain of MB6 is connected to the drain and gate of MB10. The drain of MB7 is connected to both the gate of MB8 and one end of the nMOS current source, and the other end of the nMOS current source is connected to GND. The drain of MB8 is directly connected to GND, and its source is connected to both the gate of MB9 and one end of the pMOS current source, and the other end of the pMOS current source is connected to VDD. The source of MB9 is connected to VDD, and the source of MB10 is connected to GND. Here, VDD is the power supply voltage, and GND is ground.

[0026] When V in <V GS,N +V DS,N When V is present, the bias-complementary pMOS-DFVF pair can operate; when V is present... in >VDD-V GS,P -V DS,P When the bias-complementary nMOS-DFVF pair is in operation; when V GS,N +V DS,N <V in <VDD-V GS,P -V DS,P At this time, both the bias-complementary pMOS-DFVF pair and the bias-complementary nMOS-DFVF pair can operate, wherein V GS,N V is the gate-source voltage of the nMOS transistor. DS,N V is the drain-source voltage of the nMOS transistor. GS,P V is the gate-source voltage of the pMOS transistor.DS,P VDD is the drain-source voltage of the pMOS transistor, VDI is the power supply voltage, and Vin is the input voltage.

[0027] The input voltage is equal to the output voltage.

[0028] The beneficial effects of this invention are:

[0029] This invention employs a "bias-complementary DFVF pair," combining two different types of DFVFs to achieve rail-to-rail functionality. This ensures that a DFVF in the buffer is always operational, thus guaranteeing that the output transistor always receives bias voltage from the DFVF. Consequently, under various large signal inputs, the dynamic current of the output transistor is always much larger than the static current, resulting in a consistently high slew rate in the buffer and reducing input-to-output delay. Attached Figure Description

[0030] Figure 1(a) is a schematic diagram of the FVF using an nMOS as the input transistor in the prior art;

[0031] Figure 1(b) is a schematic diagram of an FVF using a pMOS as the input transistor in the prior art;

[0032] Figure 2(a) is a schematic diagram of a DFVF using nMOS as the differential input pair transistor in the prior art;

[0033] Figure 2(b) is a schematic diagram of a DFVF using pMOS as the differential input pair transistor in the prior art;

[0034] Figure 3 This is a typical schematic diagram of a DFVF-based rail-to-rail buffer in existing technology;

[0035] Figure 4 It is a dynamic waveform diagram of the input voltage switching between VDD and 0 in the existing technology;

[0036] Figures 5(a) and 5(b) are schematic diagrams illustrating how Vout follows Vin when Vin changes within a small range in a DFVF-based track-to-track buffer in the prior art.

[0037] Figure 6 This is a circuit diagram in an embodiment of the present invention;

[0038] Figure 7(a) is a schematic diagram of a buffer based on a bias-complementary nMOS-DFVF pair in an embodiment of the present invention;

[0039] Figure 7(b) is a schematic diagram of a buffer based on a bias-complementary pMOS-DFVF pair in an embodiment of the present invention;

[0040] Figure 8(a) is a schematic diagram of the delay when Vout follows Vin's change when Vin jumps in a higher voltage range in an embodiment of the present invention;

[0041] Figure 8(b) is a schematic diagram showing the delay of Vout following Vin's change when Vin jumps in a lower voltage range in an embodiment of the present invention;

[0042] Figure 8(c) is a schematic diagram of the delay when Vout follows Vin changes over a large range in an embodiment of the present invention;

[0043] In the figure, 1-upper bias complementary DFVF pair, 2-lower bias complementary DFVF pair, 3-output stage, 4-nMOS-DFVF on the left, 5-nMOS-DFVF on the right, 6-nMOS phase converter, 7-pMOS-DFVF on the left, 8-pMOS-DFVF on the right, 9-pMOS phase converter. Detailed Implementation

[0044] To make the technical solutions and advantages of the present invention clearer, the technical solutions of the embodiments of the present invention will be fully described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0045] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0046] Figure 3 The condition for the buffer in the prior art to achieve a high slew rate is that the DFVF circuit providing the bias voltage to the output transistor can function properly. Because when V in From VDD to VDD-V GS,P -V DS,P When V is not working, the pMOS-DFVF cannot provide a bias voltage for the nMOS output transistor MN, and the output stage cannot replicate a large dynamic current, thus limiting the slew rate of the buffer; similarly, because when V in From 0 to V in an instant GS,N +V DS,N When the nMOS-DFVF is not working, it cannot provide a bias voltage for the pMOS output transistor MP, and the output stage also cannot replicate a large dynamic current, so the slew rate of the buffer is also limited.

[0047] To address the issue of limited slew rate in buffers, in some embodiments, this invention provides a high slew rate voltage buffer based on a flip-flop voltage follower differential structure. This ensures that regardless of input voltage fluctuations, the buffer maintains a high slew rate during large signal transitions. Furthermore, the buffer proposed in this invention can ensure V... out =V in .

[0048] This invention proposes a buffer that provides complementary bias voltages to the output stage by combining two symmetrical DFVFs with a "phase converter," such as... Figure 6 As shown in the figure. When analyzing this buffer, it can be first divided into upper bias complementary DFVF pair 1 and lower bias complementary DFVF pair 2 according to the division of the dashed box in the figure. Let these two parts share MN and MP of the output stage 3 within the dotted box in the figure. Then each "bias complementary DFVF pair" combined with the output stage can form a buffer, as shown in Figure 7(a) and Figure 7(b).

[0049] Figure 7(a) shows a buffer with two completely symmetrical nMOS-DFVFs: the left nMOS-DFVF4 provides a bias voltage to the pMOS output transistor MP through MA5; the right nMOS-DFVF5 converts the pMOS bias voltage generated by MB5 into an nMOS bias voltage through an nMOS phase converter 6, and uses this as the bias voltage for the nMOS output transistor MN. Therefore, the two completely symmetrical nMOS-DFVFs can provide complementary bias voltages to different types of MOS transistors (pMOS output transistor MP and nMOS output transistor MN) in the output stage. Thus, the two completely symmetrical nMOS-DFVFs, together with the "phase converter," constitute a "complementary bias nMOS-DFVF pair."

[0050] The left-hand nMOS-DFVF contains five nMOS transistors (MA1, MA2, MA3, MA4) and an nMOS current source, and two pMOS transistors (MA5 and a pMOS current source). The gates of MA1 and MA2 are connected to the input and output voltages, respectively, and their sources are connected to the drain of MA4. The drain of MA1 is connected to both the drain and gate of MA5. The drain of MA2 is connected to both the gate of MA3 and one end of the pMOS current source, with the other end of the pMOS current source connected to VDD. The drain of MA3 is directly connected to VDD, and its source is connected to both the gate of MA4 and one end of the nMOS current source, with the other end of the nMOS current source connected to GND. The source of MA4 is connected to GND, and the source of MA5 is connected to VDD.

[0051] The right-side nMOS-DFVF contains five nMOS transistors: MB1, MB2, MB3, MB4, and an nMOS current source, as well as two pMOS transistors: MB5 and a pMOS current source. The gates of MB1 and MB2 are connected to the output and input voltages, respectively. Specifically, the gate of MB1 is connected to the gate of MB2, and the gate of MB2 is connected to the gate of MB1. Their sources are connected to the drain of MB4. The drain of MB1 is connected to the drain and gate of MB5. The drain of MB2 is connected to both the gate of MB3 and one end of the pMOS current source, with the other end of the pMOS current source connected to VDD. The drain of MB3 is directly connected to VDD, and its source is connected to both the gate of MB4 and one end of the nMOS current source, with the other end of the nMOS current source connected to GND. The source of MB4 is connected to GND, and the source of MB5 is connected to VDD. Here, VDD is the power supply voltage, and GND is ground.

[0052] Similarly, in the buffer shown in Figure 7(b), the "bias-complementary pMOS-DFVF pair" formed by the two completely symmetrical pMOS-DFVFs and the "phase converter" can also provide complementary bias voltages for the two MOS transistors in the output stage. Specifically, the pMOS-DFVF7 on the left provides the bias voltage to the nMOS output transistor MN through MA10; the pMOS-DFVF8 on the right converts the nMOS transistor bias voltage generated by MB10 into the pMOS transistor bias voltage through the pMOS phase converter 9. Therefore, when the buffer shown in Figure 7 performs large signal conversion, the dynamic current of its output stage is always greater than the static current, resulting in a high slew rate under various large signal inputs.

[0053] The left-hand pMOS-DFVF contains five pMOS transistors: MA6, MA7, MA8, MA9, and a pMOS current source, as well as two nMOS transistors: MA10 and an nMOS current source. The gates of MA6 and MA7 are connected to the input and output voltages, respectively, and their sources are connected to the drain of MA9. The drain of MA6 is connected to the drain and gate of MA10. The drain of MA7 is connected to both the gate of MA8 and one end of the nMOS current source, with the other end of the nMOS current source connected to GND. The drain of MA8 is directly connected to GND, and its source is connected to both the gate of MA9 and one end of the pMOS current source, with the other end of the pMOS current source connected to VDD. The source of MA9 is connected to VDD, and the source of MA10 is connected to GND.

[0054] The pMOS-DFVF on the right contains five pMOS transistors: MB6, MB7, MB8, MB9, and a pMOS current source, as well as two nMOS transistors: MB10 and an nMOS current source. The gates of MB6 and MB7 are connected to the output and input voltages, respectively. Specifically, the gates of MB6 and MB7 are connected, and the gates of MB7 and MB6 are connected together. Their sources are connected to the drain of MB9. The drain of MB6 is connected to both the drain and gate of MB10. The drain of MB7 is connected to both the gate of MB8 and one end of the nMOS current source, with the other end of the nMOS current source connected to GND. The drain of MB8 is directly connected to GND, and its source is connected to both the gate of MB9 and one end of the pMOS current source, with the other end of the pMOS current source connected to VDD. The source of MB9 is connected to VDD, and the source of MB10 is connected to GND. Here, VDD is the power supply voltage, and GND is ground.

[0055] The specific implementation principle of the high slew rate of the buffer shown in Figure 7(a) is as follows:

[0056] When V in From VDD to VDD-V GS,P -V DS,P Time (where V) GS,P V is the gate-source voltage of the pMOS transistor. DS,P (where V is the drain-source voltage of the pMOS transistor), because V out The current cannot be changed immediately, so both MA1 and MB2 are cut off. The cutoff of MA1 causes MA5 and the pMOS output transistor MP to also be cut off; the cutoff of MB2 causes the gate voltage of MB3 to rise, which in turn causes the gate voltage of MB4 to rise, thus significantly increasing the current flowing through MB4. The current in MB4 can only come from MB5, so the current in MB5 also increases significantly. The current in MB5, after being inverted by the phase converters MC1 and MC2, is mirrored to the nMOS output transistor MN, thus significantly increasing the current in MN. Therefore, the slew rate of the circuit is improved, the capacitor can discharge quickly, and the output voltage can quickly equalize with the input voltage, reducing the delay from input to output.

[0057] The specific implementation principle of the high slew rate of the buffer shown in Figure 7(b) is as follows:

[0058] When V in From 0 to V in an instant GS,N +V DS,N Time (where V) GS,N V is the gate-source voltage of the nMOS transistor. DS,N (where V is the drain-source voltage of the nMOS transistor), because V outThe current cannot be changed immediately; both MA6 and MB7 are cut off. The cutoff of MA6 causes MA10 and the nMOS output transistor MN to also be cut off. The cutoff of MB7 causes a drop in the gate voltage of MB8, which in turn causes a drop in the gate voltage of MB9, thus significantly increasing the current flowing through MB9. The current in MB9 can only come from MB10, so the current in MB10 also increases significantly. The current in MB10, after being inverted by phase converters MC3 and MC4, is mirrored to the pMOS output transistor MP, thus significantly increasing the current in MP. Therefore, the slew rate of the circuit is improved, the capacitor can discharge quickly, and the output voltage equalizes with the input voltage as soon as possible, reducing the delay from input to output.

[0059] In summary, neither of the two buffers shown in Figure 7 exhibits a slew rate limitation issue. Figure 3 The buffer shown implements the same principle for track-to-track functionality because... Figure 6 Combining the two different types of DFVFs shown in Figure 7, based on nMOS and pMOS, when V in <V GS,N +V DS,N When V is active, the pMOS-DFVF can operate; when V is active, the pMOS-DFVF can operate. in >VDD-V GS,P -V DS,P When V is present, the nMOS-DFVF can operate; when V is present... GS,N +V DS,N <V in <VDD-V GS,P -V DS,P At that time, both types of DFVF can work. Therefore, regardless of V... in Within any range, at least one type of DFVF in the buffer can function correctly, thus ensuring not only V out =V in Furthermore, it ensures that the output stage can replicate the large dynamic current generated by the FVF during dynamic operation. Therefore, this buffer can achieve rail-to-rail functionality and guarantee a high slew rate under various large signal inputs.

[0060] The dynamic waveform of the buffer is shown in Figure 8. Comparing Figure 8(a) and Figure 5(a), it can be clearly seen that under the same large signal input, Figure 6 The output voltage V of the buffer shown out Following V in Jumping from VDD to VDD-V GS,P -V DS,P (or more than VDD-V) GS,P -V DS,P At higher voltages, the delay t delay2 much smaller Figure 3 The buffer shown; comparing Figure 8(b) and Figure 5(b), it can be clearly seen that under the same large signal input, Figure 6 The output voltage V of the buffer shown out Following V in From 0 to V GS,N +V DS,N (or V) GS,N +V DS,N At lower voltages, the delay t delay2 much smaller Figure 3 The above comparison demonstrates the advantage of the improved buffer's higher slew rate. Figure 8(c) shows that the improved buffer still possesses... Figure 3 The original advantages of the buffer are shown.

[0061] Although Figure 3 Existing technologies also use two identical FVFs, but only to achieve differential input to differential output. Therefore, the two FVFs serve the same purpose, and only one FVF needs to be analyzed when analyzing the circuit. This invention proposes a single-ended input to single-ended output buffer. This buffer uses a "bias-complementary DFVF pair." Based on two identical DFVFs, a phase converter is matched to one of them, allowing the two symmetrical DFVFs to provide complementary bias voltages to two different types of output transistors. Combining these two different types of DFVFs achieves rail-to-rail functionality. Compared to... Figure 3 The original scheme shown does not increase design complexity with the new scheme. However, the introduction of two different types of "bias-complementary DFVF pairs" ensures that there is always a DFVF in the buffer, so the output transistor always receives a bias voltage from the DFVF. Therefore, under various large signal inputs, the dynamic current of the output transistor is always much larger than the static current, giving the buffer a high slew rate and reducing the input-to-output delay. Thus, the scheme proposed in this invention successfully solves the problem of the original buffer's limited slew rate and will be widely used in more analog circuits.

[0062] In the description of this specification, references to terms such as "an embodiment" and "example" refer to specific features, structures, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms are not necessarily intended to refer to corresponding embodiments or examples in a suitable manner.

[0063] It must be pointed out that the above description of the embodiments is not intended to limit the invention but only to help understand the core idea of ​​the invention. For those skilled in the art, any improvements to the invention and equivalent alternatives made to the invention without departing from the principle of the invention are also within the scope of protection of the claims of the invention.

Claims

1. A high slew rate voltage buffer based on a differential structure of a flip-flop voltage follower, characterized in that, It includes an output stage and two different types of bias complementary DFVF pairs, wherein one end of each bias complementary DFVF pair is connected to the input voltage and the other end is connected to the output stage, and the output stage includes two different types of output transistors connected to the output voltage; The two complementary bias DFVF pairs can provide complementary bias voltages for the two different types of output transistors, ensuring that there is always a DFVF in operation, so that the dynamic current of the output stage is always greater than the static current when performing large signal conversion.

2. The high slew rate voltage buffer based on a differential structure of a flip-flop voltage follower according to claim 1, characterized in that, The two different types of output transistors are a pMOS output transistor and an nMOS output transistor.

3. The high slew rate voltage buffer based on a differential structure of a flip-flop voltage follower according to claim 2, characterized in that, The bias-complementary DFVF pair includes two sequentially connected first DFVF and second DFVF, and a phase converter connected to the second DFVF, wherein the first DFVF and the second DFVF are completely symmetrical, and the phase converter is used to convert the bias voltage of one type of output transistor to the bias voltage of another type of output transistor.

4. The high slew rate voltage buffer based on a differential structure of a flip-flop voltage follower according to claim 3, characterized in that, The two bias-complementary DFVF pairs are a bias-complementary nMOS-DFVF pair and a bias-complementary pMOS-DFVF pair, respectively.

5. The high slew rate voltage buffer based on a differential structure of a flip-flop voltage follower according to claim 4, characterized in that, The bias-complementary nMOS-DFVF pair includes two sequentially connected and completely symmetrical first nMOS-DFVF and second nMOS-DFVF, and an nMOS-phase converter connected to the second nMOS-DFVF. The first nMOS-DFVF provides a bias voltage to the pMOS output transistor. The second nMOS-DFVF provides a bias voltage to the nMOS output transistor through the nMOS phase converter.

6. The high slew rate voltage buffer based on a differential structure of a flip-flop voltage follower according to claim 5, characterized in that, The first nMOS-DFVF includes five nMOS transistors, namely MA1, MA2, MA3, MA4 and an nMOS current source, and two pMOS transistors, namely MA5 and a pMOS current source. The gates of MA1 and MA2 are connected to the input voltage and the output voltage, respectively, and their sources are connected to the drain of MA4. The drain of MA1 is connected to the drain and gate of MA5. The drain of MA2 is connected to both the gate of MA3 and one end of the pMOS current source, and the other end of the pMOS current source is connected to VDD. The drain of MA3 is directly connected to VDD, and its source is connected to both the gate of MA4 and one end of the nMOS current source, and the other end of the nMOS current source is connected to GND. The source of MA4 is connected to GND, and the source of MA5 is connected to VDD. The second nMOS-DFVF includes five nMOS transistors, namely MB1, MB2, MB3, MB4, and an nMOS current source for the nMOS-DFVF, and two pMOS transistors, namely MB5 and a pMOS current source for the nMOS-DFVF. The gates of MB1 and MB2 are connected to the output voltage and the input voltage, respectively, and their sources are connected to the drain of MB4. The drain of MB1 is connected to the drain and gate of MB5. The drain of MB2 is connected to both the gate of MB3 and one end of the pMOS current source, and the other end of the pMOS current source is connected to VDD. The drain of MB3 is directly connected to VDD, and its source is connected to both the gate of MB4 and one end of the nMOS current source, and the other end of the nMOS current source is connected to GND. The source of MB4 is connected to GND, and the source of MB5 is connected to VDD. Here, VDD is the power supply voltage, and GND is ground.

7. The high slew rate voltage buffer based on a differential structure of a flip-flop voltage follower according to claim 4, characterized in that, The bias-complementary pMOS-DFVF pair includes two sequentially connected and completely symmetrical first pMOS-DFVF and second pMOS-DFVF, and a pMOS-phase converter connected to the second pMOS-DFVF. The first pMOS-DFVF provides a bias voltage to the nMOS output transistor. The second pMOS-DFVF provides a bias voltage to the pMOS output transistor through the pMOS-phase converter.

8. The high slew rate voltage buffer based on a differential structure of a flip-flop voltage follower according to claim 7, characterized in that, The first pMOS-DFVF includes five pMOS transistors, namely MA6, MA7, MA8, MA9 and a pMOS current source for the pMOS-DFVF, and two nMOS transistors, namely MA10 and an nMOS current source for the pMOS-DFVF. The gates of MA6 and MA7 are connected to the input voltage and the output voltage, respectively, and their sources are connected to the drain of MA9. The drain of MA6 is connected to the drain and gate of MA10. The drain of MA7 is connected to both the gate of MA8 and one end of the nMOS current source. The other end of the nMOS current source is connected to GND. The drain of MA8 is directly connected to GND, and the source is connected to both the gate of MA9 and one end of the pMOS current source, with the other end of the pMOS current source connected to VDD; the source of MA9 is connected to VDD, and the source of MA10 is connected to GND. The second pMOS-DFVF includes five pMOS transistors, namely MB6, MB7, MB8, MB9, and a pMOS current source for the pMOS-DFVF, and two nMOS transistors, namely MB10 and an nMOS current source for the pMOS-DFVF. The gates of MB6 and MB7 are connected to the output voltage and the input voltage, respectively, and their sources are connected to the drain of MB9. The drain of MB6 is connected to the drain and gate of MB10. The drain of MB7 is connected to both the gate of MB8 and one end of the nMOS current source, and the other end of the nMOS current source is connected to GND. The drain of MB8 is directly connected to GND, and its source is connected to both the gate of MB9 and one end of the pMOS current source, and the other end of the pMOS current source is connected to VDD. The source of MB9 is connected to VDD, and the source of MB10 is connected to GND. Here, VDD is the power supply voltage, and GND is ground.

9. The high slew rate voltage buffer based on a differential structure of a flip-flop voltage follower according to claim 4, characterized in that, When V in <V GS,N +V DS,N When V is present, the bias-complementary pMOS-DFVF pair can operate; when V is present... in >VDD-V GS,P -V DS,P When the bias-complementary nMOS-DFVF pair is in operation; when V GS,N +V DS,N <V in <VDD-V GS,P -V DS,P At this time, both the bias-complementary pMOS-DFVF pair and the bias-complementary nMOS-DFVF pair can operate, wherein V GS,N V is the gate-source voltage of the nMOS transistor. DS,N V is the drain-source voltage of the nMOS transistor. GS,P V is the gate-source voltage of the pMOS transistor. DS,P VDD is the drain-source voltage of the pMOS transistor, VDI is the power supply voltage, and Vin is the input voltage.

10. The high slew rate voltage buffer based on a differential structure of a flip-flop voltage follower according to claim 1, characterized in that, The input voltage is equal to the output voltage.

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