A method for optimizing NAND Flash performance based on wordline grouping

Abstract

The present application relates to the field of memory, in particular to a method for optimizing NAND Flash performance based on wordline grouping, comprising the following steps: sequentially grouping a Block into a first-level, a second-level and a third-level group; performing normal reading and writing in the first-level group, saving different time lengths in the second-level group, and allocating different read interference numbers to each group in the third-level group; reading the block using different voltage axes; selecting WL groups under each single variable and sequentially grouping them into X groups, Y groups and Z groups, then splitting the X groups, Y groups and Z groups into more detailed A groups, and finally reading the entire Block using different voltage axes. The present application solves the problem of a large number of errors caused by reading the entire Block using a single voltage axis, and can improve the service life and performance of NAND by reading the entire Block using flexible voltage axes.

Description

Technical Field

[0001] This invention relates to the field of memory, and more specifically to a method for optimizing NAND Flash performance based on wordline grouping. Background Technology

[0002] NAND Flash is a non-volatile memory characterized by data retention when power is off, high storage efficiency, and small size. Generally, a single NAND Flash chip has multiple chip select (CE) signals, each CE contains multiple blocks, each block contains multiple word lines (WL), and each word line contains several pages. Users can perform erase, write, and read operations on NAND Flash. The smallest addressable unit for an erase operation is a block, for a write operation it is a word line, and for a read operation it is a page.

[0003] During the reading of certain data in NAND Flash, there is a phenomenon where the read data differs significantly from the written data. Specifically, NAND Flash may exhibit bit reversal during operation, meaning that a 1 in the written data is read as a 0, or vice versa. One reason for this phenomenon is that the operating principle of NAND Flash is limited by the manufacturing process.

[0004] To avoid the aforementioned issues, NAND Flash datasheets specify the maximum number of wear cycles and the longest retention time. Therefore, increasing the maximum number of wear cycles and the longest retention time of NAND Flash can improve its performance. Current technologies typically use a single voltage axis to read the entire block to reduce the probability of read errors. However, this method may not meet the error correction standards of Low-Density Parity-Check (LDPC), resulting in an inability to optimize the read error probability. Summary of the Invention

[0005] This invention provides a method for optimizing NAND Flash performance based on wordline grouping, which solves the problem of high difference rate between NAND Flash read data and write data.

[0006] The technical solution of this application is as follows:

[0007] A method for optimizing NAND Flash performance based on wordline grouping includes the following steps:

[0008] S01) Group the Blocks into i primary groups based on the degree of wear;

[0009] S02) The first-level group is normally erased and written once at a certain temperature, and the time when the writing amount reaches 100% is recorded;

[0010] S03) Based on the primary grouping results, each primary group is divided into j secondary groups on average;

[0011] S04) Based on the maximum storage duration given by the NAND Flash manufacturer, the storage duration is divided into j storage durations and assigned to j of the secondary groups. The storage duration values ​​form an arithmetic sequence with the first term being 0, the last term being the maximum storage duration, and the common difference being the maximum storage duration / (j-1).

[0012] S05) Each of the secondary groups is saved at a certain temperature according to the allocated storage time; the initial time of the storage time is the time when the write volume reaches 100% in step S02);

[0013] S06) Based on the secondary grouping results, each secondary group is divided into k tertiary groups on average;

[0014] S07) Based on the maximum number of read interferences given by the NAND Flash manufacturer, the number of read interferences is divided into k number of read interferences and assigned to k of the three-level groups. The read interference numbers of each of the three-level groups form an arithmetic sequence. The first term of the arithmetic sequence is 0, the last term is the maximum number of read interferences, and the common difference is the maximum number of read interferences / (k-1).

[0015] S08) Read the block at the same temperature using different voltage axes.

[0016] S09) Select tertiary groups from different primary groups that have the same storage duration and the same number of read interferences among secondary groups, and extract wordlines with similar error numbers and / or the same trend of change to form X1, X2…X n Group; the X1, X2…X n Together they form group X;

[0017] Select tertiary groups with the same number of read interferences among different secondary groups under the same primary group, and extract word lines with similar error numbers and / or the same trend of change to form Y1, Y2…Y m Group; the Y1, Y2…Y m Together they form group Y;

[0018] Select all tertiary groups under the same secondary grouping, and extract wordlines with similar error counts and / or the same trend of change to form Z1, Z2…Z s Group; the Z1, Z2…Z s Together they form Group Z;

[0019] S10) Merge groups X, Y, and Z into group A, which includes A1, A2, A3…A p Group, A1, A2, A3…A p The groups are X1, X2…X n Group, Y1, Y2…Y m Group, Z1, Z2...Z s The order of the intersection of groups.

[0020] S11) Using A1, A2, A3…A p The voltage axis reads the block corresponding to each group.

[0021] Furthermore, the erase / write temperature in step S02) is the same as the read temperature in step S08).

[0022] Preferably, the erase / write temperature in step S02) and the read temperature in step S08) are both 40°C.

[0023] Preferably, the storage temperature in step S05) is the same as the erase / write temperature in step S02).

[0024] Preferably, the storage temperature in step S05) is different from the erase / write temperature in step S02).

[0025] Furthermore, in step S05), the storage time can be shortened by increasing the temperature; when using high-temperature storage, the temperature acceleration coefficient is first calculated. OF :

[0026] ,

[0027] in, exp Represented by natural constant e An exponential function with base 0. EA The voltage is 1.0~1.1 eV. kB Boltzmann's constant, Tnow To maintain the block at a high Kelvin temperature, This indicates the Kelvin temperature corresponding to 40℃;

[0028] The high-temperature storage time is equal to the storage time allocated at 40℃ multiplied by the temperature acceleration factor.

[0029] Furthermore, after high-temperature preservation, the temperature must be lowered to 40°C before proceeding to step S06.

[0030] Furthermore, when A i and A i+1When using the same three sets of voltage axes to read data under different wear levels, storage durations, and read interference counts can meet the error correction requirements of low-density parity-check codes, A i and A i+1 They can be combined into one group.

[0031] Due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0032] This invention groups wordlines classified into three levels based on wear level, storage duration, and read interference under different voltage axes. By controlling a single variable to read the error count corresponding to different voltage axes, the wordline groups under different variables are merged into the same group. Each group is read using an independent voltage axis. This reduces the overall number of errors read from the block, thereby increasing the wear count and storage duration of the NAND Flash, ultimately extending the lifespan and optimizing the performance of the NAND Flash. Attached Figure Description

[0033] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0034] Figure 1 This is a flowchart of the method. Detailed Implementation

[0035] Example 1:

[0036] As attached Figure 1 As shown, a method for optimizing NAND Flash performance based on wordline grouping includes the following steps:

[0037] S01) The Blocks are grouped for the first time based on the degree of wear, resulting in i primary groups.

[0038] S02) Perform a normal erase and write operation on the first-level group once, and record the moment when the write volume reaches 100%;

[0039] In this embodiment, the erase / write temperature is 40°C.

[0040] S03) Based on the primary grouping results, each primary group is divided into j secondary groups on average;

[0041] The number of secondary groups is determined by the user based on the maximum storage duration and requirements. In this embodiment, the maximum storage duration given by NANDFlash is 90 days, and j is 11.

[0042] S04) Based on the maximum storage duration given by the NAND Flash manufacturer, the data is divided into j storage durations and assigned to j of the secondary groups. The storage duration values ​​form an arithmetic sequence with the first term being 0, the last term being the maximum storage duration, and the common difference being the maximum storage duration / (j-1).

[0043] In this embodiment, the manufacturer specifies a maximum storage time of 90 days at 40°C, with j set to 11. Therefore, each primary group has 11 secondary groups, and the storage times for the 11 secondary groups under each primary group are different, while the storage times for the 11 secondary groups under different primary groups correspond one-to-one. In this embodiment, the storage times assigned to the secondary groups under a primary group are 0, 9 days, 18 days...90 days.

[0044] S05) Each of the secondary groups is saved at a certain temperature according to the allocated storage time; the initial time of the storage time is the time when the write volume reaches 100% in step S02).

[0045] S06) Based on the secondary grouping results, each secondary group is divided into k tertiary groups on average. The value of k is determined by the user based on the maximum number of read interferences; in this embodiment, k is 3.

[0046] S07) Based on the maximum number of read interferences given by the NAND Flash manufacturer, the number of read interferences is divided into k number of read interferences and assigned to k of the three-level groups. The read interference numbers of each of the three-level groups form an arithmetic sequence. The first term of the arithmetic sequence is 0, the last term is the maximum number of read interferences, and the common difference is the maximum number of read interferences / (k-1).

[0047] In this embodiment, the maximum number of read interferences given by the manufacturer is 1000 block interferences. Therefore, the number of read interferences allocated to the third-level groups corresponding to each second-level group are 0, 500, and 1000, respectively.

[0048] S08) Read the block using different voltage axes at the same temperature. In this embodiment, the temperature is 40°C.

[0049] S09) Select tertiary groups from different primary groups that have the same storage duration and the same number of read interferences among secondary groups, and extract wordlines with similar error numbers and / or the same trend of change to form X1, X2…X n Group; the X1, X2…X n Together they form group X;

[0050] In this embodiment, the wordline of group X is 0~383, 384~767.

[0051] Select tertiary groups with the same number of read interferences among different secondary groups under the same primary group, and extract word lines with similar error numbers and / or the same trend of change to form Y1, Y2…Y m Group; the Y1, Y2…Y m Together they form group Y;

[0052] In this embodiment, the wordline of group Y is 0~5, 6~389, 390~767.

[0053] Select all tertiary groups under the same secondary grouping, and extract wordlines with similar error counts and / or the same trend of change to form Z1, Z2…Z n Group; the Z1, Z2…Z s Together they form Group Z;

[0054] In this embodiment, the wordline of group Z is 0~191 and 192~767.

[0055] S10) Divide groups X, Y, and Z into group A, which includes A1, A2, A3…A p Group, A1, A2, A3…A p The groups are X1, X2…X n Group, Y1, Y2…Y m Group, Z1, Z2...Z s The order of the intersection of groups.

[0056] In this embodiment, the split group A consists of 0~5, 6~191, 192~383, 384~389, and 390~767.

[0057] S11) Using A1, A2, A3…A p The voltage axis reads the block corresponding to each group.

[0058] In this embodiment, the entire block is read using the voltage axis corresponding to the number of errors when the wordline is 0~5, 6~191, 192~383, 384~389, or 390~767.

[0059] This embodiment avoids the performance degradation of NAND Flash caused by a high number of errors in local wordlines when reading the entire block using a single voltage axis. This embodiment uses a flexible voltage axis to read the entire block, thereby increasing the wear resistance and storage life of the NAND Flash, ultimately optimizing the NAND Flash performance.

[0060] Example 2:

[0061] In this embodiment, the wordline in S11) of embodiment 1 is partially merged, and the resulting group A is: 0~191, 192~383, 384~767.

[0062] This embodiment can reduce the number of wordline groups, thereby reducing the complexity of hardware or firmware processing wordline groups and improving grouping efficiency.

[0063] Example 3:

[0064] In this embodiment, the 90-day storage time at 40°C is shortened by increasing the temperature, with a target temperature of 85°C.

[0065] First, calculate the temperature acceleration coefficient. OF :

[0066] ,

[0067] in, exp This represents an exponential function with base e. EA The voltage is 1.0~1.1 eV (1.1 in this example). kB Here is Boltzmann's constant (8.6171 * 10^-5 in this example). Tnow The Kelvin temperature for high-temperature storage of the Block (85 + 273.15 in this example). This represents the Kelvin temperature corresponding to 40℃ (40 + 273.15 in this example), and the resulting... OF It is 0.005965

[0068] The high-temperature storage time is equal to the storage time allocated at 40℃ multiplied by the temperature acceleration factor, therefore the high-temperature storage time is 773 minutes.

[0069] In addition, the temperature needs to be lowered to 40°C before proceeding to the next step.

[0070] The above description is merely the basic principle and preferred embodiment of the present invention. Improvements and substitutions made by those skilled in the art based on the present invention are within the scope of protection of the present invention.

Claims

1. A method for optimizing NAND Flash performance based on wordline grouping, characterized in that, Includes the following steps, S01) Group the Blocks into i primary groups based on the degree of wear; S02) The first-level group is normally erased and written once at a certain temperature, and the time when the writing amount reaches 100% is recorded; S03) Based on the primary grouping results, each primary group is divided into j secondary groups on average; S04) Based on the maximum storage duration given by the NAND Flash manufacturer, the storage duration is divided into j storage durations and assigned to j of the secondary groups. The storage duration values ​​form an arithmetic sequence with the first term being 0, the last term being the maximum storage duration, and the common difference being the maximum storage duration / (j-1). S05) Each of the secondary groups is saved at a certain temperature according to the allocated storage time; the initial time of the storage time is the time when the write volume reaches 100% in step S02); S06) Based on the secondary grouping results, each secondary group is divided into k tertiary groups on average; S07) Based on the maximum number of read interferences given by the NAND Flash manufacturer, the number of read interferences is divided into k number of read interferences and assigned to k of the three-level groups. The read interference numbers of each of the three-level groups form an arithmetic sequence. The first term of the arithmetic sequence is 0, the last term is the maximum number of read interferences, and the common difference is the maximum number of read interferences / (k-1). S08) Read the block at the same temperature using different voltage axes; S09) Select tertiary groups from different primary groups that have the same storage duration and the same number of read interferences among secondary groups, and extract wordlines with similar error numbers and / or the same trend of change to form X1, X2…X n Group; the X1, X2…X n Together they form group X; Select tertiary groups with the same number of read interferences among different secondary groups under the same primary group, and extract word lines with similar error numbers and / or the same trend of change to form Y1, Y2…Y m Group; the Y1, Y2…Y m Together they form group Y; Select all tertiary groups under the same secondary grouping, and extract wordlines with similar error counts and / or the same trend of change to form Z1, Z2…Z s Group; the Z1, Z2…Z s Together they form Group Z; S10) Merge groups X, Y, and Z into group A, which includes A1, A2, A3…A p Group, A1, A2, A3…A p The groups are X1, X2…X n Group, Y1, Y2…Y m Group, Z1, Z2...Z s The order of the intersection of groups; S11) Using A1, A2, A3…A p The voltage axis reads the block corresponding to each group.

2. The method for optimizing NAND Flash performance based on wordline grouping as described in claim 1, characterized in that, The erase / write temperature in step S02) is the same as the read temperature in step S08).

3. The method for optimizing NAND Flash performance based on wordline grouping as described in claim 2, characterized in that, The erase / write temperature in step S02) and the read temperature in step S08) are both 40°C.

4. The method for optimizing NAND Flash performance based on wordline grouping as described in claim 2, characterized in that, The storage temperature in step S05) is the same as the erase / write temperature in step S02).

5. The method for optimizing NAND Flash performance based on wordline grouping as described in claim 2, characterized in that, The storage temperature in step S05) is different from the erase / write temperature in step S02).

6. The method for optimizing NAND Flash performance based on wordline grouping as described in claim 5, characterized in that, In step S05), the storage time is shortened by increasing the temperature; when using high-temperature storage, the temperature acceleration coefficient is first calculated. AF : ， in, exp Represented by natural constant e An exponential function with base 0. EA The voltage is 1.0~1.1 eV. kB Boltzmann's constant, Tnow To maintain the block at a high Kelvin temperature, This indicates the Kelvin temperature corresponding to 40℃; The high-temperature storage time is equal to the storage time allocated at 40℃ multiplied by the temperature acceleration factor.

7. The method for optimizing NAND Flash performance based on wordline grouping as described in claim 6, characterized in that, After high-temperature storage is completed, the temperature must be lowered to 40°C before proceeding to step S06.

8. A method for optimizing NAND Flash performance based on wordline grouping as described in any one of claims 1-7, characterized in that, When A i and A i+1 When using the same three sets of voltage axes to read data under different wear levels, storage durations, and read interference counts can meet the error correction requirements of low-density parity-check codes, A i and A i+1 They can be combined into one group.

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