Method and apparatus for optimization of integrated circuit layout
By identifying power rails and power domains, performing design specification verification and current and voltage analysis, defining paths to be corrected, and adjusting the type and number of vias, the electromigration problem in integrated circuit layout was solved, and the layout of power rails was optimized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- REALTEK SEMICON CORP
- Filing Date
- 2022-02-08
- Publication Date
- 2026-06-30
Smart Images
Figure CN116611385B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to an integrated circuit design technology, and more particularly to an optimization method, apparatus, and non-transitory computer-readable medium for integrated circuit layout. Background Technology
[0002] After the circuit layout is completed, standard cells are placed throughout the IC. Power rails are metal lines connected in series with the power pins or ground pins of these standard cells. For multiple standard cells at the same horizontal height, the corresponding power rails are directly connected in series. Depending on the design of different standard cells, they may also be connected in series via the same vertical line.
[0003] In circuit layout, power rails not only share the metal layer winding resources with signal routing, but also need to maintain high utilization. Therefore, compared with the overall power plan, the metal lines of power rails are thinner and finer. As a result, relatively severe electromigration is more likely to occur on power rails.
[0004] In order to reduce the negative impact of power migration on power rails during power planning, most existing methods involve using more routing resources for power planning, such as increasing the width of the power rails. However, using more power rails will reduce the routing resources and increase the design complexity. Summary of the Invention
[0005] The technical problem to be solved by the present invention is to provide an optimization method, apparatus and non-transitory computer-readable medium for integrated circuit layout, which addresses the shortcomings of the prior art.
[0006] To address the aforementioned technical problems, one technical solution adopted by this invention is to provide an optimization method for integrated circuit layout, comprising: identifying multiple power rails and corresponding power domains in an integrated circuit design file; performing design rule check (DRC) verification on multiple circuit cells generated after placement and routing in the integrated circuit design file to calculate multiple usable areas corresponding to the power rails; performing simulated current and voltage analysis on the circuit cells to determine multiple electromigration violations and related current information corresponding to the power rails; defining multiple paths to be corrected on the power rails corresponding to the electromigration violations based on the electromigration violations and the current information; replacing the types of multiple vias on the power rails that do not overlap with the paths to be corrected; and correcting the number of multiple vias on the power rails that overlap with the paths to be corrected based on the current direction and the position of the electromigration violations, thereby reducing the number of electromigration violations.
[0007] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is to provide an optimization device for integrated circuit layout, including a memory and a processor. A memory configured to store a plurality of computer-executable instructions; and a processor electrically coupled to the memory and configured to retrieve and execute the computer-executable instructions to perform an optimization method comprising: identifying a plurality of power rails and corresponding power domains in an integrated circuit design document; performing a design rule check (DRC) on a plurality of circuit cells generated by place and route in the integrated circuit design document to calculate a plurality of usable areas corresponding to the power rails; performing simulated current and voltage analysis on the circuit cells to determine a plurality of electromigration violations and related current information corresponding to the power rails; defining a plurality of paths to be corrected on the power rails corresponding to the electromigration violations based on the electromigration violations and the current information; replacing the types of a plurality of vias on the power rails that do not overlap with the paths to be corrected; and correcting the number of a plurality of vias on the power rails that overlap with the paths to be corrected based on the current direction and the location of the electromigration violations, thereby reducing the number of electromigration violations.
[0008] To address the aforementioned technical problems, another technical solution adopted by the present invention is to provide a non-transitory computer-readable medium, comprising multiple computer-readable instructions, wherein when these computer-readable instructions are executed by a processor of a computer system, the processor performs an optimization method, the optimization method comprising: identifying multiple power rails and corresponding multiple power domains in an integrated circuit design document; and performing design rule verification on multiple circuit units generated in the integrated circuit design document after placement and routing. The system performs a check (DRC) to calculate multiple usable areas corresponding to the power rails; simulates and analyzes the current and voltage of the circuit units to determine multiple electromigration violations and related current information corresponding to the power rails; defines multiple paths to be corrected on the power rails corresponding to the electromigration violations based on the electromigration violations and the current information; replaces the types of multiple vias on the power rails that do not overlap with the paths to be corrected; and corrects the number of multiple vias on the power rails that overlap with the paths to be corrected based on the current direction and the position of the electromigration violations, thereby reducing the number of electromigration violations.
[0009] One of the beneficial effects of this invention is that the optimization method, apparatus, and non-transitory computer-readable medium for integrated circuit layout provided by this invention can detect, based on Design Rule Check (DRC) of circuit element connection relationships, whether a segment of double-layer power rails after placement and routing can adjust the via density and disperse current flow. Therefore, the negative impact of electromigration can be reduced without violating design rules.
[0010] To further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description
[0011] Figure 1 This is a functional block diagram of an optimization device for integrated circuit layout according to an embodiment of the present invention.
[0012] Figure 2 This is a flowchart of an embodiment of the optimization method for integrated circuit layout according to the present invention.
[0013] Figure 3 This is a layout diagram of an integrated circuit according to an embodiment of the present invention.
[0014] Figure 4According to an embodiment of the present invention, a first schematic diagram is defined in the layout schematic diagram of an integrated circuit to define the path to be corrected.
[0015] Figure 5 According to an embodiment of the present invention, a second schematic diagram is provided in which the path to be corrected is defined in the layout schematic diagram of the integrated circuit.
[0016] Figure 6 According to an embodiment of the present invention, a third schematic diagram is provided in the layout schematic diagram of an integrated circuit to define the path to be corrected.
[0017] Symbol Explanation
[0018] 1: Optimization device
[0019] 3: Integrated Circuits
[0020] 10: Memory
[0021] 11: Processor
[0022] 12: Network Unit
[0023] 13: Storage unit
[0024] 14: Input / output interfaces
[0025] 15: Bus
[0026] 30: Circuit Unit
[0027] 31, 32: Power rails
[0028] 33, 34: Usable Areas
[0029] 40, 50, 60: Paths to be corrected
[0030] 41, 51: Partial
[0031] 100: Computer-readable instructions
[0032] 102: Integrated Circuit Design File
[0033] 104: Simulation Tools
[0034] 310, 320: Contact
[0035] D1: First predetermined distance
[0036] D2: Second predetermined distance
[0037] D3: Third predetermined distance
[0038] D4: Fourth predetermined distance
[0039] em1, em2, em3: Illegal points of electromigration
[0040] I1, I2: Current
[0041] V1: Large guide hole
[0042] V11, V12, V13, V21: Guide holes
[0043] V2: Small guide hole Detailed Implementation
[0044] The following specific embodiments illustrate the implementation of the "Optimization Method, Apparatus, and Non-Transient Computer-Readable Medium for Integrated Circuit Layout" disclosed in this invention. Those skilled in the art can understand the advantages and effects of this invention from the content disclosed in this specification. This invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of this invention. Furthermore, the accompanying drawings are for simple illustration only and are not depictions of actual dimensions, as stated in advance. The following embodiments will further describe the relevant technical content of this invention in detail, but the disclosed content is not intended to limit the scope of protection of this invention. Additionally, the term "or" as used herein may include, depending on the actual situation, any combination of any one or more of the associated listed items.
[0045] Figure 1 This is a functional block diagram of an integrated circuit layout optimization device according to an embodiment of the present invention. (See also...) Figure 1 As shown, an embodiment of the present invention provides an optimization apparatus 1 for integrated circuit layout, which includes a memory 10, a processor 11, a network unit 12, a storage unit 13, and an input / output interface 14. The above-mentioned components can communicate with each other, for example, but not limited to, a bus 15.
[0046] The memory 10 can be any storage device that can be used to store data, such as, but not limited to, random access memory (RAM), read-only memory (ROM), flash memory, hard disk, or other storage devices that can be used to store data. The memory 10 is configured to store at least a plurality of computer-readable instructions 100. In one embodiment, the memory 10 can also be used to store temporary data generated by the processor 11 during computation.
[0047] The processor 11 is electrically coupled to the memory 10 and configured to access computer-readable instructions 100 from the memory 10 to control the components in the power rail design device 1 to perform the functions of the power rail design device 1.
[0048] The network unit 12 is configured to access the network under the control of the processor 11. The storage unit 13 may be, for example, but is not limited to, a disk or optical disk, for storing data or instructions under the control of the processor 11. The input / output unit 14 is operable by a user to communicate with the processor 11 and input and output data.
[0049] Figure 2 This is a flowchart of an embodiment of the optimization method for integrated circuit layout according to the present invention. Figure 2 This provides an optimization method for integrated circuit layout, which can be applied to... Figure 1 The optimization apparatus 1 shown may be implemented by other hardware components such as a database, a general processor, a computer, a server, or other unique hardware devices with specific logic circuits or specific functions, such as integrating program code and a processor / chip into unique hardware. More specifically, the optimization method can be implemented using a computer program to control the components of the optimization apparatus 1. The computer program can be stored in a non-transitory computer-readable recording medium, such as a read-only memory, flash memory, floppy disk, hard disk, optical disk, USB flash drive, magnetic tape, a network-accessible database, or a computer-readable recording medium with similar functionality readily conceived by those skilled in the art.
[0050] See Figure 2 As shown, the optimization method for integrated circuit layout includes the following steps:
[0051] Step S200: In the integrated circuit design file, identify multiple power rails and their corresponding power domains. In some embodiments, the integrated circuit design file 102 may be stored in, for example, but not limited to, memory 10, and accessed by processor 11. The integrated circuit design file contains design data for multiple different circuit units and power rails.
[0052] In detail, in this step, "power rails" refers to multiple double-layer power rails. A single double-layer power rail comprises two power rails respectively disposed in two metal layers, connected by multiple vias. Subsequent steps primarily determine whether the via density of each double-layer power rail can be increased or decreased, and thereafter it will no longer be emphasized that it refers to double-layer power rails.
[0053] Please refer to Figure 3 This is a layout schematic diagram of integrated circuit 3 according to an embodiment of the present invention. Figure 3As shown, the integrated circuit 3 exemplaryly includes at least one circuit unit 30 and power rails 31 and 32. In this embodiment, power rails 31 and 32 are both double-layer power rails, with power rail 31 having multiple large vias V1 and power rail 32 having multiple small vias V2. In this embodiment, the number of circuit units 30, power rails 31 and 32, large vias V1 and small vias V2 is merely an example, and the invention is not limited thereto.
[0054] The circuit unit 30 may be, for example, various logic gates, arithmetic units, or other circuits with specific functions, to perform operations and processes on the input data. In some embodiments, the circuit unit 30 may be a standard cell, which is the smallest circuit unit.
[0055] Power rails 31 and 32 are electrically coupled to circuit unit 30 via power contacts, such as contacts 310 and 320, respectively. In one embodiment, power rail 31 may be supplied with power from a voltage source to circuit unit 30, while power rail 32 may be connected to a ground wire with a ground potential to provide a ground potential to circuit unit 30. For circuit units 30 with different requirements, power rails 31 and 32 may provide power at different voltages, or at the same voltage but from different sources. Therefore, when circuit units 31 and 32 operate according to different power supplies, they will belong to different power domains.
[0056] Step S201: Perform design rule check (DRC) on multiple circuit cells generated in the integrated circuit design file after placement and routing to calculate multiple usable areas corresponding to these power rails.
[0057] To comply with design specifications, circuit unit 30 typically does not utilize all available design space, allowing for flexibility. Therefore, after generating circuit unit 30 through layout and routing, and performing DRC, multiple usable areas are obtained. At least some of these usable areas are adjacent and correspond to power rails 31 and 32, for example... Figure 3 The usable areas shown are 33 and 34.
[0058] Step S202: Perform simulation to generate current and voltage analysis on these circuit units to determine multiple electromigration violations and related current information corresponding to the power rails.
[0059] In this step, after obtaining the usable areas 33 and 34, the circuit unit 30 in the integrated circuit design file 102 can be simulated to generate current and voltage analysis in order to determine the areas of the corresponding power rails 31 and 32 that are easily affected by electromigration (EM).
[0060] In detail, memory 10 may store simulation tool 104, which can be executed after being accessed by processor 11. Simulation tool 104 can be configured to perform voltage and current simulations to determine the current from one or more components within integrated circuit 3, and compare the current with a set current limit to identify the electromigration violation point corresponding to power rails 31, 32. Simultaneously, simulation tool 104 can also obtain multiple current directions and multiple current magnitudes on the power rails corresponding to the electromigration violation point.
[0061] For example, if the current on power rails 31 and 32 violates the current limit, an electromigration violation is identified. In some embodiments, simulation tool 104 may include an integrated circuit importance simulation program (SPICE) simulator.
[0062] Step S203: Based on the equipotential migration violation point and current information, define multiple paths to be corrected on the corresponding power rail of the equipotential migration violation point.
[0063] In detail, there are several ways to define the path to be corrected.
[0064] Please refer to Figure 4 This is a first schematic diagram in which the path to be corrected is defined in the layout schematic diagram of integrated circuit 3 according to an embodiment of the present invention.
[0065] like Figure 4 As shown, for one electromigration violation point, such as electromigration violation point em1, the side with higher current is identified based on the current information. Figure 4 For example, if the current I2 on one side of the electromigration violation point em1 is greater than the current I1 on the other side, then a first predetermined distance D1 is extended along the corresponding power rail 31 towards the side with the larger current I2 as one of the paths to be corrected 40.
[0066] Please refer to Figure 5 This is a second schematic diagram in which the path to be corrected is defined in the layout schematic diagram of integrated circuit 3 according to an embodiment of the present invention.
[0067] like Figure 5 As shown, for one electromigration violation point, such as electromigration violation point em2, the side with lower current is identified based on the current information. Figure 5 For example, if the current I2 on one side of the electromigration violation point em2 is less than the current I1 on the other side, then a second predetermined distance D2 is extended along the corresponding power rail 31 to the side with the smaller current I2 as one of the paths to be corrected 50.
[0068] Please refer to Figure 6This is a third schematic diagram in which the path to be corrected is defined in the layout schematic diagram of integrated circuit 3 according to an embodiment of the present invention.
[0069] like Figure 6 As shown, for one electromigration violation point, such as electromigration violation point em3, the first side with lower current and the second side with higher current are identified based on the current information. Figure 6 For example, if the current I1 on the first side of the electromigration violation point em3 is less than the current I2 on the second side, then a third predetermined distance D3 is extended along the corresponding power rail 31 to the first side with the smaller current I1, and a fourth predetermined distance D4 is extended along the corresponding power rail 31 to the second side with the larger current I2, as one of the paths to be corrected 60.
[0070] Step S204: Replace the types of multiple vias on the power rails that do not overlap with the path to be corrected. For example, after step S203, replace the power rails for which no path to be corrected was found, such as... Figure 5 On the power rail 31, the type of via V13 in the portion 51 corresponding to the usable area 33 is replaced. For example, the via size of via V13 can be replaced with a larger via size to guide a larger current to these areas by reducing impedance, thereby reducing the number of electromigration violations in the layout of integrated circuit 3. On the other hand, although Figure 4 Unless otherwise specified, if Figure 4 The power rail 32 is connected to a specific electromigration violation point, and the type of the guide hole V21 in part 41 of the usable area 34 can be replaced to reduce the number of electromigration violation points.
[0071] Step S205: Based on the current direction and the location of the electromigration violation point, correct the number of multiple vias on the power rails that overlap with the path to be corrected, so as to reduce the number of electromigration violation points.
[0072] In detail, this step reduces electromigration violations by adjusting the orifice density in the path to be corrected.
[0073] Therefore, with Figure 4 For example, since there is a high current on the path to be corrected 40, some or all of the vias V11 on the path to be corrected 40 are removed to divert the larger current I2 to the side with a lower current I1 by increasing the impedance, until the corresponding electromigration violation point em1 disappears, or the violation degree of the electromigration violation point em1 is reduced as much as possible, for example, the current of the electromigration violation point em1 is kept as close as possible to the set current limit and does not exceed too much.
[0074] by Figure 5For example, since the path 50 to be corrected has a low current, additional vias are added to the path 50 to be corrected, or the type of via is changed to increase the via size, so as to guide the larger current I1 to the side with the lower current I2 by reducing the impedance, until the corresponding electromigration violation point em2 disappears, or the violation degree of the electromigration violation point em2 is reduced as much as possible, for example, the current of the electromigration violation point em2 is kept as close as possible to the set current limit and does not exceed too much.
[0075] Next, with Figure 6 For example, since the first side of the path 60 to be corrected has a lower current I1 and the second side has a higher current I2, additional vias are added to the portion of the path 60 extending towards the first side, or the type of via is changed to increase the via size. Simultaneously, in the portion of the path 60 extending towards the second side, some or all of these vias V12 are removed. This is done by reducing the impedance of the low-current portion and increasing the impedance of the high-current portion, thus diverting the larger current I2 to the side with the lower current I1, until the corresponding electromigration violation point em3 disappears, or the violation degree of the electromigration violation point em3 is minimized as much as possible. It is important to note that during the via removal step, it is necessary to determine whether the via can be removed to avoid affecting the normal operation of the circuit unit 30.
[0076] Therefore, by using the above method, in addition to reducing the negative impact of electromigration on the power rail, it is not necessary to occupy the existing winding resources. Furthermore, since the usable area has passed the design rule check, it is not necessary to perform a design rule check again to correct the changes in the orifice density.
[0077] [Beneficial Effects of the Examples]
[0078] One of the beneficial effects of this invention is that the optimization method, apparatus, and non-transitory computer-readable medium for integrated circuit layout provided by this invention can detect, based on Design Rule Check (DRC) of circuit element connection relationships, whether a segment of double-layer power rails after placement and routing can adjust the via density and disperse current flow. Therefore, the negative impact of electromigration can be reduced without violating design rules.
[0079] The above-disclosed content is only a preferred embodiment of the present invention and is not intended to limit the claims of the present invention. Therefore, all equivalent technical changes made based on the description and drawings of the present invention are included within the scope of the claims of the present invention.
Claims
1. An optimization method for integrated circuit layout, comprising: In an integrated circuit design document, identify multiple power rails and their corresponding power supply domains; Design specification verification is performed on multiple circuit units generated after layout and routing in the integrated circuit design file to calculate multiple usable areas corresponding to the multiple power rails; The multiple circuit units are simulated to generate current and voltage analysis in order to determine multiple electrical migration violations and related current information corresponding to the multiple power rails; Based on the multiple electromigration violation points and the current information, multiple paths to be corrected are defined on the multiple power rails corresponding to the multiple electromigration violation points; The types of the multiple guide holes on the multiple power rails that do not overlap with the multiple paths to be corrected are replaced; as well as Based on multiple current directions and the locations of the multiple electromigration violation points, the number of multiple vias on the multiple power rails that overlap with the multiple paths to be corrected is adjusted to reduce the number of the multiple electromigration violation points.
2. The optimization method as described in claim 1, wherein, The step of changing the type of the plurality of guide holes includes replacing the plurality of guide holes with a plurality of guide holes having a larger size.
3. The optimization method as described in claim 1, wherein, The steps for defining the plurality of paths to be corrected include: For one of the electrical migration violations, the side with higher current is identified based on the current information, and a first predetermined distance is extended along the corresponding power rail to that side as one of the paths to be corrected.
4. The optimization method as described in claim 3, wherein, The step of correcting the number of the plurality of guide holes further includes removing the plurality of guide holes on the plurality of paths to be corrected.
5. The optimization method as described in claim 1, wherein, The steps for defining the plurality of paths to be corrected include: For one of the electrical migration violations, the side with lower current is identified based on the current information, and a second predetermined distance is extended along the corresponding power rail to that side as one of the paths to be corrected.
6. The optimization method as described in claim 5, wherein, The step of correcting the number of the plurality of guide holes also includes adding additional guide holes on the plurality of paths to be corrected.
7. The optimization method as described in claim 1, wherein, The steps for defining the plurality of paths to be corrected include: For one of the electromigration violations, based on the current information, a first side with lower current and a second side with higher current are identified. A third predetermined distance is extended along the corresponding power rail to the first side, and a fourth predetermined distance is extended along the corresponding power rail to the second side, as one of the paths to be corrected.
8. The optimization method as described in claim 7, wherein, The step of correcting the number of the plurality of guide holes further includes adding additional guide holes in the portion extending toward the first side and reducing the number of guide holes in the portion extending toward the second side in the plurality of paths to be corrected.
9. The optimization method as described in claim 1, wherein the current information includes multiple current directions and multiple current magnitudes of the multiple power rails corresponding to the multiple electromigration violation points.
10. An optimization apparatus for integrated circuit layout, comprising: A memory configured to store multiple computer-executable instructions; as well as A processor, electrically coupled to the memory, and configured to receive and execute the computer-executable instructions to perform an optimization method comprising: In an integrated circuit design document, identify multiple power rails and their corresponding power supply domains; Design specification verification is performed on multiple circuit units generated after layout and routing in the integrated circuit design file to calculate multiple usable areas corresponding to the multiple power rails; The multiple circuit units are simulated to generate current and voltage analysis in order to determine multiple electrical migration violations and related current information corresponding to the multiple power rails; Based on the multiple electromigration violation points and the current information, multiple paths to be corrected are defined on the multiple power rails corresponding to the multiple electromigration violation points; The types of vias on the multiple power rails that do not overlap with the multiple paths to be corrected are replaced; and Based on the current direction and the location of the multiple electromigration violation points, the number of multiple vias on the multiple power rails that overlap with the multiple paths to be corrected is adjusted to reduce the number of the multiple electromigration violation points.