An anti-four-node flip latch circuit and module based on reinforcement technology

Abstract

The present invention relates to the technical field of integrated circuit design, and more specifically, to a latch circuit for resisting four-node flips based on hardening technology, and a module encapsulated based on the latch circuit for resisting four-node flips. In the present invention, the storage nodes X0, X3, X4, X7, X8, and X11 are all surrounded by PMOS transistors to form polarity hardening, effectively avoiding flips. The present invention uses source isolation technology, so that the storage nodes X1, X2, X5, X6, X9, and X10 also only generate voltage pulses of "1-0" and "0-0", which can effectively reduce the number of sensitive nodes in the circuit and improve the circuit stability. The present invention constructs a C unit part with multi-stage inputs, which can cooperate to ensure the correct output of Q when multiple nodes are bombarded. The circuit of the present invention has complete capabilities of resisting SNU, DNU, TNU, and QNU, and has low delay, low power consumption, and small area.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and more specifically, to a quadruple-node upset resistant latch circuit based on hardening technology (which can be simply referred to as QNURDL latch), and a module encapsulated based on the quadruple-node upset resistant latch circuit. Background Art

[0002] With the progress of the world's scientific and technological level and the booming development of the aerospace industries of various countries, the on-orbit working time of spacecraft has also increased. The environment in outer space is very different from that on the earth. The most important thing is that there is no atmosphere protection in outer space. Spacecraft are exposed to various ray radiation environments for a long time, which will affect the electronic chips in its electronic equipment, causing some reactions and thus changing their working states.

[0003] The radiation environment is the biggest threat to the normal operation of spacecraft. Among them, single event upset (SEU) caused by the radiation environment is the biggest reason for spacecraft failures. However, in highly integrated nano-CMOS technology, due to charge sharing, high-energy impact particles can simultaneously change the logic states of adjacent dual nodes or even triple nodes, resulting in multiple node upsets (MNU), including dual node upset (DNU), triple node upset (TNU), and quadruple node upset (QNU).

[0004] In order to improve the ability of cells to resist multiple node upsets, the following main solutions are included in the prior art:

[0005] 1) As Figure 1 shown, a structure unit based on C cells (simply referred to as LCTNURL latch) has a total of 12 nodes, and the anti-radiation performance of the circuit is improved by interlocking different C cells. This structure has the ability to resist triple node upsets. The number of transistors used in this circuit is relatively small, so the power consumption is low. However, a fast data channel is not used to reduce the transmission delay, so the delay of this circuit is large, and this circuit does not have the ability to resist quadruple node upsets.

[0006] 2) As Figure 2 shown, a structure unit based on inverters (simply referred to as LCTNUT latch) has a total of 11 nodes, and the anti-radiation performance of the circuit is improved by interlocking different inverters. This structure has the ability to resist triple node upsets. The number of transistors used in this circuit is relatively small, so the power consumption is low, and a transmission gate is used in this circuit to reduce the transmission delay, so the delay of this circuit is small. Although the performance of this circuit is relatively excellent, it does not have the ability to resist quadruple node upsets.

[0007] 3) As Figure 3The C-cell based structural unit (abbreviated as SCLCRL latch) shown in the figure has a total of 14 nodes. By interlocking different C-cells, it improves the radiation resistance of the circuit. This structure has the ability to resist triple-node flips. The number of transistors used in this circuit is relatively small, so the power consumption is low. And this structure uses a fast data channel to reduce the transmission delay. Therefore, the circuit delay is smaller compared to Figure 1 the circuit of

[0008] 4) The C-cell based structural unit (abbreviated as LSEDUT latch) shown in Figure 4 the figure improves the resistance performance of nodes by connecting C-cells and inverters to each other, and finally outputs through multiple-stage input C-cells. This circuit uses transmission gates to reduce the circuit delay, and uses clock-controlled C-cells and inverters to reduce the competition of stored data inside the transistors in the transparent mode. Although this circuit has a small delay and has the resistance to quadruple-node flips, it uses more transistors and has a large power consumption. Summary of the Invention

[0009] Based on this, it is necessary to provide an anti-quadruple-node flip latch circuit and module based on hardening technology for the problem that existing latches cannot achieve a better match in terms of anti-node flip ability, power consumption index, area overhead, and delay index.

[0010] The present invention is implemented by the following technical solutions:

[0011] In the first aspect, the present invention provides an anti-quadruple-node flip latch circuit based on hardening technology, including an upper pull transistor part, a lower pull transistor part, an inverter one, an inverter two, a transmission transistor part, a C-cell part, and a transmission gate.

[0012] The upper pull transistor part includes 18 PMOS transistors P1 to P12, P14, P15, P18, P19, P22, P23 for pulling up storage nodes X0 to X11. The lower pull transistor part includes 6 PMOS transistors P13, P16, P17, P20, P21, P24 and 12 NMOS transistors N1 to N12 for pulling down storage nodes X0 to X11. Among them, X0, X3, X4, X7, X8, X11 are all surrounded by PMOS transistors to form polarity hardening; P2 and P14, P3 and P15, P6 and P18, P7 and P19, P10 and P22, P11 and P23 form source isolation hardening.

[0013] Inverter one includes one NMOS transistor N39 and one PMOS transistor P39, which are used to invert the input signal D into the inverted input signal DN. Inverter two includes one NMOS transistor N40 and one PMOS transistor P40, which are used to invert the clock signal CLK into the inverted clock signal CLKB.

[0014] The transmission tube part includes twelve NMOS transistors N13 to N24, all of which are connected to CLK. Among them, X0, X2, X4, X6, X8, X10 are correspondingly connected to D through N13, N15, N17, N19, N21, N23, and X1, X3, X5, X7, X9, X11 are correspondingly connected to DN through N14, N16, N18, N20, N22, N24.

[0015] The C cell part includes C cell one, C cell two, C cell three, C cell four, C cell five, and C cell six. C cell one includes two PMOS transistors P25, P26 and two NMOS transistors N25, N26, which are used to output the intermediate signal X12 according to X3 and X5. C cell two includes two PMOS transistors P27, P28 and two NMOS transistors N27, N28, which are used to output the intermediate signal X13 according to X7 and X9. C cell three includes two PMOS transistors P29, P30 and two NMOS transistors N29, N30, which are used to output the intermediate signal X14 according to X11 and X1. C cell four includes two PMOS transistors P31, P32 and two NMOS transistors N31, N32, which are used to output the intermediate signal X15 according to X12 and X13. C cell five includes two PMOS transistors P33, P34 and two NMOS transistors N33, N34, which are used to output the intermediate signal X16 according to X13 and X14. C cell six includes three PMOS transistors P35 to P37 and three NMOS transistors N35 to N37, which are used to output the output signal Q according to X15, X16, CLK, and CLKB.

[0016] The transmission gate includes one NMOS transistor N38 and one PMOS transistor P38, which are used to open or close according to CLK. When CLK = 1, the transmission gate is opened, and the anti-four-node flip latch circuit is in the transparent mode, and D is directly output as Q through the transmission gate. When CLK = 0, the transmission gate is closed, and the anti-four-node flip latch circuit is in the hold mode, and D and DN are correspondingly stored in X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, and Q is output through the C cell part.

[0017] The implementation of this anti-four-node flip latch circuit based on the reinforcement technology is based on the method or process of the embodiments of the present disclosure.

[0018] In a second aspect, the present invention discloses an anti-four-node flip latch latch module, which is encapsulated by using the anti-four-node flip latch circuit disclosed in the first aspect.

[0019] The implementation of this anti-four-node flip latch latch module is based on the method or process of the embodiments of the present disclosure.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] 1. The circuit of the present invention has complete anti-SNU, DNU, TNU, and QNU capabilities, and has low latency, low power consumption, and small area.

[0022] 2. The storage nodes X0, X3, X4, X7, X8, and X11 of the present invention are all surrounded by PMOS transistors to form polarity reinforcement. In this way, even if a space particle bombards the sensitive node PMOS transistor, only positive pulses of "1-1" and "0-1" are generated on X0, X3, X4, X7, X8, and X11, and this pulse cannot affect the states of other transistors due to the existence of the gate capacitance, effectively avoiding the flipping of X0, X3, X4, X7, X8, and X11.

[0023] 3. The present invention uses source isolation technology, so that the storage nodes X1, X2, X5, X6, X9, and X10 also only generate voltage pulses of "1-0" and "0-0", which can effectively reduce the number of sensitive nodes in the circuit and improve the circuit stability; if other non-critical nodes are bombarded by particles, then the entire circuit is less likely to be affected.

[0024] 4. The present invention constructs a multi-stage input C unit part, which effectively improves the radiation resistance of the circuit; when the inputs are the same, it is equivalent to an inverter, and the output is the inverse of the input; when the inputs are different, the output remains the same as the previous value, which can cooperate to ensure the correct output of Q when multiple nodes are bombarded. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0026] Figure 1 It is the circuit structure diagram of the LCTNURL latch mentioned in the background art of the present invention;

[0027] Figure 2It is the circuit structure diagram of the LCTNUT latch mentioned in the background art of the present invention;

[0028] Figure 3 It is the circuit structure diagram of the SCLCRL latch mentioned in the background art of the present invention;

[0029] Figure 4 It is the circuit structure diagram of the LSEDUT latch mentioned in the background art of the present invention;

[0030] Figure 5 It is the circuit structure diagram of the QNURDL latch provided in Embodiment 1 of the present invention;

[0031] Figure 6 is Figure 5 The timing waveform diagram of the QNURDL latch against single-node, double-node, and triple-node bombardment;

[0032] Figure 7 is Figure 5 The timing waveform diagram of the QNURDL latch against four-node bombardment;

[0033] Figure 8 is Figure 5 The comparison diagram of the delay time between the QNURDL latch and four other latches;

[0034] Figure 9 is Figure 5 The comparison diagram of the static power consumption between the QNURDL latch and four other latches. Detailed implementation manners

[0035] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0036] It should be noted that when a component is referred to as being "installed on" another component, it can be directly on the other component or there may also be an intermediate component. When a component is considered to be "set on" another component, it can be directly set on the other component or there may be an intermediate component at the same time. When a component is considered to be "fixed to" another component, it can be directly fixed to the other component or there may be an intermediate component at the same time.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this invention belongs. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "or / and" used herein includes any and all combinations of one or more of the related listed items.

[0038] Embodiment 1

[0039] Refer to Figure 5 , which is the circuit structure diagram of the QNURDL latch provided for this Embodiment 1. Generally speaking, the TNURH latch includes 40 NMOS transistors and 40 PMOS transistors. The 40 NMOS transistors are sequentially denoted as N1 to N40, and the 40 PMOS transistors are sequentially denoted as P1 to P40.

[0040] Functionally divided, the TNURH latch includes a pull-up transistor part, a pull-down transistor part, an inverter one, an inverter two, a transmission transistor part, a C cell part, and a transmission gate.

[0041] Among them, 18 PMOS transistors P1 to P12, P14, P15, P18, P19, P22, P23 serve as pull-up transistors to form the pull-up transistor part, pulling up the storage nodes X0 to X11. 6 PMOS transistors P13, P16, P17, P20, P21, P24 and 12 NMOS transistors N1 to N12 serve as pull-down transistors to form the pull-down transistor part, pulling down the storage nodes X0 to X11.

[0042] Specifically, the sources of P1 to P12 are connected to VDD; the sources of N1 to N12 are grounded to GND;

[0043] X0 is connected to the drain of P1, the source of P13, the gates of P2 and P4, and the source of N13;

[0044] X1 is connected to the gate of N1, the drain of P14, the drains of N2 and P15, the gates of N3, P16, the source of N14, the gate of P30, and the gate of N29;

[0045] X2 is connected to the gates of P13 and P14, the gate of N2, the drain of P15, the drains of N3 and N4, and the source of N15;

[0046] X3 is connected to the gates of P1 and P3, the drain of P4, the source of P16, the source of N16, the gate of P25, and the gate of N26;

[0047] X4 is connected to the drain of P5, the source of P17, the gates of P6 and P8, and the source of N17;

[0048] X5 connects to the gate of N5, the drain of P18, the drain of N6, the gate of P19, the gate of N7, the gate of P20, the source of N18, the gate of P26, and the gate of N25;

[0049] X6 connects to the gate of P17, the gate of P18, the gate of N6, the drain of P19, the drain of N7, the gate of N8, and the source of N19;

[0050] X7 connects to the gate of P5, the gate of P7, the drain of P8, the source of P20, the source of N20, the gate of P27, and the gate of N28;

[0051] X8 connects to the drain of P9, the source of P21, the gate of P10, the gate of P12, and the source of N21;

[0052] X9 connects to the gate of N9, the drain of P22, the drain of N10, the gate of P23, the gate of N11, the gate of P24, the source of N22, the gate of P28, and the gate of N27;

[0053] X10 connects to the gate of P21, the gate of P22, the gate of N10, the drain of P23, the drain of N11, the gate of N12, and the source of N23;

[0054] X11 connects to the gate of P9, the gate of P11, the drain of P12, the source of P24, the source of N24, the gate of P29, and the gate of N30.

[0055] The pull-up transistor section and the pull-down transistor section form a storage section, which can be divided into three storage sub-units with the same structure, as Figure 5 shown: X0 to X3 are in the first storage sub-unit, X4 to X7 are in the second storage sub-unit, and X8 to X11 are in the third storage sub-unit.

[0056] The above adopts polarity reinforcement and source isolation reinforcement:

[0057] X0, X3, X4, X7, X8, and X11 are all surrounded by PMOS transistors to form polarity reinforcement, more specifically called a P-type polarity reinforcement structure. According to the polarity reinforcement principle, when space particles bombard the sensitive node PMOS transistors, only "1-1" and "0-1" voltage pulses are generated on X0, X3, X4, X7, X8, and X11, that is, only positive pulses are generated, and due to the existence of the gate capacitance, this pulse cannot affect the states of other transistors, effectively preventing X0, X3, X4, X7, X8, and X11 from flipping.

[0058] P2 and P14 are stacked, that is, the top PMOS transistor is isolated from the underlying PMOS transistor using shallow trench isolation technology to form source isolation reinforcement. Similarly, source isolation reinforcement is also formed for P3 and P15, P6 and P18, P7 and P19, P10 and P22, P11 and P23. Only "1-0" and "0-0" voltage pulses are generated on X1, X2, X5, X6, X9, X10, that is, only negative pulses are generated, and due to the existence of gate capacitance, this pulse cannot affect the states of other transistors, effectively preventing X1, X2, X5, X6, X9, X10 from flipping.

[0059] One NMOS transistor N39 and one PMOS transistor P39 form inverter one, which is used to invert the input signal D into the inverted input signal DN; one NMOS transistor N40 and one PMOS transistor P40 form inverter two, which is used to invert the clock signal CLK into the inverted clock signal CLKB.

[0060] Specifically, the source of P39 is connected to VDD, the gate is connected to D, and the drain is connected to DN; the source of N39 is grounded to GND, the gate is connected to the gate of P39, and the drain is connected to the drain of P39. The source of P40 is connected to VDD, the gate is connected to CLK, and the drain is connected to CLKB; the source of N40 is grounded to GND, the gate is connected to the gate of P40, and the drain is connected to the drain of P40.

[0061] Twelve NMOS transistors N13 to N24 form a transmission tube section. N13 to N24 are all connected to CLK. X0, X2, X4, X6, X8, X10 are correspondingly connected to D through N13, N15, N17, N19, N21, N23, and X1, X3, X5, X7, X9, X11 are correspondingly connected to DN through N14, N16, N18, N20, N22, N24.

[0062] Specifically, the drain of N13 is connected to D, the gate is connected to CLK, and the source is connected to X0; the drain of N14 is connected to DN, the gate is connected to CLK, and the source is connected to X1; the drain of N15 is connected to D, the gate is connected to CLK, and the source is connected to X2; the drain of N16 is connected to DN, the gate is connected to CLK, and the source is connected to X3; the drain of N17 is connected to D, the gate is connected to CLK, and the source is connected to X4; the drain of N18 is connected to DN, the gate is connected to CLK, and the source is connected to X5; the drain of N19 is connected to D, the gate is connected to CLK, and the source is connected to X6; the drain of N20 is connected to DN, the gate is connected to CLK, and the source is connected to X7; the drain of N21 is connected to D, the gate is connected to CLK, and the source is connected to X8; the drain of N22 is connected to DN, the gate is connected to CLK, and the source is connected to X9; the drain of N23 is connected to D, the gate is connected to CLK, and the source is connected to X10; the drain of N24 is connected to DN, the gate is connected to CLK, and the source is connected to X11.

[0063] The C cell section includes six C cells. Among them, two PMOS transistors P25, P26, two NMOS transistors N25, N26 form C cell one (abbreviated as CE1), which is used to output the intermediate signal X12 according to X3 and X5. Two PMOS transistors P27, P28, two NMOS transistors N27, N28 form C cell two (abbreviated as CE2), which is used to output the intermediate signal X13 according to X7 and X9. Two PMOS transistors P29, P30, two NMOS transistors N29, N30 form C cell three (abbreviated as CE3), which is used to output the intermediate signal X14 according to X11 and X1. Two PMOS transistors P31, P32, two NMOS transistors N31, N32 form C cell four (abbreviated as CE4), which is used to output the intermediate signal X15 according to X12 and X13. Two PMOS transistors P33, P34, two NMOS transistors N33, N34 form C cell five (abbreviated as CE5), which is used to output the intermediate signal X16 according to X13 and X14. Three PMOS transistors P35 to P37, three NMOS transistors N35 to N37 form C cell six (abbreviated as CE6), which is used to output the output signal Q according to X15, X16, CLK, and CLKB.

[0064] When the input values of the C cell are the same, the C cell acts as an inverter: that is, when all the input values of the C cell are the same, its output value is the inverse of the input value. However, when the input values of the C cell change, its output can temporarily hold the previous value (enter the high-impedance state). This means that if the change in the input value of the C cell is caused by an error, the C cell can intercept this error.

[0065] The specific connection relationship of the C cell section is as follows:

[0066] The source of P25 is connected to VDD, and the gate is connected to X3; the source of P26 is connected to the drain of P25, the gate is connected to X5, and the drain is connected to X12; the drain of N25 is connected to the drain of P26, and the gate is connected to the gate of P26; the source of N26 is connected to GND, the gate is connected to the gate of P25, and the drain is connected to the source of N25.

[0067] The source of P27 is connected to VDD, and the gate is connected to X7; the source of P28 is connected to the drain of P27, the gate is connected to X9, and the drain is connected to X13; the drain of N27 is connected to the drain of P28, and the gate is connected to the gate of P28; the source of N28 is connected to GND, the gate is connected to the gate of P27, and the drain is connected to the source of N27.

[0068] The source of P29 is connected to VDD, and the gate is connected to X11; the source of P30 is connected to the drain of P29, the gate is connected to X1, and the drain is connected to X14; the drain of N29 is connected to the drain of P30, and the gate is connected to the gate of P30; the source of N30 is connected to GND, the gate is connected to the gate of P29, and the drain is connected to the source of N29.

[0069] The source of P31 is connected to VDD, and the gate is connected to X12; the source of P32 is connected to the drain of P31, the gate is connected to X13, and the drain is connected to X15; the drain of N31 is connected to the drain of P32, and the gate is connected to the gate of P32; the source of N32 is connected to GND, the gate is connected to the gate of P31, and the drain is connected to the source of N31.

[0070] The source of P33 is connected to VDD, and the gate is connected to X13; the source of P34 is connected to the drain of P33, the gate is connected to X14, and the drain is connected to X16; the drain of N33 is connected to the drain of P34, and the gate is connected to the gate of P34; the source of N34 is connected to GND, the gate is connected to the gate of P33, and the drain is connected to the source of N33.

[0071] The source of P35 is connected to VDD, and the gate is connected to X15; the source of P36 is connected to the drain of P35, and the gate is connected to X16; the source of P37 is connected to the drain of P36, the gate is connected to CLK, and the drain is connected to Q; the drain of N35 is connected to the drain of P37, and the gate is connected to CLKB; the gate of N36 is connected to the gate of P36, and the drain is connected to the source of N35; the source of N37 is connected to GND, the gate is connected to the gate of P35, and the drain is connected to the source of N36.

[0072] One NMOS transistor N38 and one PMOS transistor P38 form a transmission gate, which is used to open or close according to CLK, so as to reduce the delay from D to Q:

[0073] Specifically, the gate of N38 is connected to CLK, the drain is connected to D, and the source is connected to Q; the gate of P38 is connected to CLKB, the drain is connected to the source of N38, and the source is connected to the drain of N38.

[0074] When CLK = 1, the transmission gate is open, and the QNURDL latch is in transparent mode. D is directly output as Q through the transmission gate. Therefore, P19 and N17 are closed at this time. Taking D = 0 as an example, when X0 = X2 = X4 = X6 = X8 = X10 = 0 and X1 = X3 = X5 = X7 = X9 = X11 = 1, P2, P4, P6, P8, P10, P12, P13, P14, P17, P18, P21, P22, N1, N3, N5, N7, N9, N11 are opened, and P1, P3, P5, P7, P9, P11, P15, P16, P19, P20, P23, P24, N2, N4, N6, N8, N10, N12 are closed. Therefore, the feedback loop is quickly established, and these internal nodes can be latched, so that the internal storage nodes keep these stored values unchanged unless D rises to 1.

[0075] When CLK = 0, the transmission gate is closed, and the QNURDL latch is in hold mode. D and DN are correspondingly stored in X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, and output as Q through the C cell part. N13 - N24 are closed, and no new values are written to the transmission tube part. Therefore, the internal nodes keep the previous stored values unchanged, and the path from D to Q is interrupted. The C cell part is enabled, and the corresponding stored values are output to Q through the C cell part. Therefore, the latched value on Q will be retained until the next transparent mode occurs.

[0076] The bombardment occurs in the hold mode (CLK = 0, CLKB = 1, at this time P37 and N35 in CE6 are opened). Generally speaking, when the storage nodes are bombarded, the QNURDL latch either restores the storage nodes or, even if some storage nodes cannot be restored, performs fault tolerance through the function of the C cell part (mainly CE1, CE2, CE3, CE4, CE5 perform fault tolerance) to ensure the correct output of Q.

[0077] Generally speaking, the three storage sub-units corresponding to X0 - X11 are the same. Therefore, the sensitivity of the internal storage nodes corresponding to each storage sub-unit will also be the same. Therefore, X0 - X11 belong to the same type of storage nodes - internal storage nodes. X12 - X14 are all generated by the internal storage nodes, so these three nodes belong to the same type of storage nodes - intermediate storage nodes. X15 and X16 are generated by the intermediate storage nodes, so these two nodes belong to the same type of storage nodes - regenerated storage nodes. Q is a separate type of node - output node.

[0078] In this Embodiment 1, the gate length of all MOS transistors is 65 nm, and the gate widths of P13, P16, P17, P20, P21, P24, N1, N4, N5, N8, N9, and N12 are all 420 nm, while the gate widths of all the remaining MOS transistors are 140 nm.

[0079] Regarding the anti - flip ability of the QNURDL latch, taking the stored data X0 = X2 = X4 = X6 = X8 = X10 = 0, X1 = X3 = X5 = X7 = X9 = X11 = 1 as an example: P2, P4, P6, P8, P10, P12, P13, P14, P17, P18, P21, P22, N1, N3, N5, N7, N9, N11 are turned on, and P1, P3, P5, P7, P9, P11, P15, P16, P19, P20, P23, P24, N2, N4, N6, N8, N10, N12 are turned off. In this state, the QNURDL latch has a total of 12 sensitive nodes, namely X0, X1, X4, X5, X8, X9, X12, X13, X14, X15, X16, Q.

[0080] (1) Bombard X0, X1, X4, X5, X8, X9, X12, X13, X14, X15, X16, Q separately, a total of 12 cases, which can be divided into four major categories according to the node type. The results show that recovery can be achieved in all cases, so the correct output of Q can be guaranteed. It shows that the TNURH latch can completely resist SNU.

[0081] Category 1.1: That is, the internal storage node is bombarded.

[0082] Taking X0 as an example, when X0 is bombarded and flips from "0" to "1", it will cause P2 and P4 to turn off. However, since the states of the pull - up transistor P15 and the pull - down transistor N3 of X2 will not change, the stored value of X2 will not change. Considering X1, the states of the pull - up transistor P14 and the pull - down transistor N2 of the X1 node will not change, so the stored value of X1 will not be affected. Similarly, the states of the pull - down transistor P16 and N4 of X3 will not change, so the state of X3 will not change. Therefore, the pull - up transistor P1 of X0 remains off, the pull - down transistors P13 and N1 of X0 remain on, and X0 will discharge through the pull - down transistors P13 and N1 and return to the correct logic value "0", and this error will not affect the correctness of the output Q value.

[0083] Taking X1 as an example, when X1 is bombarded and flipped from "1" to "0", it will cause P15 and P16 to open and N1 and N3 to close. However, the states of other pull-up and pull-down transistors such as X0, X2, and X3 do not change. Therefore, the values of these three storage nodes do not change. Then, the pull-down transistor N2 of X1 remains closed, and the pull-up transistors P2 and P14 of X1 remain open. X1 will return from the incorrect value "0" to the correct value "1".

[0084] Similar situations will not be elaborated further.

[0085] Category 1.2: The intermediate storage node is bombarded.

[0086] Taking X12 as an example, when X12 is bombarded and flipped from "0" to "1", this error will not affect the values of other nodes. The inputs X3 and X5 of X12 do not have incorrect flips. Therefore, X12 will be pulled back to the correct logical value "0" by X3 and X5. So, this error has no effect on the output Q value either.

[0087] Similar situations will not be elaborated further.

[0088] Category 1.3: The regenerated storage node is bombarded.

[0089] Taking X15 as an example, when X15 is flipped from "1" to "0", this error will not affect other nodes. The inputs X12 and X13 of X15 do not have incorrect flips. Therefore, X15 will be pulled back to the correct logical value "1" by X12 and X13. So, this error has no effect on the output Q value either.

[0090] Similar situations will not be elaborated further.

[0091] Category 1.4: The output node is bombarded. When Q is bombarded and flipped from "0" to "1", this error will not affect the values of other nodes. The inputs X15 and X16 of Q do not have incorrect flips. Therefore, Q will be pulled back to the correct logical value "0" by X15 and X16. So, even if SNU occurs at Q, it will be pulled back to the correct output value by other nodes.

[0092] As Figure 6 shown, the above four categories of situations are presented, as shown in Table 1 specifically.

[0093] Table 1 Situations after a single node is bombarded

[0094]

[0095] (2) As Figure 6As shown, bombarding any two points among X0, X1, X4, X5, X8, X9, X12, X13, X14, X15, X16, and Q results in 66 cases, which can be divided into three major categories. The results show that recovery can be achieved in all cases, thus ensuring the correct output of Q. This indicates that the TNURH latch can completely resist DNU.

[0096] For ease of explanation, the intermediate storage node, the regenerated storage node, and the output node are collectively referred to as external nodes.

[0097] Category 2.1: Two internal storage nodes are flipped, and the external nodes are not flipped.

[0098] Category 2.1 is divided into two sub-categories:

[0099] The first case is that the two nodes are within the same storage sub-unit. In this case, the internally flipped nodes cannot be restored. However, since the entire circuit outputs through the C unit part, it will not cause an incorrect flip of the output Q. Taking the flip of the <X0, X1> node pair as an example, when X0 flips from "0" to "1" and X1 flips from "1" to "0", it will cause the internal logic of the first storage sub-unit where X0 and X1 are located to be disordered, and the two nodes cannot restore the correct value. But due to the interception of the error by CE1 - CE6, this error will not be transmitted to Q, so Q still maintains the correct logical value. Similar cases will not be elaborated further.

[0100] The second case is that the two nodes are in two different storage sub-units. Since the storage sub-unit can resist any single-node flip, the flipped nodes in this case can be self-restored through the internal circuit, and it will not affect the correctness of the output node Q either.

[0101] Category 2.2: One internal storage node is flipped and one external node is flipped.

[0102] Taking the flip of the <X0, X12> node pair as an example, assuming X0 flips from "0" to "1" and X12 flips from "0" to "1", through the analysis of resisting SNU, it can be known that the flip of X0 can be self-restored and will not cause the logical disorder of other storage nodes. X12 is controlled by X3 and X5, and these two nodes have not flipped, so they will pull the already flipped X12 back from the incorrect "1" to the correct "0". Therefore, the flip of these two nodes will not transmit the error value to Q, and Q still maintains the correct logical value. Similar cases will not be elaborated further.

[0103] Category 2.3: The internal storage nodes are not flipped, and two external nodes are flipped.

[0104] Taking the flip of the <X12, X13> node pair as an example, assume that X12 flips from "0" to "1" and X13 flips from "0" to "1". These two nodes are the input node pair of CE4, and their flip will cause the logical value of X15 to also flip. However, since there is one input value that does not have a logical error in the inputs of CE5 and CE6 respectively, the outputs of these two C units will not have an error. That is, the incorrect flip of this node pair will not be transmitted to Q, and Q will still maintain the correct output. Moreover, X12 and X13 are controlled by X3, X5 and X7, X9 respectively, and their inputs do not have an error, so the correct input values will pull them back to the correct logical values.

[0105] As Figure 6 shown, the above three major categories of situations are presented, as shown in Table II specifically.

[0106] Table II Situations after Double Nodes are Bombarded

[0107]

[0108]

[0109] (3) As Figure 6 shown, bombarding any three points among X0, X1, X4, X5, X8, X9, X12, X13, X14, X15, X16, Q results in 220 situations, which are divided into four major categories. The results show that recovery can be achieved in all cases, so the correct output of Q can be guaranteed. This indicates that the TNURH latch can be completely resistant to TNU.

[0110] For the convenience of explanation, the intermediate storage nodes, the regenerated storage nodes, and the output nodes are collectively referred to as external nodes.

[0111] Category 3.1: Three internal storage nodes flip, and the external nodes do not flip.

[0112] Category 3.1 is divided into two sub-categories:

[0113] The first is that the three flipped nodes are in two storage sub-units. Taking <X0, X1, X4> as an example, assume that X0 flips from "0" to "1", X1 flips from "1" to "0", and X4 flips from "0" to "1". Then, in the first storage sub-unit where X0 and X1 are located, the two sensitive nodes flip together, and the unit cannot recover itself internally. In the second storage sub-unit where X4 is located, only one sensitive node flips, and the unit can recover itself internally. However, since the output depends on the C unit part to block errors, whether it recovers or not, this error will ultimately be filtered by the C unit part and will not affect the correctness of Q. Similar situations will not be elaborated further.

[0114] The second case is that the three flip nodes are located in three storage sub-units. Taking <X0, X4, X8> as an example, assuming that X0 flips from "0" to "1", X4 flips from "0" to "1", and X8 flips from "0" to "1", then the three flip nodes can all perform self-recovery in their respective storage sub-units, and finally it will not affect the correctness of Q. Similar cases will not be elaborated further.

[0115] Class 3.2: Two internal storage nodes flip and one external node flips.

[0116] Among them, there are also two sub-categories for the flipping of two internal storage nodes, which have been described in the anti-DNU, and will not be repeated here. Only one of the cases will be taken as an example:

[0117] Taking <X0, X1, X12> as an example, assuming that X0 flips from "0" to "1", X1 flips from "1" to "0", and X12 flips from "0" to "1". Since X0 and X1 are in the same first storage sub-unit and flip simultaneously, these two nodes cannot perform self-recovery inside the first storage sub-unit. And X12 is jointly controlled by X3 and X5, and these two nodes do not flip, so X12 will be pulled back to the correct value. Due to the role of the C unit part, the wrong value of X1 will not affect the correctness of X14, so the error of the entire circuit will not be transmitted to Q, that is, the entire circuit maintains the correct Q. Similar cases will not be elaborated further.

[0118] Class 3.3: One internal storage node flips and two external nodes flip.

[0119] Taking <X0, X12, X13> as an example, assuming that X0 flips from "0" to "1", X12 flips from "0" to "1", and X13 flips from "0" to "1". Through the SNU resistance analysis, it can be seen that the flip of X0 occurs within the first storage sub-unit and can perform self-recovery, while the inputs of X12 and X13 do not flip, so X12 and X13 will be pulled back to the correct values by the correct inputs, and the wrong values will not be transmitted to Q, so the entire circuit will maintain the correct Q. Similar cases will not be elaborated further.

[0120] Class 3.4: No internal storage node flips and three external nodes flip.

[0121] Taking <X12, X13, X14> as an example, assuming that X12 flips from "0" to "1", X13 flips from "0" to "1", and X14 flips from "0" to "1", this node group serves as the full input for CE4 and CE5, which will cause X15 and X16 to flip, and finally cause Q to flip. However, since all the input values of this node group have incorrect flips, this node group will be pulled back to the correct logic value by the correct input, successively pulling the flipped X15 and X16 back to the correct values, and then pulling Q back to the correct value. Therefore, the output of Q remains correct. Similar situations will not be elaborated further.

[0122] As Figure 6 shown, the above four major categories of situations are presented, as shown in Table III specifically.

[0123] Table III Situations after the three-node is bombarded

[0124]

[0125] (4) Bombarding any four points among X0, X1, X4, X5, X8, X9, X12, X13, X14, X15, X16, and Q results in 495 situations, which are divided into five major categories. The results show that recovery can be achieved in all cases, thus ensuring the correct output of Q. This indicates that the TNURH latch can fully resist QNU.

[0126] For the convenience of explanation, the intermediate storage node, the regenerated storage node, and the output node are collectively referred to as external nodes.

[0127] Category 4.1: Four internal storage nodes flip, and the external nodes do not flip.

[0128] Category 4.1 is divided into two sub-categories:

[0129] The first is that the four flipped nodes are located in two storage sub-units. Taking <X0, X1, X4, X5> as an example, assuming that X0 flips from "0" to "1", X1 flips from "1" to "0", X4 flips from "0" to "1", and X5 flips from "1" to "0", then there are two sensitive nodes flipping in each storage sub-unit, and the node values cannot be restored within the unit. However, since Q is based on the output of the C unit part, the internal error values will be intercepted by the C unit part and will not be transmitted to Q, and Q maintains the correct output. Similar situations will not be elaborated further.

[0130] The second case is that the four flip nodes are located in three storage sub-units. Taking <X0, X1, X4, X8> as an example, assuming that X0 flips from "0" to "1", X1 flips from "1" to "0", X4 flips from "0" to "1", and X8 flips from "0" to "1", then there are two sensitive nodes flipping simultaneously in the first storage sub-unit where X0 and X1 are located, and self-recovery cannot be performed internally. While in the second storage sub-unit where X4 is located and the third storage sub-unit where X8 is located, only one sensitive node flips, so self-recovery can be performed internally. The flip errors that cannot be recovered internally will be intercepted by the multi-stage input C cell part, and the error value will not be passed to Q, and Q maintains the correct output. Other similar situations will not be elaborated here.

[0131] Class 4.2: Three internal storage node flips and one external node flip.

[0132] For the case of three internal storage node flips, refer to Class 3.1, which will not be repeated here. Only take one case as an example:

[0133] Taking <X0, X1, X4, X12> as an example, assuming that X0 flips from "0" to "1", X1 flips from "1" to "0", X4 flips from "0" to "1", and X12 flips from "0" to "1". Since X0 and X1 are in the first storage sub-unit and flip simultaneously, these two nodes cannot perform self-recovery inside the first storage sub-unit. In the second storage sub-unit where X4 is located, only one sensitive node flips, so self-recovery can be performed inside the second storage sub-unit. X12 is controlled by X3 and X5, and these two nodes do not flip, so X12 will be pulled back to the correct value. Due to the obstruction of the multi-stage input C cell part, the errors that cannot be recovered internally will not be output to Q, so the output of Q is still correct. Other similar situations will not be elaborated here.

[0134] Class 4.3: Two internal storage node flips and two external node flips.

[0135] For the case of two internal storage node flips, refer to Class 2.1, which will not be repeated here. Only take one case as an example:

[0136] Taking <X0, X1, X12, X13> as an example, assuming that X0 flips from "0" to "1", X1 flips from "1" to "0", X12 flips from "0" to "1", and X13 flips from "0" to "1". Since X0 and X1 are in the same storage sub-unit and flip simultaneously, these two nodes cannot perform self-recovery inside the storage sub-unit. The inputs X3 and X5 of X12 and the outputs X7 and X9 of X13 do not have errors, so these two nodes will be pulled back to the correct value by the correct input values, and finally Q will also maintain the correct output. Other similar situations will not be elaborated here.

[0137] Class 4.4: One internal storage node flips, and three external nodes flip.

[0138] Taking <X0, X12, X13, X14> as an example, X12, X13, and X14 are used as the full inputs of CE4 and CE5, which will cause X15 and X16 to flip, and finally cause Q to flip. However, through the SNU resistance analysis, it can be known that the flip of X0 occurs within the first storage subunit and can be self-recovered without affecting the correct values of other nodes, that is, all the inputs of X12 to X14 are correct values. Therefore, X12 to X14 will be pulled back to the correct logic values by the correct inputs, and the flipped X15 and X16 will be pulled back to the correct values in turn, and then Q will be pulled back to the correct value. So the output of Q is still correct. Other similar situations will not be elaborated here.

[0139] Class 4.5: The internal storage node does not flip, and four external nodes flip.

[0140] Taking <X12, X13, X14, X15> as an example, assuming that X12 flips from "0" to "1", X13 flips from "0" to "1", X14 flips from "0" to "1", and X15 flips from "1" to "0". Although the flip will cause Q to flip at the beginning, since the inputs of CE1 to CE3 have not flipped, X12, X13, X14, X15, and X16 will be pulled back to the correct values in turn, and finally Q will also output correctly.

[0141] As Figure 7 shown, the above five major categories of situations are shown, as specifically shown in Table IV.

[0142] Table IV Conditions after the four nodes are bombarded

[0143]

[0144]

[0145] In addition, the inventor also carried out simulation comparisons between the TNURH latch and the four latches proposed in the background technology.

[0146] First, referring to Table V, it is a comparison table of anti-flip capabilities.

[0147] Table V Comparison table of anti-flip capabilities

[0148]

[0149]

[0150] Obviously, only the LSEDUT latch and the QNURDL latch have complete anti-SNU / DNU / TNU / QNU capabilities. However, a total of 100 MOS transistors are required to build the LSEDUT latch, while the TNURH latch only requires 80 MOS transistors, and the area overhead is significantly reduced.

[0151] Then, referring to Figure 8 , the delay of the QNURDL latch is close to that of the LSEDUT latch, slightly greater than that of the LCTNUT latch, and much smaller than that of the LCTNURL latch and the SCLCRL latch. This shows that the QNURDL latch has the advantage of low delay while having complete anti-SNU / DNU / TNU / QNU capabilities.

[0152] Referring again to Figure 9 , although the power consumption of the QNURDL latch is greater than that of the LCTNURL latch, the LCTNUT latch, and the SCLCRL latch, it is lower than that of the LSEDUT latch. This shows that the QNURDL latch has the advantage of low power consumption while having complete anti-SNU / DNU / TNU / QNU capabilities.

[0153] In addition, the delay-power product of the LSEDUT latch and the QNURDL latch was compared: the delay-power product of the LSEDUT latch is 6.58181, and the delay-power product of the QNURDL latch is 5.89107. It can be seen that a part of the delay sacrificed by the QNURDL latch can result in a greater reduction in power consumption. Therefore, the QNURDL latch also has an advantage compared to the LSEDUT latch.

[0154] Embodiment 2

[0155] This Embodiment 2 discloses an anti-four-node flip latch module, which is encapsulated by the anti-four-node flip latch circuit of Embodiment 1. The encapsulation into a module mode makes it easier to promote and apply the above anti-four-node flip latch circuit.

[0156] The pins of the anti-four-node flip latch module include 5 pins: the first pin, the second pin, the third pin, the fourth pin, and the fifth pin.

[0157] The first pin is used to connect to VDD. Specifically, the first pin connects to the sources of P1 to P12.

[0158] The second pin is used to connect to GND. Specifically, the second pin connects to the sources of N1 to N12.

[0159] The third pin is used for inputting the clock signal CLK. Specifically, the third pin is connected to the gates of N38, P40, N40, P37, and N13 to N24.

[0160] The fourth pin is used for inputting the input signal D. Specifically, the fourth pin is connected to the drain of N38 and the source of P38; the fourth pin is connected to the gates of P39 and N39; the fourth pin is connected to the sources of N13, N15, N17, N19, N21, and N23.

[0161] The fifth pin is used for outputting the output signal Q. Specifically, the fifth pin is connected to the drains of P37 and N35.

[0162] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0163] The above-described embodiments only represent several implementation manners of the present invention, and the description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the invention patent should be subject to the appended claims.

Claims

1. An anti-four-node flip latch circuit based on reinforcement technology, characterized in that, it includes: The pull-up transistor part, which includes 18 PMOS transistors P1~P12, P14, P15, P18, P19, P22, P23, and is used to pull up the storage nodes X0~X11; The pull-down transistor part, which includes 6 PMOS transistors P13, P16, P17, P20, P21, P24 and 12 NMOS transistors N1~N12, and is used to pull down the storage nodes X0~X11; Among them, X0, X3, X4, X7, X8, X11 are all surrounded by PMOS transistors to form polarity reinforcement; P2 and P14, P3 and P15, P6 and P18, P7 and P19, P10 and P22, P11 and P23 form source isolation reinforcement; The first inverter, which includes 1 NMOS transistor N39 and 1 PMOS transistor P39, and is used to invert the input signal D into the inverted input signal DN; The second inverter, which includes 1 NMOS transistor N40 and 1 PMOS transistor P40, and is used to invert the clock signal CLK into the inverted clock signal CLKB; The transmission transistor part, which includes 12 NMOS transistors N13~N24, all connected to CLK; among them, X0, X2, X4, X6, X8, X10 are correspondingly connected to D through N13, N15, N17, N19, N21, N23, and X1, X3, X5, X7, X9, X11 are correspondingly connected to DN through N14, N16, N18, N20, N22, N24; The C cell part, which includes C cell one, C cell two, C cell three, C cell four, C cell five, C cell six; the C cell one includes 2 PMOS transistors P25, P26, 2 NMOS transistors N25, N26, and is used to output the intermediate signal X12 according to X3, X5; the C cell two includes 2 PMOS transistors P27, P28, 2 NMOS transistors N27, N28, and is used to output the intermediate signal X13 according to X7, X9; the C cell three includes 2 PMOS transistors P29, P30, 2 NMOS transistors N29, N30, and is used to output the intermediate signal X14 according to X11, X1; the C cell four includes 2 PMOS transistors P31, P32, 2 NMOS transistors N31, N32, and is used to output the intermediate signal X15 according to X12, X13; the C cell five includes 2 PMOS transistors P33, P34, 2 NMOS transistors N33, N34, and is used to output the intermediate signal X16 according to X13, X14; the C cell six includes 3 PMOS transistors P35~P37, 3 NMOS transistors N35~N37, and is used to output the output signal Q according to X15, X16, CLK, CLKB; and A transmission gate, which includes one NMOS transistor N38 and one PMOS transistor P38, and is used to be opened or closed according to CLK; when CLK = 1, the transmission gate is opened, and the anti-four-node flip latch circuit is in transparent mode, and D is directly output as Q through the transmission gate; when CLK = 0, the transmission gate is closed, and the anti-four-node flip latch circuit is in hold mode, and D and DN are respectively stored into X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, and output as Q through the C cell part.

2. The anti-four-node flip latch circuit based on hardening technology according to claim 1, characterized in that, the sources of P1~P12 are connected to VDD; the sources of N1~N12 are grounded to GND; X0 is connected to the drain of P1, the source of P13, the gate of P2, the gate of P4, and the source of N13; X1 is connected to the gate of N1, the drain of P14, the drain of N2, the gate of P15, the gate of N3, the gate of P16, the source of N14, the gate of P30, and the gate of N29; X2 is connected to the gate of P13, the gate of P14, the gate of N2, the drain of P15, the drain of N3, the gate of N4, and the source of N15; X3 is connected to the gate of P1, the gate of P3, the drain of P4, the source of P16, the source of N16, the gate of P25, and the gate of N26; X4 is connected to the drain of P5, the source of P17, the gate of P6, the gate of P8, and the source of N17; X5 is connected to the gate of N5, the drain of P18, the drain of N6, the gate of P19, the gate of N7, the gate of P20, the source of N18, the gate of P26, and the gate of N25; X6 is connected to the gate of P17, the gate of P18, the gate of N6, the drain of P19, the drain of N7, the gate of N8, and the source of N19; X7 is connected to the gate of P5, the gate of P7, the drain of P8, the source of P20, the source of N20, the gate of P27, and the gate of N28; X8 is connected to the drain of P9, the source of P21, the gate of P10, the gate of P12, and the source of N21; X9 is connected to the gate of N9, the drain of P22, the drain of N10, the gate of P23, the gate of N11, the gate of P24, the source of N22, the gate of P28, and the gate of N27; X10 is connected to the gate of P21, the gate of P22, the gate of N10, the drain of P23, the drain of N11, the gate of N12, and the source of N23; X11 is connected to the gate of P9, the gate of P11, the drain of P12, the source of P24, the source of N24, the gate of P29, and the gate of N30.

3. The anti-four-node flip latch circuit based on hardening technology according to claim 2, characterized in that, the source of P39 is connected to VDD, the gate is connected to D, and the drain is connected to DN; the source of N39 is grounded to GND, the gate is connected to the gate of P39, and the drain is connected to the drain of P39.

4. The anti-four-node flip latch circuit based on the reinforcement technology according to claim 3, characterized in that, the source of P40 is connected to VDD, the gate is connected to CLK, and the drain is connected to CLKB; the source of N40 is grounded to GND, the gate is connected to the gate of P40, and the drain is connected to the drain of P40.

5. The anti-four-node flip latch circuit based on the reinforcement technology according to claim 4, characterized in that, the drain of N13 is connected to D, and the gate is connected to CLK; the drain of N14 is connected to DN, and the gate is connected to CLK; the drain of N15 is connected to D, and the gate is connected to CLK; the drain of N16 is connected to DN, and the gate is connected to CLK; the drain of N17 is connected to D, and the gate is connected to CLK; the drain of N18 is connected to DN, and the gate is connected to CLK; the drain of N19 is connected to D, and the gate is connected to CLK; the drain of N20 is connected to DN, and the gate is connected to CLK; the drain of N21 is connected to D, and the gate is connected to CLK; the drain of N22 is connected to DN, and the gate is connected to CLK; the drain of N23 is connected to D, and the gate is connected to CLK; the drain of N24 is connected to DN, and the gate is connected to CLK.

6. The anti-four-node flip latch circuit based on the reinforcement technology according to claim 4, characterized in that, the source of P25 is connected to VDD, and the gate is connected to X3; the source of P26 is connected to the drain of P25, the gate is connected to X5, and the drain is connected to X12; the drain of N25 is connected to the drain of P26, and the gate is connected to the gate of P26; the source of N26 is connected to GND, the gate is connected to the gate of P25, and the drain is connected to the source of N25; the source of P27 is connected to VDD, and the gate is connected to X7; the source of P28 is connected to the drain of P27, the gate is connected to X9, and the drain is connected to X13; the drain of N27 is connected to the drain of P28, and the gate is connected to the gate of P28; the source of N28 is connected to GND, the gate is connected to the gate of P27, and the drain is connected to the source of N27; the source of P29 is connected to VDD, and the gate is connected to X11; the source of P30 is connected to the drain of P29, the gate is connected to X1, and the drain is connected to X14; the drain of N29 is connected to the drain of P30, and the gate is connected to the gate of P30; the source of N30 is connected to GND, the gate is connected to the gate of P29, and the drain is connected to the source of N29; the source of P31 is connected to VDD, and the gate is connected to X12; the source of P32 is connected to the drain of P31, the gate is connected to X13, and the drain is connected to X15; the drain of N31 is connected to the drain of P32, and the gate is connected to the gate of P32; the source of N32 is connected to GND, the gate is connected to the gate of P31, and the drain is connected to the source of N31; the source of P33 is connected to VDD, and the gate is connected to X13; the source of P34 is connected to the drain of P33, the gate is connected to X14, and the drain is connected to X16; the drain of N33 is connected to the drain of P34, and the gate is connected to the gate of P34; the source of N34 is connected to GND, the gate is connected to the gate of P33, and the drain is connected to the source of N33; The source of P35 is connected to VDD, and the gate is connected to X15; the source of P36 is connected to the drain of P35, and the gate is connected to X16; the source of P37 is connected to the drain of P36, the gate is connected to CLK, and the drain is connected to Q; the drain of N35 is connected to the drain of P37, and the gate is connected to CLKB; the gate of N36 is connected to the gate of P36, and the drain is connected to the source of N35; The source of N37 is connected to GND, the gate is connected to the gate of P35, and the drain is connected to the source of N36.

7. The anti-four-node flip latch circuit based on the hardening technology according to claim 6, characterized in that, The gate of N38 is connected to CLK, the drain is connected to D, and the source is connected to Q; The gate of P38 is connected to CLKB, the drain is connected to the source of N38, and the source is connected to the drain of N38.

8. The anti-four-node flip latch circuit based on the hardening technology according to claim 1, characterized in that, The gate length of all MOS transistors is 65 nm, and the gate widths of P13, P16, P17, P20, P21, P24, N1, N4, N5, N8, N9, N12 are all 420 nm, and the gate widths of all the remaining MOS transistors are 140 nm.

9. An anti-four-node flip latch module, characterized in that, It is encapsulated by using the anti-four-node flip latch circuit described in any one of claims 1-8.

10. The anti-four-node flip latch module according to claim 9, characterized in that, The pins of the anti-four-node flip latch module include: The first pin is used to connect to VDD; The second pin is used to connect to GND; The third pin is used to input the clock signal CLK; The fourth pin is used to input the input signal D; and The fifth pin is used to output the output signal Q.

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