Semiconductor structure and method of manufacturing the same

Abstract

The embodiment of the present disclosure relates to the field of semiconductor, and provides a semiconductor structure and a manufacturing method thereof, the semiconductor structure comprising: a plurality of memory cells spaced apart along a first direction and a second direction and arranged in an array, the first direction and the second direction are both perpendicular to a third direction, and the included angle between the first direction and the second direction is less than 90°, the memory cell comprising a first transistor and a second transistor arranged along the third direction, the first end of the first transistor and the control end of the second transistor are electrically connected; a first word line extending along the second direction and a first bit line extending along the first direction, the first word line is electrically connected with the control end of the first transistor, and the first bit line is electrically connected with the second end of the first transistor; a second word line extending along the first direction and a second bit line extending along the second direction, the second word line is electrically connected with the first end of the second transistor, and the second bit line is electrically connected with the second end of the second transistor. At least the integration density of the memory cell array structure can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] Common Dynamic Random Access Memory (DRAM) is of the 1T1C type, meaning that a single transistor's source or drain is electrically connected to a capacitor to form a memory cell structure. This structure uses capacitors to store data, but because reading data consumes the capacitor's charge, and the capacitor itself can leak current, the charge in the capacitor needs to be constantly refreshed. This results in high power consumption and unstable electrical performance for DRAM. Furthermore, the large area required for capacitor manufacturing makes miniaturization a significant challenge.

[0003] To overcome the challenges posed by capacitance, 2TOC-type memory cell structures have been applied. In this structure, the source or drain of one transistor is electrically connected to the gate of another transistor to form a memory cell. The gate of one of the transistors can form a natural capacitor, allowing charge storage and flow. However, the integration density of semiconductor structures using 2TOC-type memory cells in current technology still needs improvement. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and its manufacturing method, which at least helps to improve the integration density of memory cells.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, including: a plurality of memory cells, the plurality of memory cells being spaced apart and arranged in an array along a first direction and a second direction, the first direction and the second direction being perpendicular to a third direction, and the angle between the first direction and the second direction being less than 90°, each memory cell including a first transistor and a second transistor arranged along the third direction, a first terminal of the first transistor being electrically connected to a control terminal of the second transistor; a first word line and a first bit line, the first word line extending along the second direction, the first bit line extending along the first direction, and the first word line being electrically connected to a control terminal of the first transistor, the first bit line being electrically connected to a second terminal of the first transistor; a second word line and a second bit line, the second word line extending along the first direction, the second bit line extending along the second direction, and the second word line being electrically connected to a first terminal of the second transistor, the second bit line being electrically connected to a second terminal of the second transistor.

[0006] In some embodiments, the angle between the first direction and the second direction is 60°.

[0007] In some embodiments, the distance between the first transistors in any adjacent memory cells is the same; the distance between the second transistors in any adjacent memory cells is the same.

[0008] In some embodiments, the first transistor is a write transistor and the second transistor is a read transistor.

[0009] In some embodiments, the first transistor includes: a semiconductor pillar; a first word line facing at least a portion of the side of the semiconductor pillar; and first source / drain doped regions located within the semiconductor pillar on opposite sides of the first word line, wherein one of the first source / drain doped regions serves as a first terminal of the first transistor and is electrically connected to a control terminal of the second transistor, and the other of the first source / drain doped regions serves as a second terminal of the first transistor and is electrically connected to the first bit line.

[0010] In some embodiments, the semiconductor pillar is made of IGZO.

[0011] In some embodiments, the second transistor includes: a semiconductor layer; a second gate, which is opposite to at least a portion of the semiconductor layer and is electrically connected to a first end of the first transistor; and second source-drain doped regions located at opposite ends of the semiconductor layer along a third direction, wherein one of the second source-drain doped regions serves as a first end of the second transistor and is electrically connected to the second word line, and the other second source-drain doped region serves as a second end of the second transistor and is electrically connected to the second bit line.

[0012] In some embodiments, the second gate is columnar; the semiconductor layer faces the side and bottom surfaces of the second gate, and the top surface of the second gate is electrically connected to the first terminal of the first transistor; wherein, one second source / drain doped region is adjacent to the top surface of the second gate, and another second source / drain doped region is adjacent to the bottom surface of the second gate.

[0013] In some embodiments, the second transistor further includes: a first electrical connection layer electrically contacting the second source / drain doped region adjacent to the top surface of the second gate; and a second electrical connection layer electrically contacting the second source / drain doped region adjacent to the bottom surface of the second gate; wherein the first electrical connection layer is electrically contacting one of the second bit line or the second word line, and the second electrical connection layer is electrically contacting the other of the second bit line or the second word line.

[0014] In some embodiments, the semiconductor layer is made of IGZO.

[0015] According to some embodiments of this disclosure, another aspect of this disclosure provides a method for manufacturing a semiconductor structure, comprising: forming a plurality of memory cells, the plurality of memory cells being spaced apart and arranged in an array along a first direction and a second direction, the first direction and the second direction being perpendicular to a third direction, and the angle between the first direction and the second direction being less than 90°, each memory cell including a first transistor and a second transistor arranged along the third direction, a first terminal of the first transistor being electrically connected to a control terminal of the second transistor; forming a first word line and a first bit line, the first word line extending along the second direction, the first bit line extending along the first direction, and the first word line being electrically connected to a control terminal of the first transistor, and the first bit line being electrically connected to a second terminal of the first transistor; forming a second word line and a second bit line, the second word line extending along the first direction, the second bit line extending along the second direction, and the second word line being electrically connected to a first terminal of the second transistor, and the second bit line being electrically connected to a second terminal of the second transistor.

[0016] In some embodiments, forming the second transistor includes forming a semiconductor layer and a second gate, the second gate being columnar, the semiconductor layer having a side surface and a bottom surface facing the second gate, the top surface of the second gate being electrically connected to a first end of the first transistor, the semiconductor layer having second source / drain doped regions at opposite ends along the third direction, wherein one of the second source / drain doped regions serves as a first end of the second transistor and is electrically connected to the second word line, and the other of the second source / drain doped regions serves as a second end of the second transistor and is electrically connected to the second bit line, one of the second source / drain doped regions being adjacent to the top surface of the second gate, and the other of the second source / drain doped regions being adjacent to the bottom surface of the second gate.

[0017] The technical solutions provided in this disclosure have at least the following advantages:

[0018] The semiconductor structure provided in this disclosure includes: a plurality of memory cells spaced apart and arranged in an array along a first direction and a second direction, both the first and second directions being perpendicular to a third direction, and the angle between the first and second directions being less than 90°; each memory cell includes a first transistor and a second transistor arranged along the third direction, with a first terminal of the first transistor electrically connected to a control terminal of the second transistor; a first word line extending along the second direction and a first bit line extending along the first direction, the first word line being electrically connected to the control terminal of the first transistor and the first bit line being electrically connected to a second terminal of the first transistor; a second word line extending along the first direction and a second bit line extending along the second direction, the second word line being electrically connected to a first terminal of the second transistor and the second bit line being electrically connected to a second terminal of the second transistor. In this disclosure embodiment, the angle between the first direction of extension of the first bit line and the second word line and the second direction of extension of the second bit line and the first word line is less than 90°. Compared to conventional technologies where the first and second directions are perpendicular, this method increases the integration density of memory cells and reduces the size of the semiconductor structure without changing the spacing between adjacent memory cells. This reduces the area enclosed by four adjacent memory cells, thus reducing the area occupied by each memory cell in the array structure and improving the miniaturization of the semiconductor structure. Furthermore, since the first and second transistors together constitute the memory cell, capacitors are unnecessary, which helps reduce the size of the memory cell structure itself and further increases its integration density. Attached Figure Description

[0019] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A partial top view schematic diagram of a semiconductor structure;

[0021] Figure 2 This is a partial top view of a semiconductor structure provided in an embodiment of the present disclosure;

[0022] Figure 3 This is a three-dimensional structural diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0023] Figure 4 A simplified circuit diagram corresponding to a semiconductor structure provided in one embodiment of this disclosure;

[0024] Figure 5 This is a schematic diagram of a local region in a semiconductor structure provided in an embodiment of the present disclosure.

[0025] Figure 6 This is a schematic diagram of a local region in a semiconductor structure provided in another embodiment of the present disclosure;

[0026] Figure 7 This is a three-dimensional structural diagram of another local region in a semiconductor structure provided in an embodiment of the present disclosure.

[0027] Figure 8 A schematic cross-sectional view of a step in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

[0028] Figure 9 A cross-sectional structural schematic diagram corresponding to a step in a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure;

[0029] Figure 10 This is a three-dimensional structural schematic diagram corresponding to another step in the manufacturing method of a semiconductor structure provided in an embodiment of the present disclosure. Detailed Implementation

[0030] As can be seen from the background technology, current semiconductor structures suffer from the problem of low integration density of memory cells.

[0031] refer to Figure 1 , Figure 1 This is a top view schematic diagram of a semiconductor structure. The semiconductor structure includes a plurality of memory cells 10 spaced apart and arranged in an array along a first direction X and a second direction Y, with the first direction X and the second direction Y being perpendicular. Each memory cell 10 includes a first transistor and a second transistor. The semiconductor structure also includes a first word line, a first bit line, a second word line, and a second bit line, which are not shown in the figure. The first word line extends along the second direction Y, the first bit line extends along the first direction X, the second word line extends along the first direction X, and the second bit line extends along the second direction Y. The first word line and the first bit line are electrically connected to the first transistor, and the second word line and the second bit line are electrically connected to the second transistor.

[0032] Analysis revealed that in the aforementioned semiconductor structure, the array of multiple memory cells 10 is arranged in a square. If the distance between two adjacent memory cells 10 is 'a', then the area enclosed by four adjacent memory cells 10 in the array structure should be 'a'. 2Because the area enclosed by four adjacent memory cells 10 in the memory cell 10 structure is relatively large, the integration density of memory cells in the semiconductor structure is low. If a semiconductor structure can be provided that reduces the area enclosed by four adjacent memory cells without changing the distance between two adjacent memory cells, the above problem can be solved and the integration density of the memory cell structure can be improved.

[0033] This disclosure provides a semiconductor structure including: a plurality of memory cells spaced apart along a first direction and a second direction and arranged in an array, wherein the angle between the first direction and the second direction is less than 90°, and each memory cell includes a first transistor and a second transistor. A first word line extends along the second direction, a first bit line extends along the first direction, a second word line extends along the first direction, and a second bit line extends along the second direction. Thus, the array structure of the plurality of memory cells in the semiconductor structure is hexagonally arranged. If the distance between two adjacent memory cells is 'a', the area enclosed by four adjacent memory cells in the memory cell array of the semiconductor structure is less than 'a'. 2 By changing the integrated array configuration of memory cells, the area enclosed by four adjacent memory cells can be reduced without altering the spacing between them. This reduces the area occupied by each memory cell in the array structure, thereby improving the miniaturization of the semiconductor structure and increasing the integration density of the memory cells.

[0034] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of the present disclosure to enable the reader to better understand the present disclosure. However, the technical solutions claimed in the present disclosure can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0035] Figure 2 This is a partial top view of a semiconductor structure provided in an embodiment of the present disclosure. Figure 3 This is a three-dimensional structural diagram of a semiconductor provided in an embodiment of the present disclosure.

[0036] refer to Figures 2 to 3The semiconductor structure includes: a plurality of memory cells 100, which are spaced apart and arranged in an array along a first direction X and a second direction Y, both of which are perpendicular to a third direction Z, and the angle between the first direction X and the second direction Y is less than 90°. Each memory cell 100 includes a first transistor 110 and a second transistor 120 arranged along the third direction Z, with a first terminal of the first transistor 110 electrically connected to a control terminal of the second transistor 120; a first word line 130 and a first bit line 140. Word line 130 extends along the second direction Y, first bit line 140 extends along the first direction X, and first word line 130 is electrically connected to the control terminal of first transistor 110, and first bit line 140 is electrically connected to the second terminal of first transistor 110; second word line 150 and second bit line 160, second word line 150 extends along the first direction X, second bit line 160 extends along the second direction Y, and second word line 150 is electrically connected to the first terminal of second transistor 120, and second bit line 160 is electrically connected to the second terminal of second transistor 120.

[0037] refer to Figure 2 ,according to Figure 2 It can be seen that the array structure of multiple memory cells 100 in the semiconductor structure is arranged in a hexagon. If the distance between two adjacent memory cells 100 is 'a', then the area enclosed by four adjacent memory cells 100 in the semiconductor structure should be less than 'a'. 2 Because the area enclosed by four adjacent memory cells 100 in the memory cell 100 structure is small, and the size occupied by each memory cell 100 is small, the integration density of the memory cell 100 structure in the semiconductor structure can be improved.

[0038] refer to Figure 3 In the semiconductor structure, each memory cell 100 includes a first transistor 110 and a second transistor 120 arranged along a third direction Z. Furthermore, a first bit line 140, a first word line 130, a second bit line 160, and a second word line 150 are sequentially provided in the direction from the first transistor 110 to the second transistor 120. The first bit line 140 and the second word line 150 extend along a first direction X, and the first word line 130 and the second bit line 160 extend along a second direction Y.

[0039] refer to Figures 3 to 4 , Figure 4This is a simplified circuit diagram corresponding to a semiconductor structure provided in one embodiment of the present disclosure. In some embodiments, the first transistor 110 can be a write transistor, and the second transistor 120 can be a read transistor. When the semiconductor structure is operating, charge is stored in the gate capacitance of the second transistor 120, that is, in the control terminal of the second transistor 120. The location where the charge is stored is generally referred to as the storage node SN. The 2TOC memory cell is controlled by the first transistor 110 for write operations and by the second transistor 120 for read operations. By utilizing the gate capacitance of the transistors to store charge, studies have shown that transistors fabricated using metal-oxide-semiconductor (MOS) transistors have a smaller cutoff current, allowing the charge stored in the gate capacitance to be retained for a longer period of time.

[0040] It should be noted that, in order to make the diagram more concise and clear, Figure 3 The entire structure of the first transistor 110, the entire structure of the second transistor 120, and the connection structure between the components are not clearly shown.

[0041] For example, thin-film transistors (TFTs) fabricated based on IGZO have a density of less than 10. 22 The extremely low cutoff current of A / μm reduces the leakage current of the fabricated 2T0C memory cell. For example, a 2T0C memory cell fabricated based on two IGZO-TFTs has a retention time greater than 400 seconds and a current of approximately 3 × 10⁻⁶ μm. -19 The extremely low shutdown current of A / μm can improve the data retention capability of the 2T0C memory cell.

[0042] The memory cell structure is of the 2T0C type, without capacitors, which helps to reduce the size of the memory cell structure. Moreover, the first transistor 110 and the second transistor 120 are stacked vertically along the third direction Z, which helps to reduce the layout space of the memory cell structure along the first direction X and the second direction Y, thereby helping to improve the integration density of the memory cell 100 structure.

[0043] refer to Figure 2 In some embodiments, the angle between the first direction X and the second direction Y can be 60°. The array structure of memory cells 100 arranged in this way can be a regular hexagon. If the distance between two adjacent memory cells 100 is 'a', in the array structure of memory cells 100 in the semiconductor structure, the area enclosed by four adjacent memory cells 100 should be... It can be seen that, compared to the area a of the region enclosed by four adjacent memory cells in a memory cell array where the first direction X and the second direction Y are perpendicular, 2In this array structure of memory cells 100, the area enclosed by four adjacent memory cells 100 is relatively small. That is to say, the size occupied by each memory cell 100 in the semiconductor structure in the first direction X or the second direction Y is relatively small, which can improve the miniaturization of the semiconductor structure and increase the integration density of memory cells.

[0044] Continue to refer to Figure 2 In some embodiments, the distance between the first transistors 110 in any adjacent memory cells 100 can be the same; the distance between the second transistors 120 in any adjacent memory cells 100 can also be the same. That is, the distance between any adjacent memory cells 100 can be the same. If the angle between the first direction X and the second direction Y is 60°, the array structure of the memory cells 100 can be arranged in a regular hexagon, and the distance between any two adjacent memory cells 100 can be the same. Therefore, the distance between any adjacent memory cells 100 can be selected from the minimum distance that can be selected between adjacent transistors in the semiconductor structure, thereby further reducing the distance between adjacent memory cells 100, reducing the size occupied by each memory cell 100 in the first direction X or the second direction Y in the semiconductor structure, further improving the miniaturization of the semiconductor structure, and further increasing the integration density of the memory cells 100.

[0045] Figure 5 A first transistor 110 in a semiconductor structure provided in an embodiment of this disclosure (reference) Figure 3 A cross-sectional structural diagram of ). Figure 6 This is a cross-sectional view of a first transistor 110 in a semiconductor structure provided in another embodiment of the present disclosure.

[0046] refer to Figure 5In some embodiments, the first transistor 110 may be a gate-all-around FET (GAA). In a gate-all-around FET, the gate may surround the periphery of the channel. The first transistor 110 may include: a semiconductor pillar 111; a first word line 130 facing at least a portion of the side of the semiconductor pillar 111; and first source / drain doped regions 112 located within the semiconductor pillar 111 on opposite sides of the first word line 130, wherein one first source / drain doped region 112 serves as the first terminal of the first transistor 110 and is electrically connected to the control terminal of the second transistor 120, and the other first source / drain doped region 112 serves as the second terminal of the first transistor 110 and is electrically connected to the first bit line 140. The region in the semiconductor pillar 111 facing the first word line 130 may be the channel region of the first transistor 110, and the first word line 130 may serve as the gate of the first transistor 110. Doping can be performed in the first source / drain doped regions 112 located within the semiconductor pillars 111 on either side of the first word line 130. If N-type doping is required, N-type ions, such as nitrogen ions or phosphorus ions, can be implanted. If P-type doping is required, P-type ions, such as boron ions or aluminum ions, can be implanted.

[0047] refer to Figure 4 as well as Figure 5 The first and second terminals of the first transistor 110 can be the source and drain of the first transistor 110, and the control terminal of the first transistor 110 is the gate of the first transistor 110. The first terminal of the first transistor 110 can be the source of the first transistor 110. The first terminal of the first transistor 110 is connected to the control terminal of the second transistor 120 and forms a memory node SN of the semiconductor structure. The second terminal of the first transistor 110 can be the drain of the first transistor 110. The second terminal of the first transistor 110 is electrically connected to the first bit line 140. The control terminal of the first transistor 110, that is, the gate of the first transistor 110, is electrically connected to the first word line 130.

[0048] It should be noted that semiconductor structures can also contain interconnect structures. For the sake of clarity and simplicity in the diagram, the interconnect structures are... Figure 3 Not fully shown, the connection structure can electrically connect the second terminal of the first transistor to the first bit line.

[0049] In some embodiments, the material of the semiconductor pillar 111 may include IGZO (indium gallium zinc oxide). IGZO contains indium, gallium, and zinc, and is a novel semiconductor material. Using IGZO material in the semiconductor pillar 111 as a channel in a semiconductor structure can improve the performance of the semiconductor structure. Compared to amorphous silicon channel layers, the carrier mobility of a channel layer made of IGZO is 20-30 times that of amorphous silicon, and IGZO can also improve the charge and discharge rate of the semiconductor structure, thereby improving the energy efficiency of the semiconductor structure.

[0050] In other embodiments, the semiconductor pillar 111 may also include other materials, for example, the material of the semiconductor pillar 111 may also include ITO (Indium Tin Oxide).

[0051] Continue to refer to Figure 5 In some embodiments, the first transistor 110 may further include a first gate dielectric layer 113, which may be located at least between the first word line 130 and the semiconductor pillar 111. The material of the first gate dielectric layer 113 may include silicon oxide or aluminum oxide, etc. The presence of the first gate dielectric layer 113 can improve the electronic conductivity of the first transistor 110, making electron conduction in the semiconductor structure smoother. Furthermore, the first gate dielectric layer 113 can control the current, preventing excessive current from causing overheating or short circuits in the device. It can form a charge channel to control the flow of electrons in the device, improve the stability and efficiency of the device, and protect the device from environmental factors to a certain extent. In addition, the first gate dielectric layer 113 also has a certain surface activity and can serve as a surface active layer in the semiconductor structure, which can be used to receive or place other substances.

[0052] refer to Figure 6 In some embodiments, the first transistor 110 may further include a first gate 114, which may face at least a portion of the side surface of the semiconductor pillar 111. The semiconductor pillars 111 located on opposite sides of the first gate 114 may contain first source / drain doped regions 112, and the portion of the semiconductor pillar 111 facing the first gate 114 may constitute the channel of the first transistor 110. A first word line 130 may cover the surface of the first gate 114 away from the semiconductor pillar 111 and be electrically connected to the first gate 114. A first gate dielectric layer 113 may be located between the first gate 114 and the semiconductor pillar 111.

[0053] Figure 7 A second transistor 120 in a semiconductor structure provided in this disclosure (reference) Figure 3 A cross-sectional structural diagram of ).

[0054] refer to Figure 7 In some embodiments, the second transistor 120 can be a vertical-ring-channel transistor (CAA). In a CAA transistor, the channel can surround the periphery of the gate. The second transistor 120 may include: a semiconductor layer 121; a second gate 122, which is directly opposite to at least a portion of the semiconductor layer 121 and electrically connected to a first terminal of the first transistor 110; and second source / drain doped regions 123 located at opposite ends of the semiconductor layer 121 along a third direction (Z), wherein one second source / drain doped region 123 serves as the first terminal of the second transistor 120 and is electrically connected to a second word line 150, and the other second source / drain doped region 123 serves as the second terminal of the second transistor 120 and is electrically connected to a second bit line 160. The portion of the semiconductor layer 121 directly opposite the second gate 122 can serve as the channel of the second transistor 120, and the second source / drain doped regions 123 located at opposite ends of the first transistor 110 along a third direction (Z) can also be directly opposite the second gate 122. The second source / drain doped region 123 can be doped. If N-type doping is required, N-type ions, such as nitrogen ions or phosphorus ions, can be implanted. If P-type doping is required, P-type ions, such as boron ions or aluminum ions, can be implanted.

[0055] refer to Figure 4 as well as Figure 7 The control terminal of the second transistor 120 is electrically connected to the first terminal of the first transistor 110, meaning the second gate 122 of the second transistor 120 can be electrically connected to the source of the first transistor 110 to form a memory node SN. The first and second terminals of the second transistor 120 can be its source and drain. The first terminal of the second transistor 120 can be its source, and is electrically connected to the second word line 130. The second terminal of the second transistor 120 can be its drain, and is electrically connected to the second bit line 160.

[0056] Continue to refer to Figure 7In some embodiments, the second gate 122 can be columnar; the semiconductor layer 121 faces the side and bottom surfaces of the second gate 122, and the top surface of the second gate 122 is electrically connected to the first terminal of the first transistor 110; wherein, one second source / drain doped region 123 is adjacent to the top surface of the second gate 122, and another second source / drain doped region 123 is adjacent to the bottom surface of the second gate 122. The semiconductor layer 121 surrounds the side surface of the second gate 122 and also faces the bottom surface of the second gate 122, that is, the semiconductor layer 121 can form a semi-enclosed space, in which the columnar second gate 122 extends, and the top surface of the second gate 122 extends out of the top of the space enclosed by the semiconductor layer 121 and is electrically connected to the first terminal of the first transistor 110. The second gate 122 faces the channel in the semiconductor layer 121 and the two second source / drain doped regions 123, but only the semiconductor layer 121 located between the two second source / drain doped regions 123 along the third direction Z is the channel of the second transistor 120. Along the third direction Z, the first transistor 110 is located on the top surface of the second transistor 120, and the first end of the first transistor 110 can be in contact with the top surface of the second gate 122 in the second transistor 120.

[0057] In some embodiments, the second transistor 120 may further include a second gate dielectric layer 124. The second gate dielectric layer 124 may be located at least between the second gate 122 and the semiconductor layer 121. The material of the second gate dielectric layer 124 may include silicon oxide or aluminum oxide, etc. The provision of the second gate dielectric layer 124 can improve the electronic conduction performance of the second transistor 120, making electron conduction in the semiconductor structure smoother. Furthermore, the second gate dielectric layer 124 can also control the current, preventing excessive current from causing overheating or short circuits. It can form a charge channel to control the flow of electrons in the device, and can also improve the stability and efficiency of the device, and to a certain extent protect the device from environmental factors. In addition, the second gate dielectric layer 124 also has a certain degree of surface activity and can serve as a surface active layer in the semiconductor structure, which can be used to receive or place other substances.

[0058] Continue to refer to Figure 7In some embodiments, the second transistor 120 further includes: a first electrical connection layer 125, electrically contacting a second source / drain doped region 123 adjacent to the top surface of the second gate 122; and a second electrical connection layer 126, electrically contacting a second source / drain doped region 123 adjacent to the bottom surface of the second gate 122. The first electrical connection layer 125 is electrically contacted with either the second bit line 160 or the second word line 150, and the second electrical connection layer 126 is electrically contacted with the other of the second bit line 160 or the second word line 150. The first electrical connection layer 125 and the second electrical connection layer 126 are the source and drain of the second transistor 120. The first electrical connection layer 125 can be electrically connected to the second bit line 160, serving as the drain of the second transistor 120. The second electrical connection layer 126 can be electrically connected to the second word line 150, serving as the source of the second transistor 120. It should be noted that, for the sake of clarity and simplicity, [the following is an explanation of the diagram and its implications]. Figure 3 The first electrical connection layer 125 and the second electrical connection layer 126 are not shown in the diagram. Figure 7 The full structure of the first electrical connection layer 125 and the second electrical connection layer 126 is not shown. The first electrical connection layer 125 and the second electrical connection layer 126 only need to realize their connection function in the semiconductor structure. The first electrical connection layer 125 is electrically connected to one of the second source / drain doped regions 123 in the second transistor 120 and one of the second word line 150 or the second bit line 160. The second electrical connection layer 126 is electrically connected to the other second source / drain doped region 123 in the second transistor 120 and the other of the second word line 150 or the second bit line 160.

[0059] In some embodiments, the material of semiconductor layer 121 may include IGZO (indium gallium zinc oxide). IGZO contains indium, gallium, and zinc, and is a novel semiconductor material. Using IGZO material in semiconductor layer 121 as a channel in a semiconductor structure can improve the performance of the semiconductor structure. Compared to amorphous silicon channel layers, the carrier mobility of a channel layer using IGZO material is 20-30 times that of amorphous silicon, and IGZO can also improve the charge and discharge rate of the semiconductor structure, thereby improving the energy efficiency of the semiconductor structure.

[0060] In other embodiments, the semiconductor layer 121 may also include other materials, for example, the material of the semiconductor layer 121 may also include ITO (Indium Tin Oxide).

[0061] The semiconductor structure provided in this disclosure includes a plurality of memory cells spaced apart along a first direction and a second direction and arranged in an array. The angle between the first direction and the second direction is less than 90°. Each memory cell includes a first transistor and a second transistor. A first word line extends along the second direction, a first bit line extends along the first direction, a second word line extends along the first direction, and a second bit line extends along the second direction. Thus, by changing the integrated array configuration of the memory cells, without changing the spacing between adjacent memory cells, the area enclosed by four adjacent memory cells can be reduced. This reduces the area occupied by each memory cell in the memory cell array structure, thereby improving the miniaturization of the semiconductor structure and increasing the integration density of the memory cells.

[0062] Accordingly, another embodiment of this disclosure also provides a method for manufacturing a semiconductor structure, which can be used to form the above-mentioned semiconductor structure. The semiconductor structure provided by another embodiment of this disclosure will be described in detail below with reference to the accompanying drawings. For parts that are the same as or corresponding to the previous embodiment, please refer to the corresponding descriptions of the foregoing embodiments; detailed descriptions will not be repeated below.

[0063] Figure 8 This is a schematic cross-sectional view of a memory cell in the step of forming a memory cell in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure.

[0064] refer to Figure 8 This forms multiple storage units 100 (reference) Figure 2 Multiple memory cells 100 are spaced apart and arranged in an array along a first direction X and a second direction Y. Both the first direction X and the second direction Y are perpendicular to a third direction Z. Each memory cell 100 includes a first transistor 110 and a second transistor 120 arranged along the third direction Z. A first terminal of the first transistor 110 is electrically connected to a control terminal of the second transistor 120. Along the third direction Z, the first transistor 110 is located on the top surface of the second transistor 120, and a first segment of the first transistor 110 is in contact with and electrically connected to the top surface of the control terminal of the second transistor 120.

[0065] In some embodiments, forming a memory cell 100 includes forming a second transistor 120, forming a first transistor 110, and arranging the second transistor 120 and the first transistor 110 in a memory cell 100 along a third direction Z, with the second transistor 120 located on the bottom surface of the first transistor 110.

[0066] Continue to refer to Figure 8In some embodiments, forming the second transistor 120 may include forming a semiconductor layer 121 and a second gate 122. The second gate 122 is columnar, with the sides and bottom surfaces of the semiconductor layer 121 and the second gate 122 facing each other. The top surface of the second gate 122 is electrically connected to the first end of the first transistor 110. The semiconductor layer 121 has second source / drain doped regions 123 at opposite ends along a third direction Z. One second source / drain doped region 123 serves as the first end of the second transistor 120 and is electrically connected to the second word line 150, while the other second source / drain doped region 123 serves as the second end of the second transistor 120 and is electrically connected to the second bit line 160. One second source / drain doped region 123 is adjacent to the top surface of the second gate 122, and the other second source / drain doped region 123 is adjacent to the bottom surface of the second gate 122. The formed second transistor may be a vertical-annular channel transistor (CAA). In a vertical-annular channel transistor, the channel may surround the periphery of the gate. The second source / drain doped region 123 in the formed second transistor 120 needs to be doped. If N-type doping is required, N-type ions, such as nitrogen ions or phosphorus ions, can be implanted. If P-type doping is required, P-type ions, such as boron ions or aluminum ions, can be implanted.

[0067] In some embodiments, the second gate 122 in the formed second transistor 120 can be columnar, with the semiconductor layer 121 facing the side and bottom of the second gate 122, and the top surface of the second gate 122 exposed. A second source / drain doped region 123 is adjacent to the top surface of the second gate 122, and another second source / drain doped region 123 is adjacent to the bottom surface of the second gate 122.

[0068] In some embodiments, the formed second transistor 120 may further include a second gate dielectric layer 124, which may be located at least between the second gate 122 and the semiconductor layer 121. The material of the second gate dielectric layer 124 may include silicon oxide or aluminum oxide, etc.

[0069] In some embodiments, forming the second transistor 120 may further include forming a first electrical connection layer 125 and a second electrical connection layer 126, wherein the first electrical connection layer 125 is in electrical contact with a second source / drain doped region 123 adjacent to the top surface of the second gate 122, and the second electrical connection layer 126 is in electrical contact with a second source / drain doped region 123 adjacent to the bottom surface of the second gate 122. The first electrical connection layer 125 and the second electrical connection layer 126 may be used to electrically connect the second bit line 160 and the second word line 150, respectively.

[0070] In some embodiments, the first transistor 110 can be a gate-all-around FET (GAA). In a gate-all-around FET, the gate can surround the periphery of the channel. Forming the first transistor 110 may include forming a semiconductor pillar 111, with two first source / drain doped regions 112 on both sides along a third direction Z. One of the first source / drain doped regions 112 serves as the first end of the first transistor 110, covering the top surface of the second gate 122 of the second transistor 120, and the first end of the first transistor 110 is electrically connected to the second gate 122 of the second transistor 120. The other first source / drain doped region 112 serves as the second end of the first transistor 110. The first source / drain doped regions 112 located on opposite sides of the semiconductor pillar 111 need to be doped. If N-type doping is required, N-type ions, such as nitrogen ions or phosphorus ions, can be implanted. If P-type doping is required, P-type ions, such as boron ions or aluminum ions, can be implanted.

[0071] In some embodiments, forming the first transistor 110 may further include forming a first gate dielectric layer 113, which may be located at least between the first word line 130 and the semiconductor pillar 111. The material of the first gate dielectric layer 113 may include silicon oxide or aluminum oxide, etc.

[0072] Figure 9 This is a schematic cross-sectional view of a memory cell region after the formation of a first word line, a second bit line, a second word line, and a second bit line in a method for manufacturing a semiconductor structure according to an embodiment of this disclosure. Figure 10 This is a three-dimensional structural diagram showing the semiconductor structure after the formation of the first word line, the first bit line, the second word line, and the second bit line in the manufacturing method of the semiconductor structure provided in the embodiments of this disclosure.

[0073] refer to Figure 9 as well as Figure 10A first word line 130 and a first bit line 140 are formed. The first word line 130 extends along the second direction Y, and the first bit line 140 extends along the first direction Z. The angle between the first direction X and the second direction Y is less than 90°. The first word line 130 is electrically connected to the control terminal of the first transistor 110, and the first bit line 140 is electrically connected to the second terminal of the first transistor 110. Multiple parallel first word lines 130 and multiple parallel first bit lines 140 can be formed in the semiconductor structure. Along the third direction Z, each first word line 130 and each first bit line 140 can be located on the same horizontal plane. The arrangement of the first word line 130 and the first bit line 140 can, to a certain extent, determine the array arrangement of the first transistor 110 in the semiconductor structure. Since the angle between the extension directions of the first word line 130 and the first bit line 140 is less than 90°, without changing the distance between adjacent first transistors 110, the area enclosed by four adjacent first transistors 110 will be smaller than the area enclosed by four adjacent first transistors 110 when the extension directions of the first word line 130 and the first bit line 140 are perpendicular. Therefore, this arrangement of the first word line 130 and the first bit line 140 allows for a denser array arrangement of the first transistors 110 in the semiconductor structure, with each first transistor 110 occupying a smaller size along the first direction X and the second direction Y, thereby increasing the integration density of the memory array.

[0074] refer to Figure 9 as well as Figure 10A second word line 150 and a second bit line 160 are formed. The second word line 150 extends along a first direction X, and the second bit line 160 extends along a second direction Y. The angle between the first direction X and the second direction Y is less than 90°. The second word line 150 is electrically connected to the first terminal of the second transistor 120, and the second bit line 160 is electrically connected to the second terminal of the second transistor 120. Multiple parallel second word lines 150 and multiple parallel second bit lines 160 can be formed in the semiconductor structure. Along a third direction Z, each second word line 150 and each second bit line 160 can be located on the same horizontal plane. The arrangement of the second word lines 150 and the second bit lines 160 can, to a certain extent, determine the array arrangement of the second transistor 120 in the semiconductor structure. Since the angle between the extending directions of the second word lines 150 and the second bit lines 160 is less than 90°, this arrangement structure can reduce the area enclosed by four adjacent second transistors 120 without changing the distance between adjacent second transistors 120. Therefore, the second word line 150 and the second bit line 160 configured in this way can make the array arrangement of the second transistor 120 in the semiconductor structure more dense, and each second transistor 120 occupies a smaller size along the first direction X and the second direction Y, thereby improving the integration density of the memory array.

[0075] The first transistor 110 and the second transistor 120 constitute the memory cell 100. As described above, the arrangement of the first word line 130 and the second bit line 140 makes the array structure of the first transistor 110 more dense, and the arrangement of the second word line 150 and the second bit line 160 makes the array structure of the second transistor 120 more dense. Therefore, the angle between the first direction X and the second direction Y is less than 90°, which makes the array structure of the memory cell 100 more dense and improves the integration density of the memory array in the semiconductor structure.

[0076] The semiconductor structure manufacturing method provided in this disclosure includes: forming a plurality of memory cells spaced apart and arranged in an array along a first direction and a second direction, wherein the angle between the first direction and the second direction is less than 90°, and the memory cells include a first transistor and a second transistor arranged along a third direction; forming a first word line, a first bit line, a second word line, and a second bit line, wherein the first word line extends along the second direction, the first bit line extends along the first direction, the second word line extends along the first direction, and the second bit line extends along the second direction. Thus, by changing the angle between the first direction and the second direction, the integrated array configuration of the memory cells is changed. Without changing the spacing between adjacent memory cells, the area enclosed by four adjacent memory cells can be reduced, thereby reducing the area occupied by each memory cell in the memory cell array structure, thereby improving the miniaturization of the semiconductor structure and increasing the integration density of the memory cells.

[0077] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Multiple storage cells are spaced apart and arranged in an array along a first direction and a second direction. The first direction and the second direction are both perpendicular to the third direction, and the angle between the first direction and the second direction is less than 90°. Each storage cell includes a first transistor and a second transistor arranged along the third direction. A first terminal of the first transistor is electrically connected to a control terminal of the second transistor. The first word line and the first bit line extend along the second direction, the first word line extends along the first direction, and the first word line is electrically connected to the control terminal of the first transistor, and the first bit line is electrically connected to the second terminal of the first transistor. The second word line and the second bit line extend along the first direction and the second bit line extend along the second direction. The second word line is electrically connected to the first terminal of the second transistor and the second bit line is electrically connected to the second terminal of the second transistor.

2. The semiconductor structure according to claim 1, characterized in that, The angle between the first direction and the second direction is 60°.

3. The semiconductor structure according to claim 1, characterized in that, The distance between the first transistors in any adjacent memory cells is the same; the distance between the second transistors in any adjacent memory cells is the same.

4. The semiconductor structure according to claim 1, characterized in that, The first transistor is a write transistor, and the second transistor is a read transistor.

5. The semiconductor structure according to any one of claims 1-4, characterized in that, The first transistor includes: Semiconductor pillars; The first word line is directly opposite at least a portion of the side surface of the semiconductor pillar; The first source / drain doped regions are located in the semiconductor pillars on opposite sides of the first word line, wherein one of the first source / drain doped regions serves as the first terminal of the first transistor and is electrically connected to the control terminal of the second transistor, and the other of the first source / drain doped regions serves as the second terminal of the first transistor and is electrically connected to the first bit line.

6. The semiconductor structure according to claim 5, characterized in that, The semiconductor pillar is made of IGZO.

7. The semiconductor structure according to any one of claims 1-4, characterized in that, The second transistor includes: Semiconductor layer; A second gate is directly opposite at least a portion of the semiconductor layer and is electrically connected to a first terminal of the first transistor. The second source / drain doped regions are respectively located at opposite ends of the semiconductor layer along the third direction, wherein one of the second source / drain doped regions serves as the first end of the second transistor and is electrically connected to the second word line, and the other second source / drain doped region serves as the second end of the second transistor and is electrically connected to the second bit line.

8. The semiconductor structure according to claim 7, characterized in that, The second gate is columnar; the semiconductor layer is opposite to the side and bottom of the second gate, and the top surface of the second gate is electrically connected to the first terminal of the first transistor; wherein, one second source / drain doped region is adjacent to the top surface of the second gate, and another second source / drain doped region is adjacent to the bottom surface of the second gate.

9. The semiconductor structure according to claim 8, characterized in that, The second transistor also includes: The first electrical connection layer is in electrical contact with the second source / drain doped region adjacent to the top surface of the second gate; The second electrical connection layer is in electrical contact with the second source / drain doped region adjacent to the bottom surface of the second gate. The first electrical connection layer is in electrical contact with one of the second bit line or the second word line, and the second electrical connection layer is in electrical contact with the other of the second bit line or the second word line.

10. The semiconductor structure according to claim 7, characterized in that, The semiconductor layer is made of IGZO.

11. A method for manufacturing a semiconductor structure, characterized in that, include: Multiple memory cells are formed, and the multiple memory cells are spaced apart and arranged in an array along a first direction and a second direction. The first direction and the second direction are both perpendicular to the third direction, and the angle between the first direction and the second direction is less than 90°. Each memory cell includes a first transistor and a second transistor arranged along the third direction. The first terminal of the first transistor is electrically connected to the control terminal of the second transistor. A first word line and a first bit line are formed. The first word line extends along the second direction, the first bit line extends along the first direction, and the first word line is electrically connected to the control terminal of the first transistor, and the first bit line is electrically connected to the second terminal of the first transistor. A second word line and a second bit line are formed. The second word line extends along the first direction, and the second bit line extends along the second direction. The second word line is electrically connected to the first terminal of the second transistor, and the second bit line is electrically connected to the second terminal of the second transistor.

12. The manufacturing method according to claim 11, characterized in that, Forming the second transistor includes: A semiconductor layer and a second gate are formed. The second gate is columnar. The side and bottom surfaces of the semiconductor layer and the second gate are directly opposite each other. The top surface of the second gate is electrically connected to the first terminal of the first transistor. The semiconductor layer has second source / drain doped regions at opposite ends along the third direction. One of the second source / drain doped regions serves as the first terminal of the second transistor and is electrically connected to the second word line. The other second source / drain doped region serves as the second terminal of the second transistor and is electrically connected to the second bit line. One second source / drain doped region is adjacent to the top surface of the second gate, and the other second source / drain doped region is adjacent to the bottom surface of the second gate.

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