Mission mode Vmin prediction and calibration

Abstract

A low-end operating voltage of an integrated circuit is adjusted. Oscillations are counted at a ring oscillator on the integrated circuit during a specified clock cycle. Based on the number of oscillations, a predictive model associated with a first set of device degradation data and a second set of static random access memory (SRAM) low-end operating voltage data is used to select a low-end operating voltage limit for a processor on the integrated circuit. The low-end operating voltage of the processor is set based on the selected low-end operating voltage limit. These steps are repeated multiple times during operation of the processor. A method for testing an integrated circuit to provide data for generating the predictive model is also provided.

Description

Background Art

[0001] The lowest supply voltage at which a semiconductor device can reliably operate is commonly referred to as "Vmin" and is an important parameter for considerations such as power efficiency and battery life. After a semiconductor part such as a processor chip is deployed, Vmin slowly increases during the operating life of the part due to known effects such as HCI (hot carrier injection), BTI (bias temperature instability), etc. as the part is stressed during operation. This increase means that if the low-end operating voltage is set at or close to the initial Vmin of the processor chip, the chip will function properly when initially deployed, but will eventually experience errors and failures.

[0002] A common solution to compensate for Vmin increases is to configure semiconductor parts to add a guard band to the initial Vmin value when setting the low-end operating voltage of the part. The guard band is set to take into account the Vmin excursions expected to occur after a specified period of use under known usage scenarios. Using this technique means using a fixed pessimistic guard band on all parts from the start of use. While this technique helps ensure good yield and quality metrics, such as defective parts per million (DPPM), it is detrimental to power efficiency associated with Vmin-limited operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 An accelerated processing unit according to some embodiments is shown in block diagram form;

[0004] Figure 2 A block diagram is shown in accordance with some embodiments. Figure 1 Power Supply Monitor (PSM) used in APUs;

[0005] Figure 3 is a graph showing exemplary degradation data obtained during high temperature operating life (HTOL) stress testing of a set of integrated circuits;

[0006] Figure 4 is a flow chart of a process for configuring a low-side operating voltage control process for a target integrated circuit according to some embodiments; and

[0007] Figure 5 is a flow chart of a process for adjusting a low-side operating voltage of an integrated circuit according to some embodiments.

[0008] In the following description, the same reference numerals are used in different drawings to represent similar or identical items. Unless otherwise specified, the word "couple" and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise specified, any description of direct connection also means an alternative embodiment using an appropriate form of indirect electrical connection. DETAILED DESCRIPTION

[0009] A method for configuring a low-end operating voltage control process for a target integrated circuit. The method includes performing a high temperature operating life (HTOL) stress test on a group of integrated circuits of the same model as the target integrated circuit, and saving the resulting first set of device degradation data. During the HTOL test, the method measures the low-end operating voltage of a static random access memory (SRAM) on the group of integrated circuits, and saves the resulting second set of SRAM low-end operating voltage data. A prediction model associated with the first set of device degradation data and the second set of SRAM low-end operating voltage data is generated. The method includes: deploying the prediction model to a data processing system including the target integrated circuit, and configuring the target integrated circuit to: (a) count the number of oscillations of at least one ring oscillator on the target integrated circuit during a specified clock cycle; (b) based on the number of oscillations, access the prediction model, and select a low-end operating voltage limit for a processor on the target integrated circuit from the prediction model; (c) set the low-end operating voltage of the processor based on the selected low-end operating voltage limit, and operate the processor at the low-end operating voltage; and (d) repeat paragraphs (a) to (c) multiple times during operation of the data processing system.

[0010] A method for adjusting a low-end operating voltage of an integrated circuit is disclosed. The method includes counting the number of oscillations of at least one ring oscillator on the integrated circuit during a specified clock cycle. Based on the number of oscillations, the method accesses a prediction model associated with a first set of device degradation data and a second set of static random access memory (SRAM) low-end operating voltage data, and selects a low-end operating voltage limit for a processor on the integrated circuit from the prediction model. The method sets the low-end operating voltage of the processor based on the selected low-end operating voltage limit. These steps are repeated multiple times during operation of the processor.

[0011] An integrated circuit includes a processor core and a system management unit that sets a voltage level at which the processor core operates. The system management unit is operable to adjust a low-end operating voltage of the processor core by obtaining an oscillation count of at least one ring oscillator on the integrated circuit during a specified clock cycle. Based on the count, the system management unit accesses a prediction model associated with a first set of device degradation data and a second set of static random access memory (SRAM) low-end operating voltage data, and selects a current low-end operating voltage limit for the processor core. The system management unit then sets the low-end operating voltage of the processor core to the selected low-end operating voltage limit. This is repeated multiple times during operation of the integrated circuit.

[0012] Figure 1 An accelerated processing unit (APU) 100 is shown in block diagram form. APU 100 is an integrated circuit suitable for use as a processor in a host data processing system, and typically includes a central processing unit (CPU) core complex 110 (including CPU cores 112 and 114), an extensible control structure (SCF) 183, a system management unit controller (SMU) 180, an extensible data structure 125, and a plurality of peripheral controllers. As will be appreciated by one of ordinary skill in the art, APU 100 may not have all of these elements present in every embodiment, and may also have additional elements included therein. For example, in some embodiments, a graphics processing unit (GPU) is present instead of or in addition to the CPU core. In addition, APU 100 may be comprised of one or more integrated circuits in a system, such as a multi-chip module.

[0013] The CPU core complex 110 includes a CPU core 112 and a CPU core 114. Multiple CPU core complexes 110 are used. In this example, the CPU core complex 110 includes two CPU cores, but in other embodiments, the CPU core complex 110 may include more CPU cores, such as four, eight, or sixteen. Each of the CPU cores 112 and 114 is bidirectionally connected to the SCF 183 (which forms a control structure) and the SDF 125, and is capable of providing memory access requests and communications through the SDF 125. The CPU cores 112 and 114 each include a second level (L2) cache 116 and a power supply monitor (PSM) 115 located near the respective L2 cache 116 for monitoring conditions associated with circuit degradation, as further described below. In this embodiment, the CPU cores 112 and 114 share certain resources of the CPU core complex 110, such as the depicted third level (L3) cache 118. The L3 cache 118 also includes a PSM 115 for monitoring circuit degradation conditions. In this embodiment, PSM 115 is positioned near a static random access memory (SRAM) structure (such as the depicted cache memory) because SRAM memory is generally more sensitive to long-term degradation than many other parts of the circuit. However, in other embodiments, PSM 115 may be placed in other locations.

[0014] The SDF 125 includes a crossbar switch for routing memory access requests and memory responses between any memory access agent and the Universal Memory Controllers (UMC) 141 and 142. The SDF 125 also includes a system memory map defined by the Basic Input / Output System (BIOS) for determining the destination of memory accesses based on the system configuration, and a buffer for each virtual connection. Because the buffers in this embodiment are constructed with SRAM memory, a PSM 115 is included near the buffers to monitor circuit degradation.

[0015] The SMU 180 is a local controller that controls the operation of resources on the APU 100 and synchronizes the communication between these resources. The SMU 180 manages the power-up sequencing of the various processors on the APU 100 and controls multiple off-chip devices via reset, enable and other signals. The SMU 180 manages one or more clock sources (not shown), such as a phase-locked loop (PLL), to provide clock signals for each component of the APU 100. The SMU 180 also manages the power of the various processors and other functional blocks, and can receive measured power consumption values ​​from the CPU cores 112 and 114 and the graphics core 120 to determine the appropriate power state. The SMU communicates with various circuit blocks through the SCF 193 to complete system management, including a test block 184, a thermal monitoring block 185, a clock control circuit (CLK) 186, a fuse reading circuit 187, and a system management input / output (SMUIO) block 188. The SMU 180 also communicates with each PSM 115 to activate them to monitor conditions and report results. The SMU 180 can adjust the low-end operating voltage (commonly referred to as "Vmin", interchangeable with the actual Vmin that can be measured for semiconductor circuits) of the relevant voltage domain based on access to a prediction model 182, which provides a predicted safe low-end operating voltage based on results obtained from the PSM 115, as further described below. The SMU 180 also implements various system monitoring and power saving functions. For example, if the APU 100 becomes hot, the SMU 180 can reduce the frequency and voltage of the CPU cores 112 and 114. The SMU 180 can also receive thermal events from external sensors via the SCF 183, and in response, the SMU 180 can reduce the clock frequency and / or the power supply voltage.

[0016] Peripheral controllers 160 include a Universal Serial Bus (USB) controller 162 and a Serial Advanced Technology Attachment (SATA) interface controller 164, each of which is bidirectionally connected to a system hub 166 and the SMN bus. These two controllers are merely examples of peripheral controllers that may be used with APU 100.

[0017] A high-speed peripheral component interconnect (PCIe) controller 174 and a USB controller 162 are bidirectionally connected to an input / output (I / O) hub 176. The PCIe controller includes a multiplexer / demultiplexer (MUS / DEMUX) adapted to route traffic to various PCIe PHYs. The USB controller 162 is connected to a plurality of USB PHYs. The I / O hub 176 is bidirectionally connected to the system hub 166 and the SDF 125. Thus, for example, the CPU core can program registers in the USB controller 162, the PCIe controller 174, or various other controllers (not shown), where access is routed through the SDF 125 and the I / O hub 176. The software and firmware for the APU 100 are stored in a system data drive or system BIOS memory (not shown), which can be any of a variety of non-volatile memory types, such as read-only memory (ROM), flash electrically erasable programmable ROM (EEPROM), etc. Typically, the BIOS memory is accessed through the PCIe bus, and the system data drive is accessed through the SATA interface.

[0018] Each of the UMCs 141 and 142 is connected to the SDF 125. The UMCs 141 and 142 are connected to memory physical layer interfaces (PHYs) 151 and 152, which can be connected to existing technology DDR memories, such as fourth generation DDR (DDR4), low power DDR4 (LPDDR4), fifth generation graphics DDR (GDDR5), and high bandwidth memory (HBM), and can be adapted to future memory technologies. These memories provide high bus bandwidth and high-speed operation. At the same time, they also provide low power modes to save power for battery-powered applications such as laptops, and also provide built-in thermal monitoring.

[0019] Figure 2 The block diagram shows a suitable Figure 1 A power supply monitor (PSM) 200 is used in the APU 100 of FIG. 1 . In general, the PSM 200 includes a plurality of ring oscillators 201-204, each connected to a corresponding counter 205 for counting oscillations from the ring oscillators. An enable signal EN enables the counters for a specified period measured by a system reference clock. The counter values ​​may also be averaged or otherwise combined with other digital logic not shown.

[0020] Each of the ring oscillators 201 to 204 includes a series of logic gates configured to oscillate with a feedback connection from the end of the series to the beginning. Although only at least one ring oscillator is required, the preferred embodiment uses multiple oscillators composed of different logic gates and different device (transistor) types in order to characterize the degradation of devices in the APU 100 during their operating life. The depicted arrangement is provided to show an example of how different oscillators can be used. As shown, the ring oscillator 201 is composed of a first type of logic gates and a first type of device, while the ring oscillator 202 uses the first type of logic gates but uses a second type of device. The logic gate type is selected from various types, such as inverters, NAND gates, NOR gates, D-type flip-flops, or other common logic gates used within the CPU core complex 110. The device type is selected from various transistor types or sizes that can be used within the CPU core complex 110. For example, a high voltage threshold (Vt) device and a low Vt device of the same transistor can be used. Different sizes and transistor designs can also be used. As shown, various combinations of gate type and device type may be used, where ring oscillator 203 uses a second gate type with a first device type, and ring oscillator 204 uses a second gate type with a second device type. The combination of gate type and device type is selected to characterize degradation over time due to known effects such as HCI (hot carrier injection), BTI (bias temperature instability), etc., which cause an increase in shift / increase over time when the chip is used / stressed.

[0021] Counter 205 may be implemented using any suitable counter design, such as a ripple counter comprising a series of edge-triggered latches, and operates on a reference clock signal. In operation, PSM 200 is comprised of SMU 180 ( Figure 1 ) controls to enable ring oscillators 201-204 and counter 205 for specified time periods measured by a reference clock, such as a system clock. Counter 205 counts the number of oscillations of the corresponding ring oscillator within a predetermined time period, thereby providing an indication of how much the speed of the corresponding ring oscillator has changed as various gate and device types degrade over time. The resulting value may be reported directly to SMU 180, or may be averaged or otherwise manipulated by digital logic circuitry before being reported.

[0022] Figure 3 FIG. 3 is a graph 300 showing exemplary degradation data obtained during high temperature operating life (HTOL) stress testing of a set of integrated circuits. Figure 4Describe the test process. In chart 300, the vertical axis shows the degradation that occurs as the Vmin amplitude increases, while the horizontal axis shows the number of hours of HTOL stress testing. A first curve chart is drawn, which shows the Vmin degradation of the SRAM on the integrated circuit. A second curve chart is drawn, which shows the degradation of the PSM circuit including the ring oscillator, thereby indicating how much additional voltage is required to obtain a specified ring oscillator frequency / count as the ring oscillator degrades over time. As described below, in the voltage calibration process of the present invention, a ring oscillator circuit similar to the ring oscillator circuit of PSM 200 is used, and the speed of the ring oscillator is measured by counting to identify the speed associated with each degradation point. The ring oscillator degradation is related to the SRAM degradation as shown on the chart, so that the runtime calibration process described below can predict the current degradation level and identify the low-end operating voltage of the SRAM.

[0023] Figure 4 4 is a flow chart 400 of a process for configuring a low-side operating voltage control process for a target integrated circuit according to some embodiments. For example, the process may be performed, for example, by accessing Figure 2 PSM 200 PSM circuit SMU 180 ( Figure 1 ) is executed under the control of ).

[0024] The process begins at block 402, where parts are selected to cover a range of process conditions. The selected parts typically include "corner" parts, which include various characteristics produced by semiconductor manufacturing at the ends of the allowed range of variation. Typical parts, i.e., parts in the center of the range of variation, may also be included. The tested parts are of the same model or design as the target integrated circuit, as further described below, for which the operating life prediction model will be deployed.

[0025] At block 404, the process begins by performing HTOL stress testing. HTOL stress testing is performed by stressing the integrated circuit with elevated temperatures, high voltages, and dynamic operations for a predetermined period of time (typically in the hundreds of hours, e.g., Figure 3 ) to simulate the manner in which degradation occurs over the expected operating life of the integrated circuit (e.g., 2 years or more).

[0026] During the HTOL test, the process of block 406 measures the speed of the ring oscillator circuit within a voltage and temperature range. This measurement is performed periodically throughout the HTOL test, as shown in the loop in flow chart 400. The voltage range used includes a sufficiently low operating voltage to determine the low-end operating voltage (Vmin) of various temperatures during the simulated life of the integrated circuit. The low-end voltage can be identified in any suitable manner, such as identifying the voltage at which the ring oscillator slows down to an acceptable speed or less. In this embodiment, speed measurement is completed by counting the oscillations within a specified time period measured by the clock speed. Such counts are obtained under the conditions of the low-end operating voltage measured in the test and at a higher voltage, so that the count can be used to identify the degradation amount when operating at a higher voltage.

[0027] At block 408 (which is also repeated during HTOL testing), the process measures the minimum operating voltage of the SRAM memory circuit within the integrated circuit. This measurement identifies the low-end operating voltage of the memory, which can be determined in any suitable manner, such as by reducing the voltage until an error is found, reducing the voltage until the memory slows down to below an acceptable speed, or measuring other characteristics of the memory at various voltage increments. The resulting data from block 408 is saved as a second set of SRAM low-end operating voltage data.

[0028] As shown in block 410, the process repeats blocks 406 and 408 multiple times during the HTOL test to obtain Figure 3 The degradation data over the simulated life of the integrated circuit is shown in FIG. 4. At block 412, a predictive model is created based on the data. In this embodiment, the predictive model includes the ring oscillator speed data in the form of count values ​​and data associated with the measurements of blocks 406 and 408 that allow predicted degradation levels to be identified based on the oscillation counts of the ring oscillator. The predicted degradation levels are preferably stored as expected low-end operating voltages associated with each data point of the speed data. In other embodiments, a mathematical model may be employed that takes the measured speed data or ring oscillator counts as input and has a low-end operating voltage limit as output. In those embodiments, block 412 includes curve matching the data to create a mathematical equation or model to convert the SRAM degradation data ( Figure 3 ) is related to the measured ring oscillator speed.

[0029] At block 414, the predictive model is deployed to a data processing system that includes the integrated circuit design that performs the HTOL test. The predictive model data is saved to the system, typically in non-volatile memory accessible by a system management controller such as SMU 180. The SMU is configured with software or firmware to perform low-end operating voltage adjustments during the life of the integrated chip.

[0030] Figure 55 is a flow chart of a process for adjusting the low-side operating voltage of an integrated circuit. In this embodiment, the process is performed during "mission mode" or deployment operation of the integrated circuit and is managed under firmware control by a system management processor such as SMU 180. Other embodiments may control the process with suitable digital circuitry.

[0031] The process begins at block 502, where the number of oscillations of at least one ring oscillator on the target integrated circuit during a specified clock cycle is counted. Figure 2 The more than one ring oscillator with different gate types and different device types performs counting. In this embodiment, counting is performed by enabling the PSM circuit including the ring oscillator and receiving the resulting count value from a counter such as counter 205 connected to the ring oscillator.

[0032] At block 504 , based on the number of oscillations, the process accesses a predictive model and selects a low-side operating voltage for a processor on the target integrated circuit from the model.

[0033] At block 506, the process sets the low end operating voltage of the processor based on the selected low end operating voltage and then operates the processor. This voltage adjustment may be performed for other circuits besides the processor and for multiple voltage domains where the SRAM is present. For example, if the SDF 125 operates in a separate voltage domain, a separate adjustment may be made to that domain. In addition, the process sets the voltage or Vmin operating voltage as the low end, but the processor may of course change the operating voltage to above the minimum value during operation based on performance requirements and other relevant conditions (such as temperature).

[0034] At block 508, the process repeats blocks 502 through 506 multiple times during operation of the data processing system. For example, the blocks may be repeated at boot time and at selected intervals during operation of the host data processing system after it has been booted or reset.

[0035] Figure 1The APU 100 or any portion thereof (such as the SMU 180) may be described or represented by a computer accessible data structure in the form of a database or other data structure that can be read by a program and used directly or indirectly to manufacture an integrated circuit. For example, the data structure may be a behavioral level description or a register transfer level (RTL) description of hardware functionality in a high-level design language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool, which may synthesize the description to produce a netlist including a list of gates from a synthesis library. The netlist includes a set of gates that also represent the functionality of the hardware comprising the integrated circuit. The netlist may then be placed and routed to produce a data set describing the geometry to be applied to the mask. The mask may then be used in various semiconductor manufacturing steps to produce the integrated circuit. Alternatively, the database on the computer accessible storage medium may be a netlist (with or without a synthesis library) or a data set (as desired) or a Graphic Data System (GDS) II data.

[0036] As can be understood from this disclosure, the above techniques provide a mission mode calibration cycle to dynamically determine the correct amount of Vmin compensation to be added at any desired time during the use of the chip based on the actual use conditions and degradation of each given chip. This greatly improves power efficiency under Vmin limited operation for most of the life of most parts.

[0037] In various embodiments, the techniques herein can be used with any suitable system that employs a large capacity memory expansion module (e.g., media servers and data processing platforms.) In addition, the above techniques are widely applicable to use with processors implemented with CPUs and accelerated processors, including memory-centric architectures in which memory expansion devices are connected to the processor via a high-speed bus or communication link.

[0038] Although specific embodiments have been described, various modifications to these embodiments will be apparent to those skilled in the art. For example, a predictive model may include Figure 4 The data obtained from the tests described in the , or may include a mathematical model based on the results of such tests that maps the speed measurements of the oscillator to the predicted Vmin of the SRAM circuitry. Therefore, the appended claims are intended to cover all modifications of the disclosed embodiments that fall within the scope of the disclosed embodiments.

Claims

1. A method for configuring a low-end operating voltage control process for a target integrated circuit, the method comprising: Performing a high temperature operating life (HTOL) stress test on a group of integrated circuits having the same model as the target integrated circuit, and saving a first group of device degradation data obtained; During the HTOL stress test, measuring the low-end operating voltage of the static random access memory SRAM on the group of integrated circuits, and saving the obtained second group of SRAM low-end operating voltage data; generating a prediction model associated with the first set of device degradation data and the second set of SRAM low-end operating voltage data; The prediction model is deployed to a data processing system including the target integrated circuit, and the target integrated circuit is configured to: (a) counting the number of oscillations of at least one ring oscillator on the target integrated circuit during a specified clock cycle; (b) based on the number of oscillations, accessing the prediction model and selecting a low-end operating voltage limit for a processor on the target integrated circuit from the prediction model; (c) setting the low-end operating voltage of the processor based on the low-end operating voltage limit; and (d) Repeating paragraphs (a) through (c) a plurality of times during operation of the data processing system.

2. The method of claim 1, wherein the HTOL stress test comprises counting oscillations of at least one ring oscillator on each integrated circuit in the group of integrated circuits under varying temperature, voltage, and aging conditions.

3. The method of claim 1 , wherein the HTOL stress test comprises counting oscillations at a plurality of ring oscillators located in different regions on each integrated circuit in the group of integrated circuits under varying temperature, voltage, and aging conditions. 4 . The method of claim 3 , wherein the plurality of ring oscillators comprises a first ring oscillator comprising a first series of logic gates and a second ring oscillator comprising a series of logic gates different from the first series.

5. The method of claim 3 , wherein the plurality of ring oscillators comprises a first ring oscillator comprising a first series of logic gates constructed using transistors of a first type, and a second ring oscillator comprising a series of logic gates constructed using transistors of a second type different from the first type.

6. A method for adjusting a low-end operating voltage of an integrated circuit, comprising: (a) counting the number of oscillations of at least one ring oscillator on the integrated circuit during a specified clock cycle; (b) based on the number of oscillations, accessing a prediction model associated with a first set of device degradation data provided from a high temperature operating life (HTOL) stress test of a group of integrated circuits having the same design as the integrated circuit and a second set of static random access memory (SRAM) low side operating voltage data provided by measuring low side operating voltages of SRAM memories on the group of integrated circuits during the HTOL stress test, and selecting a low side operating voltage limit for a processor on the integrated circuit from the prediction model; (c) setting the low-end operating voltage of the processor based on the low-end operating voltage limit; and (d) Repeating paragraphs (a) through (c) a plurality of times during operation of the processor. 7 . The method of claim 6 , wherein counting the number of oscillations of at least one ring oscillator further comprises counting oscillations at a plurality of ring oscillators located in different portions of the integrated circuit.

8. The method according to claim 7, wherein counting the number of oscillations of at least one ring oscillator further comprises: Oscillations at a first ring oscillator comprising a first series of logic gates are counted, and oscillations at a second ring oscillator comprising a series of logic gates different from the first series are counted.

9. The method of claim 7 , wherein counting the number of oscillations of at least one ring oscillator further comprises counting oscillations at a first ring oscillator and a second ring oscillator, the first ring oscillator comprising a first series of logic gates constructed with transistors of a first type, and the second ring oscillator comprising a series of logic gates constructed with transistors of a second type different from the first type.

10. The method of claim 6, wherein accessing the predictive model comprises accessing the first set of device degradation data.

11. The method of claim 6, wherein accessing the prediction model comprises accessing the second set of SRAM low-side operating voltage data.

12. The method of claim 6, wherein accessing the prediction model comprises first accessing the first set of device degradation data, and based on the results obtained therefrom, accessing the second set of SRAM low-side operating voltage data.

13. An integrated circuit comprising: Processor core; A system management unit, the system management unit setting the voltage level at which the processor core operates, the system management unit being operable to adjust the low-end operating voltage of the processor core by the following steps: (a) obtaining an oscillation count of at least one ring oscillator on the integrated circuit during a specified clock cycle; (b) based on the count, accessing a prediction model associated with a first set of device degradation data provided from a high temperature operating life (HTOL) stress test of a group of integrated circuits having the same design as the integrated circuit and a second set of static random access memory (SRAM) low side operating voltage data provided by measuring low side operating voltages of SRAM memories on the group of integrated circuits during the HTOL stress test, and selecting a low side operating voltage limit for the processor core from the model; (c) setting the low-end operating voltage of the processor core based on the low-end operating voltage limit; and (d) Repeating paragraphs (a) to (c) a plurality of times during operation of the integrated circuit.

14. The integrated circuit of claim 13, wherein the at least one ring oscillator comprises a plurality of ring oscillators located in different portions of the integrated circuit.

15. The integrated circuit of claim 14, wherein the plurality of ring oscillators comprises a first ring oscillator comprising a first series of logic gates and a second ring oscillator comprising a series of logic gates different from the first series.

16. The integrated circuit of claim 14, wherein the plurality of ring oscillators comprises a first ring oscillator comprising a first series of logic gates constructed using transistors of a first type, and a second ring oscillator comprising a series of logic gates constructed using transistors of a second type different from the first type.

17. The integrated circuit of claim 13, wherein accessing the predictive model comprises accessing the first set of device degradation data.

18. The integrated circuit of claim 13, wherein accessing the predictive model comprises accessing the second set of SRAM low-side operating voltage data.

19. The integrated circuit of claim 13, wherein accessing the predictive model comprises first accessing the first set of device degradation data, and based on results obtained therefrom, accessing the second set of SRAM low-side operating voltage data.

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