Satellite signal receiving apparatus, control method thereof, satellite signal processing apparatus, and electronic device
By using an intermittently driven receiving channel and sampling clock output circuit, the problem of excessive power consumption in multi-GNSS satellite signal receivers was solved, achieving power saving and improved positioning performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEIKO EPSON CORP
- Filing Date
- 2023-02-20
- Publication Date
- 2026-06-05
AI Technical Summary
While existing multi-GNSS satellite signal receiving devices improve positioning accuracy and expand the positioning area, they also suffer from increased power consumption.
The first and second receiving channels are driven intermittently. Combined with the sampling clock output circuit, the first and second GNSS signals are processed by the control circuit. The first and second RF receiving circuits and the baseband processing circuit are used for intermittent driving to reduce unnecessary power consumption.
It effectively suppressed power consumption while ensuring the ability to process multiple GNSS signals, thereby improving positioning accuracy and the locationable area.
Smart Images
Figure CN116626708B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to, for example, satellite signal receiving devices, satellite signal processing devices, control methods for satellite signal receiving devices, and electronic devices. Background Technology
[0002] GPS (Global Positioning System) is a well-known positioning system, and is mostly integrated into portable or small electronic devices that operate on batteries, thus requiring low power consumption. Therefore, a technique has been proposed to suppress power consumption by intermittently driving an RF receiving circuit that receives satellite signals and a baseband processing circuit that processes the satellite signals received by the RF receiving circuit (see, for example, Patent Document 1).
[0003] Positioning systems are generally referred to as Global Navigation Satellite Systems (GNSS). GPS, mentioned above, is also a type of GNSS. Other known systems include Beidou, GLONASS, and Galileo.
[0004] In recent years, satellite signal receiving devices that combine multiple GNSS technologies and correspond to so-called multi-GNSS (e.g., see Patent Document 2, in particular) have been proposed. Figure 7 (Records).
[0005] Patent Document 1: Japanese Patent Application Publication No. 2013-228250
[0006] Patent Document 2: Japanese Patent Application Publication No. 2017-173046
[0007] In the satellite signal receiving device corresponding to multiple GNSS described in Patent Document 2, it is possible to obtain signals from more satellites, which is expected to improve positioning accuracy and expand the positioning area. However, on the other hand, there is the problem of increased power consumption. Summary of the Invention
[0008] One aspect of the satellite signal receiving apparatus disclosed herein includes: a first receiving channel for processing a first satellite signal of a first GNSS; a second receiving channel for processing a second satellite signal of a second GNSS; and a sampling clock output circuit that receives a reference clock and outputs a sampling clock. The first receiving channel has: a first RF receiving circuit capable of intermittently driving a repeated on / off operation, wherein if the on operation is performed, the first satellite signal received by a first receiving antenna is down-converted to output a first intermediate signal; and a first baseband processing circuit that processes the first intermediate signal according to the reference clock. The second receiving channel has: a second RF receiving circuit capable of performing the intermittent driving, wherein if the on operation is performed, the second satellite signal received by a second receiving antenna is down-converted to output a second intermediate signal; and a second baseband processing circuit that processes the second intermediate signal according to the sampling clock. Attached Figure Description
[0009] Figure 1 This is a diagram showing a schematic structure of a satellite signal receiving device according to an embodiment.
[0010] Figure 2 This is a diagram showing the structure of a satellite signal receiving device.
[0011] Figure 3 This is a diagram showing the structure of the first PLL circuit in the first RF receiving circuit.
[0012] Figure 4 This is a diagram showing the structure of the second PLL circuit in the second RF receiving circuit.
[0013] Figure 5 This is a diagram showing the structure of the sampling clock output circuit in a satellite signal receiving device.
[0014] Figure 6 This is a diagram illustrating the operation of a satellite signal receiving device according to an embodiment.
[0015] Figure 7 This is a diagram illustrating the operation of a satellite signal receiving device according to an embodiment.
[0016] Figure 8 This is a diagram showing the structure of the RF receiving circuit of the satellite signal receiving device of the first comparative example.
[0017] Figure 9 This is a diagram showing the structure of the RF receiving circuit of the satellite signal receiving device of the second comparative example.
[0018] Figure 10 This is a diagram showing a schematic structure of a modified satellite signal processing device.
[0019] Figure 11 This is a diagram showing the structure of a modified satellite signal processing device.
[0020] Figure 12 This is a diagram showing the structure of an electronic device with a satellite signal receiving device.
[0021] Label Explanation
[0022] 1: Electronic clock; 10: Satellite signal receiving device; 11: First receiving channel; 12: Second receiving channel; 104: Sampling clock output circuit; 110: First RF receiving circuit; 113: First frequency divider circuit; 114: First PLL circuit; 115: First mixing circuit; 117: First baseband processing circuit; 120: Second RF receiving circuit; 123: Second frequency divider circuit; 124: Second PLL circuit; 127: Second baseband processing circuit. Detailed Implementation
[0023] Hereinafter, a satellite signal receiving apparatus according to an embodiment of the present invention will be described with reference to the accompanying drawings.
[0024] Furthermore, the embodiments described below are preferred examples, and therefore various technically preferred limitations are attached. However, unless the spirit of the invention is specifically limited in the following description, the scope of the invention is not limited to these methods.
[0025] Figure 1 This is a diagram illustrating the structure of the satellite signal receiving device 10, control circuit 50, first receiving antenna 111, and second receiving antenna 121 according to an embodiment. The satellite signal receiving device 10 shown in this figure is a multi-GNSS receiver capable of performing positioning based on multiple satellite positioning systems.
[0026] As shown in the figure, the satellite signal receiving device 10 includes a first receiving channel 11, a second receiving channel 12, an oscillation circuit 102, and a sampling clock output circuit 104.
[0027] The oscillation circuit 102 generates a reference clock Clk_o and provides this reference clock Clk_o to the first receiving channel 11, the second receiving channel 12, and the sampling clock output circuit 104. Preferably, the oscillation circuit 102 incorporates a compensation circuit with characteristics opposite to those of a quartz oscillator, resulting in a temperature-compensated quartz oscillator with good frequency characteristics over a wide temperature range for the reference clock Clk_o.
[0028] The first receiving antenna 111 receives a first satellite signal from one of the multiple satellite positioning systems that the satellite signal receiving device 10 can utilize, such as a GPS satellite signal. The second receiving antenna 121 receives a second satellite signal from one of the multiple satellite positioning systems that the satellite signal receiving device 10 can utilize, which is different from the first satellite signal, such as a GLONASS satellite signal.
[0029] The sampling clock output circuit 104 takes a reference clock Clk_o as input and generates a sampling clock Clk_s based on the reference clock Clk_o, which is then provided to the second receiving channel 12. Alternatively, the sampling clock output circuit 104 may be a PLL (Phase Locked Loop) circuit that outputs the sampling clock Clk_s in phase synchronization with the reference clock Clk_o, as detailed later.
[0030] The first receiving channel 11 down-converts the frequency of the first satellite signal received by the first receiving antenna 111 to an intermediate frequency and digitizes it. After storing the digitized signal in a memory, it is processed. In addition, the first receiving channel 11 receives a reference clock Clk_o, and performs the conversion to the intermediate frequency and the processing of the digitized signal based on the reference clock Clk_o.
[0031] Furthermore, some elements of the first receiving channel 11 are controlled by the control circuit 50 to be either normally driven or intermittently driven. Normal drive refers to a mode in which power is always supplied, thus enabling the on-state operation, while intermittent drive refers to a mode used to alternately and repeatedly perform the on-state operation of being supplied with power and the off-state operation of being cut off power to reduce power consumption.
[0032] The second receiving channel 12 down-converts the frequency of the second satellite signal received by the second receiving antenna 121 to an intermediate frequency and digitizes it. After storing the digitized signal in a memory, it is processed. In addition, the second receiving channel 12 receives a reference clock Clk_o, performs the conversion to the intermediate frequency based on the reference clock Clk_o, and processes the digitized signal based on the sampling clock Clk_s.
[0033] In addition, some elements of the second receiving channel 12 are controlled by the control circuit 50 to be normally driven or intermittently driven.
[0034] Based on the processing results of the first receiving channel 11 and / or the second receiving channel 12, the control circuit 50 uses the current position or time to enable the display device (not shown) to display, or to correct the internal clock.
[0035] Furthermore, the control circuit 50 controls the driving of the first receiving channel 11 based on the processing results of the first receiving channel 11, specifically, based on the receiving status of the first satellite signal in the first receiving antenna 111, etc. The control circuit 50 controls the driving of the second receiving channel 12 based on the processing results of the second receiving channel 12, specifically, based on the receiving status of the second satellite signal in the second receiving antenna 121, etc.
[0036] For example, if the reception status of the first receiving antenna 111 is good, sufficient position information can be obtained solely from the first satellite signal. Therefore, the control circuit 50 intermittently drives or disconnects certain elements of the second receiving channel 12. Conversely, if the reception status of the first receiving antenna 111 is poor or unreceived, the control circuit 50 intermittently drives or disconnects certain elements of the first receiving channel 11, while the second receiving channel 12 is normally driven, attempting to obtain position information via the second satellite signal.
[0037] Figure 2 This is a block diagram showing the structure of the satellite signal receiving device 10, and in particular the structure of the first receiving channel 11 and the second receiving channel 12.
[0038] As shown in the figure, the first receiving channel 11 includes a first RF receiving circuit 110, an AD conversion circuit 116, and a first baseband processing circuit 117. The first RF receiving circuit 110 includes an amplifier circuit 112, a first frequency divider circuit 113, a first PLL circuit 114, and a first mixing circuit 115.
[0039] The first frequency divider circuit 113 divides the reference clock Clk_o and outputs the divided signal as the first clock Clk_1.
[0040] The first PLL circuit 114 outputs a first local signal Lo_1 that is phase-synchronized with the first clock Clk_1. Each element in the first PLL circuit 114 operates when the control circuit 50 specifies an on-time action, and the power supply is cut off and the operation stops when the control circuit 50 specifies an off-time action.
[0041] Amplifier circuit 112 amplifies the first satellite signal received by the first receiving antenna 111. First mixing circuit 115 mixes (multiplies) the output signal of amplifier circuit 112 and the first local signal Lo_1 of first PLL circuit 114, thereby downconverting it to an intermediate frequency and outputting it as the first intermediate signal If_1.
[0042] The AD conversion circuit 116 converts the analog first intermediate signal If_1 into a digital signal. The first baseband processing circuit 117 is a baseband processing unit that performs processing using a reference clock Clk_o. Specifically, the first baseband processing circuit 117 stores the digitized first intermediate signal If_1 in a memory with a predetermined capacity, generates a copy code corresponding to the type of GNSS corresponding to the first satellite signal and the satellite being received, and performs correlation processing between the first intermediate signal If_1 stored in the memory and the generated copy code.
[0043] The second receiving channel 12, like the first receiving channel 11, includes a second RF receiving circuit 120, an AD conversion circuit 126, and a second baseband processing circuit 127. The second RF receiving circuit 120 includes an amplifier circuit 122, a second frequency divider circuit 123, a second PLL circuit 124, and a second mixing circuit 125.
[0044] The second frequency divider circuit 123 divides the reference clock Clk_o and outputs the divided signal as the second clock Clk_2. The second PLL circuit 124 outputs a second local signal Lo_2 that is phase-synchronized with the second clock Clk_2.
[0045] Each element in the second PLL circuit 124 operates when the control circuit 50 specifies an on-action, and the power is cut off and the operation stops when the control circuit 50 specifies an off-action.
[0046] Amplifier circuit 122 amplifies the second satellite signal received by the second receiving antenna 121. Second mixing circuit 125 mixes (multiplies) the output signal of amplifier circuit 122 and the second local signal Lo_2 of second PLL circuit 124, thereby downconverting it to an intermediate frequency, which is then output as the second intermediate signal If_2.
[0047] The AD conversion circuit 126 converts the analog second intermediate signal If_2 into a digital signal. The second baseband processing circuit 127 is a baseband processing unit that performs processing using the sampling clock Clk_s. It stores the digitized second intermediate signal If_2 in a memory with a specified capacity, generates a copy code corresponding to the type of GNSS corresponding to the second satellite signal and the satellite being received, and performs related processing on the second intermediate signal If_2 stored in the memory and the generated copy code.
[0048] The control circuit 50 controls the driving of the first PLL circuit 114 in the first receiving channel 11 and / or the second PLL circuit 124 in the second receiving channel 12 based on the receiving status of the first satellite signal obtained during the correlation processing of the first baseband processing circuit 117 and / or the receiving status of the second satellite signal obtained during the correlation processing of the second baseband processing circuit 127.
[0049] Figure 3 This is a block diagram showing the structure of the first PLL circuit 114. As shown in the figure, the first PLL circuit 114 includes a phase frequency detector (PFD) 1141, a charge pump (CP) circuit 1142, a low-pass filter (LPF) 1143, a voltage-controlled oscillator (VCO) circuit 1144, and a divider circuit 1145.
[0050] Phase-frequency comparator circuit 1141 compares the phase of the first clock Clk_1 with the phase of the first reference signal Ref_1 output from frequency divider circuit 1145, and outputs a pulse signal of voltage corresponding to the phase difference. Charge pump circuit 1142 converts the voltage of the pulse signal output from phase-frequency comparator circuit 1141 into current. Low-pass filter 1143 converts the current output from charge pump circuit 1142 into voltage and smooths it. Voltage-controlled oscillator circuit 1144 generates a signal with a frequency corresponding to the voltage output from low-pass filter 1143, and outputs it as the first local signal Lo_1. Frequency divider circuit 1145 divides the first local signal Lo_1, and feeds the divided signal back to phase-frequency comparator circuit 1141 as the first reference signal Ref_1.
[0051] Therefore, in the first PLL circuit 114, the oscillation in the voltage-controlled oscillator circuit 1144 is controlled in a way that eliminates the frequency difference between the first clock Clk_1 and the first reference signal Ref_1. Thus, the frequency of the first local signal Lo_1 becomes the frequency after doubling the frequency of the first clock Clk_1, and the first local signal Lo_1 is output synchronously with the first clock Clk_1.
[0052] Figure 4 This is a block diagram showing the structure of the second PLL circuit 124. As shown in the figure, the second PLL circuit 124, like the first PLL circuit 114, includes a phase-frequency comparison circuit 1241, a charge pump circuit 1242, a low-pass filter 1243, a voltage-controlled oscillator circuit 1244, and a frequency divider circuit 1245.
[0053] Therefore, in the second PLL circuit 124, the oscillation in the voltage-controlled oscillator circuit 1244 is controlled in a way that eliminates the frequency difference between the second clock Clk_2 and the second reference signal Ref_2 output from the frequency divider circuit 1245. As a result, the frequency of the second local signal Lo_2 output from the voltage-controlled oscillator circuit 1244 becomes the frequency after doubling the frequency of the second clock Clk_2, and the second local signal Lo_2 is output synchronously with the second clock Clk_2.
[0054] Figure 5 This is a block diagram showing the structure of the sampling clock output circuit 104. As shown in the figure, the sampling clock output circuit 104, like the first PLL circuit 114, includes a phase-frequency comparison circuit 1041, a charge pump circuit 1042, a low-pass filter 1043, a voltage-controlled oscillator circuit 1044, and a frequency divider circuit 1045.
[0055] Therefore, in the sampling clock output circuit 104, the oscillation in the voltage-controlled oscillator circuit 1044 is controlled in a way that eliminates the frequency difference between the reference clock Clk_o and the reference signal Ref_o output from the frequency divider circuit 1045. As a result, the frequency of the sampling clock Clk_s output from the voltage-controlled oscillator circuit 1044 becomes the frequency after doubling the frequency of the reference clock Clk_o, and the sampling clock Clk_s is output synchronously with the reference clock Clk_o.
[0056] Figure 6 as well as Figure 7 This is a diagram showing the relationship between the first clock Clk_1, which is the input, and the first local signal Lo_1, which is the output, in the first PLL circuit 114.
[0057] Figure 6 This diagram illustrates the relationship between the first clock Clk_1 and the first local signal Lo_1 during normal operation or when the on-state action is active. As shown in the diagram, during normal operation, the first local signal Lo_1 is provided synchronously with the first clock Clk_1.
[0058] Figure 7 This diagram illustrates the relationship between the first clock Clk_1 and the first local signal Lo_1 during intermittent driving, which involves repeated on / off actions. As shown in the figure, during normal driving, the first local signal Lo_1 is supplied synchronously with the first clock Clk_1.
[0059] also, Figure 6 as well as Figure 7The downward-pointing triangle in the diagram indicates the timing of the first clock Clk_1 rising from level L to level H when the first PLL circuit 114 is configured to activate in either normal or intermittent drive mode. In other words, the triangle is used to indicate the synchronization of the first local signal Lo_1 with respect to the first clock Clk_1.
[0060] Furthermore, in the second PLL circuit 124, the relationship between the second clock Clk_2, which serves as the input, and the second local signal Lo_2, which serves as the output, is also related to... Figure 6 as well as Figure 7 same.
[0061] Frequency divider circuits such as the first frequency divider circuit 113, the second frequency divider circuit 123, and frequency divider circuits 1045, 1145, and 1245 are generally constructed by cascading multiple counters. In this structure, after the input clock signal or other signal, a signal delayed by several cycles is output as the divided frequency signal. Therefore, even when transitioning from an off-state to an on-state operation, the frequency-divided signal cannot be output immediately after the input clock signal or other signal.
[0062] In this embodiment, even if the first frequency divider circuit 113 and the second frequency divider circuit 123 become disconnected during intermittent operation, the power supply is not cut off, and the frequency division operation continues. Therefore, even if the first PLL circuit 114 becomes disconnected, the first clock Clk_1 is continuously output from the first frequency divider circuit 113. Similarly, even if the second PLL circuit 124 becomes disconnected, the second clock Clk_2 is continuously output from the second frequency divider circuit 123.
[0063] On the other hand, in the frequency divider circuit 1045 included in the first PLL circuit 114, when it is in an off-state operation, the power supply is cut off, thus interrupting the frequency division operation. Therefore, even when transitioning from an off-state operation to an on-state operation, the first reference signal Ref_1, serving as the frequency-divided clock, is not immediately output. Similarly, in the frequency divider circuit 1245 included in the second PLL circuit 124, when it is in an off-state operation, the power supply is cut off, thus interrupting the frequency division operation. Therefore, even when transitioning from an off-state operation to an on-state operation, the second reference signal Ref_2, serving as the frequency-divided clock, is not immediately output.
[0064] However, in the phase-frequency comparison circuit 1141, immediately after transitioning from an off operation to an on operation, a pulse signal is output that corresponds to the voltage difference between the phase of the first clock Clk_1, which was also continuously output during the off operation, and the phase of the first reference signal Ref_1, which was not immediately output. Therefore, in the first PLL circuit 114, even when transitioning from an off operation to an on operation, such as Figure 7As shown, the first local signal Lo_1 based on the pulse signal is also output immediately in sync with the first clock Clk_1, specifically in sync with the rise timing of the first clock Clk_1.
[0065] Similarly, for the second PLL circuit 124, even immediately after changing from an off action to an on action, the second local signal Lo_2 is output in sync with the rising timing of the second clock Clk_2.
[0066] The sampling clock output circuit 104 is the same PLL circuit as the first PLL circuit 114 and the second PLL 124, but because it is always powered, it will not be disconnected. Therefore, the sampling clock Clk_s is always output regardless of the operating mode.
[0067] Furthermore, the frequency of the sampling clock Clk_s is approximately 1 / 10 of the frequency of the reference clock Clk_o. Compared to the power consumption suppressed by intermittently driving the first PLL circuit 114 and the second PLL circuit 124, the power consumed by normally driving the sampling clock output circuit 104 is negligible.
[0068] Thus, in this embodiment, power consumption can be suppressed by intermittently driving the first PLL circuit 114 in the first receiving channel 11 and the second PLL circuit 124 in the second receiving channel 12. Furthermore, since a local signal is output immediately when transitioning from a disconnection to a connection during intermittent driving, delays in the first baseband processing circuit 117 and the second baseband processing circuit 127 can be suppressed.
[0069] Next, the advantages of this embodiment over the comparative example will be explained.
[0070] Figure 8 This is a diagram showing the structure of the satellite signal receiving device 10b of the first comparative example. The satellite signal receiving device 10b includes a first receiving channel 11 capable of intermittent operation, but can only correspond to one GNSS.
[0071] Figure 9 This is a diagram showing the structure of the satellite signal receiving device 10c of the second comparative example. It is the same as the embodiment and the first comparative example in having a first receiving channel 11 corresponding to the first GNSS, but it is the same as the embodiment in having a second receiving channel 12c corresponding to the second GNSS, unlike the first comparative example.
[0072] In the second comparative example, the frequency divider circuit 128 divides the second local signal Lo_2 of the second PLL circuit 124 in the second receiving channel 12c, and outputs the divided signal as the sampling clock Clk_s.
[0073] In this structure, in the second receiving channel 12c, when the second PLL circuit 124 is in the off position, the second local signal Lo_2 is not output. Therefore, even when the operation changes from off to on, the frequency divider circuit 128 cannot immediately output the sampling clock Clk_s, so the second receiving channel 12c is not suitable for intermittent driving.
[0074] In contrast, in this embodiment, intermittent driving can be performed in either the first receiving channel 11 or the second receiving channel 12, and a local signal can be output immediately when the action changes from disconnection to connection during intermittent driving.
[0075] Furthermore, while GPS is exemplified as the first GNSS and GLONASS as the second GNSS in this embodiment, it can also be applied to other satellite positioning systems, such as Galileo and BeiDou. Alternatively, it can be configured to provide a third receiving channel and divide the reference clock Clk_o using a separately provided frequency divider circuit, using the divided signal as a sampling clock to process the third intermediate signal obtained by reducing the third satellite signal to an intermediate frequency. In this way, two or more receiving channels are sufficient.
[0076] exist Figure 1 and Figure 2 The diagram illustrates the structure of a satellite signal receiving device 10, including a first baseband processing circuit 117 and a second baseband processing circuit 127. This structure is not limited to this one; any structure that, during intermittent operation, inputs a reference clock Clk_o to the RF receiving sections of the first RF receiving circuit 110 and the second RF receiving circuit 120, and inputs a sampling clock corresponding to the reference clock Clk_o to the first baseband processing circuit 117 and the second baseband processing circuit 127, is acceptable. For example, as shown... Figure 10 and Figure 11 As shown, the control unit 50, which controls the intermittent driving of the first RF receiving circuit 110 and the second RF receiving circuit 120, may also include a first baseband processing circuit 117 and a second baseband processing circuit 127, treating the satellite signal receiving device 10 and the control unit 50 as a satellite signal processing device. Additionally, a reference clock Clk_o and a sampling clock Clk_s are input to the control unit 50.
[0077] Next, the electronic equipment of the satellite signal receiving device 10 with the embodiment will be described.
[0078] Figure 12 This is a block diagram showing the circuit structure of an electronic clock 1, which is an example of an electronic device.
[0079] In addition to the satellite signal receiving device 10, control circuit 50, first receiving antenna 111, and second receiving antenna 121 of the embodiment, the electronic clock 1 also has a timing device 171, a storage device 172, an input device 173, a drive mechanism 181, and a display device 182.
[0080] The control circuit 50 in the electronic clock 1 is a processor such as a CPU (Central Processing Unit). By executing various programs stored in the storage device 172, in addition to constructing the function of intermittently driving the first receiving channel 11 and the second receiving channel 12 in the satellite signal receiving device 10, it also constructs the following functions.
[0081] That is, in the control circuit 50, in addition to the receiving control unit 51 which functions as the intermittent drive of the first receiving channel 11 and the second receiving channel 12 in the satellite signal receiving device 10, a time zone setting unit 52, a time correction unit 53 and a display control unit 54 are also constructed.
[0082] The time zone setting unit 52 sets the time zone data based on the location information obtained from the processing results of the satellite signal receiving device 10. The time correction unit 53 corrects the time data based on the time information obtained from the processing results of the satellite signal receiving device 10 and the time zone data set by the time zone setting unit 52. The display control unit 54 controls the operation of the drive mechanism 181 and controls the display content of the display device 182.
[0083] The timing device 171 includes, for example, a quartz oscillator, and uses a reference signal based on the oscillation signal of the quartz oscillator to update the time data. The input device 173 is, for example, an operating element such as a button or a lever. The operating signal generated by operating the element is provided to the control circuit 50.
[0084] Furthermore, while an electronic device with a satellite signal receiving device 10 has been described here, it can also be described as having... Figure 10 and Figure 11 The satellite signal processing device shown is implemented using electronic equipment.
[0085] Although electronic clock 1 was described as an example of an electronic device, electronic devices are not limited to electronic clock 1. Other examples of electronic devices include wearable terminals, smartphones, tablet terminals, portable navigation devices, car navigation devices, personal computers, etc.
[0086] <Postscript>
[0087] Based on the above description, the preferred embodiments of this disclosure can be understood, for example, as follows. It should be noted that, for ease of understanding, the reference numerals in the accompanying drawings are shown in parentheses below, but this is not intended to limit the invention to the illustrated embodiments.
[0088] <Postscript 1>
[0089] A satellite signal receiving device (10) in one mode (mode 1) includes: a first receiving channel (11) for processing a first satellite signal of a first GNSS; a second receiving channel (12) for processing a second satellite signal of a second GNSS; and a sampling clock output circuit (104) that takes a reference clock (Clk_o) as input and outputs a sampling clock (Clk_s). The first receiving channel (11) has: a first RF receiving circuit (110) capable of intermittently driving repeated on and off actions, wherein if an on action is performed, the first satellite signal received by the first receiving antenna (111) is processed by the second satellite signal of the third GNSS. The satellite signal is down-converted to output a first intermediate signal (If_1); and a first baseband processing circuit (117) processes the first intermediate signal (If_1) according to a reference clock (Clk_o). The second receiving channel (12) has: a second RF receiving circuit (120) capable of intermittent driving, which, if on, down-converts the second satellite signal received by the second receiving antenna (121) to output a second intermediate signal (If_2); and a second baseband processing circuit (127) processing the second intermediate signal (If_2) according to a sampling clock (Clk_s).
[0090] According to mode 1, even if the first RF receiving circuit (110) and the second RF receiving circuit (120) are disconnected, the reference clock (Clk_o) and the sampling clock (Clk_s) do not stop, so intermittent driving can be performed appropriately.
[0091] <Appendix 2>
[0092] In the satellite signal receiving device (10) of the specific method 2 of method 1, the first RF receiving circuit (110) includes: a first frequency divider circuit (113), which outputs a first clock (Clk_1) obtained by dividing the reference clock (Clk_o); a first PLL circuit (114), which outputs a first local signal (Lo_1) that is phase-synchronized with the first clock (Clk_1); and a first mixing circuit (115), which mixes the signal based on the received first satellite signal and the first local signal (Lo_1) as a first The intermediate signal (If_1) output, the second RF receiving circuit (120) includes: a second frequency divider circuit (123), which outputs a second clock (Clk_2) obtained by dividing the reference clock (Clk_o); a second PLL circuit (124), which outputs a second local signal (If_2) that is phase-synchronized with the second clock (Clk_2); and a second mixing circuit (125), which mixes the signal based on the received second satellite signal and the second local signal (If_2) as a second intermediate signal (Lo_2) output.
[0093] According to method 2, a first RF receiving circuit (11) and a second RF receiving circuit (12) are specifically configured.
[0094] <Appendix 3>
[0095] In the satellite signal receiving device (10) of the specific method 3 of method 2, when the first RF receiving circuit (110) is disconnected, the power supply of the first PLL circuit (114) is cut off, and when the second RF receiving circuit (120) is disconnected, the power supply of the second PLL circuit (124) is cut off.
[0096] According to method 3, when the first RF receiving circuit (110) is disconnected, power consumption is suppressed by cutting off the power supply of the first PLL circuit (114), and when the second RF receiving circuit (120) is disconnected, power consumption is suppressed by cutting off the power supply of the second PLL circuit (124).
[0097] <Appendix 4>
[0098] In the satellite signal receiving device (10) of the specific mode 4 of mode 3, even if the first RF receiving circuit (110) is disconnected, the power supply of the first frequency divider circuit (113) is not cut off, and even if the second RF receiving circuit (120) is disconnected, the power supply of the second frequency divider circuit (123) is not cut off.
[0099] According to method 4, even if the first RF receiving circuit (110) is disconnected, the power supply to the first frequency divider circuit (113) will not be cut off, thus outputting the first clock (Clk_1). Similarly, even if the second RF receiving circuit (120) is disconnected, the power supply to the second frequency divider circuit (123) will not be cut off, thus outputting the second clock (Clk_2). Therefore, an intermediate signal is output immediately when the operation changes from disconnected to connected.
[0100] <Appendix 5>
[0101] Another method (method 5) of satellite signal receiving device (10) includes: a sampling clock output circuit (104) that takes a reference clock (Clk_o) as input and outputs a sampling clock (Clk_s); a first RF receiving circuit (11) that takes the reference clock (Clk_o) as input and down-converts the received first satellite signal to output a first intermediate signal (Lo_1); a second RF receiving circuit (12) that takes the reference clock (Clk_o) as input and down-converts the received second satellite signal to output a second intermediate signal (Lo_2); and a control unit (50) that controls the intermittent driving of the first RF receiving circuit (11) and the second RF receiving circuit (12). The control unit (50) has: a first baseband processing circuit that takes the reference clock (Clk_o) as input and processes the first intermediate signal (Lo_1); and a second baseband processing circuit that takes the sampling clock as input and processes the second intermediate signal. According to method 5, intermittent driving can be appropriately performed.
[0102] <Appendix 6>
[0103] The control method of the satellite signal receiving device (10) of mode 6 includes a first receiving channel (11) for processing the first satellite signal of the first GNSS, a second receiving channel (12) for processing the second satellite signal of the second GNSS, and a sampling clock output circuit (104) that inputs a reference clock (Clk_o) and outputs a sampling clock (Clk_s). The first RF receiving circuit (110) capable of intermittently driving repeated on / off actions, if in an on / off action, controls the first receiving... The antenna (111) down-converts the first satellite signal received to output a first intermediate signal (Lo_1). The first baseband processing circuit (117) processes the first intermediate signal (Lo_1) according to the reference clock (Clk_o). If the second RF receiving circuit (120), which is capable of intermittent driving, is in operation, it down-converts the second satellite signal received by the second receiving antenna (121) to output a second intermediate signal (Lo_2). The second baseband processing circuit (127) processes the second intermediate signal (Lo_2) according to the sampling clock (Clk_s). According to mode 6, intermittent driving can be appropriately performed.
[0104] <Appendix 7>
[0105] The electronic device of method 7 has a satellite signal receiving device (10) of any one of methods 1 to 5. According to method 7, power consumption is suppressed by appropriate intermittent driving.
Claims
1. A satellite signal receiving device, characterized in that, The satellite signal receiving device includes: A first receiving channel is used to process a first satellite signal from a first GNSS; A second receiving channel is used to process the second satellite signals of the second GNSS; and The sampling clock output circuit takes a reference clock as input and outputs a sampling clock. The first receiving channel has: A first RF receiving circuit is capable of intermittently switching on and off. If the signal is switched on, it down-converts the first satellite signal received by the first receiving antenna and outputs a first intermediate signal. The first baseband processing circuit processes the first intermediate signal according to the reference clock. The second receiving channel has: The second RF receiving circuit is capable of performing the intermittent drive; if the on-action occurs, it down-converts the second satellite signal received by the second receiving antenna and outputs a second intermediate signal; and The second baseband processing circuit processes the second intermediate signal according to the sampling clock. The sampling clock output circuit is connected to the second baseband processing circuit. The sampling clock output circuit is always powered, thereby providing the sampling clock to the second baseband processing circuit regardless of the operation of the second RF receiving circuit.
2. The satellite signal receiving device according to claim 1, characterized in that, The first RF receiving circuit includes: The first frequency divider circuit outputs a first clock obtained by dividing the reference clock. A first PLL circuit outputs a first local signal synchronized with the phase of the first clock; and The first mixing circuit mixes the signal based on the received first satellite signal and the first local signal, and outputs it as the first intermediate signal. The second RF receiving circuit includes: The second frequency divider circuit outputs a second clock obtained by dividing the reference clock. The second PLL circuit outputs a second local signal that is phase-synchronized with the second clock; and The second mixing circuit mixes the signal based on the received second satellite signal and the second local signal to output the second intermediate signal.
3. The satellite signal receiving device according to claim 2, characterized in that, When the first RF receiving circuit performs the disconnection operation, the power supply to the first PLL circuit is cut off. When the second RF receiving circuit performs the disconnection operation, the power supply to the second PLL circuit is cut off.
4. The satellite signal receiving device according to claim 3, characterized in that, Even if the first RF receiving circuit is disconnected, the power supply to the first frequency divider circuit is not cut off. Even if the second RF receiving circuit is disconnected, the power supply to the second frequency divider circuit is not cut off.
5. An electronic device, characterized in that, The electronic device has a satellite signal receiving device as described in any one of claims 1 to 4.