Cloud gateway and method for network adapter and network adapter

Abstract

The application provides a cloud gateway, a method for a network adapter and the network adapter. The cloud gateway comprises a computing device and a network adapter connected to the computing device through a bus. The computing device comprises a plurality of processor cores configured to receive a sending message from the network adapter, process the sending message and return a resulting return message to the network adapter. The network adapter processes a message received from a network into a sending message and distributes the sending message among the plurality of processor cores on a message-by-message basis in a balanced manner, and sends the return message from the computing device in order. The cloud gateway according to the application combines the flexibility of a multi-core computing device and the high performance of a network adapter, and has better guarantee in terms of entry specification and service evolution.

Description

Technical Field

[0001] This invention relates to the field of network technology, and more specifically to a cloud gateway, a method for using a network adapter, and a network adapter. Background Technology

[0002] With the development of internet technology, cloud networks and cloud computing have gradually become important network infrastructure. As a network architecture based on cloud computing and virtualization technologies, cloud networks transform physical resources (such as servers, storage, and networks) into virtual resources via the internet and provide them to users as services. A cloud gateway, as a network device, primarily connects the local network to cloud services, providing a secure connection across the public internet. A cloud gateway can connect public cloud services from cloud service providers to an enterprise's local data center, enabling secure data transmission and management. The cloud gateway is the core forwarding node of the cloud network, characterized by statelessness and high throughput. Therefore, as the amount of data carried by cloud networks continues to increase, higher demands are placed on the processing capabilities of cloud gateways. Summary of the Invention

[0003] This application aims to provide a cloud gateway and a method for using a network adapter, as well as a network adapter that combines the flexibility of multi-core computing devices with the high performance of network adapters, providing better assurance in terms of table specifications and service evolution.

[0004] According to one aspect of this application, a cloud gateway is provided, including a computing device and a network adapter connected to the computing device via a bus, wherein:

[0005] The computing device includes a plurality of processor cores configured to receive uplink messages from the network adapter, the processor cores processing the uplink messages and returning the resulting return messages to the network adapter;

[0006] The network adapter processes the packets received from the network into upload packets and distributes them among the multiple processor cores in a balanced manner, and sends the return packets from the computing device out in order.

[0007] According to some embodiments, the network adapter includes:

[0008] The message scheduling module is used to distribute messages received from the network evenly among the multiple processor cores, and to attach a number to the message sent to the computing device, the return message containing the number;

[0009] The message ordering module is used to send the return messages from the computing device in the order in which the upload messages were sent to the computing device.

[0010] According to some embodiments, the message order preservation module is configured as follows:

[0011] A sliding window maintains message sequence information according to the uploading order of the uploaded messages, wherein the message sequence information includes the number of the uploaded message;

[0012] The window position of the return message is determined based on the number in the return message;

[0013] If the return message is located at the beginning position of the sliding window, the return message is sent out, and the sliding window is slid in the direction of increasing window position;

[0014] If the return message is located at a non-starting position of the sliding window, then after all the return messages on the side of the window position decreasing in the non-starting position have arrived and been sent out, the return message at the non-starting position is sent out, and the sliding window is slid in the direction of increasing window position.

[0015] According to some embodiments, the uploaded message contains only a message header and no message payload.

[0016] According to some embodiments, the network adapter further includes:

[0017] The parsing module is used to parse packets received from the network to extract the packet header and packet payload;

[0018] The payload caching module is used to store the message payload and the return message;

[0019] The reassembly module is used to reassemble the return message and the message payload for transmission.

[0020] According to some embodiments, the message sequence information also includes an acknowledgment identifier and a message upload timestamp.

[0021] According to some embodiments, the network adapter further includes:

[0022] The timeout polling module is used to periodically poll the message sequence information, compare the uploaded timestamp with the local clock, and when the difference between the uploaded timestamp and the local clock exceeds a threshold, confirm that the returned message has timed out and clear the information in the corresponding window.

[0023] According to some embodiments, the processor core is used to convert the uploaded message into a VxLAN encapsulated message.

[0024] According to some embodiments, the cloud gateway includes an internet gateway, a leased line gateway, and / or a virtual private cloud gateway.

[0025] According to some embodiments, the network adapter includes a network adapter implemented based on an FPGA.

[0026] According to another aspect of this application, a method for a network adapter is provided, the network adapter being connected via a bus to a computing device including multiple processor cores, the method comprising:

[0027] Messages received from the network are processed into upload messages, and the upload messages include a number;

[0028] The uploaded message is distributed message-by-message among the multiple processor cores in a balanced manner.

[0029] Receive a return message from the computing device, the return message containing the number;

[0030] The return message is sent out in the same order as the upload message sent to the computing device.

[0031] According to some embodiments, the return message is sent out in the order in which the uploaded messages were sent to the computing device, including:

[0032] A sliding window maintains message sequence information according to the uploading order of the uploaded messages, wherein the message sequence information includes the number of the uploaded message;

[0033] The window position of the return message is determined based on the number in the return message;

[0034] If the return message is located at the beginning position of the sliding window, the return message is sent out, and the sliding window is slid in the direction of increasing window position;

[0035] If the return message is located at a non-starting position of the sliding window, then after all the return messages on the side of the window position decreasing in the non-starting position have arrived and been sent out, the return message at the non-starting position is sent out, and the sliding window is slid in the direction of increasing window position.

[0036] According to another aspect of this application, an FPGA-based network adapter is provided, the network adapter being connected via a bus to a computing device including multiple processor cores, the network adapter comprising:

[0037] Logic unit; and

[0038] The storage unit stores a calculation program, which, when executed by the logic unit, implements any of the aforementioned methods.

[0039] According to another aspect of this application, a non-transitory computer-readable storage medium is provided, on which computer-readable instructions are stored, which, when executed by a processor, cause the processor to perform a cloud gateway as described in any of the preceding claims.

[0040] According to embodiments of this application, a cloud gateway includes a computing device and a network adapter connected to the computing device via a bus. The computing device includes multiple processor cores configured to receive uplink messages from the network adapter. The processor cores process the uplink messages and return the resulting return messages to the network adapter, thereby leveraging the computing device for service capability evolution and providing good flexibility in network data processing. Simultaneously, the network adapter connected to the computing device via the bus processes messages received from the network into uplink messages and distributes them among the multiple processor cores in a balanced manner, achieving high performance. Thus, the cloud gateway combines the flexibility of multi-core computing devices with the high performance of network adapters, providing better guarantees for table entry specifications and service evolution.

[0041] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this application. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below.

[0043] Figure 1 A schematic diagram of a cloud network structure according to an example embodiment is shown.

[0044] Figure 2 A schematic diagram of a cloud gateway according to an example embodiment is shown.

[0045] Figure 3A This illustrates a single-layer message format according to an example embodiment.

[0046] Figure 3B This illustrates a two-layer encapsulated message format according to an example embodiment.

[0047] Figure 4 A schematic block diagram of a network adapter according to an example embodiment is shown.

[0048] Figure 5 The example embodiment shows a message format with a number attached as accompanying element information.

[0049] Figure 6 A schematic diagram of a sliding window message ordering design for a message ordering module according to an example embodiment is shown.

[0050] Figure 7 A flowchart illustrating a method for a network adapter according to an example embodiment is shown.

[0051] Figure 8 An FPGA-based network adapter according to an example embodiment is shown. Detailed Implementation

[0052] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this application will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0053] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other cloud gateways, components, devices, steps, etc., can be employed. In other instances, well-known cloud gateways, devices, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0054] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0055] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0056] It should be understood that although the terms first, second, third, etc., may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. Therefore, the first component discussed below may be referred to as the second component without departing from the teachings of this application. As used herein, the term "and / or" includes all combinations of any one and more of the associated listed items.

[0057] The user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of the relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0058] Those skilled in the art will understand that the accompanying drawings are merely schematic diagrams of exemplary embodiments, and the modules or processes in the drawings are not necessarily essential for implementing this application, and therefore cannot be used to limit the scope of protection of this application.

[0059] Before describing the technical solution of this application, some terms involved in this application will be explained.

[0060] VPC (Virtual Private Cloud) is a cloud computing technology that uses virtualization to create a virtual private network segment within a public cloud. This segment houses virtual machines, storage, network devices, and other resources, giving it characteristics similar to a local data center. VPC provides a secure isolation mechanism, allowing users to create their own subnets and communicate using private IP addresses. It also enables interconnectivity between public and private clouds, connecting public and local resources.

[0061] VxLAN (Virtual Extensible LAN) is a network virtualization technology used to create overlay networks in data center networks. VxLAN is a transparent, data center-oriented Layer 2 protocol that can run on existing TCP / IP networks. VxLAN alleviates the limitations of the limited number of VLANs and provides scalable virtual networks for more flexible cloud computing and virtualization networks in data centers. Using VxLAN technology, different VPC environments can be connected into a single virtual network, enabling higher-level cloud computing applications.

[0062] Cloud Gateway: A forwarding node of the data center gateway type, serving as a traffic aggregation point. As an important component of the cloud gateway, the forwarding gateway plays a crucial role in the cloud network, including enabling cross-VPC communication, supporting cross-region communication, and implementing IP address mapping, among other functions.

[0063] Load balancing: Distributing traffic evenly across multiple computing devices.

[0064] Preservation of order: Maintaining the order of messages. In network communication, this refers to the technology or mechanism that ensures the consistency of the sending and receiving order of messages.

[0065] IGW: Internet gateway.

[0066] CGW: Customer gateway, leased line gateway.

[0067] VGW: VPC gateway, gateway within a VPC.

[0068] FPGA: Field Programmable Gate Array, a type of programmable logic device that can be programmed and reconfigured according to user needs to implement various digital circuit functions. Compared with application-specific integrated circuits (ASICs), FPGAs offer greater flexibility and programmability because they can be programmed and reconfigured after production. An FPGA consists of programmable logic units, input / output blocks, programmable interconnects, and configuration memory, and features parallelism and high efficiency.

[0069] Service Evolution: The service evolution of network devices refers to the continuous upgrading and updating of network devices to provide users with more comprehensive, efficient, secure, and reliable network services, adapting to ever-changing network needs and application scenarios. This process includes changes and innovations at multiple levels, such as hardware, software, and protocols. Examples include the intelligentization, virtualization, and cloudification of devices like switches, routers, and firewalls; the iteration and optimization of network protocols; and improvements in security, reliability, and performance. Service evolution of network devices makes networks more stable, flexible, and reliable in a constantly changing world, providing users with a better service experience. Software implementation of service evolution for network devices is easier because software can be flexibly expanded and upgraded through programming. Network device software can be upgraded through firmware upgrades and driver updates, which is relatively inexpensive. In contrast, hardware implementation of service evolution for network devices is more difficult because hardware needs to be redesigned and manufactured, resulting in higher costs, and hardware compatibility and stability issues must be considered.

[0070] Cloud gateways are core forwarding nodes in cloud networks, characterized by statelessness and high traffic volume. Traditional forwarding solutions based on x86 and DPDk (Data Plane Development Kit) directly deploy gateways such as IGW, CGW, and VGW on x86. Multi-core x86 processors, acting as computing units, handle job tasks. While x86 offers high flexibility and can quickly support service evolution, the processing power of a single x86 core is limited. When routing packets to a specific CPU core via hashing, the large data volume and high load of the cloud gateway, particularly in scenarios with massive data flows (like elephant streams), can easily lead to excessive single-core load (high load on a single core), impacting the online stability of cloud network operations.

[0071] Network processor-based solutions (such as TOFINO) leverage the programmability and high performance of programmable switching chips, offering high performance without the risk of single-core performance degradation. However, the chip's table resources are limited. While performance is guaranteed, the limitations of hardware table resources and other factors hinder the continuous evolution of network service capabilities.

[0072] To address this, this application proposes a novel cloud gateway system that leverages computing devices (e.g., x86-based) for service capability evolution, offering high flexibility in network data processing. Simultaneously, it utilizes network adapters connected to the computing devices via a bus to achieve high performance. Therefore, the cloud gateway system of this application supports high performance and large table entries, exhibits high flexibility, and possesses continuous evolution characteristics. Furthermore, the cloud gateway system of this application demonstrates good integration and requires no architectural modifications to existing cloud networks.

[0073] The embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0074] Figure 1 A schematic diagram of a cloud network structure according to an example embodiment is shown.

[0075] See Figure 1 When an external message is sent to the cloud network to access the private cloud, the message first enters the integrated switch from the core router. The integrated switch forwards the message to the forwarding gateway (e.g., IGW, VGW, or CGW) connected to it. After processing and forwarding the message, the forwarding gateway sends it to the load balancer.

[0076] For example, according to some embodiments, a forwarding gateway (e.g., IGW, VGW, or CGW) converts packets into VxLAN encapsulated packets. For instance, suppose a public network user accesses a public IP address on-premises; when accessing a virtual private cloud service on the cloud, the packet needs to be converted to a VxLAN encapsulated packet. In VxLAN, data packets are encapsulated within an outer UDP packet, called a VxLAN packet. A VxLAN packet contains three main parts: an outer IP header, a UDP header, and an inner packet. The VNI (Virtual Name Interface) is part of the inner packet and is used to identify the virtual network. The outer IP header is the first part of the VxLAN packet and contains the source IP address and the destination IP address. The source IP address is the sender's IP address, and the destination IP address is the receiver's IP address. The outer IP header is used to transmit VxLAN packets from one physical network to another. The inner IP is the second part of the VxLAN packet and contains the source and destination addresses of the inner packet. In a VxLAN network, the inner IP refers to the IP address of a virtual machine or group of virtual machines, and is also called the inner IP address. Because the inner IP is encapsulated within VxLAN packets, it does not directly participate in network transmission. When a computing device encapsulates internal data packets within VxLAN packets, it uses the VNI and the internal MAC address to generate a VxLAN MAC address, a process called VxLAN MAC address translation. Each VNI has a unique VxLAN MAC address space, thus uniquely identifying each virtual network within a VxLAN network. Conversely, when a packet is sent from a Virtual Private Cloud (VPC) to the public network, the VPC instance sends the packet to the VxLAN interface, which encapsulates the packet using a VxLAN header. The encapsulated packet is then routed to a forwarding gateway, which removes the outer VxLAN header and forwards the packet to the internet, traversing the public internet to reach its destination.

[0077] The load balancer selects a virtual server based on its load balancing algorithm to send packets to. To do this, the load balancer forwards the packets to the distribution layer switch. The distribution layer switch then sends the packets to the aggregation switch, which in turn sends them to the access switch. The access switch then sends the packets to the virtual gateway, which finally forwards them to the appropriate virtual server.

[0078] Easy to understand Figure 1 The structures and processes shown are for illustrative purposes only and are not intended to limit the application scenarios of the technical solutions in this application. The technical solutions in this application can be applied to forwarding nodes in various cloud network topologies, such as IGW, CGW, VGW, etc.

[0079] Figure 2 A schematic diagram of a cloud gateway according to an example embodiment is shown.

[0080] Figure 2 A block diagram of a cloud gateway according to an example embodiment of this application is shown.

[0081] like Figure 2 As shown, the cloud gateway includes a computing device 30 and a network adapter 16. According to some embodiments, the computing device 30 is a general-purpose computing device based on a multi-core x86 architecture. The cloud gateway according to the example embodiment can be the one described above. Figure 1 The description refers to the forwarding gateway.

[0082] See Figure 2 The computing device 30 includes a processor 12, a memory 14, a bus 22, and an I / O interface 18. The processor 12, the memory 14, and the I / O interface 18 can communicate with each other via the bus 22.

[0083] Memory 14 may include machine system readable media in the form of volatile memory, such as random access memory (RAM), read-only memory (ROM), solid-state memory, and / or cache memory. Memory 14 is used to store one or more programs containing instructions, as well as data.

[0084] Processor 12 may include one or more processor cores for executing relevant program instructions.

[0085] According to an example embodiment, computing device 30 includes a plurality of processor cores configured to receive uplink messages from network adapter 16, wherein the processor cores that receive the uplink messages process the uplink messages and return the resulting return messages to network adapter 16.

[0086] According to the example embodiment, the processor core that receives the uploaded message converts the uploaded message into a VxLAN encapsulated message. For example, suppose a public network user accesses a public IP address on-premises, where this public IP address is the destination IP address, and the message is in single-layer format (see [link]). Figure 3A In this context, ETH represents the Ethernet frame header, IP represents the IP packet header, TCP represents the TCP packet header, and payload represents the application data carried by the packet.

[0087] When accessing a virtual private cloud service in the cloud, it is necessary to convert the packet to VxLAN encapsulation (see...). Figure 3BThe outer VxLAN and the inner new IP (nuIP) are obtained through table lookup. For example, a table lookup can be performed using the packet's five-tuple (source IP, destination IP, protocol type, source port, destination port) as the key. The result is the outer VxLAN encapsulated VNI (Virtual Network Identifier), the outer IP2, and the new inner IP (nuIP), resulting in a large number of entries. VNIs can be used to transmit data packets between different physical networks to enable communication between different virtual networks. In VxLAN, data packets are encapsulated within an outer UDP packet, called a VxLAN packet. A VxLAN packet contains three main parts: the outer IP header (… Figure 3B The VxLAN packet consists of an outer IP header (ETH2), a UDP header, and an inner packet. The VNI (Virtual Name Intent) is part of the inner packet and identifies the virtual network. The outer IP header is the first part of the VxLAN packet, containing the source and destination IP addresses. The source IP address is the sender's IP address, and the destination IP address is the receiver's IP address. The outer IP header is used to transmit VxLAN packets from one physical network to another. The inner IP is the second part of the VxLAN packet, containing the source and destination addresses of the inner packet. In a VxLAN network, the inner IP refers to the IP address of the virtual machine or group of virtual machines, also known as the inner IP address. Because the inner IP is encapsulated within the VxLAN packet, it does not directly participate in network transmission. When a computing device encapsulates the inner packet within a VxLAN packet, it uses the VNI and the inner MAC address to generate a VxLAN MAC address (ETH2), a process called VxLAN MAC address translation. Each VNI has a unique VxLAN MAC address space, thus uniquely identifying each virtual network within a VxLAN network.

[0088] According to the example embodiment, the inner IP address of the VxLAN packet is obtained by the computing device 30 from the original IP address through a lookup table. The mapping between the original IP address and the inner IP address is stored in a lookup table called the VxLAN forwarding table. When the computing device 30 receives a packet, it checks the sender's original IP address, then looks up the corresponding entry to determine the VNI associated with the original IP address, and then uses the VNI to create a mapping between the original IP address and the inner IP address. Once the VNI is determined, the computing device 30 can use it to encapsulate an additional VxLAN header, which includes the inner IP address associated with that VNI.

[0089] Network adapter 16 can be connected to a computing device via a bus (e.g., a PCIe bus). Network adapter 16 processes packets received from the network into upload packets and distributes them across multiple processor cores in a balanced manner, sending return packets from computing device 30 in order. For example, network adapter 16 processes packets received from the network into upload packets, each containing a number. The upload packets are then distributed across multiple processor cores in a balanced manner. After receiving return packets from the computing device, the return packets can be sent in the order the upload packets were sent to the computing device. According to some embodiments, network adapter 16 can be implemented based on an FPGA, leveraging the programmability of the FPGA to achieve high-performance acceleration features through a combination of hardware and software.

[0090] Thus, the cloud gateway according to the example embodiment combines the flexibility of multi-core computing devices with the high performance of network adapters, and provides better guarantees in terms of table specifications and service evolution. In addition, by implementing per-packet load balancing and order preservation through the network adapter, the risk of elephant flows can be resolved, achieving a balance between performance, table specifications, and flexibility.

[0091] Figure 4 A schematic block diagram of a network adapter according to an example embodiment is shown.

[0092] See Figure 4 The network adapter 16 includes a message scheduling module 401 and a message ordering module 405. According to an example embodiment, the network adapter 16 communicates with the computing device 30 via a PCIe (Peripheral Component Interconnect Express) bus.

[0093] The message scheduling module 401 distributes the messages received from the network evenly across the multiple processor cores (e.g., cores 0 to 4) of the computing device 30, thus averaging the load on each core and avoiding the problem of high load on a single core due to a single stream. For example, assuming the CPU has 4 cores (cores 0 to 4), the first incoming message is distributed to core 0, the second to core 1, the third to core 2, and the fourth to core 3.

[0094] In some embodiments, when network adapter 16 performs load balancing across CPU cores, it typically uses multiple hardware queues. These hardware queues can be configured to match available CPU cores. Each hardware queue is assigned to a specific CPU core, allowing network adapter 16 to distribute network processing across multiple cores, thereby utilizing resources more efficiently and improving network performance.

[0095] After per-packet load balancing, the processing latency of each core may vary slightly, leading to inconsistencies in the order of packet uploads and returns. Network adapter 16 can provide order preservation functionality. Therefore, according to the example embodiment, the packet scheduling module 401 also adds a number to the uploaded packets sent to the computing device 30, and the packets returned from the computing device 30 also contain this number, to track and preserve the order of packets. For example, see... Figure 5 The uplink message sent to the CPU core includes a PSN (Power Message Number) as accompanying metadata, which is used for subsequent message tracking and order preservation.

[0096] The message ordering module 405 sends the return messages from the computing device 30 out in the order the uploaded messages were sent to the computing device 30, thus ensuring message order. After the CPU core processes the uploaded message, it returns the message along with its PSN to the network adapter 16. The network adapter 16 can determine whether the message is returned in order by comparing the PSN. If the uploaded order is met, it can be sent directly. If not, it can be temporarily stored and sent when the order comes up.

[0097] See you again Figure 4 According to some embodiments, network adapter 16 may also include a resolution module 407, a payload caching module 409, and a reassembly module 411.

[0098] To improve the single-core processing performance of computing device 30, packets sent to the CPU core may only include a header, without a payload; the payload is stored on network adapter 16. Therefore, parsing module 407 parses packets received from the network, extracting the header and payload. Payload caching module 409 stores the payload and packets returned by computing device 30. Reassembly module 411 reassembles the returned packets and payload for transmission.

[0099] According to the example embodiment, the network adapter includes an FPGA-based implementation, which offers greater flexibility and programmability compared to application-specific integrated circuits (ASICs), and has a significant cost advantage for the purpose of implementing the network adapter of this application.

[0100] Thus, the network adapter according to the example embodiment achieves packet balancing and order preservation, and solves the elephant flow problem by combining with computing devices, achieving a balance between performance, entry specifications, and flexibility.

[0101] Figure 6 A schematic diagram of a sliding window message ordering design for a message ordering module according to an example embodiment is shown.

[0102] See Figure 6To achieve the message order preservation function, the message order preservation module maintains a sliding window of message sequence information according to the order in which the messages are sent. The message sequence information includes the PSN of the sent message, and may also include the acknowledgment identifier ACK (ACK=1 indicates that the message has been returned) and the message sending timestamp TO. The sliding window uses left and right pointers to mark the left and right boundaries of the window, and then the left and right pointers move to form the sliding of the window.

[0103] After the CPU core processes the sent message and returns the message along with the PSN to the network adapter 16, the network adapter 16 can determine the window position of the returned message based on the number in the returned message. For example, the window position of the returned message can be determined by comparing the PSN.

[0104] If the return message is at the beginning of the sliding window, the return message can be sent, and the sliding window can be slid in the direction the window position is increasing. For example, see... Figure 6 If the returned message is located at the window position pointed to by the Tail pointer, the returned message can be sent out, and the window will slide to the right, that is, the Tail pointer will slide one window to the right.

[0105] If the return message is located at a non-starting position of the sliding window, then after all return messages in the direction of decreasing window position (non-starting position) have arrived and been sent, the return message at the non-starting position is sent out, and the sliding window slides in the direction of increasing window position. See, for example. Figure 6 If the return message is located in the second window position of the sliding window (ACK=1), the sliding window does not slide until all return messages in the left position have arrived and been sent out. Only then will the return message in the second window position be sent out and the sliding window slide to the right, that is, the pointer Tail slides one window to the right.

[0106] In some embodiments, the network adapter includes a timeout polling module. To prevent the module from crashing in the event of a lost packet, timeout polling can be implemented using uploaded timestamps. When a packet is sent to the CPU core of the computing device, an uploaded timestamp TO is recorded. The timeout polling module periodically polls the packet sequence information, compares the uploaded timestamp with the local clock, and when the difference between the uploaded timestamp and the local clock exceeds a threshold, it confirms that the returned packet has timed out and clears the information in the corresponding window.

[0107] Figure 7 A flowchart illustrating a method for a network adapter according to an example embodiment is shown.

[0108] accomplish Figure 7 The network adapter shown is connected to a computing device containing multiple processor cores via a bus.

[0109] like Figure 7As shown, in S701, the message received from the network is processed into an upload message, which includes a number.

[0110] According to some embodiments, a number is appended to the uploaded message, and the message returned from the computing device also includes this number, in order to track and maintain the order of messages. The processing delay of the computing device in verifying messages may vary slightly, causing inconsistencies in the order of message upload and return. Therefore, a number can be appended to the uploaded message sent to the computing device, and the message returned from the computing device can also include this number, thereby tracking and maintaining the order of messages. For example, see... Figure 5 The uplink message sent to the CPU core includes a PSN (Power Message Number) as accompanying metadata, which is used for subsequent message tracking and order preservation.

[0111] According to some embodiments, to improve the single-core processing performance of computing devices, packets sent to the CPU core may only contain a header and no payload; the payload is stored on the network adapter. Therefore, packets received from the network are parsed to extract the header and payload.

[0112] In the S703, the uploading message is distributed message by message in a balanced manner among multiple processor cores.

[0113] For example, suppose the CPU has 4 cores (core 0 to core 4). The first incoming packet is distributed to core 0, the second incoming packet is distributed to core 1, the third incoming packet is distributed to core 2, and the fourth incoming packet is distributed to core 3.

[0114] By balancing the load across each core, the problem of single-stream, single-core overload can be avoided.

[0115] In S705, a return message is received from the computing device, and the return message contains a number.

[0116] According to some embodiments, after the CPU core processes the sent message and returns the message along with its number to the network adapter, the network adapter can determine whether the message was returned in order based on the number in the returned message.

[0117] In S707, the return message is sent out in the same order as the upload message sent to the computing device.

[0118] According to some embodiments, the return message and message payload are reassembled for transmission.

[0119] According to some embodiments, S707 includes the following processing: maintaining a sliding window for message sequence information according to the sending order of the sent messages, the message sequence information including the number of the sent messages; determining the window position of the return message according to the number in the return message; if the return message is located at the beginning position of the sliding window, sending the return message and sliding the sliding window in the direction of increasing window position; if the return message is located at a non-beginning position of the sliding window, after all the return messages on the side of decreasing window position of the non-beginning position have arrived and been sent, sending the return message of the non-beginning position and sliding the sliding window in the direction of increasing window position.

[0120] According to some embodiments, to achieve the order-preserving function, a sliding window can be maintained to display message sequence information according to the order in which the messages are sent. The message sequence information includes the PSN (Personal Notification Number) of the sent messages, and may also include an acknowledgment flag (ACK = 1 indicates the message has been returned) and a message sending timestamp (TO). The sliding window uses left and right pointers to mark the left and right boundaries of the window, and the movement of these pointers forms the sliding of the window. After the CPU core processes the sent messages and returns the messages along with their PSNs to the network adapter, the network adapter can determine the window position of the returned message based on the PSN in the returned message; for example, the window position can be determined by comparing the PSN. If the returned message is located at the beginning of the sliding window, the returned message can be sent out, and the sliding window can be slid in the direction of increasing the window position. For example, see... Figure 6 If the return message is located at the window position pointed to by the tail pointer Tail, the return message can be sent out, and the window slides to the right, i.e., the Tail pointer slides one window to the right. If the return message is located at a non-starting position of the sliding window, after all return messages on the side of the window position decreasing in the non-starting position have arrived and been sent out, the return message at the non-starting position is sent out, and the sliding window slides in the direction of the window position increasing. For example, see Figure 6 If the returned message is located in the second window position of the sliding window (ACK=1), the sliding window does not slide until all returned messages in the left positions have arrived and been sent. Only then is the returned message in the second window position sent, and the sliding window slides to the right, i.e., the pointer Tail slides one window to the right. According to some embodiments, to prevent the module from hanging in the event of a lost message, timeout polling can be implemented using the uploaded timestamp. When a message is sent to the CPU core of the computing device, the uploaded timestamp TO can be recorded. By periodically polling the message sequence information, the uploaded timestamp is compared with the local clock. When the difference between the uploaded timestamp and the local clock exceeds a threshold, it can be confirmed that the returned message has timed out, and the information in the corresponding window is cleared.

[0121] Figure 8An FPGA-based network adapter according to an example embodiment is shown.

[0122] According to the example embodiment, the network adapter is connected via a bus to a computing device that includes multiple processor cores.

[0123] See Figure 8 The network adapter according to the example embodiment includes a logic unit 801 and a storage unit 803. The storage unit 803 stores a calculation program, which, when executed by the logic unit 801, implements the method described in the aforementioned embodiment of this application.

[0124] For example, logic unit 801 is configured according to instructions stored in storage unit 803 to process messages received from the network into upload messages, the upload messages containing a number.

[0125] According to some embodiments, a number is appended to the uploaded message, and the message returned from the computing device also contains this number, in order to track and maintain the order of messages. The processing delay of the computing device in verifying messages may vary slightly, resulting in an inconsistency between the order of message upload and return. Therefore, logic unit 801 can be configured to append a number to the uploaded message sent to the computing device, and the message returned from the computing device also contains this number, thereby tracking and maintaining the order of messages. For example, see... Figure 5 The uplink message sent to the CPU core includes a PSN (Power Message Number) as accompanying metadata, which is used for subsequent message tracking and order preservation.

[0126] According to some embodiments, to improve the single-core processing performance of a computing device, the packets sent to the CPU core may only contain a packet header and no payload, with the payload stored on the network adapter. Therefore, the logic unit 801 may be configured to parse packets received from the network and extract the packet header and payload.

[0127] The logic unit 801 is also configured, according to the instructions stored in the storage unit 803, to process messages received from the network into upload messages, each upload message containing a number. The upload messages are distributed message-by-message among multiple processor cores using a balanced distribution method.

[0128] For example, assuming the CPU has four cores (cores 0 to 4), logic unit 801 can be configured to distribute the first incoming packet to core 0, the second incoming packet to core 1, the third incoming packet to core 2, and the fourth incoming packet to core 3. By balancing the load across each core, the problem of a single stream hitting a single core with high bandwidth can be avoided.

[0129] The logic unit 801 is also configured to receive a return message from the computing device according to the instructions stored in the storage unit 803, the return message containing a number.

[0130] According to some embodiments, after the CPU core finishes processing the uploaded message and returns the message along with its number to the network adapter, the logic unit 801 can be configured to determine whether the message is returned in order based on the number in the returned message.

[0131] The logic unit 801 is also configured, according to the instructions stored in the storage unit 803, to send the return message in the order in which the uploaded message was sent to the computing device. According to some embodiments, the logic unit 801 is configured to reassemble the return message and the message payload for transmission.

[0132] According to some embodiments, to implement the order-preserving function, logic unit 801 can be configured to maintain a sliding window for message sequence information according to the upload order of the uploaded messages. The message sequence information includes the PSN of the uploaded message, and may also include an acknowledgment flag ACK (ACK=1 indicates that the message has been returned) and a message upload timestamp TO. The sliding window uses left and right pointers to mark the left and right boundaries of the window, and then the left and right pointers move to form the sliding of the window. After the CPU core processes the uploaded message and returns the message along with the PSN to the network adapter, logic unit 801 can be configured to determine the window position of the returned message based on the number in the returned message. For example, the window position of the returned message can be determined by comparing the PSN. If the returned message is located at the beginning position of the sliding window, the returned message can be sent out, and the sliding window can slide in the direction of increasing the window position. For example, see Figure 6 If the return message is located at the window position pointed to by the tail pointer Tail, logic unit 801 can be configured to send the return message and slide the window to the right, i.e., the pointer Tail slides one window to the right. If the return message is located at a non-starting position of the sliding window, after all return messages in the direction of decreasing window position have arrived and been sent, logic unit 801 can be configured to send the return message in the non-starting position and slide the sliding window in the direction of increasing window position. For example, see... Figure 6 If the returned message is located in the second window position of the sliding window (ACK=1), the sliding window does not slide until all returned messages in the left positions have arrived and been sent. Only then is the returned message in the second window position sent, and the sliding window slides to the right, i.e., the pointer Tail slides one window to the right. According to some embodiments, to prevent the module from hanging in the event of a lost message, the logic unit 801 can be configured to use the uploaded timestamp for timeout polling. When the message is sent to the CPU core of the computing device, the uploaded timestamp TO can be recorded. By periodically polling the message sequence information, the uploaded timestamp is compared with the local clock. When the difference between the uploaded timestamp and the local clock exceeds a threshold, the returned message is confirmed to have timed out, and the information in the corresponding window is cleared.

[0133] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0134] Through the description of the example embodiments, those skilled in the art will readily understand that the technical solutions according to the embodiments of this application have at least one or more of the following advantages.

[0135] According to the embodiments, service capability evolution is achieved by utilizing computing devices (e.g., x86-based), resulting in good flexibility in network data processing. Simultaneously, high performance is achieved using network adapters connected to the computing devices via a bus.

[0136] According to the embodiments, the cloud gateway combines the flexibility of multi-core computing devices with the high performance of network adapters, providing better assurance in terms of table specifications and service evolution.

[0137] According to the embodiments, per-packet load balancing and order preservation are achieved through network adapters, which can solve the risk of elephant flow and achieve a balance between performance, table specifications and flexibility, avoiding the problem of single-stream single-core high-efficiency attacks.

[0138] According to the embodiments, cloud gateways are implemented through computing devices and FPGA-based network adapters, offering good flexibility and integration without requiring architectural modifications to existing cloud networks.

[0139] According to the embodiments, the network adapter achieves packet balancing and order preservation, and solves the elephant flow problem by combining with computing devices, achieving a balance between performance, table size, and flexibility.

[0140] According to an embodiment, the network adapter is implemented based on an FPGA, which has greater flexibility and programmability compared to an application-specific integrated circuit (ASIC), and has a significant cost advantage for the purpose of implementing the network adapter of this application.

[0141] It should be noted that, in specific implementation, the above technical solutions may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above-described device may only include the components necessary for implementing the embodiments of this specification, and not necessarily all the components shown in the figures.

[0142] It should be noted that, for the sake of simplicity, the foregoing embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0143] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some service interface; the indirect coupling or communication connection between apparatuses or units may be electrical or other forms.

[0144] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0145] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0146] Those skilled in the art will clearly understand that the technical solutions of this application can be implemented using software and / or hardware. In this specification, "unit" and "module" refer to software and / or hardware capable of independently performing or cooperating with other components to perform a specific function, where the hardware may be, for example, a field-programmable gate array (FPGA), integrated circuit, etc.

[0147] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage device. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the cloud gateway of the various embodiments of this application.

[0148] This application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the above-described method. The computer-readable storage medium may include, but is not limited to, any type of disk, including floppy disks, optical disks, DVDs, CD-ROMs, microdrives, as well as magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, DRAMs, VRAMs, flash memory devices, magnetic cards or optical cards, nanosystems (including molecular memory ICs), network storage devices, cloud storage devices, or any type of medium or device suitable for storing instructions and / or data.

[0149] This application also provides a computer program product including a non-transitory computer-readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps of any of the methods described in the above embodiments.

[0150] The exemplary embodiments of this application have been specifically shown and described above. It should be understood that this application is not limited to the detailed structures, configurations, or implementations of cloud gateways described herein; rather, this application is intended to cover various modifications and equivalent configurations contained within the spirit and scope of the appended terms.

Claims

1. A cloud gateway, characterized in that, Includes a computing device and a network adapter connected to the computing device via a bus, wherein: The computing device includes a plurality of processor cores configured to receive uplink messages from the network adapter, the processor cores processing the uplink messages and returning the resulting return messages to the network adapter; The network adapter processes the packets received from the network into upload packets, distributes them among the multiple processor cores in a balanced manner, and sends the return packets from the computing device out in order. The network adapter includes: The message scheduling module is used to distribute messages received from the network evenly among the multiple processor cores, and to attach a number to the message sent to the computing device, the return message containing the number; The message sequence preservation module is used to maintain a sliding window for message sequence information according to the upload order of the uploaded messages, wherein the message sequence information includes the number of the uploaded message; The window position of the return message is determined based on the number in the return message; If the return message is located at the beginning position of the sliding window, the return message is sent out, and the sliding window is slid in the direction of increasing window position; If the return message is located at a non-starting position of the sliding window, then after all the return messages on the side of the window position decreasing in the non-starting position have arrived and been sent out, the return message at the non-starting position is sent out, and the sliding window is slid in the direction of increasing window position.

2. The cloud gateway according to claim 1, characterized in that, The uploaded message contains only a message header and no message payload.

3. The cloud gateway according to claim 2, characterized in that, The network adapter also includes: The parsing module is used to parse packets received from the network to extract the packet header and packet payload; The payload caching module is used to store the message payload and the return message; The reassembly module is used to reassemble the return message and the message payload for transmission.

4. The cloud gateway according to claim 1, characterized in that, The message sequence information also includes an acknowledgment identifier and a message upload timestamp.

5. The cloud gateway according to claim 4, characterized in that, The network adapter also includes: The timeout polling module is used to periodically poll the message sequence information, compare the uploaded timestamp with the local clock, and when the difference between the uploaded timestamp and the local clock exceeds a threshold, confirm that the returned message has timed out and clear the information in the corresponding window.

6. The cloud gateway according to claim 1, characterized in that, The processor core is used to convert the uploaded message into a VxLAN encapsulated message.

7. The cloud gateway according to claim 1, characterized in that, The cloud gateway includes an internet gateway, a leased line gateway, and / or a virtual private cloud gateway.

8. The cloud gateway according to claim 1, characterized in that, The network adapter includes a network adapter implemented based on FPGA.

9. A method for a network adapter, the network adapter being connected via a bus to a computing device comprising multiple processor cores, characterized in that, The method includes: Messages received from the network are processed into upload messages, and the upload messages include a number; The uploaded message is distributed message-by-message among the multiple processor cores in a balanced manner. Receive a return message from the computing device, the return message containing the number; A sliding window maintains message sequence information according to the uploading order of the uploaded messages, wherein the message sequence information includes the number of the uploaded message; The window position of the return message is determined based on the number in the return message; If the return message is located at the beginning position of the sliding window, the return message is sent out, and the sliding window is slid in the direction of increasing window position; If the return message is located at a non-starting position of the sliding window, then after all the return messages on the side of the window position decreasing in the non-starting position have arrived and been sent out, the return message at the non-starting position is sent out, and the sliding window is slid in the direction of increasing window position.

10. An FPGA-based network adapter, wherein the network adapter is connected via a bus to a computing device including multiple processor cores, characterized in that, The network adapter includes: Logic unit; and A storage unit stores a calculation program, which, when executed by the logic unit, implements the method as described in claim 9.

Images