Chalcogenide memory device composition

Abstract

This application relates to chalcogenide memory device compositions. Memory cells can use a chalcogenide material having a composition as described herein as a storage material, a selector material, or as a self-selecting storage material. Chalcogenide materials as described herein can include a sulfur-containing component, which can be sulfur (S) alone or can be a combination of sulfur with one or more other elements such as selenium (Se). In addition to the sulfur-containing component, the chalcogenide material can further include one or more other elements such as germanium (Ge), at least one Group III element, or arsenic (As).

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 676,708, filed February 21, 2022, entitled “Chalcogenide Memory Device Compositions”, which is assigned to its assignee and is expressly incorporated herein by reference. Technical Field

[0003] The technical field relates to chalcogenide memory device compositions. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, typically indicated by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access the information stored by the memory device, a component can read (e.g., sense, detect, retrieve, identify, determine, evaluate) the state of one or more memory cells within the memory device. To store information, a component can write (e.g., program, set, assign) one or more memory cells within the memory device to the corresponding state.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR and NAND memory devices, etc. Memory devices can be described in terms of volatile or non-volatile configurations. Volatile memory cells (e.g., DRAM) may lose their programmed state over time unless periodically refreshed by an external power supply. Non-volatile memory cells (e.g., NAND) can maintain their programmed state for a long period of time even in the absence of an external power supply. Summary of the Invention

[0006] Describe a composition. The composition may comprise: a component comprising sulfur, wherein the amount of the sulfur-containing component is greater than or equal to 40 atomic percentages (at.%) of the composition; germanium in an amount ranging from 8 at.% to 35 at.% of the composition; and at least one element selected from the group consisting of boron, aluminum, gallium, indium, and thallium, wherein the amount of said element ranges from 1 at.% to 15 at.% of the composition.

[0007] A device is described. The device may include a memory cell comprising a chalcogenide material, the chalcogenide material comprising: a sulfur-containing component, wherein the amount of the sulfur-containing component is greater than or equal to 40 atomic percent (at.%) of the chalcogenide material; germanium in an amount ranging from 8 at.% to 35 at.% of the chalcogenide material; and at least one element selected from the group consisting of boron, aluminum, gallium, indium, and thallium, the amount of said element ranging from 1 at.% to 15 at.% of the chalcogenide material.

[0008] An apparatus is described. The apparatus may include: a first access line; a second access line; and a memory cell comprising a chalcogenide material, the chalcogenide material including sulfur, germanium, and at least one of boron, aluminum, gallium, indium, or thallium, wherein the first access line is in electronic communication with the second access line via the memory cell. Attached Figure Description

[0009] Figure 1 Examples of systems supporting chalcogenide memory device compositions, as disclosed herein, are described.

[0010] Figure 2 Examples of memory dies supporting chalcogenide memory device compositions are described herein.

[0011] Figure 3 Examples of memory cells supporting chalcogenide memory device compositions are described below, based on examples disclosed herein.

[0012] Figure 4 Examples of memory arrays supporting chalcogenide memory device compositions, as disclosed herein, are described.

[0013] Figure 5A and 5B Examples of diagrams illustrating the properties of chalcogenide materials in supporting chalcogenide memory device compositions, as disclosed herein. Detailed Implementation

[0014] Some memory devices may include memory cells comprising at least one element, the element comprising a chalcogenide material (e.g., a chalcogenide composition, a chalcogenide glass, a chalcogenide alloy). For example, a memory cell may include a storage element (e.g., a component for storing one or more logic values), a selector element (e.g., a component for selectively allowing access to the memory cell when targeting a read, write, or other operation, while preventing interference with the memory cell when targeting one or more other memory cells), or a self-selecting storage element (e.g., a single component for providing both storage and selection functionality).

[0015] In some cases, the chalcogenide material included in the memory cell may contain selenium (Se), arsenic (As), and germanium (Ge), which may be referred to as SAG compositions. In some cases, the chalcogenide material included in the memory cell may further contain Group III elements—such as boron (B), aluminum (Al), gallium (Ga), indium (In), or thallium (Tl)—which can increase the threshold voltage window of the memory cell (e.g., the difference between threshold voltages corresponding to different logic states of the memory cell, which may alternatively be referred to as the read window, read budget, or read budget window). Group III elements may alternatively be referred to as Group 13 (or Column 13) elements. In some cases, SAG compositions containing Group III elements may be referred to as III-SAG compositions. However, the inclusion of Group III elements may also increase current leakage in the memory cell, which may in turn increase the power consumed by the memory cell during access operations (e.g., programming operations).

[0016] Additionally, memory cells (or elements thereof) having SAG or III-SAG compositions can have a relatively large thickness (e.g., relative to other potential methods). The thickness of the memory cell can correspond to the length of the memory cell along the direction of current flow. For example, the thickness of the memory cell can correspond to the distance between electrodes that apply a bias voltage to the memory cell during access operations (e.g., the distance between the access line or the electrode in contact with the access line and the memory cell). In some cases, memory cells with a relatively large thickness can have reduced mechanical stability, and memory cells can be used (e.g., due to the large size of the memory cells) to reduce the memory density of the memory array, or both. Therefore, compositions that require less power (e.g., less than the power of SAG or III-SAG compositions), allow for reduced memory cell thickness, increase the read window, or any combination thereof may be required.

[0017] Chalcogenide materials as described herein may contain sulfur (S)—for example, some or all of the Se in an SAG or III-SAG composition may be replaced by sulfur, relative to the SAG or III-SAG composition. That is, chalcogenide compositions as described herein may contain a sulfur-containing component (which may alternatively be referred to as a sulfur-containing component). In some cases, SAG or III-SAG compositions containing a sulfur-containing component may be referred to as SAGS or III-SAGS compositions, respectively. In some instances, the introduction of sulfur into chalcogenide materials can improve various chemical and electrical properties of the composition (e.g., compared to SAG or III-SAG compositions). For example, sulfur may bond more strongly to other components of the composition (e.g., the bond energy between sulfur and arsenic may be greater than that between selenium and arsenic), which can increase the band gap energy of the composition. Therefore, the electrical conductivity of the chalcogenide composition can be increased, which in turn can reduce leakage current.

[0018] For example, chalcogenide materials as described herein can be used, for instance, as components or elements of phase-change memory (PCM) memory cells or polarity-based memory cells (e.g., as storage elements, selection elements, or self-selection storage elements). Chalcogenide compositions may have a threshold voltage at which they become conductive (i.e., switched on to allow current flow). The threshold voltage can change over time, a phenomenon known as drift. Compositions more prone to voltage drift can limit the usefulness and performance of devices using those compositions. Chalcogenide material compositions may also have a memory window, corresponding to the difference in threshold voltage between one state (e.g., when programmed using a voltage with positive polarity) and another state (e.g., when programmed using a voltage with negative polarity). Compositions with a smaller memory window can limit the performance of devices employing those compositions. In some cases, memory cells using chalcogenide materials as described herein can support reduced memory cell thickness due to reduced leakage (e.g., the reduction in leakage current can compensate for the increase in leakage due to the reduced memory cell thickness). Furthermore, compared to SAGS or III-SAGS compositions, replacing at least some of the selenium with sulfur can reduce the threshold voltage variation of memory cells over time (e.g., reduce drift rate). Therefore, memory cells comprising chalcogenide materials as described herein can allow for reduced memory cell thickness, reduced leakage current, reduced power consumption, reduced drift rate, or any combination thereof.

[0019] Initially in reference Figure 1-3 Features of this disclosure are described in the context of the memory system, die, and array described herein. (See references...) Figure 4-5B The features of this disclosure are described in the context of the memory array and in the diagrams illustrating the properties of the chalcogenide materials.

[0020] Figure 1 This document describes an example of a system 100 using a chalcogenide memory device composition, as disclosed herein. System 100 may include a host device 105, a memory device 110, and multiple channels 115 coupling the host device 105 and the memory device 110. System 100 may include one or more memory devices, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0021] System 100 may include portions of electronic devices, such as computing devices, mobile computing devices, wireless devices, graphics processing devices, vehicles, or other systems. For example, system 100 may describe aspects of computers, laptop computers, tablet computers, smartphones, cellular phones, wearable devices, internet-connected devices, vehicle controllers, etc. Memory device 110 may be a component of the system that can be used to store data from one or more other components of system 100.

[0022] At least a portion of system 100 may be an example of host device 105. Host device 105 may be an example of a processor or other circuitry within a device that uses memory to perform processes within, for example, a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, system-on-a-chip (SoC), or other fixed or portable electronic device, and other examples. In some examples, host device 105 may refer to hardware, firmware, software, or a combination thereof that implements the functions of external memory controller 120. In some examples, external memory controller 120 may be referred to as a host or host device 105.

[0023] Memory device 110 may be a separate device or component that can provide physical memory address / space available for use or reference by system 100. In some instances, memory device 110 may be configured to work with one or more different types of host devices 105. Signaling between host device 105 and memory device 110 may be used to support one or more of the following: modulation schemes for modulating signals, various pin configurations for transmitting signals, various form factors for the physical packages of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0024] Memory device 110 may be used to store data of components of host device 105. In some instances, memory device 110 may act as a secondary or subordinate device to host device 105 (e.g., responding to and executing commands provided by host device 105 via external memory controller 120). Such commands may include one or more of write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands.

[0025] The host device 105 may include one or more of the following components: an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or, for example, one or more peripheral components or one or more input / output controllers. The components of the host device 105 may be coupled to each other via bus 135.

[0026] Processor 125 may be used to provide control or other functionality for at least a portion of system 100 or at least a portion of host device 105. Processor 125 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. In such instances, processor 125 may be an instance of a central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or SoC, and other instances. In some instances, external memory controller 120 may be implemented by processor 125 or as part of said processor.

[0027] BIOS component 130 may be a software component containing a BIOS used as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 may contain programs or software stored in read-only memory (ROM), flash memory, or another non-volatile memory.

[0028] Memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 (e.g., memory die 160-a, memory die 160-b, memory die 160-N) may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more banks, one or more tesserials, one or more segments), wherein each memory cell can be used to store at least one bit of data. Memory device 110 including two or more memory dies 160 may be referred to as a multi-die memory or multi-die package, or a multi-chip memory or multi-chip package.

[0029] Memory die 160 may be an example of a two-dimensional (2D) memory cell array or an example of a three-dimensional (3D) memory cell array. A 2D memory die 160 may contain a single memory array 170. A 3D memory die 160 may contain two or more memory arrays 170, which may be stacked one on top of the other or positioned adjacent to each other (e.g., relative to a substrate). In some instances, the memory arrays 170 in a 3D memory die 160 may be referred to as a stack, hierarchy, layer, or die. A 3D memory die 160 may contain any number of stacked memory arrays 170 (e.g., two-high stacked memory arrays, three-high stacked memory arrays, four-high stacked memory arrays, five-high stacked memory arrays, six-high stacked memory arrays, seven-high stacked memory arrays, eight-high stacked memory arrays). In some 3D memory dies 160, different stacks may share at least one common access line, such that some stacks may share one or more row lines or column lines.

[0030] Device memory controller 155 may include circuitry, logic, or components for controlling the operation of memory device 110. Device memory controller 155 may include hardware, firmware, or instructions that enable memory device 110 to perform various operations and are available to receive, transmit, or execute commands, data, or control information associated with components of memory device 110. Device memory controller 155 may be used to communicate with one or more of external memory controller 120, memory dies 160, or processor 125. In some instances, device memory controller 155 may control the operation of memory device 110 as described herein in conjunction with local memory controller 165 of memory die 160.

[0031] A local memory controller 165 (e.g., local to memory die 160) may include circuitry, logic, or components that can be used to control the operation of memory die 160. In some instances, the local memory controller 165 may be used to communicate with a device memory controller 155 (e.g., to receive or transmit data or commands, or both). In some instances, memory device 110 may not include a device memory controller 155 and a local memory controller 165 or an external memory controller 120 capable of performing the various functions described herein. Thus, the local memory controller 165 may be used to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or combinations thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165 or both may include: a receiver for receiving signals (e.g., from an external memory controller 120), a transmitter for transmitting signals (e.g., to an external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuitry or controllers that may be used to support the operation of the described device memory controller 155 or the local memory controller 165 or both.

[0032] External memory controller 120 can be used to enable the transfer of one or more of the information, data, or commands between a component of system 100 or host device 105 (e.g., processor 125) and memory device 110. External memory controller 120 can translate or translate communications exchanged between components of host device 105 and memory device 110. In some instances, the functionality of external memory controller 120 or other components of system 100 or host device 105, or as described herein, may be implemented by processor 125. For example, external memory controller 120 may be hardware, firmware, or software, or a combination thereof, implemented by processor 125 or another component of system 100 or host device 105. Although external memory controller 120 is depicted as being external to memory device 110, in some instances, external memory controller 120, or as described herein, may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

[0033] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 may be used to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium carrying information between host device 105 and memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between ends associated with components of system 100. Signal paths may be examples of conductive paths that can be used to carry signals. For example, channel 115 may include a first end comprising one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. Pins may be examples of conductive input or output points of devices of system 100, and pins may be used to serve as part of a channel.

[0034] Channel 115 (and associated signal paths and endpoints) may be dedicated to transmitting one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or combinations thereof. In some instances, single data rate (SDR) signaling or dual data rate (DDR) signaling may be used to transmit signaling through channel 115. In SDR signaling, one modulation symbol (e.g., signal level) of the signal may be registered for each clock cycle (e.g., on the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of the signal may be registered for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0035] In some cases, memory array 170 may include memory cells, and memory cells may include one or more elements having a chalcogenide composition as described herein. For example, memory cells may use a chalcogenide composition as a storage element, a selection element, or a self-selecting storage element. In some cases, memory cells containing chalcogenide materials as described herein may have reduced leakage current, which may support reduced thickness of the memory cells or both (e.g., compared to memory cells that do not contain sulfur-containing components or other aspects of chalcogenide materials as described herein). Additionally, memory cells may have an increased threshold voltage window, a reduced drift rate, or both (e.g., compared to memory cells that do not contain sulfur-containing components or other aspects of chalcogenide materials as described herein). Thus, memory device 110 including memory cells incorporating chalcogenide materials as described herein may support reduced power consumption, an increased threshold voltage window, a reduced drift rate, or a combination thereof.

[0036] Figure 2This describes an example of a memory die 200 using a chalcogenide memory device composition, as disclosed herein. The memory die 200 may be a reference. Figure 1 Examples of the described memory die 160. In some instances, the memory die 200 may be referred to as a memory chip, memory device, or electronic memory device. The memory die 200 may include one or more memory cells 205, each of which may be programmed to store different logical states (e.g., programmed to be one of a set of two or more possible states). For example, memory cells 205 may be used to store one bit of information at a time (e.g., logic 0 or logic 1). In some instances, memory cells 205 (e.g., multi-level memory cells 205) may be used to store more than one bit of information at a time (e.g., logic 00, logic 01, logic 10, logic 11). In some instances, memory cells 205 may be arranged in an array, as shown in the reference. Figure 1 The memory array 170 is described.

[0037] Memory cell 205 may use a configurable material to store logical states, said configurable material may be referred to as a memory element, memory storage element, material element, material memory element, material portion, or material portion with write polarity, etc. The configurable material of memory cell 205 may be as described herein (e.g., see reference ). Figure 5A and 5B The chalcogenide materials (compositions) described herein. For example, as described in more detail elsewhere herein, chalcogenide storage elements can be used in phase-change memory (PCM) cells, threshold processing memory cells, or self-selection memory cells.

[0038] The memory die 200 may include access lines (e.g., row lines 210 and column lines 215) arranged in a pattern such as a grid pattern. The access lines may be formed of one or more conductive materials. In some instances, row lines 210 may be referred to as word lines. In some instances, column lines 215 may be referred to as digital lines or bit lines. References to access lines, row lines, column lines, word lines, digital lines, or bit lines may be interchanged without affecting understanding or operation. Memory cells 205 may be located at the intersection of row lines 210 and column lines 215.

[0039] Read and write operations can be performed on memory cell 205 by activating or selecting one or more access lines, such as row line 210 or column line 215. A single memory cell 205 at its intersection can be accessed by applying a bias voltage to row line 210 and column line 215 (e.g., applying a voltage to row line 210 or column line 215). In a two-dimensional or three-dimensional configuration, the intersection of row line 210 and column line 215 may be referred to as the address of memory cell 205. Access lines may be conductive lines coupled to memory cell 205 and can be used to perform access operations on memory cell 205.

[0040] Access to memory cell 205 can be controlled via row decoder 220 or column decoder 225. For example, row decoder 220 can receive row addresses from local memory controller 245 and activate row line 210 based on the received row addresses. Column decoder 225 can receive column addresses from local memory controller 245 and activate column line 215 based on the received column addresses.

[0041] Sensing component 230 can be used to detect the state of memory cell 205 (e.g., material state, resistance, threshold state) and determine the logic state of memory cell 205 based on the stored state. Sensing component 230 may include one or more sensing amplifiers to amplify or otherwise convert signals generated by accessing memory cell 205. Sensing component 230 can compare the signal detected from memory cell 205 with reference 235 (e.g., reference voltage). The detected logic state of memory cell 205 can be provided as an output of sensing component 230 (e.g., provided to input / output 240) and can indicate the detected logic state to another component of the memory device including memory die 200.

[0042] The local memory controller 245 can control access to the memory cell 205 through various components (e.g., row decoder 220, column decoder 225, sensing component 230). The local memory controller 245 may be a reference. Figure 1An example of a local memory controller 165 is described. In some instances, one or more of the row decoder 220, column decoder 225, and sensing components 230 may be co-located with the local memory controller 245. The local memory controller 245 may be used to receive one or more commands or data from one or more different memory controllers (e.g., an external memory controller 120 associated with host device 105, another controller associated with memory die 200), translate the commands or data (or both) into information usable by memory die 200, perform one or more operations on memory die 200, and transfer data from memory die 200 to host device 105 based on the performance of said one or more operations. The local memory controller 245 may generate row signals and column address signals to activate target row lines 210 and target column lines 215. The local memory controller 245 may also generate and control various voltages or currents used during operation of memory die 200. Generally, the amplitude, shape, or duration of the applied voltage or current discussed herein may vary and may differ for the various operations discussed when operating the memory die 200.

[0043] The local memory controller 245 can be used to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, or activation operations, etc. In some instances, access operations may be performed or otherwise coordinated by the local memory controller 245 in response to various access commands (e.g., from the host device 105). The local memory controller 245 can be used to perform other access operations not listed herein or other operations related to the operation of the memory die 200 that are not directly related to accessing the memory cells 205.

[0044] In some cases, memory die 200 may include memory cell 205 comprising at least one element having a chalcogenide composition (e.g., SAGS or III-SAGS composition) as described herein. For example, within memory cell 205, the chalcogenide composition may be or be included in a select element, a storage element, or a self-select storage element. In some cases, memory cell 205 comprising an element having a chalcogenide composition as described herein may have reduced leakage current (e.g., compared to memory cells not comprising a chalcogenide composition as described herein), may support reduced thickness of memory cell 205, or both. Additionally, memory cell 205 may have an increased threshold voltage window, a reduced drift rate, or both. Thus, memory die 200 may support reduced power consumption, an increased threshold voltage window, a reduced drift rate, or a combination thereof.

[0045] Figure 3This describes an example of a memory array 300 as disclosed herein. The memory array 300 may be used as a reference. Figure 1 and 2 An example of a portion of a memory array or memory die as described. Memory array 300 may include a first stack 305 of memory cells positioned above a substrate (not shown) and a second stack 310 of memory cells located above the first array or stack 305. While an example of memory array 300 includes two stacks 305, 310, memory array 300 may include any number of stacks (e.g., one or more).

[0046] The memory array 300 may also include row lines 210-a, 210-b, 210-c, 210-d, column lines 215-a and 215-b, which may be as referenced. Figure 2 Examples of row lines 210 and column lines 215 are described. One or more memory cells in the first stack 305 and the second stack 310 may contain one or more chalcogenide materials in the pillars between the access lines. For example, a single stack between access lines may contain one or more of a first electrode, a first chalcogenide material (e.g., a selector assembly), a second electrode, a second chalcogenide material (e.g., a memory element), or a third electrode. Although Figure 3 Some of the components are labeled with numerical indicators, while other corresponding components are not labeled, but they are the same or will be understood as similar, in order to improve the visibility and clarity of the depicted features.

[0047] One or more memory cells in the first stack 305 may include one or more of electrodes 325-a, memory elements 320-a, or electrodes 325-b. One or more memory cells in the second stack 310 may include electrodes 325-c, memory elements 320-b, and electrodes 325-d. Memory element 320 may be or include a chalcogenide material as described herein. Memory element 320 may be a phase-change memory element, a threshold-processing memory element, or a self-selecting memory element. In some instances, memory cells in the first stack 305 and the second stack 310 may have a common conductor, such that corresponding memory cells in one or more stacks 305 and one or more stacks 310 may share column line 215 or row line 210. For example, the first electrode 325-c of the second stack 310 and the second electrode 325-b of the first stack 305 may be coupled to column line 215-a, such that column line 215-a may be shared by vertically adjacent memory cells.

[0048] In some instances, storage element 320 may be an example of a phase-change element within a phase-change memory cell. In such instances, the chalcogenide material of storage element 320 is operable to undergo a phase transition or change of physical state during normal operation of the memory cell. For example, the phase-change memory cell may have an amorphous state (e.g., a relatively disordered atomic configuration) and a crystalline state (e.g., a relatively ordered atomic configuration). The phase-change memory cell may exhibit an observable difference in resistance between the crystalline and amorphous states in the phase-change material (which may be a chalcogenide material). The material in the crystalline state may have atoms arranged in a periodic structure, which can produce a relatively low resistance. In contrast, the material in the amorphous state may not have a periodic atomic structure or has a relatively small number of periodic atomic structures, and therefore may have a relatively high resistance. The difference in resistance values ​​between the amorphous and crystalline states of the material can be significant. For example, the resistance of the material in the amorphous state may be one or more orders of magnitude greater than the resistance of the material in its crystalline state. In some instances, the material may be partially amorphous and partially crystalline, and the resistance may have a value between the resistance of a material in a fully crystalline state and a fully amorphous state. In such instances, the material may be used to store more than two logic states (e.g., three or more logic states).

[0049] In some instances, storage element 320 may be an example of a threshold processing element within a threshold processing (e.g., polarity-based, polarity-programmed) memory cell. For a threshold processing memory cell, some or all of a set of logic states supported by the memory cell may be associated with an amorphous state of the chalcogenide material (e.g., a material in a single state can be used to store different logic states). In some instances of a threshold processing memory cell, storage element 320 may be an example of a self-selecting storage element.

[0050] During programming (writing) operations of a phase-change memory cell (e.g., electrode 325-a, memory element 320-a, electrode 325-b), various parameters of the programming pulse can influence (e.g., determine, set, program) specific behavior or properties of the material of memory element 320, such as the threshold voltage or resistance of the material. To program a low-resistance state (e.g., a relatively crystalline state) in the phase-change memory cell, a programming pulse can be applied to heat or melt the material of memory element 320, which may be associated with at least temporarily forming a relatively disordered (e.g., amorphous) atomic arrangement. The amplitude of the programming pulse can decrease over a period of time (e.g., relatively slowly) to allow the material to form a crystalline structure upon cooling, thereby forming a stable crystalline material state. To program a high-resistance state (e.g., a relatively amorphous state) in the phase-change memory cell, a programming pulse can be applied to heat and / or melt the material of memory element 320. The amplitude of the programming pulse can decrease more rapidly compared to the programming pulse for the low-resistance state. In such cases, the material may cool along with the atoms in a more disordered atomic arrangement because the atoms cannot form a crystalline structure before the material reaches a stable state, thus forming a stable amorphous material state. The difference in the threshold voltage or resistance of the material of storage element 320 depends on the logic state stored in the material of storage element 320, and this difference may correspond to the read window of storage element 320. In some cases, a portion of the storage element may undergo material changes associated with the logic state.

[0051] During a programming (write) operation of a threshold-processing memory cell (e.g., including electrode 325-a, memory element 320-a, and electrode 325-b), the polarity of the voltage applied as part of the write operation (e.g., the polarity of the write voltage) relative to the polarity of the voltage applied as part of the read operation (e.g., the polarity of the read voltage) can affect (determine, set, program) specific behavior or characteristics of the material of the memory element 320, such as the threshold voltage of the material observed based on the voltage applied as part of the read operation. For example, when reading with a read voltage having the same polarity as the most recently applied write voltage, the threshold-processing memory cell may exhibit a low threshold voltage, and when reading with a read voltage having a different polarity than the most recently applied write voltage, the memory cell may exhibit a low threshold voltage. The difference in the threshold voltage of the material of storage element 320, depending on the logic state stored in the material of storage element 320 (e.g., the difference between the threshold voltage when the material stores a logic state '0' that can be associated with a write voltage of the first polarity and the threshold voltage when the material stores a logic state '1' that can be associated with a write voltage of the second polarity) can correspond to the read window of storage element 320.

[0052] In some instances, the architecture of memory array 300 may be referred to as a crosspoint architecture, where memory cells are formed at topological intersections between row lines 210 and column lines 215. This crosspoint architecture can provide relatively high-density data storage at a lower manufacturing cost compared to other memory architectures. For example, the crosspoint architecture may have memory cells with a smaller area and thus a higher memory cell density compared to other architectures. For example, compared to other architectures with a memory cell area of ​​6F² (e.g., those with three-terminal selector elements), the architecture may have a memory cell area of ​​4F², where F is the minimum feature size. For example, DRAM may use transistors, which are three-terminal devices, as selector elements for each memory cell and may have a larger memory cell area compared to the crosspoint architecture.

[0053] Although Figure 3 The example illustrates two memory stacks, but other configurations are possible. In some instances, a single memory stack of memory cells can be constructed above a substrate, which may be referred to as a two-dimensional memory. In some instances, two or more stacks of memory cells can be configured in a similar manner in a three-dimensional cross-point architecture. Additionally, in some cases, Figure 3 The elements shown or described herein may be electrically coupled to each other as shown or described but physically rearranged (e.g., storage element 320 and possible selection element or electrode 325 may be electrically connected in series between row line 210 and column line 215, but do not need to be in a column or stack configuration).

[0054] In some cases, the storage element 320 may be or comprise a chalcogenide material (e.g., a chalcogenide composition) as described herein. The storage element 320 may be a selectable storage element. Alternatively, the memory cell may use a chalcogenide material as described herein as a selectable element (not shown) or as part of a selectable element, which may be located between the storage element 320 and row lines 210 of the memory cell or between the storage element and column lines 215 of the memory cell. In some cases, a memory cell 205 comprising a storage element 320 having a chalcogenide composition as described herein may have reduced leakage current (e.g., compared to a memory cell without this element), may support reduced thickness of the memory cell (e.g., reduced thickness of the storage element 320), or both. Additionally, this memory cell may have an increased threshold voltage window, a reduced drift rate, or both. Therefore, the memory array 300 may support reduced power consumption, an increased threshold voltage window, a reduced drift rate, or a combination thereof.

[0055] Figure 4This describes an example of a memory array 400 as disclosed herein. The memory array 400 may be used as a reference. Figure 1 and 2 An example of a described memory array. Memory array 400 may include multiple levels of memory cells 410 stacked vertically relative to a substrate to produce a memory cell stack 435, which may be as shown in the reference. Figure 1 and 2 Examples of memory cells and memory cell stacks are described. In some instances, memory array 400 may therefore be referred to as a 3D memory array. Memory array 400 may include word line boards 415 and pillars 425, which may be as described in the reference. Figure 2 Examples of the described word lines and bit lines (e.g., row line 210 and column line 215).

[0056] Word line board 415 may include multiple word lines in a “comb” structure (e.g., it may resemble the structure of a tool with fingers and space between each pair of adjacent fingers). Word line board 415 may, for example, include a sheet of conductive material comprising a first portion extending in a first direction within a plane, and multiple fingers extending in a second direction within a plane. Each finger of word line board 415 may represent a word line as described herein. The number and length of the fingers (e.g., word lines) may define the size of word line board 415, wherein the size of word line board 415 may be based on the capacitance of word line board 415 relative to one or more storage class memories (SCMs). Various exemplary details of the comb structure, fingers, and other aspects of word line board 415 may be further described elsewhere herein.

[0057] Each post 425 can be selectively coupled to a corresponding post line 420 via a post selector 445 (e.g., a transistor or switching assembly). For example, a post line 450 of post 425 can be coupled to a post selector 445 of post 425, and the post selector 445 can be selectively activated or deactivated based on the voltage of the post line 450 (e.g., the voltage difference between the voltage of the post line 450 and the voltage of the post line 420). When activated (e.g., on, off, conducting), the post selector 445 of post 425 can couple post 425 to the post line 420 of post 425, and thus the voltage of post 425 can become equal to or approximately equal to the voltage of post line 420. In some cases, the pillar selector 445 may be a transistor (e.g., a thin-film transistor (TFT) or other type of transistor), and the gate of the transistor may be coupled to pillar line 450, the source of the transistor may be coupled to pillar line 420, and the drain of the transistor may be coupled to pillar 425. Therefore, in some cases, pillar line 450 may alternatively be referred to as pillar gate line, and pillar line 420 may alternatively be referred to as pillar source line. The pillar decoder as described herein can be used to selectively activate (e.g., apply a selection voltage) or deactivate (e.g., apply a deselect voltage) pillar line 450 of a set of pillar lines 450 associated with the pillar decoder, or to selectively activate (e.g., apply a selection voltage) or deactivate (e.g., apply a deselect voltage) pillar line 420 of a set of pillar lines 420 associated with the pillar decoder.

[0058] Column lines 450 and column lines 420 may span and are thus coupled to column selectors 445 corresponding to rows or columns of columns 425 within a single word plate, a single word plate, multiple word plates, or multiple word plates, as described herein. Those skilled in the art will understand that which direction (e.g., the X or Y direction) is considered row-to-column can be arbitrary. In some cases, columns 425 may correspond to (e.g., in terms of one or more functionalities) as described in the references. Figure 2 The described column line 215. Similarly, the column decoder, column column line 450, column row line 420, and column selector 445 may correspond (e.g., in terms of one or more functionalities) as described in the reference. Figure 2 The column decoder 225 is described.

[0059] In some cases, a column 425 coupled to the same column line 450 can be considered as having a comb-like structure with vertical comb-like fingers (e.g., column 425) via the corresponding column line 420 as selectable (e.g., relative to other columns 425 coupled to the same column line 450), and each memory cell 410 can be located at the intersection of the horizontal fingers of the word line plate 415 (e.g., word line) and the vertical fingers (e.g., column 425, which can be considered as a number line or part of a number line), but the teachings herein are not limited to this conceptualization.

[0060] The memory array 400 may also include an insulating layer 405, a trench insulating layer 406, a via 430, and a substrate 440. Although Figure 4 The example illustrates the column line 420 and column line 450 above the column 425, but in some embodiments, the column line 420 and column line 450 may instead be below the column 425 (e.g., between the column 425 and the substrate 440).

[0061] The insulating layer 405 may be electrically insulating and may provide insulation between alternating word lines 415. As described herein, various logic states can be stored by programming the resistance of the memory cells 410 (e.g., programming a resistor to a chalcogenide material as described herein, which may be contained within the memory cells 410). In some cases, the programming resistor comprises allowing current to flow through the memory cells 410, heating the memory cells 410, melting the material of the memory cells 410 (e.g., all or part of it), applying a voltage of a specific polarity to the memory cells, or any combination thereof—for example, the memory cells may be used as threshold processing memory cells (e.g., polarity-programmed memory cells) or phase-change memory cells. The insulating layer 405 may consist of multiple sublayers, thereby creating one or more interfaces between the memory cells 410.

[0062] Memory array 400 may comprise an array of memory cell stacks 435, and each memory cell stack 435 may comprise a plurality of memory cells 410. Memory array 400 may be fabricated by forming a stack of conductive layers (e.g., word line boards 415), wherein each conductive layer may be separated from adjacent conductive layers by one or more electrically insulating layers 405. The electrically insulating layers may comprise oxide or nitride materials, such as silicon oxide, silicon nitride, or other electrically insulating materials. In some cases, the electrically insulating layer 405 may comprise one or more sublayers. The layers of memory array 400 may be formed on a substrate 440 (e.g., a silicon wafer) or any other semiconductor or oxide substrate. Vias 430 (e.g., openings) may be formed by removing material from the layer stack via etching or mechanical techniques, or both.

[0063] In some cases, memory cells 410 (e.g., memory elements or selectable memory elements) can be formed by removing material from the conductive layer to create a recess adjacent to the via 430 and forming a variable-resistivity material in the recess. The variable-resistivity material can be a chalcogenide material as described herein. For example, material can be removed from the conductive layer by etching, and a variable-resistivity material can be deposited in the resulting recess to form memory cells 410 (e.g., memory elements). Each via 430 can be filled with an electrically conductive material and a dielectric material to create a pillar 425, which can be coupled (e.g., selectively, such as using a pillar selector 445) to a pillar line 420. In other words, memory cells 410 in the memory cell stack 435 can share a common electrode (e.g., pillar 425). Thus, each memory cell 410 can be coupled to a word line board 415 and a pillar 425. In some cases, each post 425 (e.g., located within each via 430) may be coupled to a first word line finger via a corresponding first memory cell and to a second word line finger via a corresponding second memory cell, as referenced. Figure 4 As described in further detail, the trench insulation layer 406 may be electrically insulating and may provide insulation between alternating (e.g., intersecting) word line fingers of each word line plate 415 (e.g., word line fingers on each side of the through-hole 430 in the direction of the column line 420, wherein word line fingers on opposite sides of the trench insulation layer 406 may extend away from the ridge of their respective word line plates in parallel but opposite directions, for example, the first word line finger extends to the right adjacent to the side of the trench insulation layer 406, while the second word line finger extends to the left adjacent to the opposite side of the trench insulation layer 406).

[0064] In some instances, the material of memory cell 410 (e.g., memory element) may comprise a chalcogenide material as described herein. The chalcogenide material may comprise sulfur, germanium, and at least one Group III element (e.g., at least one of boron, aluminum, gallium, indium, and thallium). The chalcogenide material may further comprise selenium. In some cases, the chalcogenide material may further comprise arsenic, oxygen (O), silicon (Si), or any combination thereof. In some cases, memory cell 410 comprising a chalcogenide material as described herein may have reduced leakage current (e.g., compared to memory cells not comprising such a chalcogenide material), may support reduced thickness of memory cell 410, or both. Additionally, memory cell 410 may have an increased threshold voltage window, a reduced drift rate, or both. Therefore, memory array 400 may support reduced power consumption, an increased threshold voltage window, a reduced drift rate, or a combination thereof.

[0065] In some instances, such as for a threshold processing memory cell or a self-select memory cell 410, some or all of a set of logic states supported by the memory cell 410 may be associated with the same state, such as an amorphous state of a chalcogenide material rather than a crystalline state of the chalcogenide material (e.g., the material can be used to store different or multiple logic states while remaining in an amorphous state). In some such instances, the memory cell 410 may be an instance of a self-select memory cell 410. In such instances, the material used in the memory cell 410 may be a chalcogenide material as described herein and is operable to undergo state changes during normal operation of the memory cell (e.g., due to ion migration or separation within the memory cell 410). For example, the self-select memory cell 410 may have a high threshold voltage state and a low threshold voltage state. The high threshold voltage state may correspond to a first logic state (e.g., a reset state), and the first polarity of the write voltage and the low threshold voltage state may correspond to a second logic state (e.g., a set state) and a second polarity of the write voltage. In some instances, memory cell 410 may alternately switch between an amorphous state and a crystalline state during operation, the amorphous state and the crystalline state corresponding to different resistances or threshold voltages and thus to different logic states, and these operations may be referred to as phase transition operations in some cases.

[0066] In some cases, during the programming (writing) operation of the self-selected memory cell 410, the polarity of one or more pulses used for the write operation can affect (determine, set, program) specific behavior or characteristics of the material of the memory cell 410, such as the threshold voltage of the material. The difference in the threshold voltage of the material of the memory cell 410 depending on the logic state stored in the material (e.g., the difference between the threshold voltage when the material stores logic state '0' and the threshold voltage when the material stores logic state '1') can correspond to the read window of the memory cell 410.

[0067] Various techniques can be used to form materials or components on substrate 440. These techniques may include, for example, chemical vapor deposition (CVD), metal-organic vapor deposition (MOCVD), physical vapor deposition (PVD), sputtering deposition, atomic layer deposition (ALD), or molecular beam epitaxy (MBE), as well as other thin film growth techniques. Various techniques can be used to remove materials, including, for example, chemical etching (also known as “wet etching”), plasma etching (also known as “dry etching”), or chemical mechanical planarization.

[0068] As described herein, the regions separating memory cells 410 (e.g., insulating layer 405, trench insulating layer 406, or both) may contain one or more interfaces. In some instances, the interface of insulating layer 405 separates memory cells 410 stacked in a vertical direction. In other words, memory cells 410 may be stacked one on top of another and separated from each other by interfaces. In some instances, the interface of trench insulating layer 406 separates word line fingers from each other in a horizontal direction.

[0069] Figure 5A Examples of chalcogenide materials according to the examples disclosed herein are illustrated in Figure 500-a. While Figure 500-a represents aspects of a ternary germanium-arsenic-sulfur-containing component scheme, it should be understood that compositions corresponding to Figure 500-a may additionally contain a Group III element (selected from the group consisting of boron, aluminum, gallium, indium, and thallium). The sulfur-containing component as described herein may be pure sulfur or a combination of sulfur with one or more other elements. For example, the sulfur-containing component may include sulfur and selenium, may include sulfur and oxygen, or may include sulfur, selenium, and oxygen.

[0070] For example, region 505 describes a composition containing a sulfur-containing component and germanium (potentially also containing arsenic) and, in some cases, may be doped with a Group III element. Region 510 describes a composition containing a sulfur-containing component and germanium (potentially also containing arsenic) and, in some cases, may also be doped with a Group III element. In some cases, region 510 may include region 515, which may describe a composition containing a sulfur-containing component and germanium, potentially also containing a Group III element, but without arsenic.

[0071] As described herein, compositions with increased memory windows and low standard deviations in threshold voltage can be used for memory elements, selectable memory elements, or other elements (e.g., components) within memory cells. Such compositions may contain at least some sulfur (and thus a sulfur-containing component, which in some cases may also contain selenium, and potentially one or more other elements) and one or more of arsenic, germanium, or at least one Group III element. Chalcogenide material compositions as described herein may consist of compositions identified in Table 1, providing a range of compositions with atomic percentages (at.%) of sulfur-containing components, arsenic, germanium, and Group III elements.

[0072]

[0073] Table 1

[0074] In some cases, the amount of sulfur-containing components may be greater than or equal to 40 at.% of the chalcogenide material. The amount of arsenic may be less than or equal to 30 at.% of the chalcogenide material. In some cases, the amount of arsenic may be less than or equal to 1 at.% of the chalcogenide material (or otherwise measured in trace or micro amounts).

[0075] In some instances, the composition may not contain arsenic. In some instances, the amount of germanium may range from 8 at.% to 35 at.% of the chalcogenide material, and in some cases, the chalcogenide material may substantially correspond to region 505. In other instances, the amount of germanium may range from 20 at.% to 35 at.% of the chalcogenide material, and in some cases, the chalcogenide material may substantially correspond to region 510.

[0076] Group III elements may be at least one element selected from the group consisting of boron, aluminum, gallium, indium, and thallium, wherein the amount of said element is in the range of 1 at.% to 15 at.% (inclusive) of the chalcogenide material. In some cases, at least one element selected from said group may consist of indium in the range of 1 at.% to 15 at.% of the chalcogenide material. In some cases, at least one element selected from said group may consist of boron in the range of 1 at.% to 15 at.% of the chalcogenide material.

[0077] In some cases, at least one element selected from the group may consist of aluminum in an amount ranging from 1 at.% to 15 at.% of the chalcogenide material. In some cases, at least one element selected from the group may consist of gallium in an amount ranging from 1 at.% to 15 at.% of the chalcogenide material. In some cases, at least one element selected from the group may consist of titanium (TI) in an amount ranging from 1 at.% to 15 at.% of the chalcogenide material.

[0078] Chalcogenide material compositions may be constituted from the compositions identified in Table 2, which provide a range of compositions containing sulfur components, arsenic, germanium, and Group III elements in atomic percentage (at.%). For example, regions 505 and 510 may represent chalcogenide compositions identified in Table 2.

[0079]

[0080] Table 2

[0081] In some cases, the amount of sulfur-containing components may be greater than or equal to 40 at.% of the chalcogenide material. The amount of arsenic may be less than or equal to 40 at.% of the chalcogenide material. In some cases, the amount of arsenic may be less than or equal to 30 at.% of the chalcogenide material, the amount of arsenic may be less than or equal to 1 at.% of the chalcogenide material, or a certain amount of arsenic may be absent from the chalcogenide material. In some instances, the amount of germanium may range from 8 at.% to 35 at.% of the chalcogenide material. In some cases, the presence of germanium may affect the threshold voltage drift. Group III elements may be at least one element selected from the group consisting of boron, aluminum, gallium, indium, and thallium, and may be included in the composition in an amount ranging from 1 at.% to 15 at.% of the composition.

[0082] Chalcogenide material compositions may be constituted from the compositions identified in Table 3, which provide a range of compositions containing sulfur components, arsenic, germanium, and Group III elements in atomic percentage (at.%). For example, region 510 may represent a chalcogenide composition identified in Table 3.

[0083]

[0084] Table 3

[0085] In some cases, the amount of sulfur-containing components may be greater than or equal to 40 at.% of the chalcogenide material. The amount of arsenic may be less than or equal to 30 at.% of the chalcogenide material. In some cases, the amount of arsenic may be less than or equal to 40 at.% of the chalcogenide material, the amount of arsenic may be less than or equal to 1 at.% of the chalcogenide material, or a certain amount of arsenic may be absent from the chalcogenide material. In some instances, the amount of germanium may be in the range of 20 at.% to 35 at.% of the chalcogenide material. Group III elements may be at least one element selected from the group consisting of boron, aluminum, gallium, indium, and thallium, and may be included in the composition in the form of an amount in the range of 1 at.% to 15 at.% of the chalcogenide material.

[0086] In some cases, arsenic may be absent from chalcogenide materials (or present only in trace amounts or otherwise). In these cases, the material composition may be completely or almost completely free of arsenic. For example, zone 515 may represent a chalcogenide composition that is free of arsenic. Making a chalcogenide material composition free of arsenic can provide values ​​regarding security costs (e.g., direct insertion processing control, selector device manufacturer availability, and environmental impact) for memory devices. In some cases, the absence of arsenic in chalcogenide materials can reduce the complexity of the composition, thereby simplifying the chemical deposition process. Compositions that may contain sulfur-containing components and germanium, and potentially Group III elements but are arsenic-free, can also enhance the integration of chalcogenide material compositions with cross-point technology development (e.g., three-dimensional cross-point architectures, ReRAM, DRAM, RAM, etc.), thereby enabling ALD deposition. In some cases, the absence of arsenic in a chalcogenide material composition can be detected using transmission electron microscopy (TEM), electron dispersion X-ray spectroscopy (EDX), or both.

[0087] Figure 5B Figure 500-b illustrates the properties of chalcogenide materials according to examples disclosed herein. For example, Figure 500-b illustrates a composition containing a sulfur-containing component and germanium, and in some cases, the composition may also be doped with a Group III element (e.g., indium). Figure 500-b, including region 520, illustrates a composition containing a chalcogenide material that does not contain arsenic (e.g., an arsenic-free composition), and may correspond, for example, to a composition included in Figure 500-a along the sulfur-containing component-germanium connecting line (e.g., including region 515).

[0088] As described herein, Group III elements can be incorporated into material compositions, such as those containing sulfur and germanium, to provide various benefits. In some cases, Group III elements can be incorporated into material compositions containing sulfur and germanium. For example, the memory window can increase with increasing amounts of Group III elements and germanium in the material composition. On the other hand, the memory window can decrease with increasing amounts of Group III elements and germanium in the material composition. In some cases, increasing the memory window can increase the scalability of the memory element's thickness.

[0089] In some instances, the chalcogenide composition may not contain arsenic. For example, region 520 may represent a composition that does not contain arsenic. In these cases, the absence of arsenic may not affect the memory window. For example, a composition that does not contain arsenic (or contains very little arsenic) as depicted by region 520 may have a memory window that is very little different from that of a composition containing arsenic (e.g., the same as, substantially the same as, or at least operationally feasible for a memory device). However, the absence of arsenic may have various benefits as discussed elsewhere herein.

[0090] In some instances, the sulfur-containing component may be pure sulfur or a combination of sulfur with one or more other elements, such as a combination of sulfur and selenium, sulfur and oxygen, or sulfur, selenium, and oxygen. For example, at least a portion of the selenium in a SAG composition or a III-SAG composition may be replaced by sulfur. That is, the relative ratios of non-sulfur-containing components (e.g., arsenic, germanium, and one or more Group III elements) may be as described above, while the sulfur-containing component may be sulfur or a mixture of sulfur with one or more other elements (e.g., sulfur and selenium).

[0091] Replacing at least some of the selenium with sulfur can affect various chemical or electrical properties of chalcogenide materials. For example, the sulfur bond energy between the non-sulfur-containing components of a chalcogenide material can be higher than the selenium bond energy between the non-sulfur-containing components (e.g., the sulfur-arsenic bond energy can be 379 kJ / mol, while the selenium-arsenic bond energy can be 96 kJ / mol). Therefore, chalcogenide compositions in which at least some of the selenium is replaced with sulfur can exhibit stronger bonds between the sulfur-containing and non-sulfur-containing components. However, the volatility of sulfur (e.g., pure or substantially pure sulfur) can be higher than that of selenium (e.g., pure or substantially pure selenium).

[0092] Furthermore, the band gap energy of a chalcogenide composition containing a sulfur-containing component can advantageously be higher than that of a chalcogenide composition not containing a sulfur-containing component. For example, due to the higher band gap energy of the chalcogenide composition containing a sulfur-containing component, the associated conductivity may be higher, which may advantageously reduce leakage current. Therefore, a memory element comprising a chalcogenide using a sulfur-containing component (and thus a memory cell comprising said memory element) may be thinner (e.g., in the direction corresponding to the direction of the voltage applied across the memory cell) compared to a memory element comprising a chalcogenide without a sulfur-containing component, while still maintaining acceptable leakage current.

[0093] Therefore, replacing at least some of the selenium with sulfur can reduce the leakage current of chalcogenide materials. For example, configuring the sulfur-containing component to contain at least 25 at.% sulfur (e.g., no more than 75 at.% selenium or other non-selenium elements) allows for a useful reduction in leakage. Thus, in some instances, the amount of sulfur contained in the sulfur-containing component may be greater than or equal to at least one-third (1 / 3) of the amount of selenium contained in the sulfur-containing component (e.g., the amount of selenium contained in the sulfur-containing component may be less than or equal to three times (3x) the amount of sulfur contained in the sulfur-containing component). Alternatively or in some instances, the sulfur-containing component may be at least 40 at.% of the chalcogenide composition, so that the sulfur-containing component containing at least 25 at.% sulfur corresponds to sulfur being at least 10 at.% of the chalcogenide composition.

[0094] Furthermore, adjusting the thickness of memory elements comprising chalcogenide materials can affect the threshold voltage of the memory cell. For example, introducing sulfur into the chalcogenide material within the memory cell may increase the threshold voltage. However, since the introduction of sulfur allows for a reduction in the thickness of the memory cell while maintaining an acceptable leakage current, and since reducing the thickness of the memory cell reduces the threshold voltage, it is advantageous to make memory cells comprising chalcogenide materials as described herein thinner while maintaining desired leakage current and voltage threshold characteristics. Therefore, replacing selenium with sulfur can reduce leakage current, allow for a reduction in the thickness of the memory cell while maintaining a fixed threshold voltage, or any combination thereof.

[0095] In some cases, replacing at least some selenium with sulfur in a chalcogenide material may further affect the difference between threshold voltages corresponding to different logic states of a memory cell containing chalcogenide material (e.g., the threshold voltage window, which may alternatively be referred to as the read window or read window budget). For example, the threshold voltage window of a memory cell may be affected by the atomic bonding strength of the components of the chalcogenide material of the memory cell. Specifically, chalcogenide materials containing more ionic components can amplify the threshold voltage window (e.g., increase the difference in threshold voltages corresponding to different logic states). In some instances, replacing at least some selenium with sulfur can increase the ionic bonding component of the chalcogenide material and thus amplify the threshold voltage window. Therefore, relative to other chalcogenide materials, for chalcogenide materials as described herein, the amount of Group III elements that can amplify the threshold voltage window but increase current leakage can be reduced or the Group III elements can be removed (e.g., because the threshold voltage window due to the increase of sulfur can compensate for the possible reduction of the threshold voltage window due to the reduction or removal of the amount of Group III elements), which can reduce leakage current.

[0096] In some cases, replacing at least some selenium with sulfur in a chalcogenide material may further affect the threshold voltage drift over time (e.g., drift rate) of a memory cell containing the chalcogenide material. For example, the drift rate of a chalcogenide material containing selenium may be lower than that of a chalcogenide material containing tellurium (Te) because selenium has a stronger bond relative to tellurium (e.g., because selenium precedes tellurium in the periodic table). Therefore, since sulfur may exhibit a stronger bond relative to selenium (e.g., because sulfur precedes selenium in the periodic table), the drift rate of a chalcogenide material containing at least some sulfur may be lower than that of a chalcogenide material without sulfur. Furthermore, by extension, chalcogenide materials containing at least some oxygen may exhibit even further reduced drift rates. Therefore, the sulfur-containing component may, in some cases, contain at least some oxygen and sulfur, and potentially selenium. Thus, memory cells containing chalcogenide materials with sulfur-containing components can allow for lower operating bias, which reduces power consumption.

[0097] A composition of substances is described. An overview of various aspects of the composition of substances as described herein is provided below:

[0098] Aspect 1: A material composition comprising: a component including sulfur (e.g., a sulfur-containing component), wherein the amount of said sulfur-containing component is greater than or equal to 40 at.% of the composition. In some examples, the material composition may contain germanium in an amount ranging from 8 at.% to 35 at.% of the composition. In some examples, the material composition may contain at least one element selected from the group consisting of boron, aluminum, gallium, indium, and thallium, said element in an amount ranging from 1 at.% to 15 at.% of the composition.

[0099] Aspect 2: The composition according to aspect 1, wherein the sulfur-containing component further comprises selenium.

[0100] Aspect 3: The composition according to any one of Aspects 1 to 2, wherein the composition comprises a first amount of sulfur and a second amount of selenium, the first amount being greater than or equal to one-third of the second amount.

[0101] Aspect 4: The composition according to any one of Aspect 1, wherein the composition does not contain selenium.

[0102] Aspect 5: The composition according to any one of Aspects 1 to 4, wherein the composition contains more than or equal to 10% sulfur.

[0103] Aspect 6: The composition according to any one of Aspects 1 to 5, wherein the sulfur-containing component further comprises oxygen.

[0104] Aspect 7: The composition according to any one of Aspects 1 to 6, wherein the composition contains less than or equal to 30 at.% of arsenic in the composition.

[0105] Aspect 8: The composition according to any one of Aspects 1 to 7, wherein the amount of germanium is in the range of 20 at.% to 35 at.% of the composition.

[0106] Aspect 9: The composition according to any one of Aspects 1 to 8, wherein the at least one element selected from the group comprises indium in an amount ranging from 1 at.% to 15 at.% of the composition.

[0107] Aspect 10: A composition according to any one of Aspects 1 to 8, wherein the at least one element selected from the group comprises boron in an amount ranging from 1 at.% to 15 at.% of the composition.

[0108] Aspect 11: The composition according to any one of Aspects 1 to 8, wherein the at least one element selected from the group comprises aluminum in an amount ranging from 1 at.% to 15 at.% of the composition.

[0109] Aspect 12: A composition according to any one of aspects 1 to 8, wherein the at least one element selected from the group comprises gallium in an amount ranging from 1 at.% to 15 at.% of the composition.

[0110] Aspect 13: A composition according to any one of aspects 1 to 8, wherein the at least one element selected from the group comprises thallium in an amount ranging from 1 at.% to 15 at.% of the composition.

[0111] A device is described. An overview of various aspects of the device as described herein is provided below:

[0112] Aspect 14: An apparatus comprising: a memory cell comprising a chalcogenide material, the chalcogenide material comprising: a component comprising sulfur, wherein the amount of the sulfur-containing component is greater than or equal to 40 at.% of the chalcogenide material; germanium in an amount ranging from 8 at.% to 35 at.% of the chalcogenide material; and at least one element selected from the group consisting of boron, aluminum, gallium, indium and thallium, the amount of said element ranging from 1 at.% to 15 at.% of the chalcogenide material.

[0113] Aspect 15: The device according to aspect 14, wherein the sulfur-containing component further comprises selenium.

[0114] Aspect 16: The apparatus according to any one of Aspects 14 to 15, wherein the chalcogenide material does not contain selenium.

[0115] Aspect 17: The apparatus according to any one of aspects 14 to 16, wherein the chalcogenide material comprises more than or equal to 10% of the sulfur in the composition.

[0116] Aspect 18: The apparatus according to any one of aspects 14 to 17, wherein the sulfur-containing component further comprises oxygen.

[0117] Aspect 19: The device according to any one of Aspects 14 to 18, wherein the memory unit includes a storage element available for storing logical values, the storage element comprising the chalcogenide material.

[0118] Aspect 20: The device according to aspect 19, wherein the storage element is a self-selected storage element.

[0119] Aspect 21: The apparatus according to any one of Aspects 19 to 20, wherein the storage element is configured to store a first logic value based at least in part on a voltage of a first polarity applied across the chalcogenide material and a second logic value based at least in part on a voltage of a second polarity applied across the chalcogenide material.

[0120] A device is described. An overview of various aspects of the device as described herein is provided below:

[0121] Aspect 22: An apparatus comprising: a first access line; a second access line; and a memory cell comprising a chalcogenide material, the chalcogenide material comprising sulfur, germanium, and at least one of boron, aluminum, gallium, indium, or thallium, wherein the first access line is in electronic communication with the second access line via the memory cell.

[0122] Aspect 23: The apparatus according to aspect 22, wherein: in the chalcogenide material, the component comprising sulfur comprises 40 at.% or greater than or equal to 40 at.% of the chalcogenide material; the amount of germanium is in the range of 8 at.% to 35 at.% of the chalcogenide material; and the amount of at least one of boron, aluminum, gallium, indium or thallium is in the range of 1 at.% to 15 at.% of the chalcogenide material.

[0123] Aspect 24: The apparatus according to aspect 23, wherein the component comprising the sulfur further comprises selenium, oxygen, or both.

[0124] Aspect 25: The device according to any one of Aspects 22 to 24, wherein the memory unit includes a storage element available for storing logical values, the storage element comprising the chalcogenide material.

[0125] The information and signals described herein can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, the signal may represent a bus of signals, which may have various bit widths.

[0126] The terms "electronic communication," "conductive contact," "connection," and "coupling" can refer to the relationship between components that enable the flow of signals between them. Components are considered to be in electronic communication (or in conductive contact, connected, or coupled) with each other if there exists any conductive path between them that enables the flow of signals at any given time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path or an indirect conductive path, which may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the flow of signals between connected components for a period of time.

[0127] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship, in which a signal is currently unable to travel between the components via a conductive path, and in which a signal can travel between the components via the conductive path. When a component, such as a controller, couples other components together, the component initially allows a change in the flow of signals between the other components via conductive paths that were previously not permitted.

[0128] The term "isolation" refers to a relationship between components in which signals are currently unable to flow between them. Components are isolated from each other if there is an open circuit between them. For example, components isolated by a switch positioned between two components are isolated from each other when the switch is open. When a controller isolates two components, it prevents signals from flowing between the components using previously permitted conductive paths.

[0129] As used herein, the term "layer" or "level" refers to the number of layers or sheets of a geometry (e.g., relative to a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or level may be a three-dimensional structure in which two dimensions are greater than the third dimension, such as a thin film. A layer or level may contain different elements, components, and / or materials. In some instances, a layer or level may consist of two or more sublayers or sublevels.

[0130] As used herein, the term “generally” means that a modified feature (e.g., a verb or adjective modified by the term “generally”) need not be absolute but must be close enough to achieve the advantages of the feature.

[0131] As used herein, the term "electrode" can refer to an electrical conductor and, in some instances, can be used as an electrical contact to a memory cell or other component of a memory array. An electrode may comprise traces, wires, conductive lines, conductive layers, etc., that provide a conductive path between elements or components of the memory array.

[0132] The devices containing memory arrays discussed herein can be formed on semiconductor substrates such as selenium, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by using doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0133] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. These terminals may be connected to other electronic components via a conductive material, such as a metal. The source and drain may be conductive and may comprise heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority of charge carriers are electrons), the FET may be called an n-type FET. If the channel is p-type (i.e., the majority of charge carriers are holes), the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can make the channel conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0134] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0135] In the accompanying drawings, similar components or features may have the same reference numerals. Additionally, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral used to differentiate them among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components that have the same first reference numeral but are independent of the second reference numeral.

[0136] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or code on or transmitted over a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distribution such that different parts of the functions are implemented in different physical locations.

[0137] For example, the various illustrative blocks and modules described in connection with this disclosure may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor; however, alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0138] As used herein (included in the claims), "or" as used in a list of items (e.g., a list of items preceding, for example, "at least one of" or "one or more of") indicates an inclusive list, such that a list of, for example, at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Similarly, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0139] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A composition comprising: The composition includes components of sulfur and selenium, wherein sulfur is present in a first amount and selenium in a second amount, the first amount being greater than or equal to one-third of the second amount, and wherein the amount of the components including sulfur and selenium is greater than or equal to 40 atomic percentages at.% of the composition. The amount of germanium in the composition is in the range of 8 at.% to 35 at.%; as well as At least one element selected from the group consisting of boron, aluminum, gallium, indium and thallium, wherein the amount of said element is in the range of 1 at.% to 15 at.% of the composition.

2. The composition according to claim 1, wherein the composition comprises the sulfur in an amount greater than or equal to 10% of the composition.

3. The composition according to claim 1, wherein the component comprising sulfur and selenium further comprises oxygen.

4. The composition according to claim 1, further comprising: The amount of arsenic is less than or equal to 30 at.% of the composition.

5. The composition according to claim 1, wherein the amount of germanium is in the range of 20 at.% to 35 at.% of the composition.

6. The composition of claim 1, wherein the at least one element selected from the group comprises indium in an amount ranging from 1 at.% to 15 at.% of the composition.

7. The composition according to claim 1, wherein the at least one element selected from the group comprises boron in an amount ranging from 1 at.% to 15 at.% of the composition.

8. The composition of claim 1, wherein the at least one element selected from the group comprises aluminum in an amount ranging from 1 at.% to 15 at.% of the composition.

9. The composition of claim 1, wherein the at least one element selected from the group comprises gallium in an amount ranging from 1 at.% to 15 at.% of the composition.

10. The composition of claim 1, wherein the at least one element selected from the group comprises thallium in an amount ranging from 1 at.% to 15 at.% of the composition.

11. A memory device comprising: Memory cells comprising chalcogenide materials, wherein the chalcogenide materials include: The composition includes sulfur and selenium, with sulfur having a first amount and selenium having a second amount, the first amount being greater than or equal to one-third of the second amount, wherein the amount of the sulfur and selenium-containing components is greater than or equal to 40 atomic percentages (at.%) of the chalcogenide material. Germanium in amounts ranging from 8 at.% to 35 at.% of the chalcogenide material; and At least one element selected from the group consisting of boron, aluminum, gallium, indium and thallium, wherein the amount of said element is in the range of 1 at.% to 15 at.% of the chalcogenide material.

12. The memory device of claim 11, wherein the chalcogenide material comprises sulfur in a first amount greater than or equal to 10% of the chalcogenide material.

13. The memory device of claim 11, wherein the component comprising sulfur and selenium further comprises oxygen.

14. The memory device of claim 11, wherein the memory cell includes a storage element capable of storing logical values, the storage element comprising the chalcogenide material.

15. The memory device of claim 14, wherein the memory element includes a selectable memory element.

16. The memory device of claim 14, wherein the memory element is configured to store a first logic value based at least in part on a voltage of a first polarity applied across the chalcogenide material and a second logic value based at least in part on a voltage of a second polarity applied across the chalcogenide material.

17. A memory device comprising: First access line; Second access line; as well as A memory cell comprising a chalcogenide material, the chalcogenide material comprising a first amount of sulfur, a second amount of selenium, germanium, and at least one of boron, aluminum, gallium, indium, or thallium, wherein the first amount is greater than or equal to one-third of the second amount, the amount of the at least one of boron, aluminum, gallium, indium, or thallium is in the range of 1 atomic percentage at.% to 15 at.% of the chalcogenide material, and wherein a first access line is in electronic communication with a second access line via the memory cell.

18. The memory device of claim 17, wherein: Within the chalcogenide material, the sulfur-containing component comprises 40 at.% or more of the chalcogenide material; and The amount of germanium is in the range of 8 at.% to 35 at.% of the chalcogenide material.

19. The memory device of claim 18, wherein the component comprising the sulfur further comprises oxygen.

20. The memory device of claim 17, wherein the memory cell includes a storage element capable of storing logical values, the storage element comprising the chalcogenide material.

Images