Application coverage of power estimation mechanisms

Abstract

A system, apparatus, and method for performing a software overlay of a power estimation mechanism are disclosed. A computing system includes a plurality of tuned parameters for generating an estimate of power consumption. The tuned parameters are generated based on post-silicon characterization of the system. After deployment, the system executes a plurality of different applications. When a particular application is launched, the system loads a corresponding set of overlay parameters that replace the plurality of tuned parameters. The system generates an estimate of power consumption using the set of overlay parameters instead of previously determined tuned parameters. Then, when executing the particular application, the system adjusts power and frequency values ​​of various system components based on the estimate of power consumption.

Description

Background Art

[0001] Related technical description

[0002] With the development of each generation of semiconductor chips, the power consumption of modern integrated circuits (ICs) has become an increasingly prominent design issue. ICs typically include a power management unit (PMU) that is used to manage the power consumption of various components (such as general-purpose processors, graphics processors, other processing units, and other components). The PMU can use dynamic voltage and frequency scaling (DVFS) technology to adjust the power performance state (P state) based on various factors. The algorithm used for P state adjustment can assume the worst-case thermal conditions. However, during typical use and environment, the worst-case thermal conditions may not actually apply. Therefore, due to the assumptions in the algorithm, a lower performance state may be unnecessarily selected during these times. Generally speaking, higher performance leads to higher power consumption. On the contrary, limiting the amount of power consumed limits the possible performance of computers or other types of processor-based electronic systems.

[0003] For some types of computing systems, the system is programmed to run at a fixed clock frequency for all applications. Since many different types of applications can run on a computing system, a clock frequency is selected for a worst-case scenario and then all applications use that worst-case clock frequency. However, the behavior of applications often varies, and the amount of power consumed by different applications when running at a fixed frequency can vary widely. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Advantages of the methods and mechanisms described herein may be better understood by referring to the following description in conjunction with the accompanying drawings, in which:

[0005] Figure 1 is a block diagram of a specific implementation of a computing system.

[0006] Figure 2 is a block diagram of one specific implementation of a system for allowing software to override hardware mechanisms for power management.

[0007] Figure 3 is a block diagram of a specific implementation of the power controller algorithm.

[0008] Figure 4 is a generalized flow chart illustrating one specific implementation of a method for enabling application overlay of a power estimation mechanism.

[0009] Figure 5 is a generalized flow chart illustrating one specific implementation of a method for loading a new power estimation equation.

[0010] Figure 6is a generalized flow chart illustrating one specific implementation of a method for using a per-application set of overlay parameters.

[0011] Figure 7 is a generalized flow chart illustrating one specific implementation of a method for allocating power budgets to components of a computing system.

[0012] Figure 8 is a generalized flow chart illustrating one specific implementation of a method for applying adjustments to tuned power estimation parameters. DETAILED DESCRIPTION

[0013] In the following description, many specific details are set forth to provide a thorough understanding of the methods and mechanisms presented herein. However, it will be appreciated by those of ordinary skill in the art that various specific implementations may be practiced without these specific details. In some cases, well-known structures, components, signals, computer program instructions, and techniques are not shown in detail to avoid blurring the methods described herein. It should be understood that, for simplicity and clarity of description, the elements shown in the accompanying drawings are not necessarily drawn to scale. For example, the size of some of these elements may be enlarged relative to other elements.

[0014] Systems, devices, and methods for enabling software overriding of power estimation parameters are disclosed. In one specific implementation, a computing system undergoes post-silicon characterization to tune various power estimation parameters. These tuned power estimation parameters are then hard-coded into the system. A power management unit uses these hard-coded parameters to perform subsequent power estimation calculations during deployment in a real-world environment. However, in order to optimize the power budget performed when allocating portions of the total power budget to different components within the system, the power management unit enables software executed on the system to override the tuned power estimation parameters on an application-by-application basis. This allows new applications to be profiled on the system to generate an alternative set of tuned power estimation parameters. The alternative set is loaded into the power management unit when the new application is executed. These and other enhanced power estimation techniques will be described throughout the remainder of this disclosure.

[0015] Reference now Figure 1 , a block diagram of one implementation of a computing system 100 is shown. In one implementation, computing system 100 includes at least processors 105A-N, input / output (I / O) interface 120, bus 125, memory controller 130, network interface 135, memory device 140, display controller 150, display 155, and power management unit (PMU) 160. In other implementations, computing system 100 includes other components and / or computing system 100 is arranged in a different manner. Processors 105A-N represent any number of processors included in system 100.

[0016] In one implementation, processor 105A is a general purpose processor, such as a central processing unit (CPU). In this implementation, processor 105A executes a driver 110 (e.g., a graphics driver) for communicating with and / or controlling the operation of one or more other processors in system 100. It should be noted that, depending on the implementation, driver 110 may be implemented using any suitable combination of hardware, software, and / or firmware. In one implementation, processor 105N is a data parallel processor with a highly parallel architecture. Data parallel processors include graphics processing units (GPUs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), and the like. In some implementations, processors 105A-N include multiple data parallel processors. In one implementation, processor 105N is a GPU that provides pixels to display controller 150 for driving to display 155.

[0017] The memory controller 130 represents any number and type of memory controllers accessible by the processors 105A-N. Although the memory controller 130 is shown as being separate from the processors 105A-N, it should be understood that this merely represents one possible implementation. In other implementations, the memory controller 130 may be embedded within one or more of the processors 105A-N, and / or the memory controller 130 may be located on the same semiconductor chip as one or more of the processors 105A-N. The memory controller 130 is coupled to any number and type of memory devices 140. The memory devices 140 represent any number and type of memory devices. For example, the types of memory in the memory devices 140 include dynamic random access memory (DRAM), static random access memory (SRAM), NAND flash memory, NOR flash memory, ferroelectric random access memory (FeRAM), etc.

[0018] The I / O interface 120 represents any number and type of I / O interfaces (e.g., a peripheral component interconnect (PCI) bus, a PCI-Extended (PCI-X), a PCIE (PCI Express) bus, a Gigabit Ethernet (GBE) bus, a Universal Serial Bus (USB)). Various types of peripheral devices (not shown) are coupled to the I / O interface 120. Such peripheral devices include (but are not limited to) a display, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, etc. The network interface 135 is capable of receiving and sending network messages over a network.

[0019] The PMU 160 manages the power consumption of the system 100 by adjusting various operating settings (e.g., voltage levels, clock frequencies) provided to the various functional units of the system 100 based on the power consumption and temperature of the system 100 during run time. In one implementation, the PMU 160 includes hard-coded parameters 165 that are used to generate an estimate of the power consumption of the system 100 during deployment. In one implementation, the parameters 165 are determined during a profiling phase of the system 100. These parameters 165 may include variables such as one or more capacitance coefficients, one or more filter coefficients, one or more error coefficients, one or more error rate coefficients, and other variables associated with the functional units of the system 100. In one implementation, the PMU 160 allows software executing on the processors 105A-N to override the parameters 165 on an application-by-application basis. The software can replace the hard-coded parameters 165 with a new set of parameters tuned for the new application. This allows the new application to precisely tune the power estimation and power allocation mechanisms of the system 100 and potentially achieve higher performance than would be possible using the hard-coded parameters 165. These and other power estimation parameter overlay techniques will be described throughout the remainder of this disclosure.

[0020] In various implementations, computing system 100 is any of a computer, a laptop, a mobile device, a game console, a server, a streaming device, a wearable device, or various other types of computing systems or devices. It should be noted that the number of components of computing system 100 varies from implementation to implementation. For example, in other implementations, there are more than 10 components. Figure 1 More or less of each component may be shown. It should also be noted that in other implementations, the computing system 100 includes Figure 1 In addition, in other specific implementations, the computing system 100 may be configured to be different from Figure 1 Constructed in the manner shown.

[0021] Now turn to Figure 2, a block diagram of a specific implementation of a system 200 for allowing software to override hardware mechanisms for power management is shown. In one specific implementation, the system 200 includes a power management unit 220 for controlling the power consumption and / or power performance states of various components 245A-N. The power management unit 220 can be implemented using any suitable combination of circuits and / or program instructions. In one specific implementation, a control unit 222 of the power management unit 220 adjusts the clock frequency and voltage provided to the components 245A-N to ensure that the system 200 operates within specified power, current, and thermal limits. In addition, in various specific implementations, the control unit 222 of the power management unit 220 attempts to maximize the performance of the system 200 while meeting the power, current, and thermal limits. The components 245A-N represent any number and type of components (e.g., CPU, GPU, memory subsystem, cache subsystem, I / O device).

[0022] In one implementation, the system 200 is tuned for power management purposes with various hard-coded parameters 205A-N generated based on the characteristics of specific physical components after manufacturing. These parameters 205A-N include one or more of the following: a first filter alpha value, a second filter alpha value, a CPU error coefficient, a CPU error rate coefficient, a GPU error coefficient, a GPU error rate coefficient, a capacitance coefficient value, etc. However, instead of using only the previously tuned parameters 205A-N, the system 200 allows software to override one or more of these parameters 205A-N. For example, in one implementation, the software sends override values ​​203A-N coupled to multiplexers 210A-N to allow the software to override the stored parameters 205A-N on a parameter-by-parameter basis. It should be understood that the multiplexers 210A-N are merely intended to illustrate a logical representation of the ability of software to override individual parameters 205A-N, and are not intended to be an exact representation of an override mechanism.

[0023] For example, in another specific implementation, the software writes the override values ​​203A-N to a specific location in memory, and then the software sends an override request or command (e.g., writes the override values ​​to an override register) to notify the power management unit 220 that the override mode should be enabled. In response, the power management unit 220 uses these override values ​​203A-N as part of the calculations performed to determine how to program the voltage levels of the voltages 235A-N and the frequencies of the clocks 240A-N. It should be noted that other ways of providing the override values ​​from the software to the power management unit 220 and other techniques for initiating the override mode are possible and contemplated.

[0024] In one implementation, the operating system (OS) (or other system software) determines whether to override the tuned parameters 205A-N on an application-by-application basis. For example, in one implementation, a first application has a first set of software override values, a second application has a second set of software override values, and so on. This allows each application to precisely tune the performance and power consumption of the system 200 based on profiling and analysis of how the application will perform on the system 200.

[0025] In various implementations, the power management unit 220 receives various inputs and / or measurements from sensors. These inputs and / or measurements include temperature measurements, current measurements, and the like. In addition, the power management unit 220 receives override values ​​203A-N and / or hard-coded parameters 205A-N via interfaces 212A-N, and the power management unit 220 generates an estimate of the real-time power consumption of the system 200 based on applying the override values ​​203A-N and / or hard-coded parameters 205A-N to the sensor inputs and measurements. It should be noted that the interfaces 212A-N may be implemented as a single interface or multiple interfaces depending on the implementation. After generating the power estimate, the power management unit 220 uses the power estimate to determine how to adjust the various voltages 235A-N and the frequencies of the clocks 240A-N provided to the components 245A-N.

[0026] For example, in one implementation, the power management unit 220 receives an indication of the voltage provided to a given component 245A-N. The power management unit 220 also retrieves the corresponding capacitance coefficient for the given component 245A-N. The capacitance coefficient may be an original hard-coded value or an override value provided by software. Then, in one implementation, the power management unit 220 multiplies the capacitance coefficient by the voltage squared times the clock frequency times the scaling factor (α) (i.e., C*V 2 *F*α). The scaling factor can be an original hard-coded value or an override value provided by software. The result of the multiplication is used as an estimate of the power consumption of the given component 245A-N. The power management unit 220 generates estimates of the power consumption of other components 245A-N in a similar manner, and then adds the estimates together to generate an estimate of the power consumption of the entire system 200. It should be understood that this is just one example of generating a power estimate. Those skilled in the art will understand that other techniques for generating power estimates may be used in other specific implementations.

[0027] In various implementations, after generating a power estimate for the system 200, the power management unit 220 compares the power estimate to the total power budget. In one implementation, if the power estimate is greater than the total power budget, the power management unit 220 reduces the voltage and / or frequency provided to the components 245A-N to reduce the power consumption of the system 200. In one implementation, the amount by which the voltage and / or frequency is reduced is proportional to the difference between the power estimate and the total power budget. If the power estimate is less than the total power budget, the power management unit 220 increases the voltage and / or frequency provided to the components 245A-N to achieve greater performance of the system 200. In another implementation, the power management unit 220 attempts to keep each component 245A-N within a given component power budget while also keeping the entire system 200 within the total power budget.

[0028] Other techniques for allocating power to components 245A-N may be implemented to achieve optimal performance. For example, in another specific implementation, the system 200 as a whole has a power budget, and one component 245A-N utilizes all remaining power from the power budget, rather than being constrained to specific per-component limits. When performing system-level power calculations, the power management unit 220 may use budget values ​​or calculated values ​​for the individual components 245A-N. In addition, in another specific implementation, the power management unit 220 allows a software application and / or OS to control the frequency and voltage provided to each component 245A-N. For example, in one specific implementation, the frequency and voltage are set by the OS or application based on the results of the profiling. Other ways of keeping the system 200 within a specified power budget while allocating power between components 245A-N are possible and contemplated.

[0029] In one specific implementation, system 200 is a video game console capable of executing any number of different games. Typically, system 200 is characterized after manufacturing, and lower-level parameters and variables (e.g., hard-coded parameters 205A-N) used for power calculations are tuned during this characterization phase. However, this does not take into account the differences in how system 200 consumes power for different types of games that will be played on system 200. Although games can be profiled on system 200 after manufacturing, this is impossible for new games developed after system 200 has been deployed. Therefore, in order to alleviate these situations, system 200 allows software to overwrite lower-level variables on a per-title basis for each different game title. This allows for performance optimization for each different game played on system 200. Although a video game console is described in this example, it should be understood that other types of systems and devices may also benefit from the methods and mechanisms described herein.

[0030] Reference now Figure 3, a block diagram of a specific implementation of the power controller algorithm 300 is shown. In one specific implementation, a computing system (e.g., Figure 1 System 100, Figure 2 The system 200 of the present invention employs a power controller algorithm 300 to adjust the operating conditions of the components of the system so as to remain within a power envelope (i.e., a given power consumption range). In another specific implementation, the power controller algorithm 300 is used to keep the system within a thermal envelope (i.e., a given temperature range). In another specific implementation, the power controller algorithm 300 is used to keep the system within a power envelope and a thermal envelope.

[0031] In one implementation, power calculation 305 is performed to generate an estimate of the power consumption of the computing system. Depending on the application executed by the computing system, power calculation 305 may use a predetermined set of parameter values, or power calculation 305 may use a target set of parameter values ​​customized for a particular application. In one implementation, power calculation 305 is performed with a set of parameters that cover a set of parameter values ​​for the system's load that were previously determined during post-silicon characterization. An example of power calculation 305 is the power equation presented previously (Power = C*V 2 *F*α). However, other types of power equations may be used in other implementations.

[0032] After performing the power calculation 305 to generate the power estimate, the power estimate is provided as an input to the filter 310. In one implementation, the filter 310 is a two-stage alpha filter having an infinite impulse response filter with one coefficient (e.g., alpha coefficient 315) that defines the time constant. It should be noted that the alpha coefficient 315 is a different variable than the alpha variable used in the power equation. The two-stage filter can be implemented as two alpha filters in series. An example of the filter 310 according to one implementation is shown in the equation in the dashed box 312 below the filter 310. In this implementation, the filter 310 has two output stages (OUTPUT_STAGE1) calculated based on the values ​​(ALPHA) and (1-ALPHA). n and OUTPUT_STAGE2 n ). It should be understood that the equation in dashed box 312 represents only one way to implement filter 310. It should be noted that in other embodiments, other types of filter equations may be used when implementing filter 310.

[0033] The output of filter 310 (i.e., FILTER_OUTPUT n) is provided to a proportional-derivative (PD) controller 320. In one implementation, the PD controller 320 uses a proportional-derivative control loop mechanism based on the P and D coefficients 325 but with the integral coefficient set to 0 to adjust the frequency target of the clock being controlled. It should be noted that the P and D coefficients 325 may also be referred to as error and error rate coefficients, respectively. An example of a specific implementation of the proportional-derivative control loop mechanism is shown in the equation of the dashed box 322. In other implementations, the PD controller 320 may use other types of control loop mechanisms besides a control loop mechanism based on proportional-derivative control.

[0034] As shown in the equation of the dashed box 322, the error term is calculated as a percentage error rather than an absolute error. In the equation of the dashed box 322, the error coefficient is referred to as "ERROR_COEFF" and the error rate coefficient is referred to as "ERROR_RATE_COEFF". The output of the proportional-derivative controller 320 is provided to the frequency change box 330 for changing the frequency target of the clock being controlled. In one specific implementation, once the output of the PD controller 320 is calculated, the output is added to the frequency target of the previous frequency target of the given controller. The final frequency target is then limited to the maximum frequency and minimum frequency of the clock. After initiating a frequency change for a given component, the power management unit waits for a certain amount of time (e.g., 1 millisecond (ms)) before starting again and performing a new power calculation 305, as indicated by the wait box 335.

[0035] Now turn to Figure 4 , shows a specific implementation of a method 400 for implementing an application coverage of a power estimation mechanism. For discussion purposes, the specific implementation and Figures 5 to 8 However, it should be noted that in various implementations of the described method, one or more of the described elements are performed simultaneously, in a different order than shown, or completely omitted. Other additional elements are also performed as needed. Any of the various systems or devices described herein is configured to implement method 400.

[0036] The computing system detects initiation of execution of a new software application (block 405). In response to detecting that the new software application is initiated, the computing system determines whether to operate in a power estimation override mode during execution of the new software application (block 410). In one implementation, the new software application includes an indication or setting that specifies whether to use a power estimation override mode during execution of the new software application. In other implementations, other ways of determining whether to implement a power estimation override mode may be used.

[0037] If the computing system decides to operate in the power estimation override mode (conditional box 415, "yes" branch), the computing system loads a given set of override parameters associated with the new software application (box 420). Next, the computing system programs the given set of override parameters into the power management unit (box 425). During the execution of the new software application, the power management unit receives runtime measurements and settings associated with various power-related values ​​(box 430). For example, these measurements may include, but are not limited to, temperature measurements, current measurements, voltage levels, frequency settings, and other measurements and settings. The power management unit then generates a power estimate during the runtime execution of the new application based on applying the given set of override parameters to the runtime measurements and settings (box 435). Next, the power management unit adjusts the voltage level and / or clock frequency provided to one or more components based on the generated power estimate (box 445). In a specific implementation, the power management unit adjusts the voltage level and / or clock frequency provided to one or more components based on the generated power estimate so as to meet a given power target. After box 445, method 400 ends.

[0038] Otherwise, if the computing system determines to operate in the standard power estimation mode (conditional block 415, "no" branch), the power management unit generates a power estimate during the runtime execution of the new application based on applying a predetermined set of parameters to the runtime measurements and settings (block 440). Following block 440, the power management unit adjusts the voltage level and / or clock frequency provided to one or more components based on the generated power estimate (block 445).

[0039] Reference now Figure 5, a specific implementation of a method 500 for loading a new power estimation equation is shown. The computing system detects a new application being executed (box 505). Next, the computing system loads a new power estimation equation associated with the new application (box 510). It should be noted that the new power estimation equation can be generated during the profiling phase when the new application is running on a test computing system that is similar to or matches the current computing system. The software (e.g., OS) running on the system programs the power management unit to use the new power estimation equation (box 515). It should be noted that the power management unit includes an existing power estimation equation that will be replaced (i.e., preempted) by the new power estimation equation, wherein the new power estimation equation is different from the existing power estimation equation. It should be noted that the existing power estimation equation can be referred to as a "first power estimation equation" and the new power estimation equation can be referred to as a "second power estimation equation". Alternatively, the power management unit can retain the existing power estimation equation, and the application can choose to use the existing or new power estimation equation. In other specific implementations, the power management unit maintains three or more separate power estimation equations, any of which can be selected by a given application.

[0040] Next, during execution of the new application, the power management unit generates a power estimate using the new power estimation equation (box 520). The power management unit makes adjustments to the operating conditions (e.g., voltage level, clock frequency) of one or more components based on the power estimate (box 525). After box 525, method 500 ends. It should be noted that if the computing system executes a different application at a later point in time, the computing system can revert to the previous power estimation equation or load another new power estimation equation specific to the other application. In some cases, each application can have its own precisely tuned power estimation equation that tracks the unique profile of the application. It should also be noted that boxes 520 and boxes 525 can be repeated any number of times during execution of the new application to generate multiple power estimates and make corresponding adjustments.

[0041] Now turn to Figure 6, shows a specific implementation of a method 600 for using an override parameter set for each application. A processor executes a first application on a computing system having a power management unit, the power management unit including a power estimation parameter override mechanism (box 605). Prior to or concurrently with executing the first application, the processor passes a first set of override parameters to the power management unit (box 610). The power management unit uses the first set of override parameters to calculate a power estimate for the computing system during execution of the first application (box 615). Next, the power management unit adjusts one or more operating settings (e.g., a supply voltage magnitude for each component, a clock frequency for each component) based on the calculated power estimate (box 620). At a later point in time, the processor switches execution to a second application different from the first application (box 625).

[0042] Prior to or during execution of the second application, the processor generates a power estimation parameter override request that is transmitted to the power management unit (block 630). In addition, the processor transmits a second set of override parameters to the power management unit, wherein the second set of override parameters is different from the first set of override parameters (block 635). In one specific implementation, the second set of override parameters is specified and / or provided by the second application. In response to detecting the power estimation parameter override request, the power management unit uses the second set of override parameters to calculate a power estimate for the computing system during execution of the second application (block 640). The power management unit then adjusts one or more operating settings based on the calculated power estimate (block 645). After block 645, method 600 ends. It should be noted that method 600 can be performed for any number of other applications, each of which has its own set of override parameters. It should also be noted that in one specific implementation, the first application and the second application represent a first game and a second game executed on a game console. In other specific implementations, the first application and the second application can be other types of software applications executed on other types of computing systems.

[0043] Reference now Figure 7 , shows one specific implementation of a method 700 for allocating power budgets to components of a computing system. A power management unit retrieves an indication of a total power budget for an entire computing system consisting of N components (block 705). The number of "N" components may vary from system to system, where N is a positive integer greater than one. The power management unit allocates power to each of the N components so as not to exceed the total power budget for the entire computing system (block 710). During runtime, the power management unit calculates the power consumption of the N components using a plurality of lower level variables (block 715). The plurality of lower level variables may include tuned variables determined during post-silicon characterization and override variables provided by an OS or software application.

[0044] Next, the power management unit determines the available power budget for the entire system by subtracting the power consumption value of each of the "N-1" components from the total power budget (block 720). The power management unit then allocates all available power budgets to the Nth component (block 725). The Nth component of method 700 can be any type of component, where the type varies with the specific implementation. For example, in one specific implementation, the Nth component is a GPU. In other embodiments, the Nth component can be any of a variety of other types of components. After block 725, method 700 ends. It should be noted that method 700 can be repeated periodically to update the power budget allocated to the Nth component.

[0045] Now turn to Figure 8 , shows a specific implementation of a method 800 for applying adjustments to tuned power estimation parameters. A computing system loads a given application to be executed on the system (block 805). As part of loading the given application, the computing system programs a plurality of override adjustment values ​​into a power management unit (block 810). The power management unit applies the plurality of adjustment values ​​to the plurality of tuned power estimation parameters (block 815). For example, if there are 12 different tuned parameters, the software may specify 12 adjustment values ​​to apply to the 12 tuned parameters. In some cases, the software may specify adjustment values ​​for a subset of the tuned parameters, rather than changing all tuned parameters. In one specific implementation, each adjustment value may be a percentage, such that the first adjustment value is 120%, the second adjustment value is 90%, and so on. In this example, the adjustment value is multiplied by the tuned parameter value to generate the adjusted parameter value.

[0046] Next, during execution of a given application, the power management unit generates a power estimate based on the adjustments applied to the tuned power estimation parameters (block 820). The power management unit then allocates power to various components based on the generated power estimate (block 825). After block 825, method 800 ends.

[0047] In various specific implementations, the program instructions of the software application are used to implement the methods and / or mechanisms described herein. For example, it is envisioned that the program instructions can be executed by a general-purpose processor or a special-purpose processor. In various specific implementations, such program instructions are represented by a high-level programming language. In other specific implementations, the program instructions are compiled from the high-level programming language into binary, intermediate or other forms. Alternatively, program instructions describing the behavior or design of the hardware are written. Such program instructions are represented by a high-level programming language such as C. Alternatively, a hardware design language (HDL) such as Verilog is used. In various specific implementations, the program instructions are stored on any non-transient computer-readable storage medium in a variety of non-transient computer-readable storage media. The storage medium can be accessed by a computing system during use to provide the computing system with program instructions for program execution. In general, such a computing system includes at least one or more memories and one or more processors configured to execute program instructions.

[0048] It should be emphasized that the above specific implementation is only a non-limiting example of a specific implementation. Once the above disclosure is fully understood, many variations and modifications will become apparent to those skilled in the art. It is intended that the following claims be interpreted as covering all such variations and modifications.

Claims

1. A computing system comprising: one or more functional circuits; A power management circuit, the power management circuit being configured to: In response to initiating execution of a first application, replacing an existing set of power estimation parameters with a first set of power estimation parameters associated with the first application; generating a first estimate of power consumption of the one or more functional circuits during run-time based on run-time measurements and the first set of power estimation parameters when the computing system executes the first application; as well as One or more power-related settings of the one or more functional circuits are adjusted based on the first estimate of power consumption.

2. The computing system of claim 1, wherein the existing set of power estimation parameters is generated during a pre-deployment characterization phase, and wherein the one or more power-related settings include at least one of a supply voltage magnitude and a clock frequency.

3. The computing system of claim 1 , wherein in response to detecting execution of the second application, the power management circuit is further configured to: responsive to execution of the second application, replacing the first set of power estimation parameters with a second set of power estimation parameters associated with the second application; generating a second estimate of power consumption of the one or more functional circuits based on the second set of power estimation parameters when the computing system executes the second application; as well as One or more power-related settings of the one or more functional circuits are adjusted based on the second estimate of power consumption.

4. The computing system of claim 1, wherein the first set of power estimation parameters comprises one or more of: a capacitance coefficient, one or more filter coefficients, an error coefficient, and an error rate coefficient for the one or more functional circuits.

5. The computing system of claim 1, wherein the one or more functional circuits include a central processing unit (CPU) and a graphics processing unit (GPU). 6 . The computing system of claim 2 , wherein the first application is configured to replace the first set of power estimation parameters in response to a power estimation override mode. 7 . The computing system of claim 6 , wherein in a non-power estimation overlay mode, the existing set of power estimation parameters is not replaced by the first set of power estimation parameters.

8. A method comprising: In response to initiating execution of a first application, replacing an existing set of power estimation parameters with a first set of power estimation parameters associated with the first application; generating, by the power management circuitry, a first estimate of power consumption of one or more functional circuits during run-time based on the run-time measurements and the first set of power estimation parameters when the computing system executes the first application; as well as One or more power-related settings of the one or more functional circuits are adjusted based on the first estimate of power consumption.

9. The method of claim 8, wherein the existing set of power estimation parameters is generated during a pre-deployment characterization phase, and wherein the one or more power-related settings include at least one of a supply voltage magnitude and a clock frequency.

10. The method of claim 8, wherein in response to detecting execution of the second application, the method comprises: responsive to execution of the second application, replacing the first set of power estimation parameters with a second set of power estimation parameters associated with the second application; generating a second estimate of power consumption of the one or more functional circuits based on the second set of power estimation parameters when the computing system executes the second application; as well as One or more power-related settings of the one or more functional circuits are adjusted based on the second estimate of power consumption.

11. The method of claim 8, wherein the first set of power estimation parameters comprises one or more of: a capacitance coefficient, one or more filter coefficients, an error coefficient, and an error rate coefficient for the one or more functional circuits.

12. The method of claim 8, wherein the one or more functional circuits include a central processing unit (CPU) and a graphics processing unit (GPU).

13. The method of claim 9, further comprising the first application being able to replace the first set of power estimation parameters in response to a power estimation override mode.

14. The method of claim 13, wherein the first application is configured to indicate the power estimation override mode by performing a write to a register.

15. A device comprising: A control circuit, the control circuit being configured to: In response to initiating runtime execution of a first application, replacing an existing set of power estimation parameters with a first set of power estimation parameters associated with the first application; generating a first estimate of power consumption during run-time of one or more functional circuits of the computing system based on the run-time measurements and the first set of power estimation parameters when the computing system executes the first application; as well as Based on the first estimate of power consumption, one or more power-related settings of the one or more functional circuits are adjusted.

16. The apparatus of claim 15, wherein the existing set of power estimation parameters is generated during pre-deployment.

17. The device of claim 15, wherein the control circuit is further configured to: In response to execution of a second application, replacing the first set of power estimation parameters with a second set of power estimation parameters associated with the second application; generating a second estimate of power consumption of the one or more functional circuits based on the second set of power estimation parameters when the computing system executes the second application; as well as One or more power-related settings of the one or more functional circuits are adjusted based on the second estimate of power consumption.

18. The apparatus of claim 15, wherein the first set of power estimation parameters comprises one or more of: a capacitance coefficient, one or more filter coefficients, an error coefficient, and an error rate coefficient for the one or more functional circuits.

19. The apparatus of claim 15, wherein the control circuit is configured to replace the existing set of power estimation parameters with the first set of power estimation parameters further in response to a power estimation override mode indication generated by the first application.

20. The apparatus of claim 15, wherein the control circuit is configured to generate, in response to the coverage request, a first estimate of power consumption of one or more functional circuits of the computing system at runtime based on runtime measurements and the first set of power estimation parameters.

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