Thermal management of optical components for temperature control

Abstract

This application relates to thermal management of optical components for temperature control. The application relates to a structure including an optical component and a method of manufacturing the structure including the optical component. The structure includes: a substrate; an optical component including a waveguide core; and a back-end process stack including a heat dissipation layer. The optical component is located vertically between the substrate and the back-end process stack. The waveguide core comprises a first material having a first thermal conductivity, and the heat dissipation layer comprises a second material having a second thermal conductivity greater than that of the first material.

Description

Technical Field

[0001] This disclosure relates to photonic chips, and more specifically to structures including optical components and methods for manufacturing structures including optical components. Background Technology

[0002] Photonic chips are used in many applications and systems, including but not limited to data communication and computing systems. Photonic chips integrate optical components (such as waveguides, photodetectors, modulators, and optical power dividers) and electronic components (such as field-effect transistors) into a unified platform. Among other factors, layout area, cost, and operational overhead can be reduced by integrating both types of components on the same chip.

[0003] Edge couplers, also known as spot size converters, are typically used to couple light of a given mode from a light source (such as a laser or optical fiber) to optical components on a photonics chip. An edge coupler may include a portion of a waveguide core defining an inverse taper with a pointed tip. In an edge coupler configuration, the narrow end of the inverse taper provides a facet located adjacent to the light source at the tip, while the wide end of the inverse taper connects to another portion of the waveguide core that routes the light to the optical components of the photonics chip.

[0004] As light travels from the light source to the edge coupler, the gradually varying cross-sectional area of ​​the inverted cone supports the mode transformation and mode size changes associated with mode conversion. The tip of the inverted cone cannot completely confine the incident mode received from the light source because its cross-sectional area is significantly smaller than the mode size. Therefore, a considerable proportion of the electromagnetic field of the incident mode is distributed around the tip of the inverted cone. As the width of the inverted cone increases, it becomes able to support the entire incident mode and confine the electromagnetic field.

[0005] Due to their poor power handling capabilities, conventional edge couplers are susceptible to irreversible power-dependent damage, which adversely affects reliability. Edge couplers, including those with silicon waveguide cores, are particularly vulnerable to power-dependent damage. At high optical input power, the nonlinear absorption effect in the silicon waveguide core can lead to severe thermal heating, and even physical melting of the waveguide core due to excessively high temperatures.

[0006] There is a need for improved structures that include optical components and methods for manufacturing structures that include optical components. Summary of the Invention

[0007] In one embodiment of the present invention, a structure includes: a substrate; an optical component including a waveguide core; and a back-end process stack including a first heat dissipation layer. The optical component is located vertically between the substrate and the back-end process stack. The waveguide core includes a first material having a first thermal conductivity, and the first heat dissipation layer includes a second material having a second thermal conductivity greater than the first thermal conductivity of the first material.

[0008] In one embodiment of the present invention, a structure includes: an optical component comprising a waveguide core having a plurality of outer surfaces; and a heat dissipation layer located on the plurality of outer surfaces of the waveguide core. The waveguide core comprises a first material having a first thermal conductivity, and the heat dissipation layer comprises a second material having a second thermal conductivity greater than the first thermal conductivity.

[0009] In one embodiment of the present invention, a method includes: forming a heat dissipation layer; and forming an optical component in a vertical direction between a substrate and the heat dissipation layer. The optical component includes a waveguide core comprising a first material having a first thermal conductivity, and the heat dissipation layer comprising a second material having a second thermal conductivity greater than the first thermal conductivity. Attached Figure Description

[0010] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with the general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention. In the drawings, the same reference numerals denote the same features in various views.

[0011] Figure 1 This is a top view of the structure of the initial manufacturing stage of the processing method according to an embodiment of the present invention.

[0012] Figure 2 It is roughly along Figure 1 The cross-sectional view of the structure cut by line 2-2 in the figure.

[0013] Figure 3 yes Figure 2 Cross-sectional view of the structure during the manufacturing stage of the subsequent processing method.

[0014] Figure 4 This is a top view of the structure according to an alternative embodiment of the present invention.

[0015] Figure 5 This is a cross-sectional view of the structure according to an alternative embodiment of the present invention.

[0016] Figure 6 This is a cross-sectional view of the structure according to an alternative embodiment of the present invention.

[0017] Figure 7This is a cross-sectional view of the structure according to an alternative embodiment of the present invention. Detailed Implementation

[0018] refer to Figure 1 , 2 According to an embodiment of the invention, structure 10 includes a waveguide core 12 as an optical component. In a representative embodiment, the waveguide core 12 may be an edge coupler, wherein the waveguide core 12 includes an inverted cone 14 and has an end face defining a facet 16. The width W1 of the inverted cone 14 increases with increasing distance from the facet 16. An inverted cone refers to the tapered portion of the waveguide core, characterized by a gradually increasing width along the mode propagation direction. The waveguide core 12 may be aligned along a longitudinal axis 15, and the waveguide core 12 may have an outer surface 13 including a top surface and opposing sidewalls meeting at the facet 16.

[0019] Waveguide core 12 may be located above dielectric layer 18 and substrate 20. In one embodiment, dielectric layer 18 may be made of a dielectric material such as silicon dioxide, and substrate 20 may be made of a semiconductor material such as monocrystalline silicon. In one embodiment, dielectric layer 18 may be a buried oxide layer in a silicon-on-insulator substrate, and dielectric layer 18 may separate waveguide core 12 from substrate 20. Waveguide core 12 may be made of a semiconductor material such as monocrystalline silicon. In one embodiment, waveguide core 12 may be formed by patterning a monocrystalline silicon device layer in a silicon-on-insulator substrate using photolithography and etching processes, and when patterning waveguide core 12, dielectric layer 18 may serve as an etch stop.

[0020] In a representative embodiment, waveguide core 12 is embodied as a ridged waveguide core. In an alternative embodiment, waveguide core 12 may be embodied as a ribbed waveguide core. In an alternative embodiment, waveguide core 12 may be embodied as a slit-like waveguide core. In a representative embodiment, waveguide core 12 is linear or straight. In an alternative embodiment, waveguide core 12 may be curved. In an alternative embodiment, waveguide core 12 may be non-tapered. In embodiments, waveguide core 12 may be part of an optical component such as a polarization mode converter, an optical coupler, a multimode interference region, etc.

[0021] refer to Figure 3 The same reference numerals indicate Figure 1 , 2 The same features are present in the waveguide core 12 and the dielectric layer 18, and in subsequent manufacturing stages, dielectric layers 22, 24, and 26 are formed in the layer stack above the dielectric layer 18. Dielectric layers 22 and 26 may be made of a dielectric material such as silicon dioxide, while dielectric layer 24 may be made of a dielectric material such as silicon nitride. In an alternative embodiment, dielectric layer 24 may be omitted from the layer stack.

[0022] The back-end process stack 32 includes a heat dissipation layer 28 formed on a layer stack including dielectric layers 22, 24, and 26. The heat dissipation layer 28 is positioned to overlap with the waveguide core 12. In one embodiment, the heat dissipation layer 28 may completely overlap with the waveguide core 12. In another embodiment, the heat dissipation layer 28 may partially overlap with the waveguide core 12.

[0023] Compared to waveguide core 12 and dielectric layers 22, 24, and 26, heat dissipation layer 28 can be made of a material with relatively high thermal conductivity. In one embodiment, the material of heat dissipation layer 28 can be an inorganic material, such as diamond. In one embodiment, the material of heat dissipation layer 28 is characterized by having a thermal conductivity near room temperature significantly greater than that of the material constituting waveguide core 12 near room temperature. In one embodiment, the material of heat dissipation layer 28 is characterized by having a thermal conductivity near room temperature significantly greater than that of the material constituting any of dielectric layers 22, 24, and 26 near room temperature. In one embodiment, the material of heat dissipation layer 28 is characterized by having a thermal conductivity near room temperature significantly greater than that of silicon dioxide near room temperature (i.e., approximately 1.3 W / mK). In one embodiment, the material of heat dissipation layer 28 is characterized by having a thermal conductivity near room temperature significantly greater than that of copper near room temperature (i.e., approximately 400 W / mK). In one embodiment, the material of heat dissipation layer 28 is characterized by having a thermal conductivity near room temperature significantly greater than that of silicon near room temperature (i.e., approximately 150 W / mK). In one embodiment, the material of the heat dissipation layer 28 is characterized by a thermal conductivity greater than 1000 W / mK near room temperature. For example, diamond, a candidate material for the heat dissipation layer 28, is characterized by a thermal conductivity of about 2000 W / mK to about 2400 W / mK near room temperature. The high thermal conductivity of the material of the heat dissipation layer 28 facilitates heat dissipation from the waveguide core 12, allowing the waveguide core 12 to exhibit a reduced operating temperature during operation.

[0024] In one embodiment, the heat dissipation layer 28 can be deposited by chemical vapor deposition. In one embodiment, the heat dissipation layer 28 can have a thickness that provides sufficient thermal mass to support heat diffusion from the waveguide core 12. In one embodiment, the heat dissipation layer 28 can be a planar layer having a uniform thickness between a planar top surface and a bottom surface. In one embodiment, the heat dissipation layer 28 can have a thickness from about 10 nanometers to about 200 nanometers.

[0025] The back-end process stack 32 may also include a dielectric layer 30 formed on the heat dissipation layer 28. The dielectric layer 30 may be made of a dielectric material such as silicon dioxide. The heat dissipation layer 28 is located vertically between the dielectric layer 26 and the dielectric layer 30. Therefore, the heat dissipation layer 28 is arranged vertically between adjacent dielectric layers 26 and 30, which have lower thermal conductivity.

[0026] The back-end stack 32 may also include additional dielectric layers 34, 35 located above the dielectric layer 30, each made of a dielectric material such as silicon dioxide or silicon nitride. In one embodiment, the heat dissipation layer 28 may be considered to be formed in the metallization level of the back-end stack 32 closest to the waveguide core 12.

[0027] Light (e.g., laser) can be emitted from a light source 50 ( Figure 1 The light is guided toward the facet 16 of the waveguide core 12. The light can have a given wavelength, intensity, mode shape, and mode size, and an edge coupler providing representative optical components can provide for spot size conversion of the light. In one embodiment, the light source 50 can be a semiconductor laser, and the semiconductor laser can be located inside a cavity formed in the substrate 20 and attached to the substrate 20.

[0028] The heat dissipation layer 28 acts as a heat sink to dissipate heat generated within the waveguide core 12 during operation, while minimizing disturbances to the optical mode of the laser guided by the waveguide core 12 and the optical guiding characteristics of the waveguide core 12. The heat dissipation layer 28 effectively prevents permanent damage to the waveguide core 12 caused by high-power lasers (e.g., lasers with power in the range of 100 mW to 200 mW). For example, the heat dissipation layer 28 can effectively mitigate the thermal spot in the waveguide core 12 caused by high-power lasers, allowing the waveguide core 12 to operate at temperatures below acceptable temperature limits. The heat dissipation layer 28 can be particularly effective in cooling silicon waveguide cores 12 that experience increased heating due to nonlinear optical absorption at high power. The heat dissipation layer 28 can relax restrictions on laser power levels and result in fewer limitations on system-level performance.

[0029] In any of the embodiments described herein, structure 10 may be integrated into a photonic chip that includes electronic components and additional optical components. For example, the electronic components may include field-effect transistors fabricated using CMOS processes.

[0030] refer to Figure 4 According to an alternative embodiment of the invention, the heat dissipation layer 28 can be patterned by photolithography and etching processes to include an edge 38 and define a shape, such as a tapered 36, positioned along the edge 38 on a portion of the waveguide core 12. The heat dissipation layer 28 can be positioned to overlap with a portion of the waveguide core 12, but not with another adjacent portion of the waveguide core 12. Therefore, with Figure 3 Compared to the complete overlap present in the waveguide core 12, the heat dissipation layer 28 only partially overlaps with the waveguide core 12. The tapered shape 36 facilitates an adiabatic transition from the portion of the waveguide core 12 that does not overlap with the heat dissipation layer 28 to the portion of the waveguide core 12 that overlaps with the heat dissipation layer 28.

[0031] refer to Figure 5 According to an alternative embodiment of the invention, the back-end process stack 32 may include additional heat dissipation layers 42, 44 formed above the waveguide core 12, each heat dissipation layer being similar to heat dissipation layer 28. In this respect, heat dissipation layers 42, 44 may be made of the same material and have the same properties as heat dissipation layer 28. For example, in one embodiment, heat dissipation layers 42, 44 may also be made of diamond. In one embodiment, heat dissipation layers 42, 44 may each have a thickness from about 10 nanometers to about 200 nanometers. In one embodiment, heat dissipation layers 42, 44 may be planar layers with a uniform thickness between respective planar top and bottom surfaces.

[0032] A dielectric layer 46 may be formed between the top surface of heat dissipation layer 28 and the bottom surface of heat dissipation layer 42, and a dielectric layer 48 may be formed between the top surface of heat dissipation layer 42 and the bottom surface of heat dissipation layer 44. The dielectric layers 46 and 48 may be made of a dielectric material such as silicon dioxide. The stack of layers including heat dissipation layers 28, 42, and 44 and dielectric layers 46 and 48 is positioned to overlap with the waveguide core 12. Heat dissipation layers 28, 42, and 44 alternate with dielectric layers 46 and 48 in the vertical direction, such that the composition alternates between materials with relatively high thermal conductivity and materials with relatively low thermal conductivity. In one embodiment, dielectric layers 46 and 48 may completely separate heat dissipation layers 28, 42, and 44 from each other. Heat dissipation layers 28, 42, and 44 and dielectric layers 46 and 48 may constitute a metamaterial, which serves as a homogeneous material characterized by a composite refractive index of different materials.

[0033] In one embodiment, heat dissipation layers 28, 42, and 44 may have the same thickness. In one embodiment, the pitch and duty cycle of heat dissipation layers 28, 42, and 44 may be uniform to define a periodic arrangement. In an alternative embodiment, the pitch and / or duty cycle of heat dissipation layers 28, 42, and 44 may be apodized (i.e., non-uniform) to define a non-periodic arrangement.

[0034] The additional heat dissipation layers 42 and 44, with high thermal conductivity, allow the heat dissipation layer 28 to be placed closer to the waveguide core 12 in the vertical direction, enabling more efficient cooling. The multilayer stacking of heterogeneous materials (e.g., alternating diamond and silicon dioxide layers) allows for a reduction in the area occupied by optical components (e.g., waveguide core 12) designed to handle transverse magnetic mode light by enhancing confinement and other mode characteristics. For example, if the waveguide core 12 is curved, the heat dissipation layers 28, 42, and 44 can reduce bending losses of light with transverse magnetic modes.

[0035] refer to Figure 6According to an alternative embodiment of the invention, the heat dissipation layer 28 may be applied as a conformal coating in contact with the outer surface 13 of the waveguide core 12 and the dielectric layer 18. In one embodiment, the heat dissipation layer 28 may be positioned to directly contact the outer surface 13 of the waveguide core 12. The heat dissipation layer 28 conforms to the contour of the waveguide core 12, and its thickness is the same or substantially the same on each outer surface 13. The dielectric layers 22, 24, 26 and the back-end process stack 32 may be formed after the heat dissipation layer 28 is formed.

[0036] refer to Figure 7 According to an alternative embodiment of the invention, before applying the heat dissipation layer 28 as a conformal layer, the dielectric layer 40 may be applied as a conformal layer contacting the outer surface 13 of the waveguide core 12 and the dielectric layer 18. In one embodiment, the dielectric layer 40 may be made of a dielectric material such as silicon dioxide, and its thermal conductivity is lower than that of the material constituting the heat dissipation layer 28. The dielectric layer 40 is disposed between the heat dissipation layer 28 and the outer surface 13 of the waveguide core 12. Both the heat dissipation layer 28 and the dielectric layer 40 are conformal to the contour of the waveguide core 12, and their thicknesses are the same or substantially the same on each outer surface 13. The dielectric layers 22, 24, 26 and the back-end process stack 32 may be formed after the formation of the heat dissipation layer 28 and the dielectric layer 40.

[0037] The method described above is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (e.g., as a single wafer with multiple unpackaged chips), as bare chips, or in packages. The chip can be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of an intermediate or final product. The final product can be any product that includes the integrated circuit chip, such as a computer product with a central processing unit or a smartphone.

[0038] References to terms modified by approximate language such as “approximately,” “roughly,” and “basically” are not limited to specified exact values. Approximate language may correspond to the precision of the instrument used to measure the value and may indicate a range of + / -10% of the value unless dependent on the precision of the instrument.

[0039] The use of terms such as “vertical” and “horizontal” in this document is illustrative rather than restrictive, in order to establish a frame of reference. As used herein, the term “horizontal” is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. As just defined, the terms “vertical” and “normal” refer to directions perpendicular to the horizontal. The term “lateral” refers to a direction within the horizontal plane.

[0040] A feature that is "connected" or "coupled" to or "coupled" to another feature can be directly connected or coupled to another feature, or conversely, one or more intermediate features may exist. If no intermediate feature exists, a feature can be "indirectly connected" or "indirectly coupled" to or "indirectly coupled" to another feature. If at least one intermediate feature exists, a feature can be "indirectly connected" or "indirectly coupled" to or "indirectly coupled" to another feature. A feature that is "located on" or "in contact with" another feature can be directly located on or in direct contact with another feature, or conversely, one or more intermediate features may exist. If no intermediate feature exists, a feature can be "directly located on" or "in direct contact with" another feature. If at least one intermediate feature exists, a feature can be "indirectly located on" or "indirectly contacting" another feature. If a feature extends above and covers a portion of another feature, the different features may "overlap".

[0041] The various embodiments of the present invention are described for illustrative purposes and are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, their practical application, or technical improvements to techniques found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A photonic chip structure, comprising: a substrate; an optical component comprising a waveguide core, the waveguide core comprising a first material having a first thermal conductivity; and a back end of line stack comprising a first heat spreading layer, the first heat spreading layer comprising a second material having a second thermal conductivity greater than the first thermal conductivity of the first material, wherein the optical component is located in a vertical direction between the substrate and the back end of line stack.

2. The photonic chip structure of claim 1, wherein, The optical component is an edge coupler.

3. The photonic chip structure of claim 1, wherein, The first material is silicon and the second material is diamond.

4. The photonic chip structure of claim 1, further comprising: a first dielectric layer located in the vertical direction between the first heat spreading layer and the optical component.

5. The photonic chip structure of claim 4, wherein, The back end of line stack comprises a second heat spreading layer, the second heat spreading layer comprising the second material, and the optical component is located in the vertical direction between the substrate and the second heat spreading layer.

6. The photonic chip structure of claim 5, further comprising: a second dielectric layer located in the vertical direction between the first heat spreading layer and the second heat spreading layer.

7. The photonic chip structure of claim 6, wherein, The first and second dielectric layers comprise silicon dioxide, the first material is silicon, and the second material is diamond.

8. The photonic chip structure of claim 4, wherein, The first dielectric layer comprises a third material having a third thermal conductivity less than the second thermal conductivity.

9. The photonic chip structure of claim 1, wherein, The waveguide core comprises a first portion and a second portion, and the first heat spreading layer overlaps only the first portion of the waveguide core.

10. The photonic chip structure of claim 9, wherein, The first heat spreading layer comprises a taper overlapping the first portion of the waveguide core.

11. A photonic chip structure, comprising: an optical component comprising a waveguide core having a plurality of outer surfaces, the waveguide core comprising a first material having a first thermal conductivity; a heat spreading layer located on the plurality of outer surfaces of the waveguide core, the heat spreading layer comprising a second material having a second thermal conductivity greater than the first thermal conductivity; a dielectric layer located on the plurality of outer surfaces of the waveguide core, wherein the heat spreading layer is a conformal coating directly contacting the dielectric layer on the plurality of outer surfaces of the waveguide core, and wherein the waveguide core comprises a first portion and a second portion, and the heat spreading layer overlaps only the first portion of the waveguide core.

12. The photonic chip structure of claim 11, wherein, The first material is silicon and the second material is diamond.

13. A method of forming a photonic chip structure, comprising: forming a first heat spreading layer, wherein the first heat spreading layer is located in a back end of line stack; and forming an optical component located in a vertical direction between a substrate and the first heat spreading layer, wherein the optical component comprises a waveguide core, the waveguide core comprising a first material having a first thermal conductivity, and the first heat spreading layer comprising a second material having a second thermal conductivity greater than the first thermal conductivity.

14. The method of claim 13, further comprising: forming a first dielectric layer located in the vertical direction between the first heat spreading layer and the optical component.

15. The method of claim 14, wherein, The back-end-of-line stack includes a second heat spreading layer adjacent to the waveguide core of the optical component, the second heat spreading layer includes the second material, and the first heat spreading layer is located between the first dielectric layer and the second heat spreading layer in the vertical direction.

16. The method of claim 15, further comprising: forming a second dielectric layer located between the first heat spreading layer and the second heat spreading layer in the vertical direction.

17. The method of claim 14, wherein, The first material is silicon, and the second material is diamond.

18. The method of claim 14, wherein, The waveguide core has a plurality of outer surfaces, and the first heat spreading layer is a conformal coating layer located on the plurality of outer surfaces.

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