Display substrate, driving method thereof, and display device

Abstract

The present disclosure provides a display substrate, comprising: a display area and a peripheral area located at the periphery of the display area, a plurality of pixel units and a plurality of light-emitting control signal lines are arranged in the display area; a first gate drive circuit and at least two first start control signal lines are arranged in the peripheral area, the first gate drive circuit comprises at least two first shift register groups corresponding to the first start control signal lines one by one and independent of each other, each first shift register group comprises at least two first shift registers connected in cascade, and the signal output end of each first shift register is connected with the corresponding light-emitting control signal line; in the first shift register group, the signal input end of the first shift register located at the first stage is connected with the first start control signal line configured for the first shift register group, and the signal input end of any first shift register except the first stage is connected with the signal output end of the first shift register of the previous stage.

Description

Technical Field

[0001] This invention relates to the field of displays, and in particular to a display substrate, its driving method, and a display device. Background Technology

[0002] The application of Active Matrix Organic Light Emitting Diode (AMOLED) panels is becoming increasingly widespread. The pixel display device of AMOLED is Organic Light-Emitting Diode (OLED). AMOLED emits light by driving thin-film transistors to generate a driving current in a saturated state, which drives the light-emitting device to emit light. Summary of the Invention

[0003] In a first aspect, embodiments of this disclosure provide a display substrate, including: a display area and a peripheral area located around the display area, wherein a plurality of pixel units are arranged in an array within the display area, and each row of pixel units is configured with a corresponding light emission control signal line;

[0004] The peripheral area is provided with a first gate driving circuit and at least two first start control signal lines configured for the first gate driving circuit. The first gate driving circuit includes at least two first shift register groups that correspond one-to-one with the first start control signal lines and are independent of each other. The first shift register group includes at least two cascaded first shift registers. The first shift register has a signal input terminal and a signal output terminal. The signal output terminal of each first shift register is connected to the corresponding light emission control signal line.

[0005] Within the first shift register group, the signal input terminal of the first shift register located in the first stage is connected to the first start control signal line configured in the first shift register group to which it belongs, and the signal input terminal of any other first shift register besides the one located in the first stage is connected to the signal output terminal of the first shift register of the previous stage.

[0006] In some embodiments, the number of the first start control signal lines is 2 to 5.

[0007] In some embodiments, the first shift register includes:

[0008] A first input circuit, connected to a signal input terminal, a first clock signal terminal, and a second node, is configured to write the signal provided by the signal input terminal to the second node in response to the control of the signal provided by the first clock signal terminal.

[0009] The second input circuit is connected to the first clock signal terminal, the first power supply terminal, and the second node, and is configured to write the first operating voltage provided by the first power supply terminal to the third node in response to the control of the signal provided by the first clock signal terminal, and to write the signal provided by the first clock signal terminal to the third node in response to the control of the voltage at the second node.

[0010] A first voltage control circuit is connected to a second clock signal terminal, a second power supply terminal, a first node, a second node, and a third node. It is configured to write the signal provided by the second clock signal terminal to the first node in response to the control of the voltage at the third node and the signal provided by the second clock signal terminal, and to write the second operating voltage provided by the second power supply terminal to the first node in response to the control of the voltage at the second node.

[0011] The second voltage control circuit is connected to the second clock signal terminal, the second power supply terminal, and the third node, and is configured to write the second operating voltage provided by the second power supply terminal to the second node in response to the voltage at the third node and the signal provided by the second clock signal terminal.

[0012] An output circuit, connected to a first power supply terminal, a second power supply terminal, a signal output terminal, a first node, and a second node, is configured to write a second operating voltage provided by the second power supply terminal to the signal output terminal in response to voltage control at the first node, and to write a first operating voltage provided by the first power supply terminal to the signal output terminal in response to voltage control at the second node.

[0013] In some embodiments, the first input circuit includes a first transistor, the second input circuit includes a second transistor and a third transistor, the first voltage control circuit includes a fourth transistor, a fifth transistor, a sixth transistor and a third capacitor, the second voltage control circuit includes a seventh transistor and an eighth transistor, and the output circuit includes a ninth transistor, a tenth transistor, a first capacitor and a second capacitor.

[0014] The control electrode of the first transistor is connected to the first clock signal terminal, the first electrode of the first transistor is connected to the signal input terminal, and the second electrode of the first transistor is connected to the second node.

[0015] The control electrode of the second transistor is connected to the first clock signal terminal, the first electrode of the second transistor is connected to the second power supply terminal, and the second electrode of the second transistor is connected to the third node;

[0016] The control electrode of the third transistor is electrically connected to the second node, the first electrode of the third transistor is connected to the third node, and the second electrode of the third transistor is connected to the first clock signal terminal.

[0017] The control electrode of the fourth transistor is connected to the third node, the first electrode of the fourth transistor is connected to the second clock signal terminal, and the second electrode of the fourth transistor is connected to the fourth node.

[0018] The control electrode of the fifth transistor is connected to the second clock signal terminal, the first electrode of the fifth transistor is connected to the fourth node, and the second electrode of the fifth transistor is connected to the first node.

[0019] The control electrode of the sixth transistor is connected to the second node, the first electrode of the sixth transistor is connected to the first node, and the second electrode of the sixth transistor is connected to the second power supply terminal.

[0020] The first terminal of the third capacitor is connected to the third node, and the second terminal of the third capacitor is connected to the fourth node;

[0021] The control electrode of the seventh transistor is connected to the third node, the first electrode of the seventh transistor is connected to the second power supply terminal, and the second electrode of the seventh transistor is connected to the first terminal of the eighth transistor.

[0022] The control electrode of the eighth transistor is connected to the second clock signal terminal, and the second electrode of the eighth transistor is connected to the second node;

[0023] The control electrode of the ninth transistor is connected to the first node, the first electrode of the ninth transistor is connected to the second power supply terminal, and the second electrode of the ninth transistor is connected to the signal output terminal.

[0024] The control electrode of the tenth transistor is connected to the second node, the first electrode of the tenth transistor is connected to the signal output terminal, and the second electrode of the tenth transistor is connected to the first power supply terminal.

[0025] In some embodiments, the first shift register further includes: a first leakage protection circuit;

[0026] The first input circuit, the second input circuit, and the second node control voltage are connected to the fifth node. The first leakage protection circuit is located between the fifth node and the second node. The first input circuit, the second input circuit, and the second node control voltage are all connected to the second node through the leakage protection node.

[0027] The first leakage protection circuit is also connected to the first power supply terminal and the third power supply terminal. The first leakage protection circuit is configured to write the third working voltage provided by the third power supply terminal to the first leakage protection node under the control of the voltage at the second node. The first leakage protection node is located between the second node and the fifth node.

[0028] In some embodiments, the first leakage protection circuit includes: an eleventh transistor, a twelfth transistor, and a thirteenth transistor;

[0029] The control electrode of the eleventh transistor is connected to the first power supply terminal, the first electrode of the eleventh transistor is connected to the fifth node, and the second electrode of the eleventh transistor is connected to the first leakage protection node.

[0030] The control electrode of the twelfth transistor is connected to the first power supply terminal, the first electrode of the twelfth transistor is connected to the first leakage protection node, and the second electrode of the twelfth transistor is connected to the second node;

[0031] The control electrode of the thirteenth transistor is connected to the second node, the first electrode of the thirteenth transistor is connected to the third power supply terminal, and the second electrode of the thirteenth transistor is connected to the first leakage protection node.

[0032] In some embodiments, the first shift register further includes: a second leakage protection circuit, wherein the output circuit is connected to a second power supply terminal through the second leakage protection circuit, and the output circuit and the second leakage protection circuit are connected to a second leakage protection node;

[0033] The second leakage protection circuit is also connected to the first node, the first power supply terminal, the second power supply terminal, and the signal output terminal. The second leakage protection circuit is configured to write the first operating voltage provided by the first power supply terminal to the second leakage protection node in response to the control of the voltage at the signal output terminal.

[0034] In some embodiments, the second leakage protection circuit includes: a fourteenth transistor and a fifteenth transistor;

[0035] The control electrode of the fourteenth transistor is connected to the first node, the first electrode of the fourteenth transistor is connected to the second power supply terminal, and the second electrode of the fourteenth transistor is connected to the second leakage protection node.

[0036] The control electrode of the fifteenth transistor is connected to the signal output terminal, the first electrode of the fifteenth transistor is connected to the first power supply terminal, and the second electrode of the fifteenth transistor is connected to the second leakage protection node.

[0037] In some embodiments, the first shift register further includes:

[0038] A global reset circuit, connected to a global reset signal terminal, a first power supply terminal, and a second node, is configured to write a first operating voltage provided by the first power supply terminal to the second node in response to a signal provided by the global reset signal terminal.

[0039] In some embodiments, the global reset circuit includes: a sixteenth transistor;

[0040] The control electrode of the sixteenth transistor is connected to the global reset signal terminal, the first electrode of the sixteenth transistor is connected to the second node, and the second electrode of the sixteenth transistor is connected to the first power supply terminal.

[0041] In some embodiments, the first gate driving circuit is further configured with a first clock signal supply line and a second clock signal supply line arranged along a first direction; both the first clock signal supply line and the second clock signal supply line extend along a second direction.

[0042] The first shift registers in the first gate drive circuit are arranged sequentially along the second direction, wherein the first clock signal terminal configured in the odd-numbered first shift register is connected to the first clock signal supply line, the second clock signal terminal configured in the odd-numbered first shift register is connected to the second clock signal supply line, the first clock signal terminal configured in the even-numbered first shift register is connected to the second clock signal supply line, and the second clock signal terminal configured in the even-numbered first shift register is connected to the first clock signal supply line.

[0043] In a second aspect, embodiments of this disclosure also provide a display device, including: the display substrate as described in the first aspect above.

[0044] Thirdly, the present disclosure also provides a driving method for a display substrate, wherein the display substrate adopts the display substrate provided in the first aspect, the first gate driving circuit includes n first shift register groups, n≥2, one frame includes n-1 black insertion driving stages, and the first gate driving circuit is configured to sequentially provide the i-th black insertion driving signal to each of the light emission control signal lines in the i-th black insertion driving stage, 1≤i≤n-1.

[0045] Each black-insertion drive phase is divided into a first sub-phase and a second sub-phase by a preset blank period. The first sub-phase is located before the blank period, and the second sub-phase is located after the blank period.

[0046] The driving method includes:

[0047] In the first sub-stage within the i-th black insertion drive stage, the i-th black insertion drive start signal is sequentially provided to the first start control signal lines configured in the 1st to nith first shift register groups, so that the first shift registers in the 1st to nith first shift register groups sequentially output the i-th black insertion drive signal.

[0048] During the blank period, none of the first shift registers output the black insertion drive signal;

[0049] In the second sub-stage within the i-th black insertion drive stage, the i-th black insertion drive start signal is sequentially provided to the first start control signal lines configured in the (n-i+1)-nth first shift register groups, so that the first shift registers in the (n-i+1)-nth first shift register groups sequentially output the i-th black insertion drive signal. Attached Figure Description

[0050] Figure 1 This is a schematic diagram of a circuit structure for a pixel unit within a display substrate, as described in the relevant technology.

[0051] Figure 2 for Figure 1 A timing diagram of one type of pixel unit shown;

[0052] Figure 3 This is a schematic diagram of another circuit structure for a pixel unit within a display substrate, as described in the related technology.

[0053] Figure 4A for Figure 3 A timing diagram of one type of pixel unit shown;

[0054] Figure 4B for Figure 3 The shown pixel unit performs external compensation sensing during the blank period, which is a working timing diagram;

[0055] Figure 5 This is a schematic diagram of the structure of a display substrate provided in an embodiment of the present disclosure;

[0056] Figure 6 for Figure 5 A schematic diagram of the circuit structure of the first gate drive circuit;

[0057] Figure 7 This is a timing diagram of the first gate driving circuit in an embodiment of the present disclosure;

[0058] Figure 8 This is a schematic diagram of a circuit structure of the first shift register in an embodiment of this disclosure;

[0059] Figure 9 A schematic diagram of another circuit structure of the first shift register provided in an embodiment of this disclosure;

[0060] Figure 10 for Figure 9 The diagram shows one possible timing diagram of the first shift register.

[0061] Figure 11This is a flowchart of a driving method for a display substrate provided in an embodiment of the present disclosure. Detailed Implementation

[0062] To enable those skilled in the art to better understand the technical solution of the present invention, a display substrate, its driving method, and a display device provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0063] The terms "first," "second," and similar terms used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as "comprising" or "including" mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, without excluding other elements or objects. Terms such as "coupled" or "connected" are not limited to physical or mechanical coupling, but can include electrical connections, whether direct or indirect.

[0064] The transistors used in the embodiments of this disclosure can all be thin-film transistors, field-effect transistors, or other devices with the same characteristics. In this embodiment, the coupling method of the drain and source of each transistor can be interchanged; therefore, the drain and source of each transistor in this disclosure embodiment are actually indistinguishable. Here, one of the two terminals of the transistor, excluding the control terminal (i.e., the gate), is called the drain, and the other is called the source. The thin-film transistors used in the embodiments of this disclosure can be N-type transistors or P-type transistors. In the embodiments of this disclosure, when an N-type thin-film transistor is used, its first terminal can be the source, and its second terminal can be the drain. In the following embodiments, the description uses an N-type thin-film transistor as an example.

[0065] In this disclosure, "effective level signal" refers to a signal that, when input to the gate electrode of a transistor, can control the transistor to conduct, and "ineffective level signal" refers to a signal that, when input to the gate electrode of a transistor, can control the transistor to cut off. For N-type transistors, a high-level signal is an effective level signal, and a low-level signal is an ineffective level signal; for P-type transistors, a low-level signal is an effective level signal, and a high-level signal is an ineffective level signal.

[0066] In the following description, an N-type transistor will be used as an example. In this case, the active level signal refers to a high-level signal, and the inactive level signal refers to a low-level signal. It is conceivable that when using a P-type transistor, the timing of the control signal needs to be adjusted accordingly. Specific details are not elaborated here, but should be within the scope of this disclosure.

[0067] Figure 1 This is a schematic diagram of a circuit structure for a pixel unit within a display substrate, as described in the relevant technology. Figure 2 for Figure 1 A timing diagram of the pixel unit shown, such as Figure 1 and Figure 2 As shown, the pixel circuit has a 3T1C structure, which includes three transistors (data write transistor QTFT, driving transistor DTFT, and sensing transistor STFT) and one capacitor (storage capacitor Cst). The control electrode of the data write transistor QTFT is connected to the first gate line G1, and the first electrode of the data write transistor QTFT is connected to the data line DATA. The control electrode of the sensing transistor STFT is connected to the second gate line G2, and the first electrode of the sensing transistor STFT is connected to the sensing line SENCE.

[0068] For a single pixel unit, it needs to go through a data writing stage and a light emission stage in one frame. During the data writing stage, the first gate line G1 controls the data writing transistor QTFT to turn on, and the data line Data writes the data voltage Vdata to the control electrode of the driving transistor DTFT. During the light emission stage, the driving transistor DTFT outputs a corresponding driving current according to the voltage at its control electrode to drive the light-emitting element OLED to emit light.

[0069] In addition, a blank period (also known as a blank period) is usually configured between two adjacent frames. The blank period can generally be used to randomly perform external compensation sensing on a certain pixel unit row.

[0070] exist Figure 1 In the pixel unit shown, the display brightness of the OLED element in one frame can only be controlled by the data voltage Vdata. However, the data voltage Vdata is output by the IC. If the IC's precision is insufficient, it will cause the problem of low grayscale not being unfolded. For example, if the IC precision is 0.1V, and the grayscale corresponding to 0.1V data voltage is L20, then the IC cannot accurately output the grayscales corresponding to L1 to L19.

[0071] To address the aforementioned technical issues, related technologies have improved the circuit structure of pixel units. Figure 3 This is a schematic diagram of another circuit structure for a pixel unit within a display substrate, as described in the related technology. Figure 4A for Figure 3 The image shows a timing diagram of one type of pixel unit. Figure 4B for Figure 3 The diagram shows a working timing diagram of the pixel unit performing external compensation sensing during the blank period, as follows: Figures 3 to 4B As shown, the new pixel unit provided by the related technology is a 4T1C structure, which not only includes Figure 1The data writing transistor (QTFT), driving transistor (DTFT), sensing transistor (STFT), and light-emitting control transistor (ETFT) are included. See, as an example, [link to example]. Figure 3 As shown, the light-emitting control transistor ETFT is disposed between the driving transistor DTFT and the power supply terminal ELVDD, and the control electrode of the light-emitting control transistor ETFT is connected to the light-emitting control signal line. As another example, the light-emitting control transistor can be disposed between the driving transistor DTFT and the light-emitting device OLED (no corresponding figure is given).

[0072] See Figure 4A As shown, for a single pixel unit, during the light-emitting phase, the light-emitting control signal line controls the conduction or cutoff of the light-emitting control transistor ETFT, thereby controlling the illumination time of the OLED element during the light-emitting phase, and consequently controlling the equivalent brightness of the OLED element in one frame (i.e., the brightness perceived by the human eye, also known as sensory brightness). Specifically, the light-emitting phase includes a lighting phase and a black-insertion phase. During the lighting phase, the light-emitting control signal line provides a light-emitting drive signal (i.e., an effective level signal) to control the conduction of the light-emitting control transistor ETFT. At this time, the drive transistor can output drive current normally, and the OLED element emits light. During the black-insertion phase, the light-emitting control signal line provides a black-insertion drive signal (i.e., an ineffective level signal) to control the cutoff of the light-emitting control transistor ETFT. At this time, the drive transistor DTFT has no drive current output, and the OLED element does not emit light. Generally, the longer the total duration of the black-insertion phase, the lower the equivalent brightness of the OLED element.

[0073] Figure 4A The example shown illustrates a scenario where the light-emitting stage includes two black insertion stages. Of course, in practical applications, the light-emitting stage can also include one, three, or more black insertion stages.

[0074] As seen above, by setting the ETFT (Emitting Power Transistor), the light-emitting element can display the brightness corresponding to lower grayscale levels, thus effectively solving the problem that insufficient IC precision prevents pixel units from displaying low grayscale brightness. However, in practical applications, it has been found that because all the shift registers inside the existing gate drive circuit used to provide the black insertion drive signal are cascaded sequentially, the existing gate drive circuit continuously and sequentially outputs the black insertion drive signal to each light-emitting control signal line. Inevitably, the light-emitting control signal line corresponding to some row pixel units will receive the black insertion drive signal during a blank period. And through... Figure 4BAs shown in the timing diagram, when performing external compensation sensing on a row of pixel units, the signal provided by the light emission control signal line connected to that row of pixel units must always be a light emission driving signal (i.e., an effective level signal). Therefore, external compensation sensing cannot be performed on pixel unit rows that receive a black insertion driving signal during blank periods. In other words, the related technology cannot support random external compensation sensing during blank periods.

[0075] To effectively address the problem that related technologies cannot support random external compensation sensing during blank periods, this disclosure provides a display substrate. The inventive principle of this disclosure will be described in detail below with reference to specific embodiments.

[0076] Figure 5 This is a schematic diagram of the structure of a display substrate provided in an embodiment of the present disclosure. Figure 6 for Figure 5 A schematic diagram of the circuit structure of the first gate drive circuit is shown below. Figure 5 and Figure 6 As shown, the display substrate 100 includes a display area 101 and a peripheral area 102 located around the display area 101. Multiple pixel units 300 arranged in an array are disposed in the display area 101, and each row of pixel units 300 is configured with a corresponding light emission control signal line EM.

[0077] The peripheral area 102 is provided with a first gate driving circuit 200 and at least two first start control signal lines STV1 to STV3 configured for the first gate driving circuit 102. The first gate driving circuit 200 includes at least two first shift register groups SRG1 to SRG3 that correspond one-to-one with the first start control signal lines STV1 to STV3 and are independent of each other. The first shift register groups SRG1 to SRG3 include at least two cascaded first shift registers SR_1 to SR_a1, SR_a1+1 to SR_a1+a2, and SR_a1+a2+1 to SR_a1+a2+a3. The first shift registers SR_1 to SR_a1+a2+a3 have a signal input terminal INPUT and a signal output terminal OUT. The signal output terminal OUT of each first shift register SR_1 to SR_a1+a2+a3 is connected to the corresponding light emission control signal line EM.

[0078] Within the first shift register groups SRG1 to SRG3, the signal input terminal INPUT of the first shift registers SR_1, SR_a1+1, and SR_a1+a2+1 located in the first stage is connected to the first start control signal lines STV1, STV2, and STV3 configured in the respective first shift register groups SRG1 to SRG3. The signal input terminal INPUT of any other first shift register SR_2 to SR_a1, SR_a1+2 to SR_a1+a2, and SR_a1+a2+2 to SR_a1+a2+a3 (excluding those located in the first stage) is connected to the signal output terminal OUT of the first shift register of its respective preceding stage.

[0079] It should be noted that the first start control signal lines STV1 to STV3 in this disclosure are connected to the signal input terminals INPUT of the first shift registers SR_1, SR_a1+1, and SR_a1+a2+1 located in the first stage of the corresponding first shift register group SRG1 to SRG3. After the first start control signal lines STV1 to STV3 provide the black insertion drive start signal to the signal input terminals INPUT of the first shift registers SR_1, SR_a1+1, and SR_a1+a2+1 located in the first stage of the corresponding first shift register group SRG1 to SRG3, the corresponding first shift registers SR_1 to SR_a1, SR_a1+1 to SR_a1+a2, and SR_a1+a2+1 to SR_a1+a2+a3 in the first shift register group SRG1 to SRG3 sequentially output the black insertion drive signal.

[0080] Furthermore, since the first shift register groups are independent of each other, meaning that there is no cascading relationship between the first shift registers located in different first shift register groups; in the first shift register group with the black insertion drive start signal input, the black insertion drive signal output by the last stage first shift register will only be provided to the corresponding light emission control signal line, and will not be provided to the first shift registers in other first shift register groups.

[0081] As can be seen from the above, unlike the related technologies where all first shift registers in the first gate driving circuit are cascaded sequentially, the technical solution of this disclosure divides all first shift registers in the first gate driving circuit into at least two independent first shift register groups. This ensures that there is no cascading relationship between the first shift registers located in different first shift register groups. Furthermore, by configuring a corresponding first start control signal line for each first shift register group, the timing of the black insertion drive signal output by each first shift register group can be independently controlled, enabling the absence of a black insertion drive signal output by any first shift register during blank periods. Therefore, the technical solution of this disclosure supports random external compensation sensing of the display substrate during blank periods.

[0082] In some embodiments, the number of first start control signal lines configured in the first gate drive circuit 200 is 2 to 5. That is, the number of first shift register groups divided by the first gate drive circuit 200 is 2 to 5.

[0083] In this embodiment of the disclosure, the number of first shift register groups divided by the first gate driving circuit 200 can be determined based on the number of black insertion stages configured in the pixel unit 300 within a light-emitting stage. Specifically, the number of first shift register groups divided by the first gate driving circuit 200 is greater than the number of black insertion stages configured in the pixel unit 300 within a light-emitting stage.

[0084] The more first shift register groups the first gate driving circuit 200 divides, the more black insertion stages the pixel unit 300 can support within a single light-emitting stage. Given a fixed total black insertion duration within a single light-emitting stage, a greater number of black insertion stages results in a shorter duration for each individual black insertion stage, effectively reducing flickering caused by the alternation of the lighting and black insertion stages. However, a greater number of first shift register groups also requires a greater number of first start control signal lines, leading to increased control difficulty and larger occupied space. To effectively balance flickering and wiring space, this disclosure preferably uses 2 to 5 first shift register groups; more preferably, the first shift register groups SRG1 to SRG3 used by the first gate driving circuit 200 are 3, correspondingly requiring 3 first start control signal lines STV1 to STV3.

[0085] In some embodiments, the first gate driving circuit 200 includes n first shift register groups, where n ≥ 2, and a frame includes n-1 black insertion driving stages. The gate driving circuit is configured to sequentially provide the i-th black insertion driving signal to each light emission control signal line in the i-th black insertion driving stage, where 1 ≤ i ≤ n-1. Each black insertion driving stage is divided into a first sub-stage and a second sub-stage by a preset blank period. The first sub-stage is located before the blank period, and the second sub-stage is located after the blank period.

[0086] In a frame driving process, the first sub-stage of each black insertion driving stage begins sequentially before the blank period. Specifically, in the first sub-stage of the i-th black insertion driving stage, the i-th black insertion driving start signal is sequentially provided to the first start control signal lines configured in the 1st to nith first shift register groups, so that the first shift registers in the 1st to nith first shift register groups sequentially output the i-th black insertion driving signal.

[0087] During the blank period, none of the first shift registers output the black insertion drive signal.

[0088] The second sub-stage of each black insertion drive stage after the blank period can start sequentially or simultaneously. Specifically, in the second sub-stage of the i-th black insertion drive stage, the i-th black insertion drive start signal is sequentially provided to the first start control signal lines configured in the (n-i+1)-nth first shift register groups, so that the first shift registers in the (n-i+1)-nth first shift register groups sequentially output the i-th black insertion drive signal.

[0089] The technical solution of this disclosure will be described in detail below with reference to a specific example. Figure 7 This is a timing diagram of the first gate driving circuit in an embodiment of this disclosure, as shown below. Figure 7 As shown, Figure 7 The diagram illustrates that the pixel unit 300 has two black insertion stages configured within one light-emitting stage, and the first gate driving circuit 200 includes three first shift register groups, with the number of first shift registers contained in the three first shift register groups being a1, a2, and a3, respectively. Figure 7 In this context, OUT_m represents the signal output terminal of the i-th first shift register within the first gate drive circuit 200, where 1≤m≤a1+a2+a3.

[0090] The pixel unit 300 is configured with two black insertion stages within one light-emitting stage. This means that the signal output terminals of each first shift register in the first gate driving circuit 200 need to sequentially output two black insertion driving signals. In this case, one frame includes two black insertion driving stages. In the first black insertion stage, the first gate driving circuit 200 sequentially provides the first black insertion driving signal to each light-emitting control signal line EM, and in the second black insertion stage, it sequentially provides the second black insertion driving signal to each light-emitting control signal line EM. The time interval between the start time of the second black insertion driving stage and the start time of the first black insertion driving stage can be preset according to actual needs. Each black insertion driving stage is divided into a first sub-stage and a second sub-stage by a preset blank period. The first sub-stage is located before the blank period, and the second sub-stage is located after the blank period.

[0091] In the first sub-stage of the first black insertion drive stage, the first start control signal lines STV1 and STV2 configured in the first and second first shift register groups SRG1 and SRG2 are provided with the first black insertion drive start signal in sequence, so that the first shift registers in the first and second first shift register groups SRG1 and SRG2 output the first black insertion drive signal in sequence. That is, the first to a1+a2 first shift registers SR_1 to SR_a1+a2 in the first gate drive circuit 200 output the first black insertion drive signal to the corresponding light emission control signal line EM in sequence.

[0092] In the first sub-stage of the second black insertion drive stage, the second black insertion drive start signal is provided to the first start control signal line STV1 configured in the first first shift register group SRG1, so that the first shift registers in the first first shift register group SRG1 sequentially output the first black insertion drive signal, that is, the first to a1 first shift registers SR_1 to SR_a1 in the first gate drive circuit 200 sequentially output the second black insertion drive signal to the corresponding light emission control signal line EM.

[0093] During the blank period, none of the first shift registers output the black insertion drive signal.

[0094] In the second sub-stage within the first black insertion drive stage, the first start control signal line STV3 configured in the third first shift register group SRG3 is provided with the first black insertion drive start signal in sequence, so that the first shift registers in the third first shift register group SRG3 output the first black insertion drive signal in sequence. That is, the a1+a2+1 to a1+a2+a3 first shift registers SR_a1+a2+1~SR_a1+a2+a3 in the first gate drive circuit 200 output the first black insertion drive signal to the corresponding light emission control signal line EM in sequence.

[0095] In the second sub-stage of the second black insertion drive stage, the first start control signal STV2 and STV3 lines configured in the second and third first shift register groups SRG2 and SRG3 are sequentially provided with the second black insertion drive start signal, so that the first shift registers in the second and third first shift register groups SRG2 and SRG376 sequentially output the second black insertion drive signal. That is, the first shift registers SR_a1+1 to SR_a1+a2+a3 in the first gate drive circuit 200 sequentially output the second black insertion drive signal to the corresponding light emission control signal line EM.

[0096] It should be noted that, Figure 7The illustration shows that the duration of the first black insertion drive start signal is shorter than the duration of the second black insertion drive start signal (i.e., the duration of the first black insertion drive signal is shorter than the duration of the second black insertion drive signal). This illustration is for illustrative purposes only and does not limit the technical solution of this disclosure. In practical applications, the duration of each black insertion drive start signal can be designed separately according to actual needs.

[0097] It should be noted that, Figure 7 The illustration shows a scenario where the second sub-stage within the first black insertion drive stage and the second sub-stage within the second black insertion drive stage start simultaneously. This scenario is for illustrative purposes only and does not limit the technical solutions of this disclosure.

[0098] Figure 8 This is a schematic diagram of a circuit structure of the first shift register in an embodiment of this disclosure, such as... Figure 8 As shown, in some embodiments, the first shift register includes: a first input circuit 21, a second input circuit 22, a first voltage control circuit 23, a second voltage control circuit 24, and an output circuit 25.

[0099] The first input circuit 21 is connected to the signal input terminal INPUT, the first clock signal terminal CKA, and the second node N2. The first input circuit 21 is configured to write the signal provided by the signal input terminal INPUT to the second node N2 in response to the control of the signal provided by the first clock signal terminal CKA.

[0100] The second input circuit 22 is connected to the first clock signal terminal CKA, the first power supply terminal, and the second node N2. The second input circuit 22 is configured to write the first operating voltage provided by the first power supply terminal to the third node N3 in response to the control of the signal provided by the first clock signal terminal CKA, and to write the signal provided by the first clock signal terminal CKA to the third node N3 in response to the control of the voltage at the second node N2.

[0101] The first voltage control circuit 23 is connected to the second clock signal terminal CKB, the second power supply terminal, the first node N1, the second node N2, and the third node N3. The first voltage control circuit 23 is configured to write the signal provided by the second clock signal terminal CKB to the first node N1 in response to the control of the voltage at the third node N3 and the signal provided by the second clock signal terminal CKB, and to write the second operating voltage provided by the second power supply terminal to the first node N1 in response to the control of the voltage at the second node N2.

[0102] The second voltage control circuit 24 is connected to the second clock signal terminal CKB, the second power supply terminal, and the third node N3. The second voltage control circuit 24 is configured to write the second operating voltage provided by the second power supply terminal to the second node N2 in response to the voltage at the third node N3 and the signal provided by the second clock signal terminal CKB.

[0103] The output circuit 25 is connected to the first power supply terminal, the second power supply terminal, the signal output terminal OUT, the first node N1, and the second node N2. The output circuit 25 is configured to write the second operating voltage provided by the second power supply terminal to the signal output terminal OUT in response to the control of the voltage at the first node N1, and to write the first operating voltage provided by the first power supply terminal to the signal output terminal OUT in response to the control of the voltage at the second node N2.

[0104] In some embodiments, the first shift register further includes a first leakage protection circuit 26; wherein, the first input circuit 21, the second input circuit 22, and the second voltage control circuit 24 are connected to the fifth node N5, the first leakage protection circuit 26 is located between the fifth node N5 and the second node N2, and the first input circuit 21, the second input circuit, and the second voltage control circuit are all connected to the second node N2 through the first leakage protection circuit 26; the first leakage protection circuit 26 is also connected to the first power supply terminal and the third power supply terminal, and the first leakage protection circuit 26 is configured to write the third operating voltage provided by the third power supply terminal to the first leakage protection node OFF1 under the control of the voltage at the second node N2, and the first leakage protection node OFF1 is located between the second node N2 and the fifth node N5.

[0105] In some embodiments, the first shift register further includes a second leakage protection circuit 27, and the output circuit 25 is connected to the second power supply terminal through the second leakage protection circuit 27. The output circuit 25 and the second leakage protection circuit 27 are connected to the second leakage protection node OFF2. The second leakage protection circuit 27 is also connected to the first node N1, the first power supply terminal, the second power supply terminal, and the signal output terminal OUT. The second leakage protection circuit 27 is configured to write the first operating voltage provided by the first power supply terminal to the second leakage protection node OFF2 in response to the control of the voltage at the signal output terminal OUT.

[0106] Figure 9 A schematic diagram of another circuit structure of the first shift register provided in the embodiments of this disclosure is shown below. Figure 9 As shown, Figure 9 The shift register shown is based on Figure 8 One specific alternative implementation of the first shift register shown.

[0107] In some embodiments, the first input circuit 21 includes a first transistor T1, the second input circuit 22 includes a second transistor T2 and a third transistor T3, the first voltage control circuit 23 includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a third capacitor C3, the second voltage control circuit 24 includes a seventh transistor T7 and an eighth transistor T8, and the output circuit 25 includes a ninth transistor T9, a tenth transistor T10, a first capacitor C1 and a second capacitor C2.

[0108] The control electrode of the first transistor T1 is connected to the first clock signal terminal CKA, the first electrode of the first transistor T1 is connected to the signal input terminal INPUT, and the second electrode of the first transistor T1 is connected to the second node N2.

[0109] The control electrode of the second transistor T2 is connected to the first clock signal terminal CKA, the first electrode of the second transistor T2 is connected to the second power supply terminal, and the second electrode of the second transistor T2 is connected to the third node N3.

[0110] The control electrode of the third transistor T3 is electrically connected to the second node N2, the first electrode of the third transistor T3 is connected to the third node N3, and the second electrode of the third transistor T3 is connected to the first clock signal terminal CKA.

[0111] The control electrode of the fourth transistor T4 is connected to the third node N3, the first electrode of the fourth transistor T4 is connected to the second clock signal terminal CKB, and the second electrode of the fourth transistor T4 is connected to the fourth node N4.

[0112] The control terminal of the fifth transistor T5 is connected to the second clock signal terminal CKB, the first terminal of the fifth transistor T5 is connected to the fourth node N4, and the second terminal of the fifth transistor T5 is connected to the first node N1.

[0113] The control electrode of the sixth transistor T6 is connected to the second node N2, the first electrode of the sixth transistor T6 is connected to the first node N1, and the second electrode of the sixth transistor T6 is connected to the second power supply terminal.

[0114] The first terminal of the third capacitor C3 is connected to the third node N3, and the second terminal of the third capacitor C3 is connected to the fourth node N4.

[0115] The control electrode of the seventh transistor T7 is connected to the third node N3, the first electrode of the seventh transistor T7 is connected to the second power supply terminal, and the second electrode of the seventh transistor T7 is connected to the first terminal of the eighth transistor T8.

[0116] The control terminal of the eighth transistor T8 is connected to the second clock signal terminal CKB, and the second terminal of the eighth transistor T8 is connected to the second node N2.

[0117] The control electrode of the ninth transistor T9 is connected to the first node N1, the first electrode of the ninth transistor T9 is connected to the second power supply terminal, and the second electrode of the ninth transistor T9 is connected to the signal output terminal OUT.

[0118] The control electrode of the tenth transistor T10 is connected to the second node N2, the first electrode of the tenth transistor T10 is connected to the signal output terminal OUT, and the second electrode of the tenth transistor T10 is connected to the first power supply terminal.

[0119] The first terminal of the first capacitor C1 is connected to the first node N1, and the second terminal of the first capacitor C1 is connected to the second power supply terminal.

[0120] The first terminal of the second capacitor C2 is connected to the signal output terminal OUT, and the second terminal of the second capacitor C2 is connected to the second node N2.

[0121] In some embodiments, the first leakage protection circuit 26 includes an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13.

[0122] Among them, the control electrode of the eleventh transistor T11 is connected to the first power supply terminal, the first electrode of the eleventh transistor T11 is connected to the fifth node N5, and the second electrode of the eleventh transistor T11 is connected to the first leakage protection node OFF1.

[0123] The control terminal of the twelfth transistor T12 is connected to the first power supply terminal, the first terminal of the twelfth transistor T12 is connected to the first leakage protection node OFF1, and the second terminal of the twelfth transistor T12 is connected to the second node N2.

[0124] The control electrode of the thirteenth transistor T13 is connected to the second node N2, the first electrode of the thirteenth transistor T13 is connected to the third power supply terminal, and the second electrode of the thirteenth transistor T13 is connected to the first leakage protection node OFF1.

[0125] In some embodiments, the second leakage protection circuit 27 includes a fourteenth transistor T14 and a fifteenth transistor T15.

[0126] The control electrode of the fourteenth transistor T14 is connected to the first node N1, the first electrode of the fourteenth transistor T14 is connected to the second power supply terminal, and the second electrode of the fourteenth transistor T14 is connected to the second leakage protection node OFF2.

[0127] The control electrode of the fifteenth transistor T15 is connected to the signal output terminal OUT, the first electrode of the fifteenth transistor T15 is connected to the first power supply terminal, and the second electrode of the fifteenth transistor T15 is connected to the second leakage protection node OFF2.

[0128] Figure 10 for Figure 9The following is a timing diagram of one type of operation of the first shift register, as shown: Figure 10 As shown, the first operating voltage provided by the first power supply terminal is a high-level operating voltage VGH1, the second operating voltage provided by the second power supply terminal is a low-level operating voltage VGL, and the third operating voltage provided by the third power supply terminal is a high-level operating voltage VGH2, wherein VGH2 is slightly greater than VGH1. Figure 9 The first shift register shown includes the following operating stages:

[0129] In the first stage t1, the signal input terminal INPUT provides a low-level signal, the first clock signal terminal CKA provides a high-level signal, and the second clock signal terminal CKB provides a low-level signal. Transistors T1, T2, T4, T7, T11, T12, and T15 are all turned on; transistors T3, T5, T6, T8, T9, T10, T13, and T14 are all turned off.

[0130] Specifically, when the first clock signal terminal CKA provides a high-level signal, both the first transistor T1 and the second transistor T2 are turned on. The low-level signal provided by the signal input terminal INPUT is written to the fifth node N5. At this time, both the eleventh transistor T11 and the twelfth transistor T12 are turned on, so the low-level signal is written to the second node N2 through the eleventh transistor T11 and the twelfth transistor T12. The voltage at the second node N2 is at a low level, so the sixth transistor T6, the thirteenth transistor T13, and the tenth transistor T10 are all turned off. At the same time, the first operating voltage VGH1 is written to the third node N3 through the second transistor T2. The voltage at the third node N3 is at a high level, and the fourth transistor T4 is turned on. The low-level signal provided by the second clock signal terminal CKB is written to the fourth node N4 through the fourth transistor T4, so the voltage at the fourth node N4 is at a low level.

[0131] Since the second clock signal is at a low level, the fifth transistor T5 is turned off. At this time, the first node N1 is in a floating state, and the voltage at the first node N1 maintains the low level state of the previous stage. Since both the ninth transistor T9 and the tenth transistor T10 are turned off, the signal output terminal OUT is in a floating state, and the signal output terminal OUT maintains the high level state of the previous stage, that is, the signal output terminal OUT outputs a high level signal. At this time, the fifteenth transistor T15 is turned on, and the first operating voltage VGH1 is written to the second leakage protection node OFF2 through the fifteenth transistor T15. This effectively prevents the voltage at the signal output terminal OUT from leaking through the ninth transistor T9, which helps to maintain the stability of the voltage at the signal output terminal OUT.

[0132] The second phase t2 consists of two alternating sub-phases s1 and s2.

[0133] In sub-stage s1, the signal input terminal INPUT provides a low-level signal, the first clock signal terminal CKA provides a low-level signal, and the second clock signal terminal CKB provides a high-level signal. Transistors T4, T5, T7, T8, T9, T11, and T12 are all turned on; transistors T1, T2, T3, T6, T10, T13, T14, and T15 are all turned off.

[0134] Specifically, when the first clock signal terminal CKA is at a low level, both the first transistor T1 and the second transistor T2 are turned off, and the third node N3 remains in a floating state at a high level. The high-level signal provided by the second clock signal terminal CKB is written to the fourth node N4 through the fourth transistor T4, causing the voltage at the fourth node N4 to change from a low level to a high level. Under the bootstrap effect of the third capacitor C3, the voltage at the third node N3 is further pulled up to a higher level. At the same time, since the second clock signal terminal CKB provides a high-level signal, the fifth transistor T5 and the eighth transistor T8 are turned on. Since both the seventh transistor T7 and the eighth transistor T8 are turned on, the second operating voltage VGL1 is written to the fifth node N5 through the seventh transistor T7 and the eighth transistor T8, and the fifth node N5 remains at a low level. Correspondingly, the eleventh transistor T11 and the twelfth transistor T12 are turned on, and the second node N2 also remains at a low level. The sixth transistor T6, the tenth transistor T10, and the thirteenth transistor T13 remain turned off.

[0135] Because the fifth transistor T5 is turned on, the high-level signal at the fourth node N4 can be written to the first node N1 through the fifth transistor T5. The voltage at the first node N1 is at a high level. At this time, both the ninth transistor T9 and the fourteenth transistor T14 are turned on. The second operating voltage VGL is written to the signal output terminal OUT through the fourteenth transistor T14 and the ninth transistor T9. The signal output terminal OUT outputs a low-level signal. Correspondingly, the fifteenth transistor T15 is turned off.

[0136] In sub-stage s2, the signal input terminal INPUT provides a low-level signal, the first clock signal terminal CKA provides a high-level signal, and the second clock signal terminal CKB provides a low-level signal.

[0137] Transistors T1, T2, T4, T7, T9, T11, and T12 are all on; transistors T3, T5, T6, T8, T10, T13, T14, and T15 are all off.

[0138] Specifically, when the first clock signal terminal CKA provides a high-level signal, both the first transistor T1 and the second transistor T2 are turned on. The low-level signal provided by the signal input terminal INPUT is written to the fifth node N5, which remains low. Correspondingly, the second node N2 also remains low. The sixth transistor T6, the tenth transistor T10, and the thirteenth transistor T13 remain off. Simultaneously, the first operating voltage is written to the third node N3 through the second transistor T2, causing the voltage at the third node N3 to drop to VGH1, placing it at a high level. The fourth transistor T4 is then turned on. The low-level signal provided by the second clock signal terminal CKB is written to the fourth node N4 through the fourth transistor T4, placing it at a low level.

[0139] Since the second clock signal terminal CKB is at a low level, both the fifth transistor T5 and the eighth transistor T8 are turned off. At this time, the first node N1 is in a floating state and maintains the high level of the previous node. The ninth transistor T9 and the fourteenth transistor T14 remain on, and the signal output terminal OUT maintains a low level signal output. Correspondingly, the fifteenth transistor T15 remains off.

[0140] In the third stage (t3), the signal input terminal INPUT provides a high-level signal, the first clock signal terminal CKA provides a low-level signal, and the second clock signal terminal CKB provides a high-level signal. Transistors T4, T5, T7, T8, T9, T11, and T12 are all turned on; transistors T1, T2, T3, T6, T10, T13, T14, and T15 are all turned off.

[0141] The specific working process of the first shift register in the third stage t3 is the same as that in the sub-stage s1, and will not be repeated here.

[0142] The fourth stage, t4, consists of two alternating sub-stages, s3 and s4.

[0143] In sub-stage s3, the signal input terminal INPUT provides a high-level signal, the first clock signal terminal CKA provides a high-level signal, and the second clock signal terminal CKB provides a low-level signal. The first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, the tenth transistor T10, the thirteenth transistor T13, and the sixteenth transistor T16 are all turned on. The fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the fourteenth transistor T14 are all turned off. The eleventh transistor T11 and the twelfth transistor T12 are first turned on and then switched to the off state.

[0144] Specifically, when the first clock signal terminal CKA is in a high-level state, both the first transistor T1 and the second transistor T2 are turned on. The high-level signal provided by the signal input terminal INPUT is written to the fifth node N5 through the first transistor T1. At this time, both the eleventh transistor T11 and the twelfth transistor T12 are turned on. Therefore, the high-level signal is written to the second node N2 through the eleventh transistor T11 and the twelfth transistor T12. The voltage at the second node N2 is in a low-level state, so the sixth transistor T6, the thirteenth transistor T13, and the tenth transistor T10 are all turned on. Because the thirteenth transistor T13 is turned on, the third operating voltage VGH2 is written to the first leakage protection node OFF1 through the thirteenth transistor T13. Correspondingly, the voltages at the fifth node N5 and the second node N2 are pulled up through the eleventh transistor T11 and the twelfth transistor T12. At this time, the gate-source voltages of the eleventh transistor T11 and the twelfth transistor T12 decrease until the gate-source voltage of the eleventh transistor T11 equals the threshold voltage of the eleventh transistor T11 and the gate-source voltage of the twelfth transistor T12 equals the threshold voltage of the twelfth transistor T12. Then, the eleventh transistor T11 and the twelfth transistor T12 are both turned off, and the first leakage protection node OFF1 is in a floating state. Through this design, leakage current can be effectively prevented from occurring at the second node N2 through other transistors, so as to maintain the voltage at the second node N2 at a high level. It should be noted that during the process of charging the fifth node N5 and the second node N2 through the eleventh transistor T11 and the twelfth transistor T12 respectively at the first leakage protection node OFF1, the voltage at the fifth node N5 and the second node N2 increases only slightly before the eleventh transistor T11 and the twelfth transistor T12 are turned off.

[0145] At the same time, the first operating voltage VGH1 is written to the third node N3 through the second transistor T2, and the voltage at the third node N3 is in a high-level state. The fourth transistor T4 is turned on, and the low-level signal provided by the second clock signal terminal CKB is written to the fourth node N4 through the fourth transistor T4, and the voltage at the fourth node N4 is in a low-level state.

[0146] Since the second clock signal is at a low level, the fifth transistor T5 is turned off. At this time, because the sixth transistor T6 is turned on, the second operating voltage VGL is written to the first node N1 through the sixth transistor T6, and the voltage at the first node N1 is at a low level. At this time, both the ninth transistor T9 and the fourteenth transistor T14 are turned off.

[0147] With the ninth transistor T9 off and the tenth transistor T10 on, the signal output terminal OUT outputs a high-level signal. Correspondingly, the fifteenth transistor T15 is turned on.

[0148] In sub-stage s4, the signal input terminal INPUT provides a high-level signal, the first clock signal terminal CKA provides a low-level signal, and the second clock signal terminal CKB provides a high-level signal. The third transistor T3, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the tenth transistor T10, the thirteenth transistor T13, and the sixteenth transistor T16 are all turned on. The first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the ninth transistor T9, and the fourteenth transistor T14 are all turned off. The eleventh transistor T11 and the twelfth transistor T12 are first turned on and then switched to the off state.

[0149] Specifically, when the first clock signal terminal CKA is in a low-level state, both the first transistor T1 and the second transistor T2 are turned off, the fifth node N5 maintains the high-level state of the previous stage, the third transistor T3 is turned on, and the low-level signal provided by the first clock signal terminal CKA is written to the third node N3 through the third transistor T3. The voltage at the third node N3 is in a low-level state, and the fourth transistor T4 and the seventh transistor T7 are turned off.

[0150] Since both the eleventh transistor T11 and the twelfth transistor T12 are off, the second node N2 is floating to maintain the high level state of the previous stage. At this time, the sixth transistor T6, the tenth transistor T10 and the thirteenth transistor T13 are all turned on, the voltage at the first node N1 is maintained at a low level, and the ninth transistor T9 and the fourteenth transistor T14 are both kept off.

[0151] With the ninth transistor T9 off and the tenth transistor T10 on, the signal output terminal OUT maintains a high-level signal. Correspondingly, the fifteenth transistor T15 is turned on.

[0152] Subsequently, when the first clock signal terminal CKA provides a high-level signal and the signal input terminal INPUT provides a low-level signal, the first stage t1 of the next cycle begins.

[0153] It should be noted that the preferred embodiment of this disclosure is the inclusion of a first leakage protection circuit 26 and a second leakage protection circuit 27 within the first shift register. The first leakage protection circuit 26 can maintain voltage stability at the second node N2 during the fourth stage t4, and the second leakage protection circuit 27 can maintain voltage stability at the signal output terminal OUT during the first stage t1. Those skilled in the art should understand that in some embodiments, the first shift register may optionally exclude the first leakage protection circuit 26 and / or the second leakage protection circuit 27.

[0154] In some embodiments, the first shift register further includes a global reset circuit 28, which is connected to a global reset signal terminal, a first power supply terminal, and a second node N2. The global reset circuit 28 is configured to write a first operating voltage provided by the first power supply terminal to the second node N2 in response to the control of a signal provided by the global reset signal terminal.

[0155] In some embodiments, the global reset circuit 28 includes a sixteenth transistor T16. The control terminal of the sixteenth transistor T16 is connected to the global reset signal terminal TRST, the first terminal of the sixteenth transistor T16 is connected to the second node N2, and the second terminal of the sixteenth transistor T16 is connected to the first power supply terminal.

[0156] As an optional implementation, during the blank period, the global reset signal terminal TRST provides a high-level signal (valid level signal) to turn on the sixteenth transistor T16 in the first shift register. At this time, the first operating voltage VGH1 is written to the fifth node N5 through the sixteenth transistor T16, thereby ensuring that the second node N2 is always in a high-level state. At this time, the tenth transistor T10 remains on, and the signal output terminal OUT outputs a high-level signal. That is to say, the first shift register will not output a black insertion drive signal during the blank period.

[0157] See also Figure 5 As shown, in some embodiments, the first gate driving circuit is further configured with a first clock signal supply line CK1 and a second clock signal supply line CK2 arranged along a first direction; both the first clock signal supply line and the second clock signal supply line extend along a second direction; the first shift registers in the first gate driving circuit are arranged sequentially along the second direction, wherein the first clock signal terminal CKA of the first shift register located in odd positions is connected to the first clock signal supply line CK1, the second clock signal terminal CKB of the first shift register located in odd positions is connected to the second clock signal supply line CK2, the first clock signal terminal CKA of the first shift register located in even positions is connected to the second clock signal supply line CK2, and the second clock signal terminal CKB of the first shift register located in even positions is connected to the first clock signal supply line CK1.

[0158] In other words, all first shift registers located within the first gate drive circuit share the first clock signal supply line CK1 and the second clock signal supply line CK2 (independent groups of first shift registers share the first clock signal supply line CK1 and the second clock signal supply line CK2). This design effectively reduces the number of signal lines, which is beneficial for narrow bezel design of the product.

[0159] In some embodiments, the global reset signal terminal TRST configured for each of the first shift registers is connected to the same global reset signal supply line Reset. That is, all the first shift registers located within the first gate drive circuit share the same global reset signal supply line Reset.

[0160] In some embodiments of this disclosure, the pixel unit may be adopted Figure 3 The 4T1C structure shown here is for the first and second gate lines within the display area ( Figure 5 (Not shown in the image), a corresponding second gate drive circuit 400 can be configured within the peripheral region. The second gate drive circuit 400 includes multiple cascaded second shift registers ( Figure 5 (Not shown in the diagram), the second shift register includes at least two signal output terminals, one of which is connected to the corresponding first gate line, and the other is connected to the corresponding second gate line. That is, for multiple first gate lines and multiple second gate lines within the display area, only one second gate drive circuit 400 needs to be configured. The specific circuit structure of the second shift register is not limited in this disclosure.

[0161] Based on the same inventive concept, this disclosure also provides a driving method for a display substrate. Figure 11 A flowchart of a driving method for a display substrate provided in an embodiment of this disclosure is shown below. Figure 11 As shown, the display substrate in this embodiment is the same as the display substrate provided in the previous embodiment; wherein, the first gate driving circuit in the display substrate includes n first shift register groups, n≥2, and one frame includes n-1 black insertion driving stages. The gate driving circuit is configured to sequentially provide the i-th black insertion driving signal to each light-emitting control signal line in the i-th black insertion driving stage, 1≤i≤n-1; each black insertion driving stage is divided into a first sub-stage and a second sub-stage by a preset blank time period, the first sub-stage being located before the blank time period and the second sub-stage being located after the blank time period; the driving method of the display substrate includes:

[0162] Step S1: Perform the first sub-stage of n-1 black insertion drive stages respectively; wherein, in the first sub-stage of the i-th black insertion drive stage, the i-th black insertion drive start signal is sequentially provided to the first start control signal line configured in the first to ni-th first shift register groups, so that the first shift register in the first to ni-th first shift register groups sequentially outputs the i-th black insertion drive signal.

[0163] Step S2: Perform the second sub-stage of each of the n-1 black insertion drive stages; wherein, in the second sub-stage of the i-th black insertion drive stage, the i-th black insertion drive start signal is sequentially provided to the first start control signal lines configured in the (n-i+1)th to the nth first shift register groups, so that the first shift registers in the (n-i+1)th to the nth first shift register groups sequentially output the i-th black insertion drive signal.

[0164] There is a blank period between steps S1 and S2, during which each of the first shift registers does not output a black insertion drive signal. Therefore, the technical solution of this disclosure supports random external compensation sensing of the display substrate during the blank period.

[0165] For a detailed description of steps S1 and S2, please refer to the relevant content in the previous embodiments, which will not be repeated here.

[0166] Based on the same inventive concept, this disclosure also provides a display device, which includes a display substrate. The display substrate is the same as the one provided in the previous embodiments. For a detailed description of the display substrate, please refer to the content in the previous embodiments, which will not be repeated here.

[0167] The display device provided in this disclosure can be any product or component with display function, such as a flexible wearable device, mobile phone, tablet computer, television set, monitor, laptop computer, digital photo frame, or navigator. Other essential components of this display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the invention.

[0168] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A driving method for a display substrate, characterized in that, The display substrate includes: a display area and a peripheral area located around the display area. The display area is provided with a plurality of pixel units arranged in an array, and each row of pixel units is configured with a corresponding light emission control signal line. The peripheral area is provided with a first gate driving circuit and at least two first start control signal lines configured for the first gate driving circuit. The first gate driving circuit includes at least two first shift register groups that correspond one-to-one with the first start control signal lines and are independent of each other. The first shift register group includes at least two cascaded first shift registers. The first shift register has a signal input terminal and a signal output terminal. The signal output terminal of each first shift register is connected to the corresponding light emission control signal line. Within the first shift register group, the signal input terminal of the first shift register located in the first stage is connected to the first start control signal line configured in the first shift register group to which it belongs, and the signal input terminal of any other first shift register except the one located in the first stage is connected to the signal output terminal of the first shift register of the previous stage. The first gate driving circuit includes n first shift register groups, n>2, and one frame includes n-1 black insertion driving stages. The first gate driving circuit is configured to sequentially provide the i-th black insertion driving signal to each of the light emission control signal lines in the i-th black insertion driving stage, 1≤i≤n-1. Each black-insertion drive phase is divided into a first sub-phase and a second sub-phase by a preset blank period. The first sub-phase is located before the blank period, and the second sub-phase is located after the blank period. The driving method includes: In the first sub-stage within the i-th black insertion drive stage, the i-th black insertion drive start signal is sequentially provided to the first start control signal lines configured in the 1st to nith first shift register groups, so that the first shift registers in the 1st to nith first shift register groups sequentially output the i-th black insertion drive signal. During the blank period, none of the first shift registers output the black insertion drive signal; In the second sub-stage within the i-th black insertion drive stage, the i-th black insertion drive start signal is sequentially provided to the first start control signal lines configured in the (n-i+1)-nth first shift register groups, so that the first shift registers in the (n-i+1)-nth first shift register groups sequentially output the i-th black insertion drive signal.

2. The driving method for a display substrate according to claim 1, characterized in that, The number of the first start control signal lines is 2 to 5.

3. The driving method for a display substrate according to claim 1, characterized in that, The first shift register includes: A first input circuit, connected to a signal input terminal, a first clock signal terminal, and a second node, is configured to write the signal provided by the signal input terminal to the second node in response to the control of the signal provided by the first clock signal terminal. The second input circuit is connected to the first clock signal terminal, the first power supply terminal, and the second node, and is configured to write the first operating voltage provided by the first power supply terminal to the third node in response to the control of the signal provided by the first clock signal terminal, and to write the signal provided by the first clock signal terminal to the third node in response to the control of the voltage at the second node. A first voltage control circuit is connected to a second clock signal terminal, a second power supply terminal, a first node, a second node, and a third node. It is configured to write the signal provided by the second clock signal terminal to the first node in response to the control of the voltage at the third node and the signal provided by the second clock signal terminal, and to write the second operating voltage provided by the second power supply terminal to the first node in response to the control of the voltage at the second node. The second voltage control circuit is connected to the second clock signal terminal, the second power supply terminal, and the third node, and is configured to write the second operating voltage provided by the second power supply terminal to the second node in response to the voltage at the third node and the signal provided by the second clock signal terminal. An output circuit, connected to a first power supply terminal, a second power supply terminal, a signal output terminal, a first node, and a second node, is configured to write a second operating voltage provided by the second power supply terminal to the signal output terminal in response to voltage control at the first node, and to write a first operating voltage provided by the first power supply terminal to the signal output terminal in response to voltage control at the second node.

4. The driving method for a display substrate according to claim 3, characterized in that, The first input circuit includes a first transistor, the second input circuit includes a second transistor and a third transistor, the first voltage control circuit includes a fourth transistor, a fifth transistor, a sixth transistor and a third capacitor, the second voltage control circuit includes a seventh transistor and an eighth transistor, and the output circuit includes a ninth transistor, a tenth transistor, a first capacitor and a second capacitor. The control electrode of the first transistor is connected to the first clock signal terminal, the first electrode of the first transistor is connected to the signal input terminal, and the second electrode of the first transistor is connected to the second node. The control electrode of the second transistor is connected to the first clock signal terminal, the first electrode of the second transistor is connected to the second power supply terminal, and the second electrode of the second transistor is connected to the third node; The control electrode of the third transistor is electrically connected to the second node, the first electrode of the third transistor is connected to the third node, and the second electrode of the third transistor is connected to the first clock signal terminal. The control electrode of the fourth transistor is connected to the third node, the first electrode of the fourth transistor is connected to the second clock signal terminal, and the second electrode of the fourth transistor is connected to the fourth node. The control electrode of the fifth transistor is connected to the second clock signal terminal, the first electrode of the fifth transistor is connected to the fourth node, and the second electrode of the fifth transistor is connected to the first node. The control electrode of the sixth transistor is connected to the second node, the first electrode of the sixth transistor is connected to the first node, and the second electrode of the sixth transistor is connected to the second power supply terminal. The first terminal of the third capacitor is connected to the third node, and the second terminal of the third capacitor is connected to the fourth node; The control electrode of the seventh transistor is connected to the third node, the first electrode of the seventh transistor is connected to the second power supply terminal, and the second electrode of the seventh transistor is connected to the first terminal of the eighth transistor. The control electrode of the eighth transistor is connected to the second clock signal terminal, and the second electrode of the eighth transistor is connected to the second node; The control electrode of the ninth transistor is connected to the first node, the first electrode of the ninth transistor is connected to the second power supply terminal, and the second electrode of the ninth transistor is connected to the signal output terminal. The control electrode of the tenth transistor is connected to the second node, the first electrode of the tenth transistor is connected to the signal output terminal, and the second electrode of the tenth transistor is connected to the first power supply terminal. The first end of the first capacitor is connected to the first node, and the second end of the first capacitor is connected to the second power supply terminal. The first end of the second capacitor is connected to the signal output terminal, and the second end of the second capacitor is connected to the second node.

5. The driving method for a display substrate according to claim 3, characterized in that, The first shift register further includes: a first leakage protection circuit; The first input circuit, the second input circuit, and the second node control voltage are connected to the fifth node. The first leakage protection circuit is located between the fifth node and the second node. The first input circuit, the second input circuit, and the second voltage control circuit are all connected to the second node through the first leakage protection circuit. The first leakage protection circuit is also connected to the first power supply terminal and the third power supply terminal. The first leakage protection circuit is configured to write the third working voltage provided by the third power supply terminal to the first leakage protection node under the control of the voltage at the second node. The first leakage protection node is located between the second node and the fifth node.

6. The driving method for a display substrate according to claim 5, characterized in that, The first leakage protection circuit includes: an eleventh transistor, a twelfth transistor, and a thirteenth transistor; The control electrode of the eleventh transistor is connected to the first power supply terminal, the first electrode of the eleventh transistor is connected to the fifth node, and the second electrode of the eleventh transistor is connected to the first leakage protection node. The control electrode of the twelfth transistor is connected to the first power supply terminal, the first electrode of the twelfth transistor is connected to the first leakage protection node, and the second electrode of the twelfth transistor is connected to the second node; The control electrode of the thirteenth transistor is connected to the second node, the first electrode of the thirteenth transistor is connected to the third power supply terminal, and the second electrode of the thirteenth transistor is connected to the first leakage protection node.

7. The driving method for a display substrate according to claim 3, characterized in that, The first shift register further includes: a second leakage protection circuit, wherein the output circuit is connected to a second power supply terminal through the second leakage protection circuit, and the output circuit and the second leakage protection circuit are connected to a second leakage protection node; The second leakage protection circuit is also connected to the first node, the first power supply terminal, the second power supply terminal, and the signal output terminal. The second leakage protection circuit is configured to write the first operating voltage provided by the first power supply terminal to the second leakage protection node in response to the control of the voltage at the signal output terminal.

8. The driving method for a display substrate according to claim 7, characterized in that, The second leakage protection circuit includes: a fourteenth transistor and a fifteenth transistor; The control electrode of the fourteenth transistor is connected to the first node, the first electrode of the fourteenth transistor is connected to the second power supply terminal, and the second electrode of the fourteenth transistor is connected to the second leakage protection node. The control electrode of the fifteenth transistor is connected to the signal output terminal, the first electrode of the fifteenth transistor is connected to the first power supply terminal, and the second electrode of the fifteenth transistor is connected to the second leakage protection node.

9. The driving method for a display substrate according to claim 8, characterized in that, The first shift register also includes: A global reset circuit, connected to a global reset signal terminal, a first power supply terminal, and a second node, is configured to write a first operating voltage provided by the first power supply terminal to the second node in response to a signal provided by the global reset signal terminal.

10. The driving method for a display substrate according to claim 9, characterized in that, The global reset circuit includes: a sixteenth transistor; The control electrode of the sixteenth transistor is connected to the global reset signal terminal, the first electrode of the sixteenth transistor is connected to the second node, and the second electrode of the sixteenth transistor is connected to the first power supply terminal.

11. The driving method for a display substrate according to any one of claims 3 to 10, characterized in that, The first gate driving circuit is further configured with a first clock signal supply line and a second clock signal supply line arranged along a first direction; both the first clock signal supply line and the second clock signal supply line extend along a second direction. The first shift registers in the first gate drive circuit are arranged sequentially along the second direction, wherein the first clock signal terminal configured in the odd-numbered first shift register is connected to the first clock signal supply line, the second clock signal terminal configured in the odd-numbered first shift register is connected to the second clock signal supply line, the first clock signal terminal configured in the even-numbered first shift register is connected to the second clock signal supply line, and the second clock signal terminal configured in the even-numbered first shift register is connected to the first clock signal supply line.

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