A system for scanning and tagging identical data before data transmission

Abstract

A system for scanning and marking the same data before data transmission, comprising: D flip-flop, XOR gate, AND gate, CPU, storage, data bus; D flip-flop is connected in series to form a first group of shift registers and a second group of shift registers; XOR gate, AND gate, the first group of shift registers, the second group of shift registers form a scanning device; CPU, storage, scanning device are connected through data bus; The relatively static data stream and the flowing data stream are sent to the first group of shift registers and the second group of shift registers respectively; Scan the same data, and mark the same data stored in the storage as the basis of compressed data.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, specifically to a system for scanning and labeling identical data before data transmission. Background Technology

[0002] Binary code: A code consisting of two basic characters '0' and '1'. A code element is a single bit of binary code. A codeword is any combination of N code elements.

[0003] Binary code language, also known as machine language, is a language that computers can directly understand without any translation. The format and meaning of the instructions on each machine are rigidly defined, hence it is called a machine-oriented language, or machine language. It was the first generation of computer languages, and machine language generally differs for different computer models.

[0004] Computer languages ​​that use binary code instructions directly. Instructions are strings of 0s and 1s, with a certain number of bits and divided into segments. Each segment represents a different meaning. For example, a computer with a word length of 16 bits has 16 binary numbers forming an instruction or other information. These 16 0s and 1s can be arranged in various combinations, converted into electrical signals through circuits, and then used by the computer to perform different operations.

[0005] Commonly used binary codes include International Standard 5 (IS5), EBCDIC, and International Telegraph 2 (ITS2).

[0006] The problem this invention aims to solve is: before transmitting communication data, scanning identical binary code in binary code files and marking identical binary code data as the basis for compressed data. Summary of the Invention

[0007] The purpose of this invention is to scan the binary code data to be transmitted and mark the same binary code data as the basis for compressed data, providing a system for scanning and marking the same data before data transmission.

[0008] The technical solution to achieve the purpose of this invention is as follows:

[0009] A system for scanning and labeling identical data before data transmission includes: D flip-flops, an XNOR gate, an AND gate, a CPU, memory, and a data bus; the D flip-flops are connected in series to form a first set of shift registers and a second set of shift registers;

[0010] The scanning device consists of an XOR gate, an AND gate, a first set of shift registers, and a second set of shift registers.

[0011] The CPU, memory, and scanning device are connected via a data bus;

[0012] The relatively stationary data stream and the flowing data stream are sent to the first set of shift registers and the second set of shift registers, respectively;

[0013] Scan the same data and label the same data to store it in the storage.

[0014] Compared with the prior art, the significant advantages of this invention are as follows: 1. The scanning device consists of an XNOR gate, an AND gate, a first set of shift registers, and a second set of shift registers. D flip-flops B1, B2, B3, and B4 are connected in series to form the first set of shift registers, and D flip-flops B1, B2, B3, and B4 are connected in series to form the second set of shift registers. When the binary number in the first set of shift registers is the same as the binary number in the second set of shift registers, and the AND gate A1 signal output is high ("1"), the same data is found. 2. The AND gate A1 signal input, AND gate A2 signal input, AND gate A3 signal input, ..., AND gate A... m The signal input terminals are connected to the data bus, AND gates A1, A2, A3, ..., A... m The connection relationship between them is combined using the CPU algorithm to increase the number of bits of the scanning unit; 3. The relatively static data stream and the flowing data stream are sent to the first group of shift registers and the second group of shift registers respectively. The scanning device finds the same binary code data and marks the same binary code data to be stored in the memory as the basis for compressed data. As communication data, the data is compressed before data transmission.

[0015] The present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart illustrating a system that scans and labels identical data before data transmission.

[0018] Figure 2 This is a schematic diagram of a scanning device for a system that scans and labels identical data before data transmission. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0020] Combination Figure 1 A flowchart illustrating a system for scanning and labeling identical data before data transmission.

[0021] Data 101 is binary code data stored in memory. The CPU sends data 101 to the first shift register and the second shift register respectively, using both relatively static and flowing data streams, forming a relatively static data stream 102 and a flowing data stream 104 within the shift registers. Data 101 is divided into data segments: S1, S2, ..., S... n S1, S2, ..., S n-1 The number of data bits is equal to the number of bits in the scanned unit cell; when S n The number of data bits is less than S1, S2, ..., S n-1 At that time, S n Not used as a scanning or comparison object; when S n The number of data bits is equal to S1, S2, ..., S n-1 At that time, S n As the object of scanning and comparison. A relatively static data stream refers to data 101 dividing data segments S1, S2, ..., S... n Data is sent intermittently to either the first or second shift register group. The register capacity of the first or second shift register group is the same as that of data segments S1, S2, ..., S... n Size matching prevents data overflow; flowing data stream refers to data 101 connecting data segments S1, S2, ..., S... n Send the data to either the second set of shift registers or the first set of shift registers in a complete and continuous manner.

[0022] The scanning detection 103 compares the data of the relatively stationary data stream 102 and the flowing data stream 104 in the shift register using a scanning device, finds the same data, and marks the data of the relatively stationary data stream 102 and the flowing data stream 104 in the shift register by marking the same data 105, and stores the marking information in the memory.

[0023] Example 1:

[0024] When S n The number of data bits is equal to S1, S2, ..., S n-1 At that time, data segment S1 of data 101 is sent to the first group of shift registers, and the complete data segments S1, S2, ..., S1 of data 101 are sent to the first group of shift registers.n The data is sent sequentially and completely into the second set of shift registers, completing the connection between data segment S1 and data segments S1, S2, ..., S... n The comparison is performed; data segment S2 of data 101 is sent to the first group of shift registers, and the complete data segments S1, S2, ..., S1 of data 101 are sent to the first group of shift registers. n The data is sent sequentially and completely into the second set of shift registers, completing the connection between data segment S2 and data segments S1, S2, ..., S... n The comparison; and so on, the data segment S of data 101. n The complete data segments S1, S2, ..., S1 of data 101 are sent to the first set of shift registers. n The data is sent sequentially and completely into the second set of shift registers to complete data segment S. n With data segments S1, S2, ..., S n Comparison;

[0025] When S n The number of data bits is less than S1, S2, ..., S n-1 At that time, data segment S1 of data 101 is sent to the first group of shift registers, and the complete data segments S1, S2, ..., S1 of data 101 are sent to the first group of shift registers. n-1 The data is sent sequentially and completely into the second set of shift registers, completing the connection between data segment S1 and data segments S1, S2, ..., S... n-1 The comparison is performed; data segment S2 of data 101 is sent to the first group of shift registers, and the complete data segments S1, S2, ..., S1 of data 101 are sent to the first group of shift registers. n-1 The data is sent sequentially and completely into the second set of shift registers, completing the connection between data segment S2 and data segments S1, S2, ..., S... n-1 The comparison; and so on, the data segment S of data 101. n-1 The complete data segments S1, S2, ..., S1 of data 101 are sent to the first set of shift registers. n-1 The data is sent sequentially and completely into the second set of shift registers to complete data segment S. n With data segments S1, S2, ..., S n-1 The comparison.

[0026] When S n The number of data bits is equal to S1, S2, ..., S n-1 At that time, data segment S1 of data 101 is sent to the second group of shift registers, and the complete data segments S1, S2, ..., S1 of data 101 are sent to the second group of shift registers. n The data is sent sequentially and completely into the first set of shift registers, completing the connection between data segment S1 and data segments S1, S2, ..., S... nThe comparison is performed; data segment S2 of data 101 is sent to the second group of shift registers, and the complete data segments S1, S2, ..., S1 of data 101 are sent to the second group of shift registers. n The data is sent sequentially and completely into the first set of shift registers, completing the connection between data segment S2 and data segments S1, S2, ..., S... n The comparison; and so on, the data segment S of data 101. n The complete data segments S1, S2, ..., S1 of data 101 are sent to the second set of shift registers. n The data is sent sequentially and completely into the first set of shift registers to complete data segment S. n With data segments S1, S2, ..., S n Comparison;

[0027] When S n The number of data bits is less than S1, S2, ..., S n-1 At that time, data segment S1 of data 101 is sent to the second group of shift registers, and the complete data segments S1, S2, ..., S1 of data 101 are sent to the second group of shift registers. n-1 The data is sent sequentially and completely into the first set of shift registers, completing the connection between data segment S1 and data segments S1, S2, ..., S... n-1 The comparison is performed; data segment S2 of data 101 is sent to the second group of shift registers, and the complete data segments S1, S2, ..., S1 of data 101 are sent to the second group of shift registers. n-1 The data is sent sequentially and completely into the first set of shift registers, completing the connection between data segment S2 and data segments S1, S2, ..., S... n-1 The comparison; and so on, the data segment S of data 101. n-1 The complete data segments S1, S2, ..., S1 of data 101 are sent to the second set of shift registers. n-1 The data is sent sequentially and completely into the first set of shift registers to complete data segment S. n With data segments S1, S2, ..., S n-1 The comparison.

[0028] Combination Figure 2 A schematic diagram of a scanning device for a system that scans and labels identical data before data transmission.

[0029] D flip-flops B1, B2, B3, and B4 are connected in series to form the first shift register. D flip-flops b1, b2, b3, and b4 are connected in series to form the second shift register. The signal outputs of D flip-flops B1 and B2 are connected to the input of the X1 gate of the NAND gate. The signal outputs of D flip-flops B2 and B2 are connected to the input of the X2 gate of the NAND gate. The signal outputs of D flip-flops B3 and B3 are connected to the input of the X3 gate of the NAND gate. The signal outputs of D flip-flops B4 and B4 are connected to the input of the X4 gate of the NAND gate. The signal outputs of the X1, X2, X3, and X4 gates of the NAND gates are connected to the input of the A1 gate of the AND gate. The input of the A1 gate of the AND gate is connected to the data bus.

[0030] Basic principle: D flip-flops B1, B2, B3, and B4 are connected in series to form the first shift register, and D flip-flops b1, b2, b3, and b4 are connected in series to form the second shift register. When the binary number in the first shift register is the same as the binary number in the second shift register, the output of AND gate A1 is high level "1".

[0031] When the signal output of D flip-flop B1 is low ("0") and the signal output of D flip-flop b1 is low ("0"), the signal output of the X1 gate is high ("1"); when the signal output of D flip-flop B1 is high ("1") and the signal output of D flip-flop b1 is high ("1"), the signal output of the X1 gate is high ("1"); when the signal output of D flip-flop B1 is low ("0") and the signal output of D flip-flop b1 is high ("1"), the signal output of the X1 gate is low ("0"); when the signal output of D flip-flop B1 is high ("1") and the signal output of D flip-flop b1 is low ("0"), the signal output of the X1 gate is low ("0").

[0032] When the signal output of D flip-flop B2 is low ("0") and the signal output of D flip-flop b2 is low ("0"), the signal output of the X2 gate is high ("1"); when the signal output of D flip-flop B2 is high ("1") and the signal output of D flip-flop b2 is high ("1"), the signal output of the X2 gate is high ("1"); when the signal output of D flip-flop B2 is low ("0") and the signal output of D flip-flop b2 is high ("1"), the signal output of the X2 gate is low ("0"); when the signal output of D flip-flop B2 is high ("1") and the signal output of D flip-flop b2 is low ("0"), the signal output of the X2 gate is low ("0").

[0033] When the signal output of D flip-flop B3 is low ("0") and the signal output of D flip-flop b3 is low ("0"), the signal output of X3 of the XNOR gate is high ("1"); when the signal output of D flip-flop B3 is high ("1") and the signal output of D flip-flop b3 is high ("1"), the signal output of X3 of the XNOR gate is high ("1"); when the signal output of D flip-flop B3 is low ("0") and the signal output of D flip-flop b3 is high ("1"), the signal output of X3 of the XNOR gate is low ("0"); when the signal output of D flip-flop B3 is high ("1") and the signal output of D flip-flop b3 is low ("0"), the signal output of X3 of the XNOR gate is low ("0").

[0034] When the signal output of D flip-flop B4 is low ("0") and the signal output of D flip-flop b4 is low ("0"), the signal output of X4 of the XNOR gate is high ("1"); when the signal output of D flip-flop B4 is high ("1") and the signal output of D flip-flop b4 is high ("1"), the signal output of X4 of the XNOR gate is high ("1"); when the signal output of D flip-flop B4 is low ("0") and the signal output of D flip-flop b4 is high ("1"), the signal output of X4 of the XNOR gate is low ("0"); when the signal output of D flip-flop B4 is high ("1") and the signal output of D flip-flop b4 is low ("0"), the signal output of X4 of the XNOR gate is low ("0").

[0035] When the output of the X1, X2, X3, and X4 gates is high, the output of the A1 gate is also high.

[0036] When the output of the X1, X2, X3, and X4 gates is low, the output of the A1 gate is also low.

[0037] When the output of the X1 gate is high ("1"), the output of the X2 gate is low ("0"), the output of the X3 gate is low ("0"), the output of the X4 gate is low ("0"), and the output of the A1 gate is low ("0").

[0038] When the output of the X1 gate is low ("0"), the output of the X2 gate is high ("1"), the output of the X3 gate is low ("0"), the output of the X4 gate is low ("0"), and the output of the A1 gate is low ("0").

[0039] When the output of the X1 signal of the XNOR gate is low level "0", the output of the X2 signal of the XNOR gate is low level "0", the output of the X3 signal of the XNOR gate is high level "1", the output of the X4 signal of the XNOR gate is low level "0", and the output of the A1 signal of the AND gate is low level "0".

[0040] When the output of the X1 gate is low ("0"), the output of the X2 gate is low ("0"), the output of the X3 gate is low ("0"), the output of the X4 gate is high ("1"), and the output of the A1 gate is low ("0").

[0041] When the output of the X1 gate is high ("1"), the output of the X2 gate is high ("1"), the output of the X3 gate is low ("0"), the output of the X4 gate is low ("0"), and the output of the A1 gate is low ("0").

[0042] When the output of the X1 gate is high ("1"), the output of the X2 gate is low ("0"), the output of the X3 gate is high ("1"), the output of the X4 gate is low ("0"), and the output of the A1 gate is low ("0").

[0043] When the output of the X1 gate is high ("1"), the output of the X2 gate is low ("0"), the output of the X3 gate is low ("0"), the output of the X4 gate is high ("1"), and the output of the A1 gate is low ("0").

[0044] When the output of the X1 gate is low ("0"), the output of the X2 gate is high ("1"), the output of the X3 gate is high ("1"), the output of the X4 gate is low ("0"), and the output of the A1 gate is low ("0").

[0045] When the output of the X1 gate is low ("0"), the output of the X2 gate is high ("1"), the output of the X3 gate is low ("0"), the output of the X4 gate is high ("1"), and the output of the A1 gate is low ("0").

[0046] When the output of the X1 gate is low ("0"), the output of the X2 gate is low ("0"), the output of the X3 gate is high ("1"), the output of the X4 gate is high ("1"), and the output of the A1 gate is low ("0").

[0047] When the output of the X1 gate is low ("0"), the output of the X2 gate is high ("1"), the output of the X3 gate is high ("1"), the output of the X4 gate is high ("1"), and the output of the A1 gate is low ("0").

[0048] When the output of the X1 gate is high ("1"), the output of the X2 gate is low ("0"), the output of the X3 gate is high ("1"), the output of the X4 gate is high ("1"), and the output of the A1 gate is low ("0").

[0049] When the output of the X1 gate is high ("1"), the output of the X2 gate is high ("1"), the output of the X3 gate is low ("0"), the output of the X4 gate is high ("1"), and the output of the A1 gate is low ("0").

[0050] When the output of the X1 gate is high ("1"), the output of the X2 gate is high ("1"), the output of the X3 gate is high ("1"), the output of the X4 gate is low ("0"), and the output of the A1 gate is low ("0").

[0051] Example 2:

[0052] The storage capacity of the shift register is increased by adding cascaded D flip-flops: D flip-flops B1, B2, B3, B4, ..., B6. n The first group of shift registers is formed by cascading D flip-flops b1, b2, b3, b4, ..., b6. n They are connected in series to form a second set of shift registers.

[0053] The signal outputs of D flip-flops B1 and B1 are connected to the input of the X1 gate of the XNOR gate; the signal outputs of D flip-flops B2 and B2 are connected to the input of the X2 gate of the XNOR gate; the signal outputs of D flip-flops B3 and B3 are connected to the input of the X3 gate of the XNOR gate; the signal outputs of D flip-flops B4 and B4 are connected to the input of the X4 gate of the XNOR gate, and so on. n Signal output terminal, D flip-flop b n The signal output terminal is connected to the XOR gate. n Signal input terminal.

[0054] The output terminals of the X1, X2, X3, and X4 gates are connected to the input terminal of the AND gate A1; the output terminals of the X5, X6, X7, and X8 gates are connected to the input terminal of the AND gate A2; four X1 gates correspond to one AND gate, and so on. 4m-3 Signal output terminal, XNOR gate X 4m-2 Signal output terminal, XNOR gate X 4m-1 Signal output terminal, XNOR gate X 4m The signal output terminal is connected to AND gate A. m Signal input terminal, 4m=n.

[0055] AND gate A1 signal input terminal, AND gate A2 signal input terminal, AND gate A3 signal input terminal, ..., AND gate A m The signal input terminals are connected to the data bus, AND gates A1, A2, A3, ..., A... m The connection relationships between them are combined using an algorithm by the CPU to increase the number of bits in the scanning unit. For example, when the detected scanning unit is 8 bits, the CPU uses an algorithm to combine AND gates A1 and A2. When AND gates A1 and A2 scan the same binary number, the output of the XNOR gate X1, XNOR gate X2, XNOR gate X3, and XNOR gate X4 is high, and the output of AND gate A1 is high; the outputs of the XNOR gate X5, XNOR gate X6, XNOR gate X7, and XNOR gate X8 are high, and the output of AND gate A2 is high.

[0056] When the unit cell being scanned is 12 bits, the CPU uses an algorithm to combine AND gates A1, A2, and A3. When AND gates A1, A2, and A3 scan the same binary number, the outputs of the XNOR gates X1, X2, X3, and X4 are all high ("1"), and the AND gate A1 is also high ("1"); the outputs of the XNOR gates X5, X6, X7, and X8 are also high ("1"), and the AND gate A2 is also high ("1"); the outputs of the XNOR gates X9 and X4 are also high ("1"); and the AND gate A2 is also high ("1"). 10 The signal output is a high level "1", and the X-OR gate is... 11 The signal output is a high level "1", and the X-OR gate is... 12The signal output terminal is high level "1", and the signal output terminal of AND gate A2 is high level "1"; and so on, increasing the number of bits of the unit cell in the detection scan.

[0057] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A system for scanning and labeling identical data before data transmission, comprising: D flip-flops, XNOR gates, AND gates, CPU, memory, and data bus; characterized in that: D flip-flops are connected in series to form a first group of shift registers and a second group of shift registers; The scanning device consists of an XOR gate, an AND gate, a first set of shift registers, and a second set of shift registers. The CPU, memory, and scanning device are connected via a data bus; The relatively stationary data stream and the flowing data stream are sent to the first set of shift registers and the second set of shift registers, respectively; Scan the same data and label the same data to store it in the storage; D flip-flops B1, B2, B3, and B4 are connected in series to form the first shift register. D flip-flops b1, b2, b3, and b4 are connected in series to form the second shift register. The signal outputs of D flip-flops B1 and B2 are connected to the input of the X1 gate of the NAND gate. The signal outputs of D flip-flops B2 and B2 are connected to the input of the X2 gate of the NAND gate. The signal outputs of D flip-flops B3 and B3 are connected to the input of the X3 gate of the NAND gate. The signal outputs of D flip-flops B4 and B4 are connected to the input of the X4 gate of the NAND gate. The signal outputs of the X1, X2, X3, and X4 gates of the NAND gates are connected to the input of the A1 gate of the AND gate. The input of the A1 gate of the AND gate is connected to the data bus. When the binary number in the first shift register is the same as the binary number in the second shift register, the output of the X1, X2, X3, and X4 gates is high, and the output of the A1 gate is high.

2. The system for scanning and labeling identical data before data transmission according to claim 1, characterized in that: Data (101) is binary code data stored in memory. The CPU sends data (101) to the first shift register and the second shift register respectively using the relatively static data stream and the flowing data stream, forming a relatively static data stream (102) in the shift register and a flowing data stream (104) in the shift register.

3. A system for scanning and labeling identical data before data transmission according to any one of claims 1 to 2, characterized in that: The scanning detection (103) is to compare the data of the relatively stationary data stream (102) in the shift register and the flowing data stream (104) in the shift register with the scanning device, find the same data, and mark the data of the relatively stationary data stream (102) in the shift register and the flowing data stream (104) in the shift register by marking the same data (105).

4. A system for scanning and labeling identical data before data transmission according to claim 2, characterized in that: Divide the data (101) into the following segments: S1, S2, ..., S n .

5. The system for scanning and labeling identical data before data transmission according to claim 1, characterized in that: The storage capacity of the shift register is increased by adding cascaded D flip-flops: D flip-flops B1, B2, B3, B4, ..., B6. n The first group of shift registers is formed by cascading D flip-flops b1, b2, b3, b4, ..., b6. n They are connected in series to form a second set of shift registers.

6. A system for scanning and labeling identical data before data transmission according to claim 1, characterized in that: AND gate A1 signal input terminal, AND gate A2 signal input terminal, AND gate A3 signal input terminal, ..., AND gate A m The signal input terminals are connected to the data bus, AND gates A1, A2, A3, ..., A... m The connection relationships between them are combined using algorithms employed by the CPU to increase the number of bits in the scanning unit.

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