Integrated triggering method and system for one-key recovery of computer based on shutdown state

Abstract

This invention relates to the field of computer integrated control technology, specifically an integrated triggering method and system for one-key recovery of a computer in a power-off state. The method involves monitoring user operations under power-off conditions via hardware circuitry. Under the constraint of the Recovery module's anti-accidental touch measures, the method arbitrates and determines user-triggered actions, generating a valid trigger signal and writing it to the wake-up register. Combining an RC delay circuit and trigger sampling analysis of power-on voltage changes, the system automatically enters Recovery mode upon the next power-on without needing to access the operating system or BIOS. After the device is powered off, power data in the power domain is read from the coin cell battery, and the PG distortion signal is reconstructed in the frequency domain. Based on this signal, stable power-on screening and CLRTC physical trigger detection are performed, automatically clearing the real-time clock data when conditions are met. The System Reset module identifies the actual system crash state by constructing a power-on anomaly variable domain and automatically triggers a system restart upon detecting a Reset signal, thus achieving one-key maintenance and recovery of the computer in a crash state.

Description

Technical Field

[0001] This invention relates to the field of computer integrated control technology, and in particular to an integrated triggering method and system for one-click restoration of a computer based on the power-off state. Background Technology

[0002] With the widespread application of computer systems in consumer electronics, industrial control, and servers, system stability and fault recovery capabilities have become key factors affecting equipment reliability and maintenance costs. Existing computers generally rely on operating system, firmware interaction, or standby power conditions to implement critical maintenance functions such as system recovery, real-time clock clearing (CLRTC), and system reset. This results in a series of problems, including limited triggering scenarios, complex operation, and insufficient reliability.

[0003] First, regarding system restore, current technologies typically rely on the operating system's built-in recovery environment or BIOS shortcuts. These methods require the device to be at least powered on or booting up, and the operation must be completed within a specific time window. When the system fails to boot due to software corruption, firmware anomalies, or misconfiguration, especially after a failed shutdown, these recovery methods become difficult to trigger. Users often have to resort to costly methods like disassembling the device and reflashing the firmware, severely reducing system maintainability. Second, regarding real-time clock clearing, current mainstream solutions still rely on shorting motherboard jumpers or removing the CMOS battery. When the device crashes abnormally or misconfigured, causing CMOS data to fail, users must physically open the case, which is not only cumbersome and inefficient but also poses risks of hardware damage and personal safety, failing to meet the demands for high reliability and convenient maintenance. Finally, regarding system restart, current technologies mostly trigger restarts through the operating system interface or software commands. When the system experiences severe anomalies such as crashes, blue screens, or kernel crashes, the operating system often becomes unresponsive, preventing restart commands from being executed and forcing the device into an unusable state for an extended period, impacting stability in continuous operation scenarios.

[0004] In addition, in the existing technology, the above three types of maintenance functions are usually implemented by different hardware interfaces or buttons, which not only occupy motherboard space and increase design complexity, but also easily cause functional failure due to differences in power supply status, making it difficult to achieve unified and reliable trigger control in various states such as shutdown, power failure and abnormal operation. Summary of the Invention

[0005] This invention overcomes the shortcomings of the prior art and provides an integrated triggering method and system for one-click computer restore based on the shutdown state.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: The first aspect of this invention provides an integrated triggering method for one-key recovery of a computer based on a shutdown state, comprising the following steps: S01: The hardware circuit monitors user operations when the computer is powered off and the Recovery module is protected against accidental touches. Based on the arbitration framework triggered by the user operation, the recovery program is started and a trigger signal is generated and saved to the wake-up register. The RC delay circuit works with the trigger to sample and analyze the voltage change during startup. The computer will automatically enter Recovery mode the next time it is powered on. S02: The button battery power management module reads the power data of the current power domain when the computer is powered off, performs stable power-on screening through the PG distortion signal reconstructed by the power data in the frequency domain, determines the current power-on state of the power domain, and detects whether the CLRTC module is physically triggered. If so, it identifies the true distribution statistics of the PG distortion signal and triggers the CLRTC module to clear the CLRTC real-time clock data based on the identification result. S03: Construct a power-on anomaly variable domain in the System Reset module, read the calibration failure data of the power fluctuation anomaly factor when the computer system handles anomalies, and map it to the power-on anomaly variable domain for fault-related weight allocation and soft voting. Based on the voting score results, detect the actual system crash state of the computer. When a crash occurs, detect the System Reset signal to automatically trigger the computer system restart.

[0007] Furthermore, in a preferred embodiment of the present invention, step S01 specifically includes the following steps: By constructing a trigger service routine framework for user operations based on trigger event types and trigger effectiveness logic criteria, the framework senses the context data of computer shutdown status and anti-accidental touch duration and analyzes it with the ideal trigger requirements for the Recovery module to execute the system recovery program. It listens for user operations, applies for effective arbitration based on the trigger service routine framework to start the system recovery program and generates a trigger signal. The trigger signal is saved to the computer's wake-up register through hardware circuitry, and the computer's RC delay unit is simultaneously powered on and initialized. After saving, read the firmware version serial number and carry flag of the wake-up register, decide on the discharge parameters of the RC delay trigger signal based on the firmware version serial number and carry flag, and control the RC delay unit to enter the discharge state according to the discharge parameters. A Kirchhoff topology circuit with RC delay unit is constructed. The voltage of the topology node in the Kirchhoff topology circuit is monitored in real time and periodically collected through hardware circuit, and a low-pass peak curve of the node voltage is established. Obtain the motherboard model and specification information, and based on the model and specification information, retrieve the rated power supply parameter range of the motherboard when the computer is running normally from the big data. Based on the rated power supply parameter range, preset the tolerance absorption range of the RC delay voltage. When the voltage peak value on the low-pass peak curve first enters the tolerance absorption range, the current computer is marked as a candidate trigger operation. The timing sampling of the node voltage is maintained for N consecutive times within the tolerance absorption range to obtain the wake-up peak voltage value during the Recovery module confirmation period. If the wake-up spike voltage value does not exceed the boundary of the tolerance absorption range, the wake-up delay is confirmed. At this time, the trigger array is triggered in coordination according to the wake-up spike voltage value, so as to wake up the motherboard and automatically enter the system recovery process of Recovery mode when the computer is powered on.

[0008] Furthermore, in a preferred embodiment of the present invention, the step of constructing a trigger service routine framework for user operations by triggering event types and triggering effectiveness logic criteria, sensing the context data of computer shutdown state and anti-accidental touch duration and analyzing it with the ideal triggering requirements for the Recovery module to execute the system recovery program, monitoring user operations, applying for effective arbitration to start the system recovery program based on the trigger service routine framework, and generating a trigger signal, specifically includes the following steps: The system acquires user operations on the hardware circuit, as well as the monitoring strategy and triggering logic criteria for these user operations, and defines the triggering event types for user operations; wherein, the user operation is pressing a Button key. By listening to the user's actions, several different predetermined trigger vectors and corresponding trigger signals are obtained, a trigger vector table is constructed, and the effective response functions for different predetermined trigger vectors are extracted according to the trigger activation logic criteria. Register the entry address of the trigger service program in the trigger vector table, map different trigger stimulus signals to the corresponding effective response function based on the entry address, thereby binding the service rules for jumping to the effective processing logic after the listening event is triggered, and outputting the trigger service routine framework for user operation; The computer shutdown state is defined as the preceding item and the anti-accidental touch duration is defined as the following item. The real-time context-aware data of the current motherboard regarding the preceding and following items is obtained through the computer's low-power polling subscription mechanism. At the same time, the ideal situation conditions and ideal context-aware data for the Recovery module to trigger the system recovery program are obtained. Based on the ideal situation conditions, a pre-triggered filtering threshold is preset. A hash mask algorithm is introduced to calculate the code segment alignment between the real-time context-aware data and the ideal context-aware data. If the code segment alignment does not exceed the pre-triggered filtering threshold, it is determined that the current motherboard has detected the target trigger event of the user operation. Based on real-time context-aware data, a trigger request instruction is generated and issued to the trigger controller of the hardware circuit, and the system automatically jumps to the trigger service routine framework to request the effective arbitration of the system recovery procedure and obtain the effective response hit rate of the target trigger event. If the effective response hit rate is greater than the preset hit rate threshold, the system recovery program will be started in the Recovery module and a trigger signal will be written based on the effective response function.

[0009] Furthermore, in a preferred embodiment of the present invention, step S02 specifically includes the following steps: The button battery power management module on the computer motherboard intercepts the state switching request code of the current power domain when the computer is powered off, and sets the switching status flag bit during the power-on critical switching period of the current power domain based on the state switching request code. The preset monitoring strategy of the power management module is obtained, and the key power parameters of the computer motherboard power supply in the switching state flag bit are continuously read in real time according to the preset monitoring strategy; wherein, the key power parameters include voltage rise slope, voltage fall slope, current change data and transient current overshoot data. By introducing the signal integrity law of progressive loading in different power domains and the frequency domain of the power-on signal, based on the signal integrity law, PG signal analysis and complete reconstruction are performed on several consecutive key power parameters in the frequency domain of the power-on signal to generate the PG distortion signal of the current power domain. Extract the continuous spectral vector and its distortion characteristic kurtosis value of the PG distortion signal, construct a stable power-on PG signal after the power is turned on in the power domain, and preset the corresponding ideal distortion characteristic threshold. If the distortion feature kurtosis value is lower than the ideal distortion feature threshold, the current power domain of the computer motherboard is marked as switching to the erroneous power-on switching state; if the distortion feature kurtosis value is lower than the ideal distortion feature threshold, the current power domain is marked as switching to the quasi-power-on switching state. When the computer motherboard is determined to be in a quasi-power-on switching state, the system checks whether the anti-accidental touch isolation structure of the CLRTC module is physically triggered. If a physical trigger has been established, the power-on observation hypothesis is defined to statistically analyze the true distribution of RTC calibration failures when the PG distortion signal is generated using variational autoencoders. The power-on fault classification tree is then used to classify the true distribution statistical results and identify the RTC timing mode, so that the CLRTC module can clear the CLRTC real-time clock data when the computer is currently powered off.

[0010] Furthermore, in a preferred embodiment of the present invention, the definition of power-on observation assumption uses variational autoencoder to statistically analyze the true distribution of RTC calibration failures when the PG distortion signal is generated, and utilizes a power-on fault classification tree to classify the true distribution statistical results and identify the RTC timing mode, so that the CLRTC module clears the CLRTC real-time clock data when the computer is currently powered off. Specifically, this includes the following steps: Obtain the power-on sequence logic and RTC clock maintenance mechanism of the current power domain, define the power-on observation hypothesis based on the power-on sequence logic and RTC clock maintenance mechanism, and construct the latent variable constraint network architecture of the variational autoencoder for power domain adaptive RTC timing based on the power-on observation hypothesis. The RTC calibration inflection point equivalent of the parameterized sampled PG distortion signal is injected into the variational autoencoder to perform statistical analysis of the true distribution of the power-on signal, thereby obtaining the true posterior distribution sequence code of the current power domain output power-on signal. Based on big data, a power-on knowledge graph of the computer motherboard is obtained. A power-on fault classification identification tree is constructed based on the power-on knowledge graph. The real posterior distribution sequence code is used as the identification index sample and imported into the power-on fault classification identification tree for traversal and search. During the traversal search process, the KL divergence algorithm is introduced to calculate the variational KL divergence between the true posterior distribution sequence code and the given posterior distribution sequence code corresponding to each leaf node on each fault level of the power-on fault classification identification tree. Only the power-on fault classification corresponding to the leaf node with the minimum variational KL divergence is extracted. It is defined as the target power-on fault classification that causes the RTC clock data calibration failure to be chained to the complete power failure of the computer. The RTC timing mode executed when the computer is completely powered off under the target power-on fault classification is extracted and marked as the current power-on RTC timing mode. By retrieving the target power-on fault classification through the power-on knowledge graph, the clock recovery concept of the current power-on RTC timing mode is obtained. Based on the clock recovery concept, the automatic clearing process of the CLRTC module is entered, and the CLRTC real-time clock data of the current computer is cleared in the power-off state.

[0011] Furthermore, in a preferred embodiment of the present invention, step S03 specifically includes the following steps: The topology is stripped to extract the anomaly perception network deployed in the current power domain to capture system operation, and the system fault response mechanism of the anomaly perception network in response to the computer in different abnormal scenarios is obtained. Based on the anomaly perception network, a power-on anomaly variable domain for abnormal shutdown under the power-on state of the computer is constructed. Read the set of power fluctuation anomaly factors and the snapshot of the verification failure status variable corresponding to each different power fluctuation anomaly factor item from the computer motherboard's operation log, which were registered in the current power domain internal register of the time frame before the computer system handled the anomaly. Based on the snapshot of the verification failure status variable, map each power fluctuation anomaly factor confidence to the power-on anomaly variable domain. During the confidence mapping process, the fault response granularity for different system operation anomalies is set based on the system fault response mechanism. Dynamic maintenance weights are assigned to different power fluctuation anomaly factors according to the fault response granularity, thereby generating a power fluctuation state field for computer system anomalies. A soft failure voting method is introduced. Local failure voting values ​​for each power fluctuation anomaly factor are generated by using the soft failure voting method in the power fluctuation state field. Each power fluctuation anomaly factor is collected and all the local failure voting values ​​are weighted and fused to form a global power fluctuation state score value for computer system anomalies. The system presets different system crash causes that lead to abnormal computer system operation, and sets a crash state score threshold range for power fluctuations in the current power domain. If the global power fluctuation score value is within the crash state score threshold range, the computer is determined to be in a system crash state, and the signal detection program of the System Reset module is entered. When the program detects that the System Reset signal is being sent in the instruction register of the System Reset module, it will automatically trigger a computer system restart.

[0012] A second aspect of this invention provides an integrated triggering system for one-key computer restore based on a power-off state, applicable to any of the integrated triggering methods for one-key computer restore based on a power-off state described in any one of the claims. The system specifically includes: A multi-function button is provided, which is used to integrate and trigger the system restore module, real-time clock clear module and system forced reset module for one-key computer system restore operation when the computer is powered off. The power-off triggered system recovery module is used to directly trigger the system recovery process by pressing the multi-function button when the external power of the computer device is turned on, and to automatically trigger the recovery process the next time the computer is turned on. A real-time clock clear (CLRTC) module is used to clear real-time clock data when the computer is powered off by pressing a multi-function button. The system force reset module is used to detect the force reset signal sent when the multi-function key is pressed when the system crashes, and trigger the computer system to restart.

[0013] This invention addresses the technical deficiencies in the prior art, and its beneficial technical effects are as follows: This invention integrates three key maintenance functions—One-Key Recovery, RTC Clear (CLRTC), and System Reset—into a single button through independent hardware circuitry and firmware collaboration. This enables reliable triggering under various extreme conditions, including when the device is plugged in but not powered on, completely powered off, and when the system malfunctions. This invention overcomes the limitations of traditional methods that rely on the operating system, BIOS, or standby power supply, freeing system recovery and maintenance from software state and power supply constraints, significantly reducing the user's operational threshold and maintenance complexity. Simultaneously, through button battery power, RC delay and anti-shake design, and a long-press detection mechanism, it effectively avoids accidental triggering, improving system stability and security. Furthermore, this invention reduces the number of buttons and jumpers on the motherboard, saving PCB space and facilitating modular porting and large-scale application, exhibiting good versatility and scalability. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained from these drawings without creative effort.

[0015] Figure 1 A flowchart of the first method of the integrated triggering method for one-key recovery of a computer based on the power-off state is shown; Figure 2 A flowchart of the second method for the integrated triggering method of one-key recovery of a computer based on the power-off state is shown; Figure 3 The system framework diagram of the integrated triggering system for one-click computer recovery based on the power-off state is shown. Detailed Implementation

[0016] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0017] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0018] The first aspect of this invention provides an integrated triggering method for one-key recovery of a computer based on a shutdown state, such as... Figure 1 As shown, it includes the following steps: S01: The hardware circuit monitors user operations when the computer is powered off and the Recovery module is protected against accidental touches. Based on the arbitration framework triggered by the user operation, the recovery program is started and a trigger signal is generated and saved to the wake-up register. The RC delay circuit works with the trigger to sample and analyze the voltage change during startup. The computer will automatically enter Recovery mode the next time it is powered on. S02: The button battery power management module reads the power data of the current power domain when the computer is powered off, performs stable power-on screening through the PG distortion signal reconstructed by the power data in the frequency domain, determines the current power-on state of the power domain, and detects whether the CLRTC module is physically triggered. If so, it identifies the true distribution statistics of the PG distortion signal and triggers the CLRTC module to clear the CLRTC real-time clock data based on the identification result. S03: Construct a power-on anomaly variable domain in the System Reset module, read the calibration failure data of the power fluctuation anomaly factor when the computer system handles anomalies, and map it to the power-on anomaly variable domain for fault-related weight allocation and soft voting. Based on the voting score results, detect the actual system crash state of the computer. When a crash occurs, detect the System Reset signal to automatically trigger the computer system restart.

[0019] Furthermore, in a preferred embodiment of the present invention, step S01 specifically includes the following steps: By constructing a trigger service routine framework for user operations based on trigger event types and trigger effectiveness logic criteria, the framework senses the context data of computer shutdown status and anti-accidental touch duration and analyzes it with the ideal trigger requirements for the Recovery module to execute the system recovery program. It listens for user operations, applies for effective arbitration based on the trigger service routine framework to start the system recovery program and generates a trigger signal. The trigger signal is saved to the computer's wake-up register through hardware circuitry, and the computer's RC delay unit is simultaneously powered on and initialized. After saving, read the firmware version serial number and carry flag of the wake-up register, decide on the discharge parameters of the RC delay trigger signal based on the firmware version serial number and carry flag, and control the RC delay unit to enter the discharge state according to the discharge parameters. A Kirchhoff topology circuit with RC delay unit is constructed. The voltage of the topology node in the Kirchhoff topology circuit is monitored in real time and periodically collected through hardware circuit, and a low-pass peak curve of the node voltage is established. Obtain the motherboard model and specification information, and based on the model and specification information, retrieve the rated power supply parameter range of the motherboard when the computer is running normally from the big data. Based on the rated power supply parameter range, preset the tolerance absorption range of the RC delay voltage. When the voltage peak value on the low-pass peak curve first enters the tolerance absorption range, the current computer is marked as a candidate trigger operation. The timing sampling of the node voltage is maintained for N consecutive times within the tolerance absorption range to obtain the wake-up peak voltage value during the Recovery module confirmation period. If the wake-up spike voltage value does not exceed the boundary of the tolerance absorption range, the wake-up delay is confirmed. At this time, the trigger array is triggered in coordination according to the wake-up spike voltage value, so as to wake up the motherboard and automatically enter the system recovery process of Recovery mode when the computer is powered on.

[0020] It should be noted that the Recovery module is a low-power hardware module designed independently of the computer motherboard. It supports maintaining trigger signal monitoring via a coin cell battery after power-off. When the hardware circuit detects the user pressing the Button, the motherboard's wake-up logic is as follows: the trigger signal is stored in the wake-up register, requiring no other cumbersome operations; the system will automatically enter Recovery mode upon the next power-on. This invention's Recovery module uses a trigger and an RC delay circuit for coordinated triggering. Therefore, by deterministically initializing the RC delay unit upon power-up, signal storage and delay environment preparation are completed synchronously. Since firmware versions differ across computer motherboards, using traditional fixed-state RC delay discharge parameter settings may lead to delayed startup failures or erroneous wake-ups during the recovery process. To address this, this method dynamically plans the discharge parameters of the RC delay unit based on the firmware version serial number and carry flag in the wake-up register. This significantly improves the compatibility of the system recovery process with different firmware or motherboard platforms, ensuring the sensitivity and reliability of the delayed trigger. Furthermore, by periodically sampling the node voltage during RC delay unit leakage, a smooth and reliable RC voltage evolution trend can be grasped. During sampling, transient spikes or glitches are filtered out to avoid misjudgment from single-point sampling and reduce the impact of leakage floating noise on triggering. Due to the differences in power supply across different motherboards, the same RC parameter exhibits inconsistent performance on different computer motherboard platforms. Therefore, voltage fluctuations during startup are easily misjudged as abnormal or trigger failure signals, preventing successful automatic entry into Recovery mode upon the next startup. To address this, this method presets a tolerance absorption range for the RC delay voltage based on the motherboard's rated power supply parameters during normal computer startup. This tolerance absorption range acts as a startup-aware filtering barrier for RC delay voltage feedback before triggering Recovery mode. By replacing a single threshold with a voltage range, the delay trigger determination in the recovery process transitions from single-point threshold triggering to process-aware triggering, eliminating jitter interference while delaying RC.

[0021] It should be noted that timing-based verification is performed on the state entering the tolerance range. The actual wake-up voltage within the Recovery confirmation window is collected to eliminate transient situations that mistakenly enter the range, effectively distinguishing transient spikes from true stable wake-ups. This ensures the continuity and authenticity of the boot trigger behavior to enter Recovery mode, reducing the probability of false triggers. If the wake-up spike voltage value does not exceed the boundary of the tolerance absorption range, it indicates that the trigger signal of the recovery process is synchronized with the motherboard's wake-up action. Therefore, the wake-up delay is further confirmed to achieve automatic entry into Recovery mode upon computer startup. This method generates a trigger signal by listening to user operations through hardware circuitry and combines an RC delay circuit with a trigger-based collaborative architecture to reliably wake the motherboard and automatically enter Recovery mode in a shutdown scenario. This overcomes the shortcomings of traditional solutions, such as high dependence on standby power supply, susceptibility to accidental touches, and poor compatibility.

[0022] Furthermore, in a preferred embodiment of the present invention, the step of constructing a trigger service routine framework for user operations by triggering event types and triggering effectiveness logic criteria, sensing the context data of computer shutdown state and anti-accidental touch duration and analyzing it with the ideal triggering requirements for the Recovery module to execute the system recovery program, monitoring user operations, applying for effective arbitration to start the system recovery program based on the trigger service routine framework, and generating a trigger signal, specifically includes the following steps: The system acquires user operations on the hardware circuit, as well as the monitoring strategy and triggering logic criteria for these user operations, and defines the triggering event types for user operations; wherein, the user operation is pressing a Button key. By listening to the user's actions, several different predetermined trigger vectors and corresponding trigger signals are obtained, a trigger vector table is constructed, and the effective response functions for different predetermined trigger vectors are extracted according to the trigger activation logic criteria. Register the entry address of the trigger service program in the trigger vector table, map different trigger stimulus signals to the corresponding effective response function based on the entry address, thereby binding the service rules for jumping to the effective processing logic after the listening event is triggered, and outputting the trigger service routine framework for user operation; The computer shutdown state is defined as the preceding item and the anti-accidental touch duration is defined as the following item. The real-time context-aware data of the current motherboard regarding the preceding and following items is obtained through the computer's low-power polling subscription mechanism. At the same time, the ideal situation conditions and ideal context-aware data for the Recovery module to trigger the system recovery program are obtained. Based on the ideal situation conditions, a pre-triggered filtering threshold is preset. A hash mask algorithm is introduced to calculate the code segment alignment between the real-time context-aware data and the ideal context-aware data. If the code segment alignment does not exceed the pre-triggered filtering threshold, it is determined that the current motherboard has detected the target trigger event of the user operation. Based on real-time context-aware data, a trigger request instruction is generated and issued to the trigger controller of the hardware circuit, and the system automatically jumps to the trigger service routine framework to request the effective arbitration of the system recovery procedure and obtain the effective response hit rate of the target trigger event. If the effective response hit rate is greater than the preset hit rate threshold, the system recovery program will be started in the Recovery module and a trigger signal will be written based on the effective response function.

[0023] It should be noted that while the coin cell battery module on the computer motherboard can independently maintain the user operation monitoring function of the hardware circuitry, it cannot distinguish between the same button actions in different usage scenarios because the buttons are only treated as physical level changes. For example, both system restore and forced reset scenarios require pressing the multi-function (Button) button, and the hardware circuitry lacks trigger event semantics, leading to triggering errors in the interpretation of multi-function button presses. Therefore, this method proposes upgrading the user operation to be monitored, "pressing the Button," as the trigger event source. Synchronously, due to the severe coupling of the triggering logic of the button for different system recovery scenarios, the trigger judgment process is cumbersome, making it difficult to accurately perceive the triggering intent of the system recovery process under its one-click multi-functionality, which is prone to conflicts or misjudgments. Therefore, during the hardware circuit's monitoring of user operations, a trigger vector table is established by abstracting different predetermined trigger vectors of user operations based on the monitoring strategy. This enables structured management of trigger types and excitation signals, providing system-level low-level monitoring support required for the Recovery process triggering under the premise of one-click multi-morphic functionality of the button. This improves the accuracy and targeting of the hardware circuit's monitoring of the Recovery module's button triggers in the power-off state, reduces the complexity of the triggering logic, and improves maintainability. In particular, because the button triggering logic and processing code between the Recovery module and other modules may be strongly coupled, the hardware circuit's monitoring path jump for the trigger event of the system recovery module triggered by power-off is chaotic, with execution uncertainty, making it difficult to achieve highly autonomous trigger effect management or reuse. To address this, this method establishes a mapping relationship between trigger stimulus signals and effective response functions by registering the service program entry address in the aforementioned trigger vector table. This ensures that after a hardware button is triggered, the system can quickly jump to the correct effective arbitration processing logic for the system recovery program, forming a complete trigger service routine framework. This achieves a highly autonomous, structured, and modular approach to the shutdown trigger system restore event listening logic.

[0024] It should be noted that the system recovery module triggered by power off has a unique anti-accidental touch setting, requiring a continuous press for 3-5 seconds to take effect. Therefore, the anti-accidental touch design is one of the key considerations for triggering the recovery process, the other being the power off state. However, traditional button trigger judgment only considers one of these factors, failing to distinguish between valid and invalid triggers and lacking strong contextual coupling. Therefore, this method uses hardware circuitry to monitor and sense the preceding data of the computer's power off state and the following data that meets the anti-accidental touch duration in real time, ensuring that the monitoring logic is based on the current valid environmental state. Subsequently, before the event enters the monitoring queue, context matching is performed, i.e., setting a pre-filtering threshold (pre-trigger filtering threshold) based on ideal situation conditions, and comparing the code segment alignment of the real-time context-aware data with the ideal context-aware data using a hash mask algorithm. The code segment alignment quantifies the deviation or misalignment between the actual trigger state of the system recovery process triggered by power off and the fixed trigger state, revealing whether the user's pressing of the button meets or satisfies the predetermined trigger requirements of this program. If the code segment alignment does not exceed the pre-triggered filtering threshold, it indicates that the current button press condition for preventing accidental touches and the power-off state both meet the basic requirements for triggering the system recovery process. Therefore, it is determined that the motherboard has detected user operation, effectively reducing the probability of trigger event storms and false triggers due to multiple judgment factors. Finally, a standardized trigger request is generated based on the real-time context, and a synchronous jump to the trigger service routine framework is performed to request the system recovery procedure to take effect arbitration. The effective response hit rate is used as a quantitative indicator for final effective confirmation, realizing safe triggering after multi-level confirmation, which greatly avoids the risk of false recovery. This method models user key operations as trigger event vectors and introduces context-aware judgment of anti-accidental touch and power-off state, as well as an effective arbitration mechanism based on the trigger service routine framework, to improve the sensitivity and reliability of hardware circuits in triggering user operations, ensuring the triggering accuracy of the Recovery system recovery process.

[0025] Furthermore, in a preferred embodiment of the present invention, S02, as... Figure 2 As shown, the specific steps include: The button battery power management module on the computer motherboard intercepts the state switching request code of the current power domain when the computer is powered off, and sets the switching status flag bit during the power-on critical switching period of the current power domain based on the state switching request code. The preset monitoring strategy of the power management module is obtained, and the key power parameters of the computer motherboard power supply in the switching state flag bit are continuously read in real time according to the preset monitoring strategy; wherein, the key power parameters include voltage rise slope, voltage fall slope, current change data and transient current overshoot data. By introducing the signal integrity law of progressive loading in different power domains and the frequency domain of the power-on signal, based on the signal integrity law, PG signal analysis and complete reconstruction are performed on several consecutive key power parameters in the frequency domain of the power-on signal to generate the PG distortion signal of the current power domain. Extract the continuous spectral vector and its distortion characteristic kurtosis value of the PG distortion signal, construct a stable power-on PG signal after the power is turned on in the power domain, and preset the corresponding ideal distortion characteristic threshold. If the distortion feature kurtosis value is lower than the ideal distortion feature threshold, the current power domain of the computer motherboard is marked as switching to the erroneous power-on switching state; if the distortion feature kurtosis value is lower than the ideal distortion feature threshold, the current power domain is marked as switching to the quasi-power-on switching state. When the computer motherboard is determined to be in a quasi-power-on switching state, the system checks whether the anti-accidental touch isolation structure of the CLRTC module is physically triggered. If a physical trigger has been established, the power-on observation hypothesis is defined to statistically analyze the true distribution of RTC calibration failures when the PG distortion signal is generated using variational autoencoders. The power-on fault classification tree is then used to classify the true distribution statistical results and identify the RTC timing mode, so that the CLRTC module can clear the CLRTC real-time clock data when the computer is currently powered off.

[0026] It should be noted that traditional methods require disassembling the computer and shorting jumpers to restore CLRTC when a computer malfunctions, which is complex and poses safety risks. The real-time clock clearing (CLRTC) module of this invention automatically clears CLRTC data when the power is off by pressing a multi-function button, without removing the chassis or shorting. To prevent false connectivity issues in the system power domain, which could lead to erroneous power-on detection and inaccurate clearing of CLRTC data, this method first intercepts the power domain state switching request code when the computer fails to power down. This request code sets a switching status flag for the current power domain, clearly indicating the critical switching period the power domain is currently entering. This allows the system to logically distinguish between the computer's transient transition from a stable, normally operating state to a sudden power failure, thus limiting the monitoring scope and time window for subsequent abnormal power data detection. This avoids misjudging unstable power as an anomaly during a power failure switching state, improving the targeting and accuracy of power-on detection before CLRTC data clearing. Next, by monitoring the power parameters on this switching status flag, it is found that traditional methods often fail to identify implicit distortions caused by gradual load loading due to the inherent implicit fluctuations in power parameters, mistakenly regarding seemingly successful fault power-on states as normal. Therefore, this method reconstructs the PG signal integrity of continuous key power parameters by introducing the signal integrity law. The PG distortion signal, at the Boolean depth level, truly reflects the power domain state transition caused by fault intervention, resulting in power-on pulse pull-downs or high jumps, serving as an explicit trigger flag for quickly locating power domain power supply anomalies. Among these, the continuous spectrum vector is a concrete symbol representing the stable linearity of power-on, while the distortion feature kurtosis value quantifies the power distortion characteristics and severity of fault power-off fluctuations.

[0027] It should be noted that if the distortion characteristic kurtosis value is lower than the ideal distortion characteristic threshold, it indicates that the power-on fluctuation caused by the power failure is relatively minor. This strongly suggests a false power domain connection under conditions where the motherboard is completely powered off due to a fault. Therefore, it is considered a power-on false triggering scenario, and the clearing of real-time clock data is not authorized. Conversely, if the value is higher, it indicates that the motherboard is only in a power-off state, but its actual connection to the power supply is still confirmed, which is a confirmed power-on scenario. Therefore, the clearing of real-time clock data is allowed, improving the accuracy and reliability of the computer system's real-time clock (CLRTC) data clearing trigger and preventing the real-time clock (CLRTC) clearing program from being triggered erroneously. In addition, the Real-Time Clock Clear (CLRTC) module is also designed with a unique physical isolation structure to prevent accidental activation. Therefore, in addition to maintaining the above-mentioned quasi-power-on state, it is also necessary to ensure that the physical isolation of the Real-Time Clock Clear (CLRTC) module is triggered synchronously before the clearing procedure can be triggered. This achieves the dual constraint of power-on judgment and user confirmation, reducing the risk of RTC data being accidentally cleared and the probability of being out of sync with the user's true intentions, and ensuring the rigor, controllability, and interpretability of the real-time clock clearing rules.

[0028] Furthermore, in a preferred embodiment of the present invention, the definition of power-on observation assumption uses variational autoencoder to statistically analyze the true distribution of RTC calibration failures when the PG distortion signal is generated, and utilizes a power-on fault classification tree to classify the true distribution statistical results and identify the RTC timing mode, so that the CLRTC module clears the CLRTC real-time clock data when the computer is currently powered off. Specifically, this includes the following steps: Obtain the power-on sequence logic and RTC clock maintenance mechanism of the current power domain, define the power-on observation hypothesis based on the power-on sequence logic and RTC clock maintenance mechanism, and construct the latent variable constraint network architecture of the variational autoencoder for power domain adaptive RTC timing based on the power-on observation hypothesis. The RTC calibration inflection point equivalent of the parameterized sampled PG distortion signal is injected into the variational autoencoder to perform statistical analysis of the true distribution of the power-on signal, thereby obtaining the true posterior distribution sequence code of the current power domain output power-on signal. Based on big data, a power-on knowledge graph of the computer motherboard is obtained. A power-on fault classification identification tree is constructed based on the power-on knowledge graph. The real posterior distribution sequence code is used as the identification index sample and imported into the power-on fault classification identification tree for traversal and search. During the traversal search process, the KL divergence algorithm is introduced to calculate the variational KL divergence between the true posterior distribution sequence code and the given posterior distribution sequence code corresponding to each leaf node on each fault level of the power-on fault classification identification tree. Only the power-on fault classification corresponding to the leaf node with the minimum variational KL divergence is extracted. It is defined as the target power-on fault classification that causes the RTC clock data calibration failure to be chained to the complete power failure of the computer. The RTC timing mode executed when the computer is completely powered off under the target power-on fault classification is extracted and marked as the current power-on RTC timing mode. By retrieving the target power-on fault classification through the power-on knowledge graph, the clock recovery concept of the current power-on RTC timing mode is obtained. Based on the clock recovery concept, the automatic clearing process of the CLRTC module is entered, and the CLRTC real-time clock data of the current computer is cleared in the power-off state.

[0029] It should be noted that real-time clock data executes differentiated RTC modes under different fault types. For different RTC clock data, strict adherence to the system timing or synchronization timestamp patterns is necessary for effective cleanup. To address this, this method defines a power-on observation hypothesis in the CLRTC module, referencing the power-on sequence logic and RTC clock maintenance mechanism. Specifically, this hypothesis assumes that PG distortion signals are randomly generated by latent variables at low-dimensional RTC misalignment points. Since RTC timing anomalies in computer systems are often considered isolated problems and cannot be correlated with the power-on sequence in the power domain, it is impossible to distinguish RTC calibration deviations caused by the current power-on loading, easily leading to overfitting in subsequent pattern recognition. Therefore, this method constructs a latent variable constraint network architecture for a power-domain adaptive RTC timing variational autoencoder based on the power-on observation hypothesis, endowing it with the ability to explore latent variables of RTC uncertainty misalignment and improving the reliability of RTC failure modeling. This method utilizes a latent variable-constrained network architecture to statistically analyze the true power-on distribution of the PG distortion signal in the current power domain, i.e., the true posterior distribution sequence code. This true posterior distribution sequence code captures the true probability structure of RTC data calibration failure, providing highly discriminative feature guidance for subsequent fault classification identification. The variational KL divergence measures the discrete misalignment between the true inaccuracy probability structure of the PG distortion signal and the corresponding inaccuracy probabilities for different fault classifications. This variational KL divergence effectively constrains the global traversal fixation or stagnation of the true posterior distribution sequence code in the power-on fault classification identification tree, thereby penalizing standard normal identification terms that deviate from the latent variable distribution, improving the accuracy and global fine-grainedness of fault classification identification. By introducing a variational autoencoder model constrained by the power domain power-on sequence and RTC maintenance mechanism, this method performs statistical learning on the true distribution of the PG distortion signal, accurately identifying the power-on fault type causing RTC calibration failure and locating the corresponding power-on RTC timing mode. This allows for targeted triggering of the CLRTC automatic clearing process under power-on conditions, significantly improving the security and ease of operation of the computer system.

[0030] Furthermore, in a preferred embodiment of the present invention, step S03 specifically includes the following steps: The topology is stripped to extract the anomaly perception network deployed in the current power domain to capture system operation, and the system fault response mechanism of the anomaly perception network in response to the computer in different abnormal scenarios is obtained. Based on the anomaly perception network, a power-on anomaly variable domain for abnormal shutdown under the power-on state of the computer is constructed. Read the set of power fluctuation anomaly factors and the snapshot of the verification failure status variable corresponding to each different power fluctuation anomaly factor item from the computer motherboard's operation log, which were registered in the current power domain internal register of the time frame before the computer system handled the anomaly. Based on the snapshot of the verification failure status variable, map each power fluctuation anomaly factor confidence to the power-on anomaly variable domain. During the confidence mapping process, the fault response granularity for different system operation anomalies is set based on the system fault response mechanism. Dynamic maintenance weights are assigned to different power fluctuation anomaly factors according to the fault response granularity, thereby generating a power fluctuation state field for computer system anomalies. A soft failure voting method is introduced. Local failure voting values ​​for each power fluctuation anomaly factor are generated by using the soft failure voting method in the power fluctuation state field. Each power fluctuation anomaly factor is collected and all the local failure voting values ​​are weighted and fused to form a global power fluctuation state score value for computer system anomalies. The system presets different system crash causes that lead to abnormal computer system operation, and sets a crash state score threshold range for power fluctuations in the current power domain. If the global power fluctuation score value is within the crash state score threshold range, the computer is determined to be in a system crash state, and the signal detection program of the System Reset module is entered. When the program detects that the System Reset signal is being sent in the instruction register of the System Reset module, it will automatically trigger a computer system restart.

[0031] It should be noted that when a computer frequently becomes unresponsive, crashes, or experiences blue screen errors, the System Reset module allows users to try the System Reset function by pressing the Reset button, which sends and detects a System Reset signal, triggering a system restart. However, during computer use, certain system operations or responses may resemble system crashes, such as brief pauses, loading screens, or buffering. These common computer operations are easily misinterpreted by the System Reset module and the user as system crashes, thus triggering a forced system restart based on the user-sent System Reset signal. This frequent forced restarts due to misinterpretations can reduce the lifespan of the computer motherboard and increase computer maintenance costs. To address this, this method constructs a power-on anomaly variable domain through an anomaly perception network. This domain represents the state space of abnormal power-on fluctuations under power-on conditions, forming a variable modeling mechanism between power-on anomalies and operational anomalies, providing a concrete basis for subsequent power fluctuation modeling. Subsequently, the power fluctuation factors stored during computer system anomaly handling are mapped to this variable domain, effectively eliminating dimensional differences and transforming different power fluctuation factors into confidence variables that can participate in decision-making and be fused for comparison, thereby tracing back the power dynamic behavior before the anomaly occurred. Furthermore, a fault response granularity is set for different system operational anomalies through the system fault response mechanism. This fault response granularity is equivalent to the processing intensity related to different system fault configurations. For example, when the system experiences frequent readouts, a fault alarm can be issued through a pop-up prompt window, which is an effective contingency plan. Therefore, this method assigns dynamic maintenance weights with quantifiable fault relevance to different power fluctuation anomaly factors based on the fault response granularity, thereby abstracting discrete anomaly factors into a continuous state field. Through the power fluctuation state field, noise disturbances can be effectively suppressed, the judgment role of key power fluctuation factors can be explored and strengthened, the accuracy and robustness of the current system operational anomaly characteristics can be significantly enhanced, and the accuracy of subsequent system crash and failure judgment can be improved.

[0032] It should be noted that if the global power fluctuation status score is within the crash status score threshold range, it indicates that the power fluctuation assessment during current system operation is highly consistent with the power fluctuation status during a crash. This suggests that the current computer system may be experiencing frequent unresponsiveness, crashes, or blue screen errors, indicating a crash state requiring an urgent system restart. This method automatically detects the restart signal from the System Reset module when the computer system crashes, thereby triggering a forced system restart program. This achieves intelligent identification and adaptive restart control of the system crash state, significantly improving the computer system's self-healing ability in complete crash scenarios and resolving the restart failure phenomenon where traditional restart methods cannot access the operating interface.

[0033] A second aspect of this invention provides an integrated triggering system for one-key computer restore based on the power-off state, such as... Figure 3 As shown, the integrated triggering method for one-key recovery of a computer based on a shutdown state, applied to any one of the above-described methods, specifically includes: A multi-function button is provided, which is used to integrate and trigger the system restore module, real-time clock clear module and system forced reset module for one-key computer system restore operation when the computer is powered off. The power-off triggered system recovery module is used to directly trigger the system recovery process by pressing the multi-function button when the external power of the computer device is turned on, and to automatically trigger the recovery process the next time the computer is turned on. A real-time clock clear (CLRTC) module is used to clear real-time clock data when the computer is powered off by pressing a multi-function button. The system force reset module is used to detect the force reset signal sent when the multi-function key is pressed when the system crashes, and trigger the computer system to restart.

[0034] It should be noted that the System Recovery module triggered by power-off is a low-power hardware module independent of the motherboard. It supports maintaining trigger signal monitoring via a coin cell battery while the device is powered off. The hardware circuitry listens for user actions (pressing the button) and triggers the recovery process. The motherboard wake-up logic stores the trigger signal in a register, requiring no other complex operations; it automatically enters Recovery mode upon the next power-on. This module uses a trigger and an RC delay circuit for coordinated triggering, eliminating jitter interference during the RC delay. Furthermore, its anti-accidental touch mechanism requires a continuous press for 3-5 seconds to take effect. The Real-Time Clock Clear (CLRTC) module is triggered by pressing the button while the power is off, automatically clearing RTC data without removing the casing or shorting, greatly improving safety and ease of use. The System Reset module is triggered when the device frequently becomes unresponsive, freezes, or experiences blue screen errors. Pressing the button in this situation sends a System Reset signal, triggering a system restart.

[0035] It should be noted that the system realizes the linkage of triggering Recovery during shutdown, power-off CLRTC, and power-on System Reset through the cooperation of the hardware backup circuit and firmware. Compared with the traditional solution that relies on the standby power supply, this solution is independently powered by a button battery to ensure that it can be triggered after power-off. In addition, in terms of the design and layout of the main board, the optimization of the wiring needs to be considered. The Button on the main board usually needs to be placed in the corner to reduce the PCB space, avoid waste of the main board PCB, and prevent accidental touch.

[0036] The above are only specific implementation manners of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. An integrated triggering method for one-key recovery of a computer based on a shutdown state, characterized in that, Includes the following steps: S01: The hardware circuit monitors user operations when the computer is powered off and the Recovery module is protected against accidental touches. Based on the arbitration framework triggered by the user operation, the recovery program is started and a trigger signal is generated and saved to the wake-up register. The RC delay circuit works with the trigger to sample and analyze the voltage change during startup. The computer will automatically enter Recovery mode the next time it is powered on. S02: The button battery power management module reads the power data of the current power domain when the computer is powered off. It performs stable power-on screening by reconstructing the PG distortion signal in the frequency domain of the power data, determines the current power-on state of the power domain, and detects whether the CLRTC module is physically triggered. If so, it identifies the true distribution statistics of the PG distortion signal and triggers the CLRTC module to clear the CLRTC real-time clock data based on the identification result. S03: Construct a power-on anomaly variable domain in the System Reset module, read the calibration failure data of the power fluctuation anomaly factor when the computer system handles anomalies, and map it to the power-on anomaly variable domain for fault-related weight allocation and soft voting. Based on the voting score results, detect the actual system crash state of the computer. When a crash occurs, detect the System Reset signal to automatically trigger the computer system restart.

2. The integrated triggering method for one-key computer restore based on shutdown state as described in claim 1, characterized in that, S01 specifically includes the following steps: By constructing a trigger service routine framework for user operations based on trigger event types and trigger effectiveness logic criteria, the framework senses the context data of computer shutdown status and anti-accidental touch duration and analyzes it with the ideal trigger requirements for the Recovery module to execute the system recovery program. It listens for user operations, applies for effective arbitration based on the trigger service routine framework to start the system recovery program and generates a trigger signal. The trigger signal is saved to the computer's wake-up register through hardware circuitry, and the computer's RC delay unit is simultaneously powered on and initialized. After saving, read the firmware version serial number and carry flag of the wake-up register, decide on the discharge parameters of the RC delay trigger signal based on the firmware version serial number and carry flag, and control the RC delay unit to enter the discharge state according to the discharge parameters. A Kirchhoff topology circuit with RC delay unit is constructed. The voltage of the topology node in the Kirchhoff topology circuit is monitored in real time and periodically collected through hardware circuit, and a low-pass peak curve of the node voltage is established. Obtain the motherboard model and specification information, and based on the model and specification information, retrieve the rated power supply parameter range of the motherboard when the computer is running normally from the big data. Based on the rated power supply parameter range, preset the tolerance absorption range of the RC delay voltage. When the voltage peak value on the low-pass peak curve first enters the tolerance absorption range, the current computer is marked as a candidate trigger operation. The timing sampling of the node voltage is maintained for N consecutive times within the tolerance absorption range to obtain the wake-up peak voltage value during the Recovery module confirmation period. If the wake-up spike voltage value does not exceed the boundary of the tolerance absorption range, the wake-up delay is confirmed. At this time, the trigger array is triggered in coordination according to the wake-up spike voltage value, so as to wake up the motherboard and automatically enter the system recovery process of Recovery mode when the computer is powered on.

3. The integrated triggering method for one-key computer restore based on shutdown state as described in claim 2, characterized in that, The framework for triggering user operations, constructed by triggering event types and triggering effectiveness logic criteria, senses contextual data such as computer shutdown status and anti-accidental touch duration, analyzes it against the ideal triggering requirements for the Recovery module to execute the system recovery procedure, listens for user operations, and, based on the triggering service routine framework, requests effective arbitration to start the system recovery procedure and generates a trigger signal. Specifically, it includes the following steps: The system acquires user operations on the hardware circuit, as well as the monitoring strategy and triggering logic criteria for these user operations, and defines the triggering event types for user operations; wherein, the user operation is pressing a Button key. By listening to the user's actions, several different predetermined trigger vectors and corresponding trigger signals are obtained, a trigger vector table is constructed, and the effective response functions for different predetermined trigger vectors are extracted according to the trigger activation logic criteria. Register the entry address of the trigger service program in the trigger vector table, map different trigger stimulus signals to the corresponding effective response function based on the entry address, thereby binding the service rules for jumping to the effective processing logic after the listening event is triggered, and outputting the trigger service routine framework for user operation; The computer shutdown state is defined as the preceding item and the anti-accidental touch duration is defined as the following item. The real-time context-aware data of the current motherboard regarding the preceding and following items is obtained through the computer's low-power polling subscription mechanism. At the same time, the ideal situation conditions and ideal context-aware data for the Recovery module to trigger the system recovery program are obtained. Based on the ideal situation conditions, a pre-triggered filtering threshold is preset. A hash mask algorithm is introduced to calculate the code segment alignment between the real-time context-aware data and the ideal context-aware data. If the code segment alignment does not exceed the pre-triggered filtering threshold, it is determined that the current motherboard has detected the target trigger event of the user operation. Based on real-time context-aware data, a trigger request instruction is generated and issued to the trigger controller of the hardware circuit, and the system automatically jumps to the trigger service routine framework to request the effective arbitration of the system recovery procedure and obtain the effective response hit rate of the target trigger event. If the effective response hit rate is greater than the preset hit rate threshold, the system recovery program will be started in the Recovery module and a trigger signal will be written based on the effective response function.

4. The integrated triggering method for one-key computer restore based on shutdown state as described in claim 1, characterized in that, S02 specifically includes the following steps: The button battery power management module on the computer motherboard intercepts the state switching request code of the current power domain when the computer is powered off, and sets the switching status flag bit during the power-on critical switching period of the current power domain based on the state switching request code. The preset monitoring strategy of the power management module is obtained, and the key power parameters of the computer motherboard power supply in the switching state flag bit are continuously read in real time according to the preset monitoring strategy; wherein, the key power parameters include voltage rise slope, voltage fall slope, current change data and transient current overshoot data. By introducing the signal integrity law of progressive loading in different power domains and the frequency domain of the power-on signal, based on the signal integrity law, PG signal analysis and complete reconstruction are performed on several consecutive key power parameters in the frequency domain of the power-on signal to generate the PG distortion signal of the current power domain. Extract the continuous spectral vector and its distortion characteristic kurtosis value of the PG distortion signal, construct a stable power-on PG signal after the power is turned on in the power domain, and preset the corresponding ideal distortion characteristic threshold. If the distortion feature kurtosis value is lower than the ideal distortion feature threshold, the current power domain of the computer motherboard is marked as switching to the erroneous power-on switching state; if the distortion feature kurtosis value is lower than the ideal distortion feature threshold, the current power domain is marked as switching to the quasi-power-on switching state. When the computer motherboard is determined to be in a quasi-power-on switching state, the system checks whether the anti-accidental touch isolation structure of the CLRTC module is physically triggered. If a physical trigger has been established, the power-on observation hypothesis is defined to statistically analyze the true distribution of RTC calibration failures when the PG distortion signal is generated using variational autoencoders. The power-on fault classification tree is then used to classify the true distribution statistical results and identify the RTC timing mode, so that the CLRTC module can clear the CLRTC real-time clock data when the computer is currently powered off.

5. The integrated triggering method for one-key computer restore based on shutdown state as described in claim 4, characterized in that, The defined power-on observation assumption uses variational autoencoder statistics to statistically analyze the true distribution of RTC calibration failures during PG distortion signal generation, and utilizes a power-on fault classification tree to classify the statistical results of the true distribution and identify the RTC timing mode, so that the CLRTC module can clear the CLRTC real-time clock data when the computer is powered off. Specifically, it includes the following steps: Obtain the power-on sequence logic and RTC clock maintenance mechanism of the current power domain, define the power-on observation hypothesis based on the power-on sequence logic and RTC clock maintenance mechanism, and construct the latent variable constraint network architecture of the variational autoencoder for power domain adaptive RTC timing based on the power-on observation hypothesis. The RTC calibration inflection point equivalent of the parameterized sampled PG distortion signal is injected into the variational autoencoder to perform statistical analysis of the true distribution of the power-on signal, thereby obtaining the true posterior distribution sequence code of the current power domain output power-on signal. Based on big data, a power-on knowledge graph of the computer motherboard is obtained. A power-on fault classification identification tree is constructed based on the power-on knowledge graph. The real posterior distribution sequence code is used as the identification index sample and imported into the power-on fault classification identification tree for traversal and search. During the traversal search process, the KL divergence algorithm is introduced to calculate the variational KL divergence between the true posterior distribution sequence code and the given posterior distribution sequence code corresponding to each leaf node on each fault level of the power-on fault classification identification tree. Only the power-on fault classification corresponding to the leaf node with the minimum variational KL divergence is extracted. It is defined as the target power-on fault classification that causes the RTC clock data calibration failure to be chained to the complete power failure of the computer. The RTC timing mode executed when the computer is completely powered off under the target power-on fault classification is extracted and marked as the current power-on RTC timing mode. By retrieving the target power-on fault classification through the power-on knowledge graph, the clock recovery concept of the current power-on RTC timing mode is obtained. Based on the clock recovery concept, the automatic clearing process of the CLRTC module is entered, and the CLRTC real-time clock data of the current computer is cleared in the power-off state.

6. The integrated triggering method for one-key computer restore based on shutdown state as described in claim 1, characterized in that, S03 specifically includes the following steps: The topology is stripped to extract the anomaly perception network deployed in the current power domain to capture system operation, and the system fault response mechanism of the anomaly perception network in response to the computer in different abnormal scenarios is obtained. Based on the anomaly perception network, a power-on anomaly variable domain for abnormal shutdown under the power-on state of the computer is constructed. Read the set of power fluctuation anomaly factors and the snapshot of the verification failure status variable corresponding to each different power fluctuation anomaly factor item from the computer motherboard's operation log, which were registered in the current power domain internal register of the time frame before the computer system handled the anomaly. Based on the snapshot of the verification failure status variable, map each power fluctuation anomaly factor confidence to the power-on anomaly variable domain. During the confidence mapping process, the fault response granularity for different system operation anomalies is set based on the system fault response mechanism. Dynamic maintenance weights are assigned to different power fluctuation anomaly factors according to the fault response granularity, thereby generating a power fluctuation state field for computer system anomalies. A soft failure voting method is introduced. Local failure voting values ​​for each power fluctuation anomaly factor are generated by using the soft failure voting method in the power fluctuation state field. Each power fluctuation anomaly factor is collected and all the local failure voting values ​​are weighted and fused to form a global power fluctuation state score value for computer system anomalies. The system presets different system crash causes that lead to abnormal computer system operation, and sets a crash state score threshold range for power fluctuations in the current power domain. If the global power fluctuation score value is within the crash state score threshold range, the computer is determined to be in a system crash state, and the signal detection program of the System Reset module is entered. When the program detects that the System Reset signal is being sent in the instruction register of the System Reset module, it will automatically trigger a computer system restart.

7. An integrated triggering system for one-key computer restore based on a power-off state, applied to the integrated triggering method for one-key computer restore based on a power-off state as described in any one of claims 1-6, the system specifically comprising: A multi-function button is provided, which is used to integrate and trigger the system restore module, real-time clock clear module and system forced reset module for one-key computer system restore operation when the computer is powered off. The power-off triggered system recovery module is used to directly trigger the system recovery process by pressing the multi-function button when the external power of the computer device is turned on, and to automatically trigger the recovery process the next time the computer is turned on. A real-time clock clear (CLRTC) module is used to clear real-time clock data when the computer is powered off by pressing a multi-function button. The system force reset module is used to detect the force reset signal sent when the multi-function key is pressed when the system crashes, and trigger the computer system to restart.

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