Level voltage generating circuit, data driver and display device

Abstract

A level voltage generating circuit, a data driver and a display device suppress output voltage deviation between data driver ICs and perform non-uniform display. The level voltage generating circuit generates M level voltages based on different N input voltages, where N≧2 and M is an integer greater than N. The level voltage generating circuit includes N differential amplifiers respectively receiving the N input voltages, each having an output end for amplifying and outputting each of the N input voltages, and a ladder resistor having N voltage supply points respectively connected to the output ends of the N differential amplifiers and M voltage output points outputting the M level voltages. The ladder resistor has a first wiring connected to the output end of one of the N differential amplifiers via one of the N voltage supply points, and a second wiring connected between one of the M voltage output points and one of the input pairs of one of the N differential amplifiers.

Description

[0001] This application is a divisional application of application number 202010959311.6, filed on September 14, 2020, entitled "Level Voltage Generation Circuit, Data Driver and Display Device". Technical Field

[0002] This invention relates to a voltage level generation circuit, a data driver, and a display device. Background Technology

[0003] In recent years, active matrix driving has become the preferred driving method for display devices incorporating display elements such as liquid crystal or organic electroluminescence (EL). In active matrix driving display devices, the display panel includes a semiconductor substrate in which pixel units and pixel switches are arranged in a matrix (e.g., in the case of a color 4K panel, 3840 × RGB pixel columns × 2160 pixel rows). The pixel switches are turned on / off via gate signals. When a pixel switch is on, a grayscale voltage signal corresponding to the image data signal is supplied to the pixel unit, thereby controlling the brightness of each pixel unit and performing display. The gate signal is supplied to the pixel switch via a scan line by a gate driver. Conversely, the grayscale voltage signal is supplied to the pixel unit via a data line by a data driver. The gate driver supplies at least a two-value gate signal, while the data driver supplies a multi-value grayscale voltage signal corresponding to the grayscale voltage.

[0004] In active matrix driven display devices, the high precision of the grayscale voltage (hereinafter referred to as output voltage) output from the data driver is required to meet the demands for multi-grayscale, high-resolution, and high-quality images. In particular, in display panels using multiple integrated circuits (ICs) as data drivers, deviations in the output voltage between the data driver ICs can cause display unevenness. For example, the deviation in output voltage between data driver ICs is required to be less than 5mV. This deviation in output voltage between data driver ICs is primarily caused by the voltage accuracy of the level voltage generation circuits within each data driver IC.

[0005] The level voltage generation circuit is integrated into the data driver IC and included within the gamma voltage / grayscale voltage generation circuit. The gamma voltage / grayscale voltage generation circuit includes a level voltage generation circuit that generates multiple gamma voltages based on a gamma reference voltage, and a level voltage generation circuit that generates voltages corresponding to the grayscale voltages based on the multiple gamma voltages. The grayscale voltage signal generated by the gamma voltage / grayscale voltage generation circuit is supplied to the digital / analog (D / A) converter. The D / A converter includes multiple decoders and output amplifiers configured for each output of the data driver IC. The multiple level voltages generated by the gamma voltage / grayscale voltage generation circuit are supplied to the multiple decoders in a shared manner. Each decoder selects one or a predetermined number of level voltages from the multiple level voltages based on the image digital signal input from the external data driver IC and supplies them to the corresponding output amplifier. Each output amplifier outputs a grayscale voltage signal obtained by operationally amplifying the level voltage selected by the decoder.

[0006] In a gamma voltage / grayscale voltage generation circuit, for example, a pair of amplifiers are provided, each receiving a gamma reference voltage. These amplifiers amplify the gamma reference voltage and supply it to both ends of a first trapezoidal resistor. Multiple gamma voltage levels are output from the first trapezoidal resistor, obtained by dividing the gamma reference voltage. Multiple gamma decoders, based on an externally input gamma adjustment digital signal, select some gamma voltages from the output voltage of the first trapezoidal resistor and supply them to multiple amplifiers. These amplifiers amplify the gamma voltages selected by the gamma decoders and supply them to a second trapezoidal resistor. Multiple voltage levels are output from the second trapezoidal resistor, obtained by dividing the gamma voltage, as the voltages corresponding to the grayscale voltages.

[0007] Figure 11A This is a schematic plan view illustrating an example of the supply of a gamma reference voltage or gamma voltage to a first or second trapezoidal resistor in a gamma voltage / grayscale voltage generation circuit. Furthermore, only one end of the trapezoidal resistor is shown here. Additionally, Figure 11B It is along Figure 11A A cross-sectional view of line AA in the diagram.

[0008] The trapezoidal resistor comprises a resistive layer 52, multiple metal wires, and contacts (in...). Figure 11A The resistor layer 52 consists of metal wires m0, m1, and m2, and contacts cn0, cn1, and cn2. The resistor layer 52 is formed, for example, by forming a thin film on a substrate such as a semiconductor substrate or an insulating substrate. Metal wire m0 is connected to the resistor layer 52 via contact cn0. Metal wire m1 is connected to the resistor layer 52 via contact cn1. Metal wire m2 is connected to the resistor layer 52 via contact cn2.

[0009] In a trapezoidal resistor, the resistor layer 52, metal wiring m0, metal wiring m1 and metal wiring m2, and contacts cn0, cn1 and cn2 are arranged such that voltages corresponding to the voltage design values ​​are derived based on the pre-fabricated resistance design values ​​and the dimensions of the sheet resistor of the resistance layer 52. For example, if the voltage design values ​​on the resistor layer 52, which is divided by the resistance design values ​​R0 and R1, are set to Vgs0, Vgs1 and Vgs2, it is expected that by setting contacts cn0, cn1 and cn2 at the voltage division points on the resistor layer 52, voltages Vgs0, Vgs1 and Vgs2 can be derived from metal wiring m0, metal wiring m1 and metal wiring m2.

[0010] Amplifier 51 receives a gamma reference voltage VG0 at its non-inverting input and outputs an output voltage Vout obtained by current amplification of VG0. The output voltage Vout from amplifier 51 is applied to its inverting input and supplied to the boundary (voltage supply point) of the region of resistor R0 in resistive layer 52 via metal wiring m0 and contact cn0. Furthermore, the output voltage of the trapezoidal resistor (i.e., the voltage divider) is derived from metal wiring m0, metal wiring m1, and metal wiring m2. Moreover, if the non-inverting and inverting inputs of amplifier 51 are considered to be at the same voltage, then in the steady state, the output voltage Vout of amplifier 51 is equal to the gamma reference voltage VG0.

[0011] The boundary point of the region of resistor R0 connected to contact cn0 in resistor layer 52 becomes the voltage supply point and voltage output point on resistor layer 52. The output voltage Vout (=VG0) of amplifier 51 is supplied to metal wiring m0, and voltage VG0 is derived from metal wiring m0.

[0012] Amplifier 51 is positioned near one end of the trapezoidal resistor, supplying the output voltage Vout (=VG0) obtained by current amplification of the gamma reference voltage VG0 to the metal wiring m0. Near the other end of the trapezoidal resistor, for example, in a position paired with amplifier 51, an amplifier (not shown) is positioned to output the gamma voltage. A current flows through the resistive layer 52 corresponding to the voltage difference between the gamma voltage and the gamma reference voltage VG0 supplied from amplifier 51. This current also flows through the metal wiring m0 and the contact cn0. Here, when the resistance value of the metal wiring m0 is set to a sufficiently small and negligible value, a voltage difference Vc corresponding to the resistance Rc of the contact cn0 is generated between the gamma reference voltage VG0 applied to the metal wiring m0 and the voltage Vgs0 at the voltage supply and output points on the resistive layer 52. That is, the relationship between the voltage VG0 of the metal wiring m0 and the voltage Vgs0 on the resistive layer 52 is VG0=Vgs0+Vc.

[0013] On the other hand, metal wirings m1 and m2, which serve as the voltage output terminals of the trapezoidal resistors, are connected to the gate portion of the amplifier that forms the grayscale voltage signal output. Therefore, no stable current flows in metal wirings m1 and m2, or in contacts cn1 and cn2. Consequently, voltages Vgs1 and Vgs2 on the resistor layer 52 are directly derived from metal wirings m1 and m2.

[0014] The resistance value between metal wiring m0 and metal wiring m1 is not the designed resistance value R0, but rather the resistance value obtained by adding the resistance value R0 to the resistance Rc of contact cn0. Therefore, the voltage divider output from the trapezoidal resistor produces a relative error between the voltages.

[0015] To eliminate the relative error between such voltage dividers, a multilevel voltage generator with the following configuration is proposed: the voltage supply point that receives the output voltage Vout from the amplifier 51 is separated from the voltage output point of the output voltage Vgs0 on the resistor layer 52 (for example, Patent Document 1).

[0016] In the multi-level voltage generator, for example, a region of resistor Rr is provided on the outer side of the region of resistor R0 in the resistor layer 52 (i.e., on the end side of the trapezoidal resistor), and a metal wiring mA is connected to the outermost part of the region of resistor Rr via a contact cn0a. Furthermore, the output voltage Vout of amplifier 51 is supplied to the resistor layer 52 via the metal wiring mA, while the output voltage of the trapezoidal resistor is derived from the metal wiring mA. At this time, no stable current flows in the resistor layer 52, therefore the voltage supply point of the resistor layer 52 connected to the contact cn0 is equal to the voltage output point of the resistor layer 52 connected to the contact cn0a, becoming voltage Vgs0. According to this configuration, a voltage corresponding to the voltage division ratio of the design resistance value R0 to the design resistance value R1 can be output from the metal wiring mA of the trapezoidal resistor, thus improving the relative error of the voltage division.

[0017] [Existing Technical Documents]

[0018] [Patent Literature]

[0019] [Patent Document 1] Japanese Patent Application Publication No. 2008-146028 Summary of the Invention

[0020] The problem that the invention aims to solve

[0021] According to the multi-level voltage generator described in the prior art, the relative error between the voltage division voltages output from the trapezoidal resistor can be improved. However, a difference still exists between the output voltage Vgs0 from the metal wiring mA and the gamma reference voltage VG0, which is the expected output value, and the voltage Vc corresponding to the resistance Rc of the contact cn0. That is, an absolute error will occur between the output voltage from the trapezoidal resistor and the expected output voltage. In addition, the resistance value of the contact is usually larger than that of the resistive layer.

[0022] Furthermore, if the resistance values ​​of the contacts connecting the resistor layer and the metal wiring between different data driver ICs deviate, the voltage level generated inside the data driver will be incorrect. As a result, the grayscale voltage signal output from the data driver will also be incorrect, leading to uneven display.

[0023] The present invention was made in view of the aforementioned problems, and its object is to provide a display device capable of suppressing output voltage deviations between data driver ICs and thus providing a display without unevenness.

[0024] Technical means to solve the problem

[0025] The voltage level generation circuit of the present invention generates M voltage levels based on N different input voltages, where N is an integer N ≥ 2 and M is an integer M > N. The voltage level generation circuit is characterized by comprising: N differential amplifiers, each receiving N input voltages and each having an output terminal for amplifying and outputting each of the N input voltages; and a trapezoidal resistor having N voltage supply points connected to the output terminals of the N differential amplifiers and M voltage output points for outputting the M voltage levels. The trapezoidal resistor has: a first wiring, connected via one of the N voltage supply points to the output terminal of one of the N differential amplifiers, and a second wiring, connected between one of the M voltage output points and one of the input pairs of the N differential amplifiers.

[0026] The data driver of this invention is connected to a display panel having multiple data lines, supplying grayscale voltage signals corresponding to image data signals to the multiple data lines. The data driver includes: a gamma voltage generation unit, which generates M gamma voltages by dividing N different reference voltages supplied to the data driver, and amplifies the M gamma voltages by an amplifier, where N is an integer N ≥ 2 and M is an integer M > N; and a grayscale voltage output unit, which generates grayscale voltage signals corresponding to the image data signals based on the M gamma voltages output from the gamma voltage generation circuit. The gamma voltage generation circuit includes: N differential amplifiers, each receiving N input voltages and having an output terminal for amplifying and outputting each of the N input voltages; and a trapezoidal resistor having N voltage supply points connected to the output terminals of the N differential amplifiers and M voltage output points for outputting M voltage levels. The trapezoidal resistor has: a first wiring, connected to the output of one of the N differential amplifiers via one of the N voltage supply points, and a second wiring, connected between one of the M voltage output points and one of the input pairs of the N differential amplifiers.

[0027] The display device of the present invention includes: a display panel having multiple data lines, multiple scan lines, pixel switches and pixel units respectively disposed at the intersections of the multiple data lines and the multiple scan lines; a gate driver that supplies a scan signal controlling the pixel switch to be turned on to the multiple scan lines during a selection period corresponding to the pulse width; and a data driver that supplies a grayscale voltage signal corresponding to an image data signal to the multiple data lines. The data driver includes: a gamma voltage generation unit that generates M gamma voltages by dividing the N different reference voltages supplied to the data driver, and amplifies the M gamma voltages by an amplifier, where N is an integer N ≥ 2 and M is an integer M > N; and a grayscale voltage output unit that generates a grayscale voltage signal corresponding to the image data signal based on the M gamma voltages output from the gamma voltage generation circuit. The gamma voltage generation circuit includes: N differential amplifiers, each receiving N input voltages and having an output terminal for amplifying and outputting each of the N input voltages; and a trapezoidal resistor having N voltage supply points connected to the output terminals of the N differential amplifiers and M voltage output points for outputting M voltage levels. The trapezoidal resistor has: a first wiring, connected via one of the N voltage supply points to the output terminal of one of the N differential amplifiers; and a second wiring, connected between one of the M voltage output points and one of the input pairs of the N differential amplifiers.

[0028] The effects of the invention

[0029] The voltage level generation circuit according to the present invention can suppress the output voltage deviation between data driver ICs and perform a display without unevenness. Attached Figure Description

[0030] Figure 1 This is a block diagram illustrating the configuration of the display device of the present invention.

[0031] Figure 2 This is a block diagram illustrating the internal structure of the data driver of the present invention.

[0032] Figure 3 This is a block diagram illustrating the configuration of the grayscale voltage generation unit of the present invention.

[0033] Figure 4A This is a schematic plan view showing the configuration of the voltage level generation circuit of Embodiment 1.

[0034] Figure 4B yes Figure 4A A cross-sectional view of the AA line of the voltage level generation circuit.

[0035] Figure 5 It is the equivalent circuit of the feedback circuit formed at the end of the voltage level generation circuit.

[0036] Figure 6A This is a schematic plan view showing the configuration of the voltage level generation circuit of the comparative example.

[0037] Figure 6B yes Figure 6A A cross-sectional view of the AA line of the voltage level generation circuit.

[0038] Figure 7A This is a schematic plan view showing the configuration of the voltage level generation circuit in Embodiment 2.

[0039] Figure 7B yes Figure 7A A cross-sectional view of the AA line of the voltage level generation circuit.

[0040] Figure 8 It is the equivalent circuit of the feedback circuit in Example 2.

[0041] Figure 9 This is a schematic plan view showing the configuration of the voltage level generation circuit in Embodiment 3.

[0042] Figure 10 This is a schematic plan view showing the configuration of the voltage level generation circuit in Embodiment 4.

[0043] Figure 11A It is a schematic plan view showing the configuration of a voltage level generation circuit.

[0044] Figure 11B yes Figure 11A A cross-sectional view of the AA line of the voltage level generation circuit.

[0045] Explanation of symbols

[0046] 100: Display device

[0047] 11: Display Panel

[0048] 12: Display Controller

[0049] 13A, 13B: Gate drivers

[0050] 14-1~14-p: Data drive

[0051] 141: Data Latching Department

[0052] 142: Control Department

[0053] 20: Gamma voltage / grayscale voltage generation section

[0054] 30-1~30-k: Decoder

[0055] 40-1~40-k: Output amplifier

[0056] 21-1~21-6: Gamma Amplifier

[0057] 22: First trapezoidal resistor

[0058] 23A~23D: Gamma Decoder

[0059] 24: Second trapezoidal resistor

[0060] 25: Resistive layer Detailed Implementation

[0061] Hereinafter, preferred embodiments of the present invention will be described in detail. Furthermore, in the following description of the embodiments and the accompanying drawings, substantially the same or equivalent parts are labeled with the same reference numerals.

[0062] [Example 1]

[0063] Figure 1 This is a block diagram illustrating the configuration of the display device 100 of the present invention. The display device 100 is a liquid crystal display device using an active matrix driving method. The display device 100 includes: a display panel 11, a display controller 12, gate drivers 13A and 13B, data drivers 14-1 to 14-p, and a reference voltage generation unit 15. Furthermore, multiple power supply voltages required by each module are supplied from a power supply IC, but the accompanying drawings would become complicated, so descriptions are omitted.

[0064] The display panel 11 includes multiple pixels arranged in a matrix. 11 ~P nm and pixel switch M 11 ~M nm A semiconductor substrate (n, m: natural numbers greater than 2). The display panel 11 has n gate lines GL1 to GLn and m data lines DL1 to DLm arranged in a manner that intersects them. Pixel section P 11 ~Pixel part P nm and pixel switch M 11 ~Pixel switch M nm It is located at the intersection of gate lines GL1 to GLn and data lines DL1 to DLm.

[0065] Pixel switch M 11 ~Pixel switch M nm The pixel unit is controlled to be turned on or off based on the gate signals Vg1 to Vgn supplied from gate drivers 13A and 13B. 11 ~Pixel part P nm Data drivers 14-1 to 14-p receive grayscale voltage signals Vd1 to Vdm corresponding to the image data. At pixel switch M... 11 ~Pixel switch M nm When activated separately, grayscale voltage signals Vd1 to Vdm are supplied to the pixel unit P. 11 ~Pixel part P nm Each pixel electrode is charged. According to the pixel P... 11 ~Pixel part P nm The pixel portion P is controlled by the grayscale voltage signals Vd1 to Vdm of each pixel electrode. 11 ~Pixel part P nm The brightness is adjusted and displayed.

[0066] When the display device 100 is a liquid crystal display device, each pixel P 11 ~Pixel part P nm It includes a transparent electrode connected to a pixel switch and a data line, and liquid crystal encapsulated between a semiconductor substrate and an opposing substrate. The opposing substrate and the semiconductor substrate are disposed facing each other and have a transparent electrode formed on their entire surface. For the backlight inside the display device, it is supplied to the pixel unit P... 11 ~Pixel part P nm The transmittance of the liquid crystal changes due to the voltage difference between the grayscale voltage signals Vd1 to Vdm and the voltage of the opposing substrate, thereby enabling display.

[0067] The display controller 12 generates a clock signal CLK with a fixed clock pulse period (hereinafter referred to as the clock period). Furthermore, the display controller 12 supplies the image data signal VDS to the data drivers 14-1 to 14-p according to the clock timing of the clock signal CLK. The image data signal VDS is configured as an image data signal serialized for a predetermined number of data lines according to the number of transmission paths.

[0068] In addition, the display controller 12 adds a control signal CS containing various settings to the image data signal VDS. The clock signal CLK is formed, for example, by embedding a clock, and the image data signal VDS, the control signal CS, and the clock signal CLK are supplied as an integrated serial signal to each data driver 14-1 to data driver 14-p to perform display control of each image data VD.

[0069] In addition, the display controller 12 supplies gate timing signals GS to the gate drivers 13A and 13B located at both ends of the display panel 11.

[0070] Gate drivers 13A and 13B supply gate signals Vg1 to Vgn to gate lines GL1 to GLn based on the gate timing signal GS supplied from the display controller 12.

[0071] Data drivers 14-1 to 14-p are provided for a predetermined number of data lines obtained by dividing data lines DL1 to DLm. Each data driver 14-1 to 14-p is formed on a semiconductor IC (Integrated Circuit) chip. For example, when each data driver has 960 outputs and each pixel column of the display panel includes one data line, a 4K panel drives the data lines using 12 data drivers, and an 8K panel drives the data lines using 24 data drivers. Data drivers 14-1 to 14-p receive a serial signal, which integrates the control signal CS, the clock signal CLK, and the image data signal VDS, from the display controller 12 through different transmission paths. When there is a pair (two paths) between the display controller 12 and each data driver, during a data period, the image data VD corresponding to the number of outputs of the data driver and the control signal CS are supplied as serialized differential signals.

[0072] The reference voltage generation unit 15 generates gamma reference voltage VG0 and gamma reference voltage VG5 and supplies them to each data driver 14-1 to data driver 14-p.

[0073] Figure 2This is a block diagram showing the internal structure of data drive 14-1. Furthermore, the other data drives 14-2 to 14-p also have the same structure.

[0074] The data driver 14-1 includes: a data latch unit 141, a control unit 142, a gamma voltage / grayscale voltage generation unit 20, decoders 30-1 to 30-k, and output amplifiers 40-1 to 40-k.

[0075] The control unit 142 receives the serial signal sent from the display controller 12 and serializes it to derive a control signal CS, a clock signal CLK, and an image data signal VDS. Furthermore, the control unit 142 outputs the image data signal VD and the latch clock signal CLKA to the data latch unit 141 based on the control signal CS. Additionally, the control unit 142 supplies a gamma adjustment digital signal GDS, specifying a voltage according to the inverse gamma characteristic of the display panel 11 (hereinafter referred to as gamma voltage), to the gamma voltage / grayscale voltage generation unit 20.

[0076] The data latch unit 141 sequentially imports a series of pixel data PDs contained in the image data signal VDS sent from the control unit 142. At this time, whenever k pixel data PDs corresponding to the grayscale voltage signal supplied by the data driver 14-1 are imported from the pixel data PDs of one horizontal scan line (N), the data latch unit 141 supplies the k pixel data PDs as pixel data P1 to pixel data Pk to the decoder 30-1 to decoder 30-k respectively, in a timing synchronized with the latch clock signal CLKA.

[0077] The gamma voltage / grayscale voltage generation unit 20 generates a gamma voltage according to the inverse gamma characteristic of the display panel 11 based on the input gamma reference voltage VG0 and gamma reference voltage VG5, and the gamma adjustment digital signal GDS output from the control unit 142. It then generates grayscale voltages Vgs0 to Vgs(q-1) that represent the brightness level that can be displayed on the display panel 11 using q grayscale (e.g., 256 grayscale), and supplies them to each decoder 30-1 to decoder 30-k.

[0078] Each decoder 30-1 to decoder 30-k selects at least one gray level voltage from gray level voltages Vgs0 to gray level voltages Vgs(q-1) that corresponds to the brightness level represented by the pixel data PD received by itself, and supplies it to output amplifiers 40-1 to output amplifiers 40-k.

[0079] Each output amplifier 40-1 to output amplifier 40-k is, for example, a voltage follower circuit containing an operational amplifier, whose output terminal is connected to its own inverting input terminal (-).

[0080] Output amplifiers 40-1 to 40-k receive grayscale voltages output from decoders 30-1 to 30-k at their respective non-inverting input terminals (+). They amplify and output the voltages corresponding to the received grayscale voltages at their respective output terminals, thereby generating data signals Vd1 to Vdk corresponding to each grayscale voltage. Data signals Vd1 to Vdk are supplied as pixel drive signals to data lines DL1 to DLk of the display panel 11.

[0081] Figure 3 This is a circuit diagram illustrating an example of the internal structure of the gamma voltage / grayscale voltage generation unit 20. The gamma voltage / grayscale voltage generation unit 20 includes: gamma amplifiers 21-1 to 21-6, a first trapezoidal resistor 22, gamma decoders 23A to 23D, and a second trapezoidal resistor 24.

[0082] Gamma amplifier 21-1 amplifies the current of the externally supplied gamma reference voltage VG0 and supplies it to one end of the first trapezoidal resistor 22. Gamma amplifier 21-2 amplifies the current of the gamma reference voltage VG5 supplied from the reference voltage generation unit 15 and supplies it to the other end of the first trapezoidal resistor 22.

[0083] The first trapezoidal resistor 22 has voltage output terminals located at multiple different positions, and generates multiple output voltage levels with different voltage values ​​obtained by linearly dividing the voltage between the gamma reference voltage VG0 and the gamma reference voltage VG5, for example.

[0084] Gamma decoders 23A, 23B, 23C, and 23D receive the input of the gamma-adjusted digital signal GDS, select gamma voltages VG1 to VG4 from the output voltages of multiple levels of the first trapezoidal resistor 22 based on the gamma-adjusted digital signal GDS, and supply them to the input terminals of gamma amplifiers 21-3 to 21-6.

[0085] Gamma amplifiers 21-3 to 21-6 amplify the current of gamma voltages VG1 to VG4 and supply it to the second trapezoidal resistor 24.

[0086] The second trapezoidal resistor 24 generates multiple output voltage levels with different values ​​obtained by dividing the voltage between the gamma reference voltage VG0, gamma voltages VG1 to VG4, and the gamma reference voltage VG5. These output voltages are then used as grayscale voltages Vgs0 to Vgs(q-1). The second trapezoidal resistor 24 has multiple voltage output terminals located at different positions, and the resistance values ​​between each voltage output terminal are designed based on the inverse gamma characteristic of the display panel 11.

[0087] The grayscale voltages Vgs0 to Vgs(q-1) output from the gamma voltage / grayscale voltage generation unit 20 are supplied to decoders 30-1 to 30-k, which are provided for each output of the data driver. Decoders 30-1 to 30-k select one or more voltages from the grayscale voltages based on digital signals Q1 to Qk and supply them to the input terminals of output amplifiers 40-1 to 40-k.

[0088] That is, the output of the first trapezoidal resistor 22 is supplied to the input terminals of gamma amplifiers 21-3 to 21-6 via the gamma decoder, and the output of the second trapezoidal resistor 24 is supplied to the input terminals of output amplifiers 40-1 to 40-k via the decoder. Here, the input terminals of the amplifiers become capacitive loads, so the stabilizing current does not flow from the outputs of the first and second trapezoidal resistors to the capacitive load.

[0089] In the connection section between each gamma amplifier 21-1 and gamma amplifier 21-2 and the first trapezoidal resistor 22, a level voltage generation circuit is formed to generate gamma voltages of multiple levels. Figure 3 In the diagram, the circuit block located at the connection point between one end of the first trapezoidal resistor 22 and the gamma amplifier 21-1 in the voltage level generation circuit is represented as voltage level generation circuit A1. Furthermore, the same circuit block is also formed at the connection point between the other end of the first trapezoidal resistor 22 and the gamma amplifier 21-2.

[0090] The level voltage generation circuit A1 includes a portion of a gamma amplifier 21-1 and a first trapezoidal resistor 22, and functions as a gamma voltage supply unit. The gamma voltage supply unit supplies the voltage obtained by dividing the gamma reference voltage VG0 and the gamma reference voltage VG5 (i.e., the output voltage of the first trapezoidal resistor 22) to the gamma decoder 23A.

[0091] Figure 4A This is a schematic diagram showing the configuration of the voltage level generation circuit A1. The first trapezoidal resistor 22 is formed, for example, using a thin film, on a substrate (not shown) such as a semiconductor substrate or an insulating substrate. Here, it is connected to the circuit of the gamma amplifier 21-1. Figure 1 The diagram shows a plan view of a portion of the resistor layer 25 that constitutes the first trapezoidal resistor 22.

[0092] The voltage level generation circuit A1 includes a resistive layer 25 formed on a substrate (not shown) using a thin film, metal wiring m0a, metal wiring m0, metal wiring m1 and metal wiring m2 including a metal layer, and contacts cn0a, contact cn0, contact cn1 and contact cn2. An insulating layer is formed between the resistive layer 25 and the metal layer. Metal wiring m0a is connected to the resistive layer 25 via contact cn0a that penetrates the insulating layer. Metal wiring m0 is connected to the resistive layer 25 via contact cn0. Metal wiring m1 is connected to the resistive layer 25 via contact cn1. Metal wiring m2 is connected to the resistive layer 25 via contact cn2.

[0093] Metal wiring m0a is located closer to the end of the resistor layer 25 than other metal wirings (i.e., the position closest to the end). Metal wiring m0 is located at a position close to the end of the resistor layer 25 after metal wiring m0a (i.e., the second position viewed from the end of the resistor layer 25). Metal wiring m1 is located at a position close to the end of the resistor layer 25 after metal wiring m0 (i.e., the third position viewed from the end of the resistor layer 25). Metal wiring m2 is located at a position close to the end of the resistor layer 25 after metal wiring m1 (i.e., the fourth position viewed from the end of the resistor layer 25).

[0094] Figure 4B It is along Figure 4A A cross-sectional view of line AA. The contacts cn0a, cn0, cn1, and cn2 on resistor layer 25 are arranged such that resistor layer 25 is divided into resistor regions Rr, R0, and R1, and the voltages at the boundaries of each resistor region are set to VgsX, Vgs0, Vgs1, and Vgs2, respectively. Furthermore, in Figure 4B The circuit diagram of the gamma amplifier 21-1 is omitted here.

[0095] exist Figure 4A In this configuration, one end of the metal wiring m0a is connected to the voltage output terminal of the gamma amplifier 21-1. The other end of the metal wiring m0 is connected to the inverting input terminal of the gamma amplifier 21-1. Additionally, a gamma reference voltage VG0 is input to the non-inverting input terminal of the gamma amplifier 21-1.

[0096] Figure 4A and Figure 4B The dashed arrows in the diagram schematically indicate the direction of current flowing from the gamma amplifier 21-1 to the resistive layer 25. Furthermore, the portion of the first trapezoidal resistor 22 other than its conductive portion is covered by an insulating layer.

[0097] The boundary point of the resistive region on the resistive layer 25 connected to the contact cn0a is the voltage supply point of the resistive layer 25, and the output voltage Vout of the gamma amplifier 21-1 is applied through the metal wiring m0a and the contact cn0a.

[0098] The boundary points of the resistive region on the resistive layer 25, which is connected to contacts cn0, cn1 and cn2, are the voltage output points of the voltage obtained by dividing the gamma reference voltage VG0 and gamma reference voltage VG5 through the first trapezoidal resistor 22.

[0099] The voltage Vgs0, which is the output voltage of the first trapezoidal resistor 22, is derived from the voltage output point of the resistor layer 25 connected to the contact cn0, and is output through the contact cn0 and the metal wiring m0. That is, in the voltage level generation circuit A1 of this embodiment, the voltage supply point and the voltage output point are separated.

[0100] The positional relationship between the resistive layer 25 and the metal wirings m0a, m0, m1, and m2 is based on the design resistance value of the first trapezoidal resistor 22 and the sheet resistance of the resistive layer 25. For example, in Figure 4B In this structure, a certain current flows through resistors Rr, R0, and R1. Therefore, the voltages VgsX, Vgs0, Vgs1, and Vgs2 on resistor layer 25 are obtained by voltage division using the design values ​​of resistors Rr, R0, and R1. Furthermore, no stable current flows into the metal wiring connected to each voltage output point on resistor layer 25, so the voltage at each output point can be directly derived regardless of the contact resistance. That is, voltage Vgs0 is output from metal wiring m0, voltage Vgs1 from metal wiring m1, and voltage Vgs2 from metal wiring m2. Moreover, the wiring resistance of each of metal wirings m0a, m0, m1, and m2 is sufficiently small compared to the resistance value of resistor layer 25.

[0101] In the resistor layer 25 of this embodiment, a region with a resistance design value Rr (hereinafter referred to as the resistance Rr region) is provided further outward than the region with the resistance design value R0 (hereinafter referred to as the resistance R0 region). Furthermore, the metal wiring m0a and the contact cn0a are provided at the outermost boundary of the resistance Rr region. On the other hand, the metal wiring m0 and the contact cn0 are provided at the boundary between the resistance R0 region and the resistance Rr region.

[0102] In addition, such as Figure 4AAs shown, metal wiring m0 is connected to the inverting input terminal of gamma amplifier 21-1, and the voltage Vgs0 output from metal wiring m0 is fed back to gamma amplifier 21-1. Gamma amplifier 21-1, contact cn0a, metal wiring m0a, metal wiring m0, and the resistance Rr region between the voltage supply point and voltage output point of resistor layer 25 constitute feedback circuit 26. Figure 4A (The circuit block shown is surrounded by dashed lines). Furthermore, here, the inverting input of the gamma amplifier 21-1 is also a capacitive load, so no stable current flows through the contact cn0 and the metal wiring m0. Therefore, the voltage Vgs0 on the resistive layer 25 can be directly derived from the metal wiring m0.

[0103] Figure 5 This is a circuit diagram showing the configuration of feedback circuit 26 as an equivalent circuit including contact resistors. Feedback circuit 26 includes: a gamma amplifier 21-1; resistors Rr and R0 of the resistive region of resistive layer 25; and resistors Rc of contacts cn0 and cn0a. Resistors Rc and Rr of contact cn0a are connected between the voltage output terminal (Vout) of gamma amplifier 21-1 and the voltage output point (Vgs0) of resistive layer 25 via a voltage supply point (VgsX). Additionally, resistor Rc of contact cn0 is connected between the inverting input terminal of gamma amplifier 21-1 and the voltage output point (Vgs0) of resistive layer 25. Furthermore, the inverting input terminal of gamma amplifier 21-1 is also connected to a metal wiring m0, which serves as the output terminal of level voltage generation circuit A1. Figure 5 The dashed arrows in the diagram schematically indicate the direction of the stable current flowing from the output of the gamma amplifier 21-1 to the resistor layer 25.

[0104] Next, the function of the voltage level generation circuit A1 in this embodiment will be explained.

[0105] like Figure 4A As shown, the differential input gamma reference voltage VG0 of gamma amplifier 21-1 and the output voltage Vgs0 from metal wiring m0 are used. Additionally, the output voltage Vout is output from the voltage output terminal of gamma amplifier 21-1 and supplied to metal wiring m0a.

[0106] Gamma amplifier 21-2 is connected to the end of resistor layer 25 opposite to the end to which gamma amplifier 21-1 is connected (not shown). Figure 3 A steady current flows through the resistive layer 25, corresponding to the voltage difference between the gamma reference voltage VG0 and the gamma reference voltage VG5, and the total resistance of the resistive layer 25.

[0107] The current flowing in the resistive layer 25 also flows in the metal wiring mA and the contact CN0A. When the resistance of the metal wiring mA is set to be sufficiently small and therefore negligible, a voltage difference Vc is generated between the output voltage Vout of the gamma amplifier 21-1 supplied to the metal wiring mA and the voltage VgsX on the resistive layer 25, caused by the resistance Rc of the contact CN0A. Additionally, a voltage difference Vr is generated between the voltage VgsX and the voltage Vout, caused by the resistance Rr of the resistive layer 25.

[0108] The voltage Vgs0 derived from metal wiring m0 is fed back to the differential input of gamma amplifier 21-1, thus becoming an imaginary short circuit and equal to the gamma reference voltage VG0. Therefore, regardless of the resistance value of contact cn0's resistor Rc, the gamma reference voltage VG0 (=Vgs0) is output from the level voltage generation circuit A1, and the voltage Vgs0 at the voltage output point at the boundary between resistors R0 and Rr of resistor layer 25 is also equal to the gamma reference voltage VG0. On the other hand, no stable current flows in metal wiring m0, metal wiring m1, and metal wiring m2, and in contacts cn0, cn1, and cn2; therefore, voltages Vgs0, Vgs1, and Vgs2 on the resistor layer are derived from metal wiring m0, metal wiring m1, and metal wiring m2.

[0109] Therefore, the level voltage generation circuit A1 can accurately derive a voltage corresponding to the designed resistance value of the resistor layer 25 relative to the gamma reference voltage VG0 without being affected by the contact resistance. Furthermore, the output voltage Vout of the gamma amplifier 21-1 becomes Vout = Vgs0 + Vr + Vc = VG0 + Vr + Vc.

[0110] Furthermore, at the end opposite to the resistive layer 25 (i.e., connected to...) Figure 3 The end of the gamma amplifier 21-2 shown also has a circuit block with the same configuration, which outputs a voltage Vgs(q-1) corresponding to the gamma reference voltage VG5.

[0111] Figure 6A The diagram shows a comparative example of a voltage level generation circuit, which is different from the voltage level circuit A1 in this embodiment. It includes a gamma amplifier 21-1 that feeds back the output voltage Vout to the inverting input terminal. Figure 6B yes Figure 6A A cross-sectional view of line AA. (and) Figure 4B Similarly, in Figure 6BIn the resistor layer 25, contacts cn0a, cn0, cn1, and cn2 are arranged to divide the resistor layer 25 into resistor regions Rr, R0, and R1, respectively, and the voltages at the boundaries of each resistor region are set to VgsX, Vgs0, Vgs1, and Vgs2, respectively. Furthermore, in... Figure 6B The circuit diagram of the gamma amplifier 21-1 is also omitted in the text.

[0112] In the comparative example's voltage generation circuit, the output voltage Vout of the gamma amplifier 21-1 is supplied to metal wiring m0. Voltages VgsX, Vgs1, and Vgs2 are output from metal wirings m0a, m1, and m2. Since no stable current flows into metal wirings m0a, m1, and m2 at each voltage output point on the resistor layer 25, the voltages at each voltage output point on the resistor layer 25 can be directly derived. Furthermore, no stable current flows through the resistor Rr, therefore Vgs0 = VgsX, and thus voltage Vgs0 can be derived from metal wiring m0a. This is due to the configuration that separates the voltage supply point (Vgs0) from the voltage output point (VgsX).

[0113] However, in the comparative example's voltage level generation circuit, an output voltage Vout (=VG0) is applied to the metal wiring m0, and a stabilizing current flows through the contact cn0 to resistors R0 and R1 of the resistor layer 25. Therefore, a voltage difference Vc is generated between the voltage Vgs0 and the output voltage VG0, corresponding to the resistance Rc of the contact cn0. That is, Vout=VG0=Vgs0+Vc. Therefore, the voltage design value using the resistance ratio for voltage division produces an absolute error in the voltage difference of the contact resistance Rc relative to the gamma reference voltage VG0. This error is caused by the resistance Rc of the contact cn0; therefore, when the value of the contact resistance Rc deviates between different data driver ICs, the grayscale voltage signal between the data driver ICs also deviates, resulting in uneven display.

[0114] In contrast, the level voltage generation circuit A1 according to this embodiment can eliminate the influence of resistance deviation between the contact portions of the connecting resistor layer 25 and each metal wiring from the output voltage of the first trapezoidal resistor 22. Therefore, a high-precision trapezoidal resistor output voltage (level voltage) with sufficiently small absolute error from the design value, not only in terms of the relative error between output voltages, can be generated.

[0115] Furthermore, in the configuration of the voltage generation circuit A1 in this embodiment, the current flowing through the resistive layer 25 enters from the voltage supply point (VgsX) located outside the voltage output point group at the connection points between the resistive layer 25 and each of the metal wirings m0 to m2. Therefore, at each voltage output point on the resistive layer 25, the current flows with a uniform current density. Thus, a voltage is output from a region of uniform current density, thereby allowing for the extraction of a high-precision voltage from each voltage output point.

[0116] Furthermore, the output voltage Vout of the gamma amplifier 21-1 in this embodiment is obtained by adding the voltage Vgs0 (=VG0) to the voltage difference Vr generated by the resistance Rr in the region of the resistance value Rr of the resistor layer 25 and the voltage difference Vc generated by the resistance Rc of the contact cn0a (i.e., VG0+Vr+Vc). The setting range of the gamma reference voltage VG0 is narrower than the range of the power supply voltage (Vr+Vc).

[0117] As described above, the voltage level generation circuit A1 according to this embodiment can output a high-precision voltage level with sufficiently small relative error between output voltages and absolute error from the design value, regardless of the resistance deviation of the contacts.

[0118] [Example 2]

[0119] Next, Embodiment 2 of the present invention will be described. The display device in this embodiment differs from that in Embodiment 1 in the configuration of the level voltage generation circuit A1.

[0120] Figure 7A This is a schematic diagram illustrating the configuration of the voltage level generation circuit A1 in this embodiment. Compared to Embodiment 1... Figure 4A Similarly, here, the circuit of gamma amplifier 21-1... Figure 1 The image shown is a plan view of a portion of the resistor layer 25 constituting the first trapezoidal resistor 22, viewed from above. Additionally, Figure 7B It is along Figure 7A A cross-sectional view of line AA. (and) Figure 4A Similarly, the contacts cn0a, cn0, cn1, and cn2 on the resistive layer 25 are arranged such that the resistive layer 25 is divided into resistive regions Rr, R0, and R1, and the voltages at the boundaries of each resistive region are set to VgsX, Vgs0, Vgs1, and Vgs2, respectively. Furthermore, in Figure 7B The circuit diagram of the gamma amplifier 21-1 is omitted here.

[0121] The voltage level generation circuit A1 in this embodiment differs from the voltage level generation circuit A1 in Embodiment 1 in terms of the connection relationship between the metal wiring m0a and the gamma amplifier 21-1. Specifically, in the voltage level generation circuit A1 of this embodiment, the metal wiring m0a is connected to the inverting input terminal of the gamma amplifier 21-1, and the metal wiring m0 is connected to the voltage output terminal of the gamma amplifier 21-1. That is, compared with the voltage level generation circuit A1 of Embodiment 1, the position of the voltage Vgs0 on the resistive layer 25 becomes the voltage supply point, and the position of the voltage VgsX becomes the voltage output point.

[0122] The output voltage Vout of the gamma amplifier 21-1 is supplied via metal wiring m0 and contact cn0 to the voltage supply point (Vgs0) located at the boundary between the resistor Rr region and the resistor R0 region of the resistor layer 25. Additionally, a voltage is derived from the voltage output point (VgsX) located at the outermost boundary of the resistor Rr region of the resistor layer 25 connected to contact cn0a. At this time, no stable current flows in the resistor Rr of the resistor layer 25, the contact cn0a, and the metal wiring m0a. Therefore, VgsX = Vgs0, and voltage Vgs0 is output from the metal wiring m0a. Similarly, voltages Vgs1 and Vgs2 are output from the metal wiring m1 and metal wiring m2, respectively, at the voltage output points of the resistor layer 25 connected to contacts cn1 and cn2.

[0123] In the voltage level generation circuit A1 of this embodiment, one of the voltage output points (VgsX) on the resistor layer 25 is positioned further outward than the voltage supply point (Vgs0). Furthermore, the voltage VgsX (=Vgs0) output from the metal wiring mA is fed back to the gamma amplifier 21-1. The gamma amplifier 21-1, contact cn0, metal wiring mA, and the resistor Rr region of the resistor layer 25 constitute the feedback circuit 27. Figure 7A The circuit block shown is surrounded by dashed lines.

[0124] Figure 8 This is a circuit diagram showing the configuration of feedback circuit 27 as an equivalent circuit including contact resistors. Feedback circuit 27 includes: a gamma amplifier 21-1; resistors Rc for contacts cn0 and cn0a; and resistors Rr and R0 for resistor layer 25. Resistor Rc for contact cn0 is connected between the voltage output terminal (Vout) of gamma amplifier 21-1 and the voltage supply point (Vgs0) of resistor layer 25. Additionally, resistors Rc and Rr for contact cn0a are connected via voltage output point (VgsX) between the inverting input terminal of gamma amplifier 21-1 and the voltage supply point (Vgs0) of resistor layer 25. Furthermore, the inverting input terminal of gamma amplifier 21-1 is also connected to metal wiring mA, which serves as the output terminal of level voltage generation circuit A1. Figure 8 The dashed arrows in the diagram schematically indicate the direction of the stable current flowing from the output of the gamma amplifier 21-1 to the resistor layer 25.

[0125] Next, the function of the voltage level generation circuit A1 in this embodiment will be explained.

[0126] like Figure 7A As shown, the differential input gamma reference voltage VG0 of gamma amplifier 21-1 and the output voltage VgsX from metal wiring m0a are used. Additionally, the output voltage Vout is output from the voltage output terminal of gamma amplifier 21-1 and supplied to metal wiring m0.

[0127] Similar to Example 1, a steady current flows in the resistive layer 25, corresponding to the voltage difference between the gamma reference voltage VG0 and the gamma reference voltage VG5, and the total resistance of the resistive layer 25. Additionally, the steady current flowing in the resistive layer 25 also flows in the metal wiring m0 and the contact cn0. When the resistance of the metal wiring m0 is sufficiently small and therefore negligible, a voltage difference Vc caused by the contact cn0 is generated between the output voltage Vout of the gamma amplifier 21-1 supplied to the metal wiring m0 and the voltage Vgs0 on the resistive layer 25. On the other hand, no steady current flows in the metal wiring m0a and the contact cn0a, the metal wiring m1 and the contact cn1, and the metal wiring m2 and the contact cn2; therefore, voltages VgsX, Vgs1, and Vgs2 at the voltage output points on the resistive layer are derived from the metal wiring m0a, the metal wiring m1, and the metal wiring m2. In addition, there is no stable current flowing in the resistor Rr of the resistor layer 25, so the voltage VgsX at the voltage output point is equal to the voltage Vgs0 at the voltage supply point.

[0128] The voltage VgsX derived from the metal wiring mA is fed back to the differential input of the gamma amplifier 21-1, thus becoming a hypothetical short circuit and equal to the gamma reference voltage VG0. Since VgsX is equal to Vgs0, Vgs0 is also equal to the gamma reference voltage VG0. Therefore, regardless of the resistance value of the contact cn0's resistor Rc, the gamma reference voltage VG0 is output from the level voltage generation circuit A1 as the voltage Vgs0 at the voltage supply point of the resistor layer 25.

[0129] Furthermore, if at the end opposite to the resistive layer 25 (i.e., connected to...) Figure 3 If a circuit block with the same configuration for generating a level voltage is also provided at the end of the gamma amplifier 21-2 shown, a voltage Vgs(q-1) equal to the gamma reference voltage VG5 can be supplied to the resistor layer 25.

[0130] According to the level voltage generation circuit A1 of this embodiment, the influence of resistance deviation between the contact portions of the connecting resistor layer 25 and each metal wiring can be eliminated from the output voltage of the first trapezoidal resistor 22. Therefore, a high-precision trapezoidal resistor output voltage (level voltage) with sufficiently small absolute error from the design value, not only in terms of the relative error between output voltages, can be generated.

[0131] Furthermore, in the configuration of the voltage level generation circuit A1 in this embodiment, near the voltage supply point of the voltage Vgs0 on the resistor layer 25, a stable current flows from the contact cn0 into the resistor layer 25. Therefore, compared with Embodiment 1, the current density becomes uneven, resulting in a slight decrease in voltage accuracy at times. However, the output voltage Vout of the gamma amplifier 21-1 is the voltage obtained by adding the voltage Vgs0 (=VG0) to the voltage difference Vc generated by the resistance Rc of the contact cn0a (i.e., VG0+Vc). Therefore, the setting range of the gamma reference voltage VG0 is narrower than the range of the power supply voltage, and the voltage difference Vc is wider than the setting range of the gamma reference voltage VG0 in Embodiment 1.

[0132] As described above, the voltage level generation circuit A1 according to this embodiment can output a high-precision voltage level with sufficiently small relative error and absolute error from the design value, regardless of the deviation of the contact resistance.

[0133] [Example 3]

[0134] Next, Embodiment 3 of the present invention will be described. Furthermore, in the description of this embodiment, the output voltage of the second trapezoidal resistor 24 (that is, the voltage obtained by dividing the output voltages of the gamma reference voltage VG0, the gamma reference voltage VG5, and the output voltages of the gamma amplifiers 21-3 to 21-6 using the second trapezoidal resistor 24) is collectively referred to as "level voltage".

[0135] A level voltage generation circuit is formed at the connection points of each gamma amplifier 21-3, gamma amplifier 21-4, gamma amplifier 21-5, and gamma amplifier 21-6 with the second trapezoidal resistor 24. Figure 3 In the diagram, the circuit block located at the connection between the second trapezoidal resistor 24 and the gamma amplifier 21-3 in the voltage level generation circuit is represented as voltage level generation circuit A2. Furthermore, the same circuit block is also formed at the connection between the second trapezoidal resistor 23 and each of the gamma amplifiers 21-4, 21-5 and 21-6.

[0136] The level voltage generation circuit A2 includes a portion of the gamma amplifier 21-3 and the second trapezoidal resistor 24, and functions as a grayscale voltage supply unit. The grayscale voltage supply unit supplies the voltage obtained by dividing the gamma voltage VG1 and the gamma voltage VG2 (i.e., the output voltage of the second trapezoidal resistor 24) to the decoders 30-1 to 30-k.

[0137] Figure 9 This is a schematic diagram showing the configuration of the voltage level generation circuit A2. The second trapezoidal resistor 24 is formed, for example, using a thin film on a substrate such as a semiconductor substrate or an insulating substrate (not shown), and here, it is connected to the circuit of the gamma amplifier 21-3. Figure 1 The diagram shows a plan view of a portion of the resistor layer 25 that constitutes the second trapezoidal resistor 24.

[0138] The voltage level generation circuit A2 includes a resistive layer 25 formed on a substrate (not shown) using a thin film, metal wirings m0c, m0, m1, m2, and mz containing metal layers, and contacts cn0c, cn0, cn1, cn2, and cnz. The resistive layer 25 is divided into regions with a designed resistance value Rz, a designed resistance value R0, and a designed resistance value R1 (hereinafter referred to as the Rz region, R0 region, and R1 region), with metal wirings connected to each region near the boundaries via contacts. Furthermore, the resistances of each of the metal wirings mz, m0, m1, and m2 are sufficiently small compared to the resistance value of the resistive layer 25.

[0139] Specifically, metal wire m0 is connected to resistor layer 25 via contact cn0, which is located at the boundary between resistor region Rz and resistor region R0. Metal wire m1 is connected to resistor layer 25 via contact cn1, which is located at the boundary between resistor region R0 and resistor region R1. Metal wire m2 is connected to resistor layer 25 via contact cn2, which is located at the boundary between resistor region R1 and its adjacent resistor region (not shown). Metal wire mz is connected to resistor layer 25 via contact cnz, which is located at the boundary between resistor region Rz and its adjacent resistor region (not shown).

[0140] Furthermore, at the boundary between the resistance Rz region and the resistance R0 region of the resistance layer 25, a protrusion is formed that includes a region containing the designed resistance Rr (hereinafter referred to as the resistance Rr region). A contact cn0c is provided on the protrusion, and the metal wiring m0c is connected to the resistance layer 25 via the contact cn0c. The metal wiring m0c and the metal wiring m0 are separated within the same layer.

[0141] The contacts cnz, cn0, cn1 and cn2 on the resistor layer 25 are arranged in such a way that the resistor layer 25 is divided into resistor regions Rz, R0 and R1, and the voltages at the boundaries of each resistor region are set as Vgsz, Vgs0, Vgs1 and Vgs2.

[0142] The protrusions at the upper boundary of resistors Rz and R0 connected to contact cn0c on resistor layer 25 serve as voltage supply points for resistor layer 25, and the output voltage Vout of gamma amplifier 21-3 is supplied to resistor layer 25 via metal wiring m0c and contact cn0c. The boundary points of the resistive regions on resistor layer 25 connected to contacts cnz, cn0, cn1, and cn2 serve as voltage output points for the voltage obtained by voltage division of the second trapezoidal resistor 24. The voltage Vgs0, which is the output voltage of the second trapezoidal resistor 24, is output via contact cn0 and metal wiring m0. That is, in the voltage level generation circuit A2 of this embodiment, the voltage supply point and the voltage output point are separated.

[0143] Additionally, metal wiring m0 is connected to the inverting input of gamma amplifier 21-3, and the voltage Vgs0 output from metal wiring m0 is fed back to gamma amplifier 21-3. Gamma amplifier 21-3, contact cn0, metal wiring m0c, the resistor Rr region of resistor layer 25, and metal wiring m0c constitute the feedback circuit.

[0144] In the voltage level generation circuit A2 of this embodiment, the voltage supply point of the gamma voltage VG1 of the resistor layer 25 and the voltage output point of the voltage Vgs0 are separated and respectively disposed in the middle part of the resistor layer 25 of the voltage level generation circuit A2 (for example, near the boundary point between the resistor Rz region and the resistor R0 region). In addition, the voltage supply point of the gamma voltage VG1 of the resistor layer 25 is disposed outside the path of the stable current flowing between the resistor Rz region, the resistor R0 region and the resistor R1 region (i.e., the protrusion). In addition, the voltage output points of the voltages Vgsz, Vgs0, Vgs1 and Vgs2, which are the output voltages of the second trapezoidal resistor 24, are disposed on the path of the stable current flowing between the resistor Rz region, the resistor R0 region and the resistor R1 region.

[0145] Next, the function of the voltage level generation circuit A2 in this embodiment will be explained.

[0146] like Figure 9 As shown, the differential input gamma voltage VG1 of gamma amplifier 21-3 and the output voltage from metal wiring m0 are represented. Additionally, the output voltage Vout is output from the voltage output terminal of gamma amplifier 21-3 and supplied to metal wiring m0c.

[0147] At this time, a current flows in the resistive layer 25 corresponding to the voltage difference between the gamma reference voltage VG0, the gamma reference voltage VG5, and the gamma voltage VG1 supplied to the two ends of the second trapezoidal resistor 24, and the resistance values ​​between each voltage supply point of the resistive layer 25. Additionally, when the stable current flowing in the resistor Rz region differs from the stable current flowing in the resistor R0 region, the stable current also flows through the metal wiring m0c, the contact cn0c, and the resistance Rr region of the protrusion. Here, when the resistance value of the metal wiring m0c is set to be sufficiently small and therefore negligible, a voltage difference (Vc+Vr) is generated between the output voltage Vout of the gamma amplifier 21-3 supplied to the metal wiring m0c and the voltage Vgs0 on the resistive layer 25, caused by the resistance Rc of the contact cn0c and the resistance Rr of the protrusion. On the other hand, since there is no stable current flowing from the resistive layer 25 into the metal wirings mz, m0, m1 and m2, as well as the contacts cnz, cn0, cn1 and cn2, the voltages Vgsz, Vgs0, Vgs1 and Vgs2 on the resistive layer are directly derived from the metal wirings mz, m0, m1 and m2.

[0148] The voltage Vgs0 derived from the metal wiring m0 is fed back to the differential input of the gamma amplifier 21-3, thus becoming a hypothetical short circuit and equal to the gamma voltage VG1. Therefore, the level voltage generation circuit A2 can, with high precision, derive a voltage corresponding to the designed resistance value of the resistor layer 25, independent of the resistance values ​​of the protrusion Rr of the resistor layer 25 and the contact cn0c Rc, relative to the gamma voltage VG1.

[0149] According to the level voltage generation circuit A2 of this embodiment, the influence of resistance deviation between the contact portions of the connecting resistor layer 25 and each metal wiring can be eliminated from the output voltage of the second trapezoidal resistor 24. Therefore, a high-precision trapezoidal resistor output voltage (level voltage) with sufficiently small absolute error from the design value, not only in terms of the relative error between output voltages, can be generated.

[0150] Furthermore, the output voltage Vout of the gamma amplifier 21-3 is the voltage obtained by adding the voltage Vgs0 (=VG1) to the voltage difference generated by the resistance Rr region of the protrusion and the voltage difference Vr generated by the resistance Rc of the contact cn0 (i.e., VG1+Vr+Vc).

[0151] As described above, the voltage level generation circuit A2 according to this embodiment can output a high-precision voltage level with sufficiently small relative error between output voltages and absolute error from the design value, regardless of the resistance deviation of the contacts.

[0152] [Example 4]

[0153] Next, Embodiment 4 of the present invention will be described. The display device in this embodiment differs from that in Embodiment 3 in the configuration of the level voltage generation circuit A2.

[0154] Figure 10 This is a schematic diagram illustrating the configuration of the voltage level generation circuit A2 in this embodiment. Here, it is related to the circuit of the gamma amplifier 21-3. Figure 1 The diagram shows a plan view of a portion of the resistor layer 25 that constitutes the second trapezoidal resistor 24.

[0155] The voltage level generation circuit A2 in this embodiment differs from the voltage level generation circuit A2 in Embodiment 3 in the connection relationship between the metal wiring m0c and the metal wiring m0 to the gamma amplifier 21-3. Specifically, in the voltage level generation circuit A2 of this embodiment, the metal wiring m0c is connected to the inverting input terminal of the gamma amplifier 21-1, and the metal wiring m0 is connected to the voltage output terminal of the gamma amplifier 21-1. That is, compared with the voltage level generation circuit A2 of Embodiment 3, the positions of the voltage supply point from the output voltage Vout of the gamma amplifier 21-3 to the resistor layer 25 and the voltage output point from the resistor layer 25 are swapped.

[0156] and Figure 9 Similarly, the contacts cnz, cn0, cn1, and cn2 on the resistor layer 25 are arranged to divide the resistor layer 25 into resistor regions Rz, R0, and R1, and the voltages at the boundaries of each resistor region are set as Vgsz, Vgs0, Vgs1, and Vgs2, respectively. The output voltage Vout of the gamma amplifier 21-1 is supplied via the metal wiring m0 and the contact cn0 to the voltage supply point (Vgs0) located at the boundary between the resistor Rz region and the resistor R0 region of the resistor layer 25.

[0157] A voltage output point Vgs1 exists at the boundary between the resistor region R0 and the resistor region R1, and is connected to a metal wire m1 via contact cn1. A voltage output point Vgs2 exists at the boundary between the resistor region R1 and its adjacent resistor region (not shown), and is connected to a metal wire m2 via contact cn2. A voltage output point Vgsz exists at the boundary between the resistor region Rz and its adjacent resistor region (not shown), and is connected to a metal wire mz via contact cnz.

[0158] Furthermore, a protrusion containing a resistance Rr region is formed at the boundary between the resistance Rz region and the resistance R0 region of the resistance layer 25. A contact cn0c is provided on the protrusion, and a metal wire m0c is connected to the resistance layer 25 via the contact cnc. The metal wire m0c and the metal wire m0 are separated within the same layer.

[0159] The metal wiring mz outputs voltage Vgsz, the metal wiring m1 outputs voltage Vgs1, and the metal wiring m2 outputs voltage Vgs2. Furthermore, the resistance of each of the metal wirings mz, m0, m1, and m2 is sufficiently small compared to the resistance value of the resistive layer 25.

[0160] The output voltage Vout of the gamma amplifier 21-3 is supplied to the voltage supply point (Vgs0) of the resistor layer 25 via the metal wiring m0 and the contact cn0. The boundary points of the resistive region on the resistor layer 25, connected to contacts cnz, cn0c, cn1, and cn2, are the voltage output points for the voltage obtained by voltage division of the second trapezoidal resistor 24. The voltage of the protrusion of the resistor layer 25, which is the output voltage of the second trapezoidal resistor 24, is output via the contact cn0c and the metal wiring m0c. That is, in the voltage level generation circuit A2 of this embodiment, the voltage supply point and the voltage output point are separated.

[0161] Additionally, the metal wiring m0c is connected to the inverting input of the gamma amplifier 21-3, and the voltage output from the metal wiring m0c is fed back to the gamma amplifier 21-3. The gamma amplifier 21-3, the metal wiring m0, the contact cn0, the resistor Rr region of the resistor layer 25, and the metal wiring m0c constitute the feedback circuit.

[0162] Next, the function of the voltage level generation circuit A2 in this embodiment will be explained.

[0163] like Figure 10 As shown, the differential input gamma voltage VG1 of gamma amplifier 21-3 and the output voltage from metal wiring m0c are represented. Additionally, the output voltage Vout is output from the voltage output terminal of gamma amplifier 21-3 and supplied to metal wiring m0.

[0164] At this time, a stable current flows in the resistive layer 25 corresponding to the voltage difference between the gamma reference voltage VG0, the gamma reference voltage VG5, and the gamma voltage VG1 supplied to the two ends of the second trapezoidal resistor 24, and the resistance value between each voltage supply point of the resistive layer 25. Additionally, when the stable current flowing in the resistor Rz region differs from the stable current flowing in the resistor R0 region, current also flows in the metal wiring m0 and the contact cn0. Here, when the resistance value of the metal wiring m0 is assumed to be sufficiently small and therefore negligible, a voltage difference Vc caused by the resistance Rc of the contact cn0 is generated between the output voltage Vout of the gamma amplifier 21-3 supplied to the metal wiring m0 and the voltage Vgs0 on the resistive layer 25. On the other hand, there is no stable current flowing in the metal wiring mz, metal wiring m0c, metal wiring m1 and metal wiring m2, contact cnz, contact cn0c, contact cn1, contact cn2 and the resistance region Rr of the protrusion. Therefore, the voltage at the connection point between the protrusion of the resistance layer 25 and the contact cn0c is equal to the voltage Vgs0. Thus, the voltages Vgsz, Vgs0, Vgs1 and Vgs2 on the resistance layer are directly derived from the metal wiring mz, metal wiring m0c, metal wiring m1 and metal wiring m2.

[0165] The voltage Vgs0 derived from the metal wiring m0c is fed back to the differential input of the gamma amplifier 21-3, thus becoming a hypothetical short circuit and equal to the gamma voltage VG1. Therefore, the level voltage generation circuit A2 can, with high precision, derive a voltage corresponding to the designed resistance value of the resistor layer 25, independent of the resistance values ​​of the protrusions Rr of the resistor layer 25 and the resistance Rc of the contacts cn0 and cn0c, relative to the gamma voltage VG1.

[0166] Furthermore, the output voltage Vout of the gamma amplifier 21-3 is the voltage obtained by adding the voltage Vgs0 (=VG1) to the voltage difference Vc generated by the resistance Rc of the contact cn0 (i.e., VG1+Vc).

[0167] As described above, according to the level voltage generation circuit A2 of this embodiment, by eliminating the influence of the resistance deviation between the contact portions of the connecting resistor layer 25 and each metal wiring, a high-precision level voltage (output voltage of the trapezoidal resistor) with sufficiently small relative error between the output voltages and absolute error with the design value can be output by the output voltage of the second trapezoidal resistor 24.

[0168] Furthermore, the present invention is not limited to the described embodiments. For example, in Embodiments 1 and 2, the connection portions between each gamma amplifier 21-1 and gamma amplifier 21-2 and the first trapezoidal resistor 22 are formed as follows: Figure 4A or Figure 4BAn example of a circuit block as shown (i.e., the level voltage generation circuit A1) has been described. However, unlike this, a circuit block with the same configuration can also be formed at the connection portion between each gamma amplifier 21-1 and gamma amplifier 21-2 and the second trapezoidal resistor 24. That is, as long as the level voltage generation circuit with a circuit block configured as in Embodiments 1 and 2 forms a circuit block as described above between the first trapezoidal resistor 22 and each gamma amplifier 21-1 and gamma amplifier 21-2, or between the second trapezoidal resistor 24 and each gamma amplifier 21-1 and gamma amplifier 21-2, the circuit block can be formed as described above.

Claims

1. A voltage level generation circuit, which generates M voltage levels based on N different input voltages, where N is an integer N ≥ 2 and M is an integer M > N, characterized in that the voltage level generation circuit comprises: N differential amplifiers, each receiving one of the N input voltages, and each having an output terminal, are used to amplify and output each of the N input voltages; as well as The trapezoidal resistor has N voltage supply points respectively connected to the output terminals of the N differential amplifiers, and M voltage output points for outputting the M voltage levels. The trapezoidal resistor described herein has: The first wiring connects to the output of one of the N differential amplifiers via one of the N voltage supply points. The second wiring is connected between one of the M voltage output points and one of the input pairs of the N differential amplifiers. The M voltage output points are connected to the capacitive load on the input side of the amplifier, which forms the load. One of the input pairs of one of the N differential amplifiers is connected to one of the M voltage output points, wherein the voltage output point outputs a voltage level that is closest to the voltage of the one of the N voltage supply points. The other input pair of one of the N differential amplifiers is an input voltage that accepts one of the N input voltages, and the voltage supply point and the voltage output point are located at different positions on the trapezoidal resistor.

2. The level voltage generation circuit according to claim 1, characterized in that, The trapezoidal resistor has a wiring group that includes the second wiring. The first wiring is configured to be adjacent to the second wiring.

3. A data driver, connected to a display panel having multiple data lines, supplies a grayscale voltage signal corresponding to an image data signal to the multiple data lines, characterized in that the data driver comprises: The gamma voltage generation circuit generates M gamma voltages by dividing the N different reference voltages supplied to the data driver, and amplifies the M gamma voltages by an amplifier, where N is an integer N ≥ 2 and M is an integer M > N. The grayscale voltage output unit generates a grayscale voltage signal corresponding to the image data signal based on the M gamma voltages output from the gamma voltage generation circuit. The gamma voltage generation circuit includes: N differential amplifiers, each receiving the N reference voltages, and each having an output terminal, are used to amplify and output the N reference voltages. as well as The trapezoidal resistor has N voltage supply points respectively connected to the output terminals of the N differential amplifiers, and M voltage output points for outputting the M gamma voltages. The trapezoidal resistor described herein has: The first wiring connects to the output of one of the N differential amplifiers via one of the N voltage supply points. The second wiring is connected between one of the M voltage output points and one of the input pairs of the N differential amplifiers. The M voltage output points are connected to the capacitive load on the input side of the amplifier, which forms the load. One of the input pairs of one of the N differential amplifiers is connected to one of the M voltage output points, wherein the voltage output point outputs a voltage level that is closest to the voltage of the one of the N voltage supply points. The other input pair of one of the N differential amplifiers is an input voltage that accepts one of the N reference voltages, and the voltage supply point and the voltage output point are located at different positions on the trapezoidal resistor.

4. A display device, comprising: The display panel has multiple data lines, multiple scan lines, pixel switches and pixel units respectively disposed at the intersections of the multiple data lines and the multiple scan lines; The gate driver, during a selection period corresponding to the pulse width, supplies a scan signal controlling the pixel switch to be on to the plurality of scan lines; and A data driver supplies grayscale voltage signals corresponding to image data signals to the plurality of data lines. The display device is characterized in that... The data driver has: The gamma voltage generation circuit generates M gamma voltages by dividing the N different reference voltages supplied to the data driver, and amplifies the M gamma voltages by an amplifier, where N is an integer N ≥ 2 and M is an integer M > N. The grayscale voltage output unit generates a grayscale voltage signal corresponding to the image data signal based on the M gamma voltages output from the gamma voltage generation circuit. The gamma voltage generation circuit includes: N differential amplifiers, each receiving the N reference voltages, and each having an output terminal, are used to amplify and output the N reference voltages. as well as The trapezoidal resistor has N voltage supply points respectively connected to the output terminals of the N differential amplifiers, and M voltage output points for outputting the M gamma voltages. The trapezoidal resistor described herein has: The first wiring connects to the output of one of the N differential amplifiers via one of the N voltage supply points. The second wiring is connected between one of the M voltage output points and one of the input pairs of the N differential amplifiers. The M voltage output points are connected to the capacitive load on the input side of the amplifier, which forms the load. One of the input pairs of one of the N differential amplifiers is connected to one of the M voltage output points, wherein the voltage output point outputs a voltage level that is closest to the voltage of the one of the N voltage supply points. The other input pair of one of the N differential amplifiers is an input voltage that accepts one of the N reference voltages, and the voltage supply point and the voltage output point are located at different positions on the trapezoidal resistor.

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