System and method for improved double-tail latch with wide input common-mode range

Abstract

Embodiments of the present application relate to systems and methods for improving double-tail latches with a wide input common-mode range. A memory device includes an interface that receives one or more clock signals and one or more data signals; and a dual-sensing-stage double-tail latch disposed at the interface. The dual-sensing-stage double-tail latch includes a sensing stage that senses a differential voltage between a first signal and a second signal and provides a first differential voltage output and a second differential voltage output to a first node and a second node, respectively. The dual-sensing-stage double-tail latch includes a complementary sensing stage disposed in parallel with the sensing stage and sensing the differential voltage between the first signal and the second signal, wherein the first complementary differential output voltage and the second complementary differential output of the complementary sensing stage are coupled to the first node and the second node. The dual-sensing-stage double-tail latch includes a latch stage that receives the outputs from the first node and the second node.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to the field of semiconductor devices and, more particularly, to double-tail latches in memory devices. Background Art

[0002] This section is intended to introduce the reader to various technical aspects that may be related to various aspects of the present technology described and / or claimed below. It is believed that this discussion is helpful in providing the reader with background information to facilitate a better understanding of various aspects of the present disclosure. Therefore, it should be understood that these statements should be read in this light and not as admissions of prior art.

[0003] Semiconductor devices (such as memory devices) can use a comparator or a combination of a sensing stage and a latch stage (such as a double-tailed latch) to latch a signal without the need for additional electronic components. The double-tailed latch can be implemented with n-type input transistors or p-type input transistors, allowing sensing of different voltage levels within a wide common-mode range. However, conventional double-tailed latches with n-type input transistors or p-type input transistors at both stages of the double-tailed latch may have difficulty sensing and latching data in systems with wide input swings (such as rail-to-rail) because the input transistors may operate in the cutoff region. That is, in certain applications, using a conventional double-tailed latch architecture may result in data eye distortion, reduced rank margin tool (RMT) margin, and decision feedback equalization (DFE) training difficulties because the input transistors operate in the cutoff region. Therefore, it is desirable to implement a system that improves the double-tailed latch.

[0004] Embodiments of the present disclosure may be directed to addressing one or more of the above-mentioned issues. Summary of the Invention

[0005] A device is described. In some embodiments, the device includes an interface configured to receive one or more clock signals and one or more data signals; and a dual-sensing stage dual-tail latch disposed at the interface. The dual-sensing stage dual-tail latch includes a sensing stage configured to sense a differential voltage between a first signal and a second signal and provide a first differential voltage output and a second differential voltage output to a first node and a second node, respectively; a complementary sensing stage disposed in parallel with the sensing stage and configured to sense the differential voltage between the first signal and the second signal, wherein the first complementary differential output voltage and the second complementary differential output of the complementary sensing stage are coupled to the first node and the second node; and a latch stage configured to receive the outputs from the first node and the second node.

[0006] A system is described. In some embodiments, the system includes: one or more external devices configured to generate one or more data signals; and a memory device coupled to the one or more external devices. The memory device includes: an input / output (I / O) interface configured to receive one or more clock signals and the one or more data signals. The I / O interface includes a dual-sensing stage dual-tail latch. The dual-sensing stage dual-tail latch includes: a sensing stage configured to sense a difference between a first signal and a second signal and provide a first differential output and a second differential output to a first node and a second node, respectively; a complementary sensing stage arranged in parallel with the sensing stage and configured to sense a difference between the first signal and the second signal, wherein the first complementary differential output and the second complementary differential output of the complementary sensing stage are coupled to the first node and the second node; and a latch stage configured to latch the outputs received from the sensing stage and the complementary sensing stage at the first node and the second node in response to at least one of the one or more clock signals.

[0007] A memory device is described. In some embodiments, the memory device includes a dual-sensing stage dual-tail latch arranged at an interface of the memory device. The dual-sensing stage dual-tail latch includes a sensing stage, a complementary sensing stage, and a latch stage. The sensing stage includes one or more n-type input transistors configured to: sense a differential voltage between a first signal and a second signal; amplify the differential voltage; and provide the amplified differential voltage to a first node and a second node. The complementary sensing stage includes one or more p-type transistors configured to: sense a complementary differential voltage between the first signal and the second signal; amplify the complementary differential voltage; and provide the amplified complementary differential voltage to the first node and the second node. The latch stage is configured to receive the amplified differential voltage or the amplified complementary differential voltage from the first node and the second node. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various aspects of the present disclosure may be better understood after reading the following detailed description and referring to the accompanying drawings, in which:

[0009] Figure 1 is a simplified block diagram illustrating some features of a memory device according to an embodiment of the present disclosure;

[0010] Figure 2 is a circuit diagram of a double-tail latch having n-type transistors;

[0011] Figure 3 is a block diagram of an improved double-tail latch according to an embodiment of the present disclosure; and

[0012] Figure 4 According to an embodiment of the present disclosure Figure 3 Circuit diagram of the improved double-tail latch. DETAILED DESCRIPTION

[0013] One or more specific embodiments are described below. To provide a concise description of these embodiments, not all features of an actual implementation are described in this specification. It should be understood that in the development of any such actual implementation, as with any engineering or design project, many implementation-specific decisions must be made to achieve developer-specific goals, which may vary from implementation to implementation, such as meeting system-related and business-related constraints. Furthermore, it should be understood that such a development effort may be complex and time-consuming, but will nevertheless be a routine design, fabrication, and manufacturing task for those of ordinary skill having the benefit of this disclosure.

[0014] During operation, a memory device receives signals with varying voltage levels and can latch the incoming signals within the receiver. Each signal can have a voltage level within a common-mode range, and each signal can be amplified for processing in the memory device. To alleviate the need for additional electronic components (such as operational amplifiers), a double-tailed latch having a sensing stage for comparing and amplifying the input signal and a latch stage for latching the output signal from the sensing stage can be implemented with input transistors for each stage having a common transistor type (such as an n-type transistor or a p-type transistor) used as the input transistor in each stage. This can allow sensing of different voltage levels within a wide common-mode range.

[0015] However, when a double-tail latch is implemented with either n-type or p-type input transistors as inputs to the sensing and latching stages, the double-tail latch may have difficulty reliably sensing and latching the inputs, particularly in applications with wide input voltage swings (e.g., rail-to-rail), where significant headroom loss may be observed. Embodiments disclosed herein provide a system for implementing a second sensing stage within a double-tail latch to ensure proper capture of input signals, even signals within a wide input common-mode range. As described below, the second sensing stage is connected in parallel with the first sensing stage and employs input elements (e.g., transistors) that are complementary to the first sensing stage to provide improved performance by generating a larger, more symmetrical data eye compared to a double-tail latch with only a single sensing stage.

[0016] Figure 1is a simplified block diagram illustrating some features of a memory device 10. According to one embodiment, the memory device 10 may be a fifth-generation double data rate synchronous dynamic random access memory (DDR5 SDRAM) device. Various features of DDR5 SDRAM allow for reduced power consumption, increased bandwidth, and increased storage capacity compared to previous generations of DDR SDRAM. Memory device 10 represents a portion of a single memory chip (e.g., an SDRAM chip) having several memory banks 12. Memory banks 12 may be, for example, DDR5 SDRAM memory banks. Memory banks 12 may be disposed on one or more chips (e.g., SDRAM chips) arranged on a dual in-line memory module (DIMM). Each DIMM may include several SDRAM memory chips (e.g., 8 or 16 memory chips). Each SDRAM memory chip may include one or more memory banks 12.

[0017] For DDR5, the memory banks 12 can be arranged to form memory bank groups. For example, a memory chip can include 16 memory banks 12 for an 8-gigabyte (8Gb) DDR5 SDRAM. The memory banks 12 can be arranged into 8 memory bank groups, each memory bank group including 2 memory banks. For example, for a 16-gigabyte (16Gb) DDR5 SDRAM, a memory chip can include 32 memory banks 12 arranged into 8 memory bank groups, each memory bank group including 4 memory banks 12.

[0018] Various other configurations, organizations, and sizes of the banks 12 on the memory device 10 may be utilized depending on the application and design of the overall system. In one embodiment, each bank 12 includes a bank control block 22 that controls the execution of commands to and from the bank 12 to perform various functionalities in the memory device 10, such as decoding, timing control, data control, and any combination thereof.

[0019] The command interface 14 of the memory device 10 is configured to receive and transmit a number of signals, such as signal 15. Signal 15 may be received from an external device (not shown), such as a processor or controller. The processor or controller may provide various signals 15 to the memory device 10 to facilitate the transmission and reception of data written to or read from the memory device 10.

[0020] It should be understood that the command interface 14 may include, for example, several circuits (e.g., clock input circuitry 18 and command address input circuitry 20) to ensure proper handling of the signal 15. The command interface 14 may receive one or more clock signals from an external device. Generally, double data rate (DDR) memory utilizes a differential pair of system clock signals, referred to herein as a true clock signal (Clk_t) and a complementary clock signal (Clk_c). A positive clock edge in DDR refers to the point where a rising true clock signal Clk_t crosses a falling complementary clock signal Clk_c. A negative clock edge indicates a transition between a falling true clock signal Clk_t and a rising complementary clock signal Clk_c. Commands (e.g., read commands, write commands, etc.) are typically input on the positive edge of the clock signal. Data can be transmitted or received on both positive and negative clock edges.

[0021] Clock input circuit 18 receives a true clock signal (Clk_t) and a complementary clock signal (Clk_c) and generates an internal clock signal CLK. Internal clock signal CLK is supplied to an internal clock generator, such as a delay-locked loop (DLL) circuit 30. DDL circuit 30 generates a phase-controlled internal clock signal LCLK based on the received internal clock signal CLK. Phase-controlled internal clock signal LCLK is supplied to, for example, I / O interface 16 and serves as a timing signal for determining the output timing of read data. In some embodiments, as discussed below, clock input circuit 18 may include circuitry that divides the clock signal into multiple (e.g., four) phases. Clock input circuit 18 may also include phase detection circuitry to detect which phase receives the first pulse when a pulse group occurs too frequently, enabling clock input circuit 18 to reset between pulses.

[0022] The internal clock signal / phase CLK may also be provided to various other components within the memory device 10 and may be used to generate various additional internal clock signals. For example, the internal clock signal CLK may be provided to a command decoder 32. The command decoder 32 may receive command signals from a command bus 34 and may decode the command signals to provide various internal commands. For example, the command decoder 32 may provide the command signals to the DLL circuit 30 via a bus 36 to coordinate the generation of the phase-controlled internal clock signal LCLK. The phase-controlled internal clock signal LCLK may be used, for example, to clock data via the I / O interface 16.

[0023] Furthermore, command decoder 32 may decode incoming commands (e.g., read commands, write commands, mode register set commands, activate commands, etc.) and provide access to the specific memory bank 12 corresponding to the command via bus path 38. It should be appreciated that memory device 10 may include various other decoders (e.g., row decoders and column decoders) to facilitate access to memory banks 12.

[0024] The memory device 10 performs operations, such as read and write commands, based on command / address signals received from an external device (e.g., a processor). In one embodiment, the command / address bus 34 may be a 14-bit bus that accommodates command / address signals (CA<13:0>). The command / address signals 15 are clocked using clock signals (Clk_t and Clk_c) for transmission to the command interface 14. The command interface 14 may include a command and address input circuit 20 configured to receive and transmit commands to provide access to the memory banks 12 via the command decoder 32. In addition, the command interface 14 may receive a chip select signal (CS_n). The CS_n signal enables the memory device 10 to process commands incoming on the CA<13:0> bus. Access to a specific memory bank 12 within the memory device 10 is encoded using commands on the CA<13:0> bus.

[0025] In addition, the command interface 14 can be configured to receive several other command signals. For example, a command / address on die termination (CA_ODT) signal can be provided to facilitate proper impedance matching within the memory device 10. A reset command (RESET_n) can be used to reset the command interface 14, status registers, state machines, and the like, for example, during power-up. The command interface 14 can also receive a command / address inversion (CAI) signal, which can be provided to invert the state of the command / address signals CA<13:0> on the command / address bus 34, for example, depending on the command / address routing for a particular memory device 10. A mirror (MIR) signal can also be provided to facilitate mirroring functionality. The MIR signal can be used to multiplex signals so that, based on the configuration of multiple memory devices (e.g., memory device 10) in a particular application, signals can be swapped to achieve a certain routing of signals to the memory device 10. Various signals can also be provided to facilitate testing of the memory device 10, such as a test enable (TEN) signal. For example, the TEN signal can be used to place the memory device 10 in a test mode for connectivity testing.

[0026] The command interface 14 can also be used to provide an alert signal (ALERT_n) to the system processor or controller of a detectable error. For example, if a cyclic redundancy check (CRC) error is detected, an alert signal (ALERT_n) can be transmitted from the memory device 10. Other alert signals can also be generated. In addition, the bus and pins used to transmit the alert signal (ALERT_n) from the memory device 10 can be used as input pins during some operations, such as the connectivity test mode performed using the TEN signal, as described above.

[0027] By transmitting and receiving data signals 40 through the I / O interface 16, data can be sent to and from the memory device 10 using the command and clock signals 15 discussed above. More specifically, data can be sent to and retrieved from the memory bank 12 via a data path 42, which includes a plurality of bidirectional data buses. Data I / O signals (often referred to as DQ signals) are typically transmitted and received on one or more bidirectional data buses. For certain memory devices (such as DDR5 SDRAM memory devices), the I / O signals can be divided into high-order and low-order bytes. For example, for a x16 memory device, the I / O signals can be divided into high-order and low-order I / O signals (e.g., DQ<15:8> and DQ<7:0>), corresponding to, for example, the high-order and low-order bytes of the data signals.

[0028] To allow for higher data rates within the memory device 10, some memory devices (such as DDR memory devices) may utilize a data strobe signal, commonly referred to as a DQS signal. The DQS signal is driven by an external processor or controller sending the data (e.g., for a write command) or by the memory device 10 (e.g., for a read command). For a read command, the DQS signal is effectively an additional data output (DQ) signal with a predetermined pattern. For a write command, the DQS signal can be used as a clock signal to capture the corresponding input data. Like the clock signals (Clk_t and Clk_c), the DQS signal can be provided as a differential pair of data strobe signals (DQS_t and DQS_c) to provide differential pair signaling during reads and writes. For some memory devices (such as DDR5 SDRAM memory devices), the differential pair of DQS signals can be divided into high-order and low-order data strobe signals (e.g., UDQS_t and UDQS_c; LDQS_t and LDQS_c), corresponding to, for example, the high-order and low-order bytes of data sent to and from the memory device 10.

[0029] An impedance (ZQ) calibration signal may also be provided to the memory device 10 via the I / O interface 16. The ZQ calibration signal may be provided to a reference pin and used to tune the output driver and ODT value by adjusting the pull-up and pull-down resistors of the memory device 10 across variations in process, voltage, and temperature (PVT) values. Because PVT characteristics can affect the ZQ resistor value, the ZQ calibration signal may be provided to the ZQ reference pin for adjusting the resistance to calibrate the input impedance to a known value. It should be understood that a precision resistor is typically coupled between the ZQ pin on the memory device 10 and GND / VSS external to the memory device 10. This resistor serves as a reference for adjusting the internal ODT and drive strength of the I / O pins.

[0030] In addition, a loopback signal (LOOPBACK) may be provided to the memory device 10 via the I / O interface 16. The loopback signal may be used during a test or debug phase to set the memory device 10 to a mode in which signals are looped back through the memory device 10 via the same pins. For example, the loopback signal may be used to set up the memory device 10 to test the data outputs (DQ) of the memory device 10. The loopback may include both data and strobe pins or may only include the data pins. This is often desirable for monitoring data captured by the memory device 10 at the I / O interface 16.

[0031] It should be understood that various other components, such as power supply circuits (for receiving external VDD and VSS signals), mode registers (for defining various modes of programmable operation and configuration), read / write amplifiers (for amplifying signals during read / write operations), temperature sensors (for sensing the temperature of the memory device 10), etc., may also be incorporated into the memory device 10. Therefore, it should be understood that Figure 1 The block diagram is provided to highlight some functional features of the memory device 10 to assist in the subsequent detailed description.

[0032] As discussed above, the memory device may receive an input signal to execute one or more commands at the I / O interface 16. Before executing the one or more commands based on the input signal, the memory device may latch the input signal in the I / O interface 16. To latch the input signal, the memory device may use a double-tailed latch to sense / amplify and latch the input signal without adding additional electronic components.

[0033] In view of the above, Figure 2 FIG1 is a circuit diagram of a double-tailed latch 50 having n-type input transistors. For example, the double-tailed latch may be located in the I / O interface 16 of the memory device 10. The double-tailed latch 50 may include a comparator or sensing stage 52 and a latch stage 74. The sensing stage 52 includes transistors (e.g., MOSFET transistors) 54, 56, 58, 60, and 62. Specifically, input transistors 58 and 60, as well as transistor 62, may be n-type transistors. Furthermore, transistors 54 and 56 may be p-type transistors. A clock signal CK (e.g., LCLK) 64 may be connected to the gates of transistors 54, 56, and 62 to clock the signals received by input transistors 58 and 60 for sensing and amplifying one or more signals at the sensing stage 52. For example, a DQ input signal 66 (e.g., DQ<15:8> / DQ<7:0>) may be connected to the gate of input transistor 58. A voltage reference 68 may be connected to the gate of input transistor 60. Additionally, a voltage source (VDD) 55 may be coupled to the sources of transistors 54 and 56 .

[0034] Latch stage 74 includes transistors (e.g., MOSFET transistors) 76, 78, 80, 82, 84, 86, 88, and 90. Specifically, transistors 76, 78, 84, and 90 may be n-type transistors. Furthermore, transistors 80, 82, 86, and 88 may be p-type transistors. An inverted clock signal CKF (e.g., an inverted version of clock signal CK 64 or LCLK) may be connected to the gates of transistors 80 and 86. A delay element 92 may be provided to ensure proper timing based on propagation delay. Additionally, a voltage source (VDD) 55 may be coupled to the sources of transistors 80 and 86. When clock signal 64 is low, transistor 62 is turned off, and the voltages at nodes 67 and 69 are reset and precharged to be equivalent to VDD 55 by transistors 54 and 56, respectively. That is, sensing stage 52 may be in a precharge phase.

[0035] When clock signal 64 is high, transistors 54 and 56 are turned off and transistors 58, 60, and 62 are turned on. Transistors 58 and 60 draw a differential current proportional to the potential difference between the voltage of DQ input signal 66 and voltage reference 68. The differential current due to the voltage discharge allows the differential voltage between node 67 and node 69 to increase relative to the differential voltage between the voltage of DQ input signal 66 and voltage reference 68 (e.g., differential gain). That is, the differential voltage is amplified and discharges the voltage at nodes 67 and 69 to VSS. As nodes 67 and 69 continue to discharge, transistors 76 and 78 turn on.

[0036] The differential voltage is established by transistors 76 and 78 and passed to transistors 82, 84, 88, and 90. Transistors 82, 84, 88, and 90 are regeneration circuits to create a full rail (e.g., digital ready) output representing the amplified DQ input signal 66. That is, there is no need to buffer the signal and wait for the gain to increase before the output is passed to the rest of the circuit.

[0037] Although the double-tail latch 50 is capable of providing a full-rail output without requiring any additional operational amplifiers, the double-tail latch 50 may encounter difficulties with a wide input swing (e.g., 100 millivolts (mV) to 900 mV) of the DQ input signal 66 voltage due to a limited common mode when there is only a pair of input transistors (e.g., n-type transistors or p-type transistors). Additionally, this may be due to transistors 58 and 60 being the same transistor type (e.g., n-type transistors or p-type transistors) as transistors 76 and 78 in latch 74. To remedy the issues associated with the wide input swing, according to embodiments described herein, a complementary sense stage may be added to cover the wide input swing of the DQ input signal 66 voltage.

[0038] In view of the above, Figure 3FIG2 is a block diagram of an improved double-tail latch 100 having a dual-component sensing stage 101 and a latch stage 74 according to an embodiment of the present invention. As used herein, the improved double-tail latch 100 having the dual-component sensing stage 101 may also be referred to as a "dual-sensing-stage double-tail latch 100." As discussed above, the double-tail latch 50 may encounter difficulties with DQ input signal 66 having a wide input swing. According to an improved embodiment, the dual-component sensing stage 101 may include sensing stage 52 and a complementary sensing stage 102. The complementary sensing stage 102 may be provided in parallel with sensing stage 52 to compensate for the wide input swing of the incoming DQ input signal 66. That is, the complementary sensing stage 102 may include input transistors of the opposite type (e.g., n-type transistors or p-type transistors) of input transistors 58 and 60, as well as the remaining transistors of sensing stage 52. The outputs of each sensing stage 52 and 102 are coupled together and provided as inputs to latch stage 74. Furthermore, the sensing stage 52 and the complementary sensing stage 102 may be clocked with the same CK signal 64. Alternatively, the complementary sensing stage 102 may be constructed with some delay depending on the device characteristics.

[0039] In this way, the improved double-tail latch 100 can accurately sense and latch an incoming DQ input signal 66 with a wide input swing. The sensing stage 52 and the complementary sensing stage 102 can each receive the DQ input signal 66 and a voltage reference 68. The sensing stage 52 and the complementary sensing stage 102 sense the DQ input signal 66 and compare the DQ input signal 66 to the voltage reference 68. Based on the voltage level of the DQ input signal 66 and the transistor type (e.g., n-type transistor or p-type transistor) of the sensing stage 52 and the complementary sensing stage 102, the sensing stage 52 or the complementary sensing stage 102 amplifies the DQ input signal 66 and transmits the amplified signal to the latch 74. The latch 74 can latch (e.g., hold) the amplified signal.

[0040] In view of the above, Figure 4 Is a Figure 3FIG1 is a circuit diagram of an improved double-tail latch 100 including a dual-component sensing stage 101 and a latch stage 74. The improved double-tail latch 100 may be located in the I / O interface 16 of the memory device 10. Furthermore, the dual-component sensing stage 101 may include a sensing stage 52 and a complementary sensing stage 102. Sense stage 52 includes transistors (e.g., MOSFET transistors) 54, 56, 58, 60, and 62. Specifically, transistors 58, 60, and 62 may be n-type transistors. Furthermore, transistors 54 and 56 may be p-type transistors. A clock signal CK (e.g., LCLK) 64 may be connected to the gates of transistors 54, 56, and 62 to sense and amplify one or more signals in the sensing stage 52. For example, DQ input signals 66 (e.g., DQ<15:8> and DQ<7:0>) may be connected to the gate of transistor 58. A voltage reference 68 may be connected to the gate of transistor 60. Additionally, a voltage source (VDD) 55 may be coupled to the sources of transistors 54 and 56 .

[0041] Complementary sensing stage 102 includes transistors 104, 106, 108, 110, 112, 114, 116, and 118. Specifically, transistors 110, 112, 114, 116, and 118 may be n-type transistors. Furthermore, complementary input transistors 106 and 108 may be p-type transistors. That is, input transistors 106 and 108 of complementary sensing stage 102 are of a type (e.g., p-type) that is complementary to input transistors 58 and 60 (e.g., n-type) of sensing stage 52. An inverted clock signal CKF (e.g., the inverse of LCLK) may be connected to the gates of transistors 104, 110, and 112. Clock signal CK 64 may be connected to the gate of transistor 118 to clock the input signal for sensing and amplifying one or more signals (e.g., signals 66 and 68) at complementary sensing stage 102. DQ input signal 66 may be connected to the gate of transistor 108, and voltage reference 68 may be connected to the gate of transistor 106. Additionally, a voltage source (VDD) may be coupled to the source of transistor 104. Note that complementary sensing stage 102 operates in parallel with sensing stage 52. That is, the outputs of sensing stage 52 and complementary sensing stage 102 are coupled together (e.g., at node 67 and nodes 69 / 170). Note that in some embodiments, the positioning of sensing stage 52 and complementary sensing stage 102 may be reversed.

[0042] As previously described, latch stage 74 includes transistors (e.g., MOSFET transistors) 76, 78, 80, 82, 84, 86, 88, and 90. Specifically, transistors 76, 78, 84, and 90 may be n-type transistors. Furthermore, transistors 80, 82, 86, and 88 may be p-type transistors. An inverted clock signal CKF may be connected to the gates of transistors 80 and 86. Additionally, a voltage source (VDD) 55 may be coupled to the sources of transistors 80 and 86.

[0043] As about Figure 2 , when clock signal 64 is high, transistors 54 and 56 are turned off and transistors 58, 60, and 62 are turned on. Transistors 58 and 60 draw a differential current proportional to the potential difference between the voltage of DQ input signal 66 and voltage reference 68. The differential current due to the voltage discharge allows the differential voltage between node 67 and node 69 to increase relative to the differential voltage between the voltage of DQ input signal 66 and voltage reference 68 (e.g., differential gain). That is, the differential voltage is amplified and discharges the voltage at nodes 67 and 69 to VDD. As nodes 67 and 69 continue to discharge, transistors 76 and 78 turn on.

[0044] However, the DQ input signal 66 may have a voltage level that is too low or too high (e.g., 100 to 900 millivolts) to be detected by the sense stage 52. Thus, the complementary sense stage 102 can assist in detecting the voltage of the DQ input signal 66. When the inverted clock signal CKF is high (e.g., when the clock signal CK 64 is low), transistors 104, 106, and 108 are turned off. Nodes 109 and 111 are reset and discharged to ground through transistors 110 and 112.

[0045] When the inverted clock signal CKF is low (e.g., when the clock signal 64 is high), transistors 110 and 112 are turned off and transistor 104 is turned on. Transistor 104 generates a differential current drawn by transistors 106 and 108 that is proportional to the potential difference between the voltage of DQ input signal 66 and voltage reference 68. That is, the differential voltage is amplified and charges the voltage at nodes 109 and 111 to VDD. As nodes 109 and 111 continue to charge, transistors 76 and 78 turn on.

[0046] The differential voltage is established by transistors 76 and 78 and passed to transistors 82, 84, 88, and 90. Transistors 82, 84, 88, and 90 are regenerative circuits to create a full-rail (e.g., digital-ready) output. That is, there is no need to buffer the signal and wait for the gain to increase before the output is passed to the rest of the circuit. It should be noted that the p-type transistors implemented in complementary sense stage 102 can cause the logic of complementary sense stage 102 to operate inversely to the logic of sense stage 52.

[0047] By employing the techniques described in this disclosure, the system described herein can allow for an improved dual-sensing stage dual-tail latch 100 in an I / O interface 16 with wide input common-mode swing sensing capability. The improved dual-tail latch 100 can use the sensing stage 52 and the complementary sensing stage 102 to ensure that incoming signals with wide input voltage swings are captured, while providing sufficient amplification of the input signal before passing the amplified signal to the latch 74. Furthermore, through the regeneration circuitry formed by the transistors in the latch 74, the improved dual-sensing stage dual-tail latch 100 can produce a full-rail (e.g., digital ready) output. By including the complementary sensing stage 102 arranged in parallel with the original sensing stage 52 and having input transistors of opposite types (i.e., p-channel and n-channel), the improved dual-sensing stage dual-tail latch 100 provides an improved output by reducing the effects of the input transistors transitioning into the cutoff region.

[0048] While only certain features of the present disclosure have been illustrated and described herein, numerous modifications and changes will occur to those skilled in the art. For example, the asserted signal polarity may be reversed for at least some signals where a logic low is asserted and a logic high is de-asserted. It should be understood, therefore, that the appended claims are intended to cover all such modifications and changes that fall within the true spirit of the embodiments described herein.

[0049] The techniques presented and claimed herein are cited and applied to practical objects and specific examples that significantly advance the art and are therefore not abstract, intangible, or purely theoretical. Furthermore, if any claim appended to the end of this specification contains one or more elements designated as "means for [performing] [the function] ..." or "a step for [performing] [the function] ...", then it is intended that these elements be interpreted under 35 U.S.C. § 112(f). However, for any claim containing elements designated in any other manner, it is not intended that such elements be interpreted under 35 U.S.C. § 112(f).

Claims

1. A memory device comprising: an interface configured to receive one or more clock signals and one or more data signals; and A dual-sensing-stage dual-tail latch arranged at the interface and comprising: a sensing stage configured to sense a differential voltage between the first signal and the second signal and provide a first differential voltage output and a second differential voltage output to the first node and the second node, respectively; a complementary sensing stage arranged in parallel with the sensing stage and configured to sense the differential voltage between the first signal and the second signal, wherein a first complementary differential output voltage and a second complementary differential output of the complementary sensing stage are coupled to the first node and the second node; and A latch stage is configured to receive the outputs from the first node and the second node. 2 . The memory device of claim 1 , wherein the complementary sense stage comprises input transistors of a type opposite to a type of input transistors of the sense stage. 3 . The memory device of claim 2 , wherein the latch stage includes input transistors of the same type as the type of input transistors of the sense stage.

4. The memory device of claim 2, wherein the type of input transistor is one of an n-type transistor or a p-type transistor.

5. The memory device of claim 1, wherein the sensing stage and the complementary sensing stage are each clocked by a same clock signal of the one or more clock signals. 6 . The memory device of claim 1 , wherein the first signal is a data DQ signal and the second signal is a reference voltage.

7. The memory device of claim 1, wherein the sensing stage and the complementary sensing stage are each configured to amplify the differential voltage between the first signal and the second signal.

8. The memory device of claim 1, wherein the complementary sensing stages are clocked with a delay based on the one or more clock signals.

9. A system for improving a double-tail latch, comprising: one or more external devices configured to generate one or more data signals; and a memory device coupled to the one or more external devices, wherein the memory device comprises: an input / output (I / O) interface configured to receive one or more clock signals and the one or more data signals, wherein the I / O interface comprises: A dual-sensing-stage dual-tail latch comprising: a sensing stage configured to sense a difference between the first signal and the second signal and provide a first differential output and a second differential output to the first node and the second node, respectively; a complementary sensing stage arranged in parallel with the sensing stage and configured to sense a difference between the first signal and the second signal, wherein first and second complementary differential outputs of the complementary sensing stage are coupled to the first and second nodes; and A latch stage is configured to latch the outputs received from the sensing stage and the complementary sensing stage at the first node and the second node in response to at least one of the one or more clock signals. 10 . The system of claim 9 , wherein the first signal is a data DQ signal among the one or more data signals and the second signal is a reference voltage.

11. The system of claim 9, wherein: The sensing stage is configured to amplify the first differential output and the second differential output before the latch stage receives the differential output; and The complementary sense stage is configured to amplify the first complementary differential output and the second complementary differential output before the latch stage receives the differential output.

12. The system of claim 9, wherein the sensing stage is clocked by a first clock signal of the one or more clock signals and the complementary sensing stage is clocked by a second clock signal of the one or more clock signals, wherein the second clock signal is the inverse of the first clock signal.

13. The system of claim 9, wherein the latch stage is configured to provide a full rail output based on the outputs from the first node and the second node.

14. The system of claim 9, wherein the complementary sensing stage includes input transistors of a type opposite to a type of input transistors of the sensing stage, wherein the type of input transistors is an n-type transistor or a p-type transistor.

15. A memory device comprising: A dual-sensing-stage dual-tail latch arranged at an interface of the memory device and comprising: A sensing stage comprising one or more n-type input transistors, the sensing stage being configured to: sensing a differential voltage between the first signal and the second signal; amplifying the differential voltage; and providing the amplified differential voltage to a first node and a second node; A complementary sensing stage comprising one or more p-type transistors, the complementary sensing stage configured to: sensing a complementary differential voltage between the first signal and the second signal; amplifying the complementary differential voltage; and providing the amplified complementary differential voltage to the first node and the second node; and A latch stage is configured to receive the amplified differential voltage or the amplified complementary differential voltage from the first node and the second node.

16. The memory device of claim 15, wherein the complementary sensing stage is arranged in parallel with the sensing stage.

17. The memory device of claim 15, wherein the latch stage comprises n-type input transistors.

18. The memory device of claim 17, wherein the input transistors of the latch stage are regenerative circuits and produce a full rail output.

19. The memory device of claim 15, wherein the sensing stage and the complementary sensing stage each receive a same clock signal of one or more clock signals.

20. The memory device of claim 15, wherein a first position of the sensing stage and a second position of a complementary sensing stage are swapped relative to the latch stage.

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