Shift register and driving method thereof, scan driving circuit, display device

Abstract

The embodiment of the present disclosure discloses a shift register and a driving method thereof, a scan driving circuit and a display device, relates to the technical field of display, and is used for avoiding flicker phenomenon of a display picture and improving uniformity of the display picture. The shift register comprises a first input circuit, a first control circuit, a first output circuit, a second input circuit, a second control circuit and a second output circuit. The first input circuit, the first control circuit, the first output circuit, the second input circuit, the second control circuit and the second output circuit each comprise at least one transistor, and the transistor is an oxide transistor. The shift register and the driving method thereof, the scan driving circuit and the display device provided by the embodiment of the present disclosure are used for image display.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a shift register and its driving method, a scanning driving circuit, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) have been widely used in the display field due to their advantages such as self-illumination, low driving voltage, high luminous efficiency, fast response speed, and flexible display capabilities. Summary of the Invention

[0003] The purpose of this disclosure is to provide a shift register and its driving method, a scan driving circuit, and a display device to avoid flickering in the display screen and improve the uniformity of the display screen.

[0004] To achieve the above objectives, the present disclosure provides the following technical solutions:

[0005] In one aspect, embodiments of this disclosure provide a shift register. The shift register includes: a first input circuit, a first control circuit, a first output circuit, a second input circuit, a second control circuit, and a second output circuit. The first input circuit is electrically connected to a first voltage signal terminal, a first clock signal terminal, and a first node. The first input circuit is configured to transmit a first voltage signal received at the first voltage signal terminal to the first node under the control of a first clock signal transmitted at the first clock signal terminal. The first control circuit is electrically connected to at least the first node, a second clock signal terminal, and a second node. The first control circuit is configured to transmit a second clock signal or an electrical signal from the first node to the second node under the control of a second clock signal transmitted at the second clock signal terminal. The first output circuit is electrically connected to a second voltage signal terminal, the second node, and a first output signal terminal. The first output circuit is configured to transmit a second voltage signal received at the second voltage signal terminal to the first output signal terminal under the control of the voltage of the second node. The second input circuit is electrically connected to an input signal terminal, the first clock signal terminal, and a third node. The second input circuit is configured to transmit the input signal received at the input signal terminal to the third node under the control of the first clock signal. The second control circuit is electrically connected to the third node, the first control signal terminal, and the control node. The second control circuit is configured to transmit the first control signal received at the first control signal terminal to the control node under the control of the voltage of the third node; the control node includes either the first node or the second node. The second output circuit is electrically connected to the first voltage signal terminal, the third node, and the first output signal terminal. The second output circuit is configured to transmit the first voltage signal to the first output signal terminal under the control of the voltage of the third node. Each of the first input circuit, the first control circuit, the first output circuit, the second input circuit, the second control circuit, and the second output circuit includes at least one transistor. The at least one transistor is an oxide transistor.

[0006] Therefore, the shift registers provided in some embodiments of this disclosure, by setting a first input circuit, a first control circuit, a first output circuit, a second input circuit, a second control circuit, and a second output circuit, and electrically connecting each circuit to a corresponding signal terminal, can utilize the cooperation between each circuit and each signal terminal to enable the first output circuit and the second output circuit to conduct in different time periods. This allows the second voltage signal output by the first output circuit and the first voltage signal output by the second output circuit to cooperate to form a first output signal that alternates between high and low levels. The waveform of this first output signal is the same as the waveform of the enable signal required by the pixel driving circuit in the display device. In this way, multiple shift registers can be used to provide enable signals to different pixel driving circuits in the display device, realizing the display driving of different sub-pixels. By using the above-mentioned shift registers to drive the display of sub-pixels, the light-emitting stage and the black-insertion stage can be alternated in an image frame, thereby reducing the light-emitting duration of the light-emitting device in an image frame, enhancing the dynamic image response time, and achieving black-insertion with a shorter time interval and a higher frequency, thus avoiding the black screen being captured by the human eye and preventing the human eye from seeing a flickering display. Furthermore, by setting the transistors included in the above-mentioned circuits as oxide transistors, this disclosure can ensure that the initial threshold voltages of each transistor are similar or equal, making the first output signal output from the first output signal terminal more stable. In turn, after providing the first output signal as an enable signal to the pixel driving circuit, it is beneficial to improve the uniformity of the brightness of the light emitted by different light-emitting devices and improve the uniformity of the display screen of the display device.

[0007] In some examples, the first input circuit includes a first transistor. The gate of the first transistor is electrically connected to the first clock signal terminal, the first terminal of the first transistor is electrically connected to the first voltage signal terminal, and the second terminal of the first transistor is electrically connected to the first node. The first output circuit includes a second transistor and a first capacitor; or, the first output circuit includes a second transistor. The gate of the second transistor is electrically connected to the second node, the first terminal of the second transistor is electrically connected to the second voltage signal terminal, and the second terminal of the second transistor is electrically connected to the first output signal terminal. The first terminal of the first capacitor is electrically connected to the second node, and the second terminal of the first capacitor is electrically connected to the second voltage signal terminal. The second input circuit includes a third transistor. The gate of the third transistor is electrically connected to the first clock signal terminal, the first terminal of the third transistor is electrically connected to the input signal terminal, and the second terminal of the third transistor is electrically connected to the third node. The second control circuit includes a fourth transistor. The gate of the fourth transistor is electrically connected to the third node, the first terminal of the fourth transistor is electrically connected to the first control signal terminal, and the second terminal of the fourth transistor is electrically connected to the control node. The second output circuit includes a fifth transistor and a second capacitor; or, the second output circuit includes a fifth transistor. The gate of the fifth transistor is electrically connected to the third node, the first terminal of the fifth transistor is electrically connected to the first voltage signal terminal, and the second terminal of the fifth transistor is electrically connected to the first output signal terminal. The first terminal of the second capacitor is electrically connected to the third node, and the second terminal of the second capacitor is electrically connected to the first output signal terminal.

[0008] In some examples, the shift register further includes a first leakage protection circuit. The first leakage protection circuit is electrically connected to a first leakage protection signal terminal, a first leakage protection node, and a first output signal terminal. The first leakage protection circuit is configured to transmit a first leakage protection signal received at the first leakage protection signal terminal to the first leakage protection node under the control of a first output signal transmitted at the first output signal terminal. The first leakage protection signal terminal includes either the first voltage signal terminal or the first output signal terminal. The first output circuit is also electrically connected to the first leakage protection node.

[0009] In some examples, the first leakage protection circuit includes a sixth transistor. The gate of the sixth transistor is electrically connected to the first output signal terminal, the first terminal of the sixth transistor is electrically connected to the first leakage protection signal terminal, and the second terminal of the sixth transistor is electrically connected to the first leakage protection node. The second transistor includes a first sub-transistor and a second sub-transistor. The gate of the first sub-transistor is electrically connected to the second node, the first terminal of the first sub-transistor is electrically connected to the second voltage signal terminal, and the second terminal of the first sub-transistor is electrically connected to the first leakage protection node. The gate of the second sub-transistor is electrically connected to the second node, the first terminal of the second sub-transistor is electrically connected to the first leakage protection node, and the second terminal of the second sub-transistor is electrically connected to the first output signal terminal.

[0010] In some examples, the first control circuit is electrically connected to the first node, the second clock signal terminal, and the second node. The first control circuit is configured to transmit the second clock signal to the second node under the control of the voltage at the first node and the second clock signal. The first control circuit includes a seventh transistor, an eighth transistor, and a third capacitor. The gate of the seventh transistor is electrically connected to the first node, the first terminal of the seventh transistor is electrically connected to the second clock signal terminal, and the second terminal of the seventh transistor is electrically connected to a fourth node. The gate of the eighth transistor is electrically connected to the second clock signal terminal, the first terminal of the eighth transistor is electrically connected to the fourth node, and the second terminal of the eighth transistor is electrically connected to the second node. The first terminal of the third capacitor is electrically connected to the first node, and the second terminal of the third capacitor is electrically connected to either the second clock signal terminal or the fourth node.

[0011] In some examples, the first control circuit is electrically connected to the first node, the second clock signal terminal, the second node, and the second voltage signal terminal. The first control circuit is configured to transmit an electrical signal from the first node to the second node under the control of the second clock signal. The first control circuit includes a ninth transistor and a fourth capacitor. The gate of the ninth transistor is electrically connected to the second clock signal terminal, the first terminal of the ninth transistor is electrically connected to the first node, and the second terminal of the ninth transistor is electrically connected to the second node. The first terminal of the fourth capacitor is electrically connected to the first node, and the second terminal of the fourth capacitor is electrically connected to the second voltage signal terminal.

[0012] In some examples, the shift register further includes a voltage regulator circuit. The voltage regulator circuit is electrically connected to the first voltage signal terminal, the third node, and the fifth node. The second input circuit is also electrically connected to the fifth node and, through the voltage regulator circuit, to the third node. The second input circuit is configured to transmit the input signal to the fifth node under the control of the first clock signal. The voltage regulator circuit is configured to transmit the electrical signal from the fifth node to the third node under the control of the first voltage signal. The control node is the second node, and the second control circuit is electrically connected to the third node, the first control signal terminal, and the second node.

[0013] In some examples, the voltage regulator circuit includes a tenth transistor. The gate of the tenth transistor is electrically connected to the first voltage signal terminal, the first terminal of the tenth transistor is electrically connected to the fifth node, and the second terminal of the tenth transistor is electrically connected to the third node. In the second input circuit, the second terminal of the third transistor is electrically connected to the fifth node. In the second control circuit, the second terminal of the fourth transistor is electrically connected to the second node.

[0014] In some examples, the shift register further includes a second leakage protection circuit. The second leakage protection circuit is electrically connected to the third node, the third voltage signal terminal, and the second leakage protection node; the second leakage protection circuit is configured to transmit a third voltage signal received at the third voltage signal terminal to the second leakage protection node under the control of the voltage of the third node. The voltage regulator circuit is also electrically connected to the second leakage protection node; the voltage of the third voltage signal is higher than the voltage of the first voltage signal.

[0015] In some examples, the second leakage protection circuit includes an eleventh transistor. The gate of the eleventh transistor is electrically connected to the third node, the first terminal of the eleventh transistor is electrically connected to the third voltage signal terminal, and the second terminal of the eleventh transistor is electrically connected to the second leakage protection node. The tenth transistor includes a third sub-transistor and a fourth sub-transistor. The gate of the third sub-transistor is electrically connected to the first voltage signal terminal, the first terminal of the third sub-transistor is electrically connected to the fifth node, and the second terminal of the third sub-transistor is electrically connected to the second leakage protection node. The gate of the fourth sub-transistor is electrically connected to the first voltage signal terminal, the first terminal of the fourth sub-transistor is electrically connected to the second leakage protection node, and the second terminal of the fourth sub-transistor is electrically connected to the third node.

[0016] In some examples, the shift register further includes a third leakage protection circuit. The third leakage protection circuit is electrically connected to the second node, the first voltage signal terminal, and the third leakage protection node; the third leakage protection circuit is configured to transmit the first voltage signal to the third leakage protection node under the control of the voltage of the second node. The second control circuit is also electrically connected to the third leakage protection node.

[0017] In some examples, the third leakage protection circuit includes a twelfth transistor. The gate of the twelfth transistor is electrically connected to the second node, the first terminal of the twelfth transistor is electrically connected to the first voltage signal terminal, and the second terminal of the twelfth transistor is electrically connected to the third leakage protection node. The fourth transistor includes a fifth sub-transistor and a sixth sub-transistor. The gate of the fifth sub-transistor is electrically connected to the third node, the first terminal of the fifth sub-transistor is electrically connected to the first control signal terminal, and the second terminal of the fifth sub-transistor is electrically connected to the third leakage protection node. The gate of the sixth sub-transistor is electrically connected to the third node, the first terminal of the sixth sub-transistor is electrically connected to the third leakage protection node, and the second terminal of the sixth sub-transistor is electrically connected to the second node.

[0018] In some examples, the shift register further includes at least one of a third control circuit, a fourth control circuit, and a reset circuit. The third control circuit is electrically connected to the fifth node, the second control signal terminal, and the first node; the third control circuit is configured to transmit a second control signal received at the second control signal terminal to the first node under the control of the voltage at the fifth node. The fourth control circuit is electrically connected to the first node, a fourth voltage signal terminal, a second clock signal terminal, and the fifth node; the fourth control circuit is configured to transmit a fourth voltage signal received at the fourth voltage signal terminal to the fifth node under the control of the voltage at the first node and the second clock signal. The reset circuit is electrically connected to the reset signal terminal, the first voltage signal terminal, and a reset node; the reset circuit is configured to transmit the first voltage signal to the reset node under the control of a reset signal transmitted at the reset signal terminal; the reset node includes either the third node or the fifth node.

[0019] In some examples, the third control circuit includes a thirteenth transistor. The gate of the thirteenth transistor is electrically connected to the fifth node, the first terminal of the thirteenth transistor is electrically connected to the second control signal terminal, and the second terminal of the thirteenth transistor is electrically connected to the first node. The fourth control circuit includes a fourteenth transistor and a fifteenth transistor. The gate of the fourteenth transistor is electrically connected to the first node, the first terminal of the fourteenth transistor is electrically connected to the fourth voltage signal terminal, and the second terminal of the fourteenth transistor is electrically connected to the first terminal of the fifteenth transistor. The gate of the fifteenth transistor is electrically connected to the second clock signal terminal, and the second terminal of the fifteenth transistor is electrically connected to the fifth node. The reset circuit includes a sixteenth transistor. The gate of the sixteenth transistor is electrically connected to the reset signal terminal, the first terminal of the sixteenth transistor is electrically connected to the first voltage signal terminal, and the second terminal of the sixteenth transistor is electrically connected to the reset node.

[0020] In some examples, the shift register further includes a third output circuit and a fourth output circuit. The third output circuit is electrically connected to the second node, the fourth voltage signal terminal, and the second output signal terminal; the third output circuit is configured to transmit a fourth voltage signal received at the fourth voltage signal terminal to the second output signal terminal under the control of the voltage of the second node. The fourth output circuit is electrically connected to the third node, the first voltage signal terminal, and the second output signal terminal; the fourth output circuit is configured to transmit the first voltage signal to the second output signal terminal under the control of the voltage of the third node.

[0021] In some examples, the second voltage signal terminal and the fourth voltage signal terminal are the same signal terminal; or, the second voltage signal terminal and the fourth voltage signal terminal are signal terminals that transmit different voltage signals, and the voltage of the second voltage signal is higher than the voltage of the fourth voltage signal.

[0022] In some examples, the first output circuit includes a second transistor and a first capacitor; the second output circuit includes a fifth transistor and a second capacitor. The third output circuit includes a seventeenth transistor. The gate of the seventeenth transistor is electrically connected to the second node, the first terminal of the seventeenth transistor is electrically connected to the fourth voltage signal terminal, and the second terminal of the seventeenth transistor is electrically connected to the second output signal terminal. The fourth output circuit includes an eighteenth transistor. The gate of the eighteenth transistor is electrically connected to the third node, the first terminal of the eighteenth transistor is electrically connected to the first voltage signal terminal, and the second terminal of the eighteenth transistor is electrically connected to the second output signal terminal.

[0023] In some examples, the first output circuit includes a second transistor, and the second output circuit includes a fifth transistor. The third output circuit includes a seventeenth transistor and a fifth capacitor. The gate of the seventeenth transistor is electrically connected to the second node, the first terminal of the seventeenth transistor is electrically connected to the fourth voltage signal terminal, and the second terminal of the seventeenth transistor is electrically connected to the second output signal terminal. The first terminal of the fifth capacitor is electrically connected to the second node, and the second terminal of the fifth capacitor is electrically connected to the fourth voltage signal terminal. The fourth output circuit includes an eighteenth transistor and a sixth capacitor. The gate of the eighteenth transistor is electrically connected to the third node, the first terminal of the eighteenth transistor is electrically connected to the first voltage signal terminal, and the second terminal of the eighteenth transistor is electrically connected to the second output signal terminal. The first terminal of the sixth capacitor is electrically connected to the third node, and the second terminal of the sixth capacitor is electrically connected to the second output signal terminal.

[0024] In some examples, the shift register further includes a fourth leakage protection circuit. The fourth leakage protection circuit is electrically connected to the second leakage protection signal terminal, the first voltage signal terminal, and the fourth leakage protection node. The fourth leakage protection circuit is configured to transmit the first voltage signal to the fourth leakage protection node under the control of the second leakage protection signal transmitted at the second leakage protection signal terminal. The second leakage protection signal terminal includes either the first output signal terminal or the second output signal terminal. The third output circuit is also electrically connected to the fourth leakage protection node.

[0025] In some examples, the fourth leakage protection circuit includes a nineteenth transistor. The gate of the nineteenth transistor is electrically connected to the second leakage protection signal terminal, the first terminal of the nineteenth transistor is electrically connected to the first voltage signal terminal, and the second terminal of the nineteenth transistor is electrically connected to the fourth leakage protection node. The seventeenth transistor includes a seventh sub-transistor and an eighth sub-transistor. The gate of the seventh sub-transistor is electrically connected to the second node, the first terminal of the seventh sub-transistor is electrically connected to the fourth voltage signal terminal, and the second terminal of the seventh sub-transistor is electrically connected to the fourth leakage protection node. The gate of the eighth sub-transistor is electrically connected to the second node, the first terminal of the eighth sub-transistor is electrically connected to the fourth leakage protection node, and the second terminal of the eighth sub-transistor is electrically connected to the second output signal terminal.

[0026] On the other hand, a driving method for a shift register is provided, the driving method being applied to a shift register as described in any of the above embodiments. The driving method includes: a first stage, a second stage, a third stage, and a fourth stage. In the first stage, in response to a first clock signal received at a first clock signal terminal, a first input circuit is turned on, transmitting a first voltage signal received at a first voltage signal terminal to a first node. In response to the first clock signal, a second input circuit is turned on, transmitting an input signal received at an input signal terminal to a third node. In the second stage, at least in response to a second clock signal received at a second clock signal terminal, a first control circuit is turned on, transmitting the second clock signal or an electrical signal from the first node to a second node. In the third stage, in response to a voltage at the second node, a first output circuit is turned on, transmitting a second voltage signal received at a second voltage signal terminal to a first output signal terminal. In the fourth stage, in response to the first clock signal, the second input circuit is turned on, transmitting the input signal to the third node. In response to a voltage at the third node, the second control circuit is turned on, transmitting a first control signal received at a first control signal terminal to a control node. In response to the voltage at the third node, the second output circuit is turned on, transmitting the first voltage signal to the first output signal terminal.

[0027] The above-described shift register driving method has the same beneficial technical effects as the shift registers provided in some of the above embodiments, and will not be described again here.

[0028] On the other hand, a scan driving circuit is provided, the scan driving circuit comprising: a plurality of shift registers as described in any of the above embodiments. The first output signal terminal of the Nth shift register is electrically connected to the input signal terminal of the (N+1)th shift register, where N is a positive integer.

[0029] The shift register included in the scan drive circuit described above has the same structure and beneficial technical effects as the shift registers provided in some of the above embodiments, and will not be described again here.

[0030] In another aspect, a scan driving circuit is provided, the scan driving circuit comprising: a plurality of shift registers as described in any of the above embodiments. The second output signal terminal of the Mth shift register is electrically connected to the input signal terminal of the (M+1)th shift register, where M is a positive integer.

[0031] In another aspect, a display device is provided, comprising a scan driving circuit as described in any of the above embodiments, and a plurality of pixel driving circuits. The pixel driving circuit includes a switching transistor, a sensing transistor, a driving transistor, a light-emitting control transistor, and a storage capacitor. A shift register in the scan driving circuit is electrically connected to the gate of the light-emitting control transistor.

[0032] The scanning drive circuit included in the above-described display device has the same structure and beneficial technical effects as the scanning drive circuit provided in some of the above embodiments, and will not be described again here. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the products involved in the embodiments of this disclosure, the actual timing of signals, etc.

[0034] Figure 1 This is a structural diagram of a display device according to some embodiments of the present disclosure;

[0035] Figure 2 This is a structural diagram of another display device according to some embodiments of the present disclosure;

[0036] Figure 3 This is a structural diagram of a sub-pixel according to some embodiments of the present disclosure;

[0037] Figure 4 According to some embodiments of this disclosure, one corresponding to Figure 3 The following is a timing diagram of the sub-pixels;

[0038] Figure 5 This is a structural diagram of a shift register according to some embodiments of the present disclosure;

[0039] Figure 6 Here is a circuit diagram of a shift register according to some embodiments of this disclosure;

[0040] Figure 7 This is a circuit diagram of another shift register according to some embodiments of the present disclosure;

[0041] Figure 8 This is a structural diagram of another shift register according to some embodiments of the present disclosure;

[0042] Figure 9Here is a circuit diagram of yet another shift register according to some embodiments of this disclosure;

[0043] Figure 10 This is a structural diagram of yet another shift register according to some embodiments of the present disclosure;

[0044] Figure 11 Here is a circuit diagram of yet another shift register according to some embodiments of this disclosure;

[0045] Figure 12 This is a structural diagram of yet another shift register according to some embodiments of the present disclosure;

[0046] Figure 13 Here is a circuit diagram of yet another shift register according to some embodiments of this disclosure;

[0047] Figure 14 Here is a circuit diagram of yet another shift register according to some embodiments of this disclosure;

[0048] Figure 15 This is a structural diagram of yet another shift register according to some embodiments of the present disclosure;

[0049] Figure 16 Here is a circuit diagram of yet another shift register according to some embodiments of this disclosure;

[0050] Figure 17 This is a structural diagram of yet another shift register according to some embodiments of the present disclosure;

[0051] Figure 18 Here is a circuit diagram of yet another shift register according to some embodiments of this disclosure;

[0052] Figure 19 This is a structural diagram of yet another shift register according to some embodiments of the present disclosure;

[0053] Figure 20 Here is a circuit diagram of yet another shift register according to some embodiments of this disclosure;

[0054] Figure 21 This is a structural diagram of yet another shift register according to some embodiments of the present disclosure;

[0055] Figure 22 Here is a circuit diagram of yet another shift register according to some embodiments of this disclosure;

[0056] Figure 23 Here is a circuit diagram of yet another shift register according to some embodiments of this disclosure;

[0057] Figure 24 This is a structural diagram of yet another shift register according to some embodiments of the present disclosure;

[0058] Figure 25 Here is a circuit diagram of yet another shift register according to some embodiments of this disclosure;

[0059] Figure 26 Here is a circuit diagram of yet another shift register according to some embodiments of this disclosure;

[0060] Figure 27 This is a structural diagram of yet another shift register according to some embodiments of the present disclosure;

[0061] Figure 28 Here is a circuit diagram of yet another shift register according to some embodiments of this disclosure;

[0062] Figure 29 Here is a circuit diagram of yet another shift register according to some embodiments of this disclosure;

[0063] Figure 30 This is a timing simulation diagram of one of the embodiments of this disclosure;

[0064] Figure 31 According to some embodiments of this disclosure, one corresponding to Figure 29 The timing simulation diagram of the shift register shown is shown below;

[0065] Figure 32 This is a structural diagram of yet another shift register according to some embodiments of the present disclosure;

[0066] Figure 33 Here is a circuit diagram of yet another shift register according to some embodiments of this disclosure;

[0067] Figure 34 Here is a circuit diagram of yet another shift register according to some embodiments of this disclosure;

[0068] Figure 35 This is a structural diagram of yet another shift register according to some embodiments of the present disclosure;

[0069] Figure 36 Here is a circuit diagram of yet another shift register according to some embodiments of this disclosure;

[0070] Figure 37 According to some embodiments of this disclosure, one corresponding to Figure 13 The diagram shown is a timing diagram of one type of shift register.

[0071] Figure 38 This is a structural diagram of a scanning drive circuit according to some embodiments of the present disclosure;

[0072] Figure 39This is a structural diagram of another scanning drive circuit according to some embodiments of the present disclosure. Detailed Implementation

[0073] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0074] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0075] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0076] In describing some embodiments, the term "connection" and its derivative expressions may be used. For example, the term "connection" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0077] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0078] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0079] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0080] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0081] The transistors used in the circuits (e.g., shift registers) provided in the embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics.

[0082] In some embodiments, the first electrode of each transistor used in the shift register is one of the source and drain electrodes of the transistor, and the second electrode is the other of the source and drain electrodes of the transistor. Since the source and drain of a transistor can be structurally symmetrical, they can be structurally indistinguishable; that is, the first and second electrodes of the transistors in the embodiments of this disclosure can be structurally indistinguishable. For example, when the transistor is a P-type transistor, the first electrode is the source and the second electrode is the drain; for example, when the transistor is an N-type transistor, the first electrode is the drain and the second electrode is the source.

[0083] For example, a P-type transistor can be turned on under the control of a low-level signal, and an N-type transistor can be turned on under the control of a high-level signal.

[0084] In the circuits provided in the embodiments of this disclosure, "node" does not refer to an actual component, but rather to a junction of related electrical connections in the circuit diagram. In other words, these nodes are equivalent to junctions of related electrical connections in the circuit diagram.

[0085] The circuits provided in the embodiments of this disclosure will be described below using N-type transistors as an example.

[0086] On the one hand, in the display field, such as OLED displays, image ghosting occurs during dynamic image transitions. However, the pixel driving circuits in related technologies struggle to achieve short time intervals and high frequencies for black pixel insertion, thus limiting the improvement of image ghosting and making it easy for the human eye to detect the inserted black pixels, resulting in a flickering display.

[0087] On the other hand, the transistors used in the shift register of the display device are LTPS (Low Temperature Poly-silicon) transistors. The initial threshold voltages of different low temperature poly-silicon transistors are generally not easy to keep consistent. This can easily reduce the stability of the electrical signal output by the shift register, which can easily lead to unevenness in the display screen of the display device.

[0088] Based on this, such as Figure 1 As shown, some embodiments of this disclosure provide a display device 1000.

[0089] For example, the display device 1000 can be any device that displays text or images, whether moving (e.g., video) or stationary (e.g., still images). More specifically, the embodiments described are contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal digital assistants (PDAs), handheld or portable computers, Global Positioning System (GPS) receivers / navigators, cameras, Moving Picture Experts Group 4 (MP4) video players, camcorders, game consoles, watches, clocks, calculators, television monitors, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0090] In some examples, such as Figure 2 As shown, the display device 1000 may include: a substrate 200, and a plurality of sub-pixels P, a plurality of gate lines GL and a plurality of data lines DL disposed on one side of the substrate 200.

[0091] The substrate 200 mentioned above includes various types, which can be selected and set according to actual needs.

[0092] For example, substrate 200 can be a rigid substrate. The rigid substrate can be, for example, a glass substrate or a PMMA (Polymethyl methacrylate) substrate.

[0093] For example, the substrate 200 can be a flexible substrate. The flexible substrate can be, for example, a PET (Polyethylene terephthalate) substrate, a PEN (Polyethylene naphthalate twoformic acid glycol ester) substrate, or a PI (Polyimide) substrate, etc.

[0094] In some examples, such as Figure 2 As shown, the display device 1000 has a display area A and a peripheral area B disposed next to the display area A. Here, "next to" refers to one side, two sides, three sides, or the perimeter of the display area A, that is, the peripheral area B can be located on one side, two sides, or three sides of the display area A, or the peripheral area B can be disposed around the display area A.

[0095] In some examples, such as Figure 2 As shown, the aforementioned multiple sub-pixels P, multiple gate lines GL, and multiple data lines DL can be located within the display area A, and the multiple gate lines GL can extend along the first direction X, and the multiple data lines DL can extend along the second direction Y.

[0096] Here, the first direction X and the second direction Y intersect each other. The angle between the first direction X and the second direction Y can be selected and set according to actual needs. For example, the angle between the first direction X and the second direction Y can be 85°, 88°, 90°, 92° or 95°, etc.

[0097] In some examples, such as Figure 3 As shown, each of the above-mentioned multiple sub-pixels P may include a pixel driving circuit 300 and a light-emitting device L electrically connected to the pixel driving circuit 300.

[0098] For example, the light-emitting device L can be an OLED.

[0099] For example, the aforementioned multiple sub-pixels P can be arranged in an array, that is, the multiple sub-pixels P can be arranged in multiple rows along the first direction X and multiple rows along the second direction Y. Sub-pixels P arranged in a row along the first direction X can be called row-level sub-pixels P, and sub-pixels P arranged in a row along the second direction Y can be called column-level sub-pixels P. Multiple pixel driving circuits 300 in the same row of sub-pixels P can be electrically connected to at least one gate line GL, and multiple pixel driving circuits 300 in the same column of sub-pixels P can be electrically connected to one data line DL. The number of gate lines GL electrically connected to the multiple pixel driving circuits 300 in the same row of sub-pixels P can be set according to the structure of the pixel driving circuit 300. This disclosure uses the example of multiple pixel driving circuits 300 in the same row of sub-pixels P being electrically connected to one gate line GL for illustration.

[0100] Of course, such as Figure 2 As shown, according to the structure of the pixel driving circuit 300, the display device 1000 may further include: a plurality of enable signal lines EL disposed on one side of the substrate 200 and extending along the first direction X.

[0101] For example, an enable signal line EL can be electrically connected to multiple pixel driving circuits 300 in the same row of sub-pixels P.

[0102] During the display process of the display device 1000, the sub-pixel P can receive a scan signal from the corresponding gate line GL, a data signal from the corresponding data line DL, and an enable signal from the corresponding enable signal line EL, forming a driving voltage to drive the light-emitting device L in the sub-pixel P to emit light. Multiple sub-pixels P cooperate with each other to enable the display device 1000 to display an image.

[0103] In some examples, such as Figure 3 As shown, the pixel driving circuit 300 includes: a switching transistor M1, a driving transistor M2, a sensing transistor M3, a light-emitting control transistor M4, and a storage capacitor C.

[0104] For example, such as Figure 3 As shown, the gate of the switching transistor M1 is electrically connected to the first scan signal terminal G1, the first terminal of the switching transistor M1 is electrically connected to the data signal terminal DATA, and the second terminal of the switching transistor M1 is electrically connected to the data node G. The switching transistor M1 is configured to transmit the data signal received at the data signal terminal DATA to the data node G under the control of the first scan signal transmitted at the first scan signal terminal G1.

[0105] For example, such as Figure 3As shown, the gate of the light-emitting control transistor M4 is electrically connected to the enable signal terminal EM, the first terminal of the light-emitting control transistor M4 is electrically connected to the fifth voltage signal terminal ELVDD, and the second terminal of the control transistor M4 is electrically connected to the first terminal of the driving transistor M2. The light-emitting control transistor M4 is configured to, under the control of the enable signal transmitted at the enable signal terminal EM, transmit the fifth voltage signal received at the fifth voltage signal terminal ELVDD to the first terminal of the driving transistor M2.

[0106] For example, such as Figure 3 As shown, the gate of the driving transistor M2 is electrically connected to the data node G, the first terminal of the driving transistor M2 is electrically connected to the second terminal of the light-emitting control transistor M4, and the second terminal of the driving transistor M2 is electrically connected to the sensing node S. The driving transistor M2 is configured to conduct under the control of the voltage of the data node G, receiving and transmitting a fifth voltage signal to the sensing node S.

[0107] For example, such as Figure 3 As shown, the first terminal of the storage capacitor C is electrically connected to the data node G, and the second terminal of the storage capacitor C is electrically connected to the sensing node S. The switching transistor M1 charges the storage capacitor C simultaneously while charging the data node G.

[0108] For example, such as Figure 3 As shown, the gate of sensing transistor M3 is electrically connected to the second scan signal terminal G2, the first terminal of sensing transistor M3 is electrically connected to the sensing signal terminal SENSE, and the second terminal of sensing transistor M3 is electrically connected to the sensing node S. Sensing transistor M3 is configured to detect the electrical characteristics of sensing node S under the control of the second scan signal transmitted through the second scan signal terminal G2, in order to achieve external compensation. These electrical characteristics include, for example, the threshold voltage and / or carrier mobility of driving transistor M2.

[0109] Here, the sensing signal terminal SENSE can provide a reset signal VREF (for example, when the first switch K1 is closed, the reset signal VREF is transmitted to the sensing signal terminal SENSE) or acquire a sensing signal (for example, when the second switch K2 is closed, the sensing signal is transmitted to the digital-to-analog converter ADC). The reset signal is used to reset the sensing node S, and the acquired sensing signal is used, for example, to acquire the threshold voltage of the driving transistor M2.

[0110] For example, such as Figure 3 As shown, the anode of the light-emitting device L is electrically connected to the sensing node S, and the cathode of the light-emitting device L is electrically connected to the sixth voltage signal terminal ELVSS. The light-emitting device L is configured to emit light in conjunction with the fifth voltage signal from the sensing node S and the sixth voltage signal transmitted from the sixth voltage signal terminal ELVSS.

[0111] Since multiple pixel driving circuits 300 in the same row of sub-pixels P are electrically connected to a gate line GL, the first scan signal terminal G1 and the second scan signal terminal G2 of the same pixel driving circuit 300 receive and transmit the same scan signal.

[0112] In an image frame, the operation of the pixel driving circuit 300 may include, for example, a blanking stage and a driving stage. The blanking stage may be used, for example, to obtain the threshold voltage of the driving transistor M2. The specific operation of the blanking stage will not be described in detail here. Figure 4 As shown, the aforementioned driving phase may include, for example, a reset and data writing phase t1 and a display phase t2.

[0113] like Figure 4 As shown, the reset and data writing phase t1 can be divided into reset phase ① and data writing phase ②.

[0114] During the reset phase ①, the levels of the first scan signal and the second scan signal are high, and the level of the data signal is low.

[0115] At this time, switching transistor M1 is turned on under the control of the first scan signal, transmitting the data signal to data node G and resetting data node G. Sensing transistor M3 is turned on under the control of the second scan signal, transmitting the reset signal to sensing node S and resetting sensing node S.

[0116] During the data writing phase ②, the levels of the first scan signal and the second scan signal are high, the level of the enable signal is high, and the level of the data signal is high.

[0117] At this time, the switching transistor M1 remains on, transmitting the data signal to the data node G, causing the data node G to be at a high level, and charging the storage capacitor C. The light-emitting control transistor M4 is turned on under the control of the enable signal, transmitting the fifth voltage signal to the first terminal of the driving transistor M2.

[0118] like Figure 4 As shown, stage t2 can be divided into alternating light-up stage ③ and black-insertion stage ④.

[0119] During the light emission stage ③, the levels of the first and second scan signals are low, while the level of the enable signal is high.

[0120] At this time, switching transistor M1 and sensing transistor M3 are turned off, causing storage capacitor C to begin discharging and maintaining the potential of data node G at a high level. Light-emitting control transistor M4 is turned on under the control of the enable signal, transmitting the fifth voltage signal to the first terminal of driving transistor M2. Driving transistor M2 is turned on under the control of data node G, transmitting the fifth voltage signal to sensing node S, causing the potential of sensing node S to rise. Due to the bootstrap effect of storage capacitor C, the potential of data node G is further raised and maintained at a high level for a period of time. Thus, based on the fifth voltage signal from sensing node S and the sixth voltage signal transmitted from the sixth voltage signal terminal ELVSS, the light-emitting device L is driven to emit light.

[0121] During the black insertion phase ④, the enable signal level is low.

[0122] At this time, the light-emitting control transistor M4 is turned off under the control of the enable signal, cutting off the transmission of the fifth voltage signal. Consequently, the fifth voltage signal cannot be transmitted to the anode of the light-emitting device L, thus causing the light-emitting device L to stop emitting light.

[0123] By alternating between the light-emitting stage ③ and the black-insertion stage ④ within an image frame, the light-emitting device L can alternately emit light and stop emitting light during the display of a frame. This reduces the light-emitting duration of the light-emitting device L within an image frame, enhances the dynamic image response time, and achieves black-insertion with shorter time intervals and higher frequency. This prevents black images from being captured by the human eye and thus avoids the human eye seeing flickering display images.

[0124] In some embodiments, the display device 1000 further includes a scan driving circuit 400. The scan driving circuit 400 and the aforementioned plurality of sub-pixels P, gate lines GL, data lines DL and enable signal lines EL may be located on the same side of the substrate 200.

[0125] In some embodiments, the scan driving circuit 400 includes a plurality of shift registers 100. The shift registers 100 are electrically connected to the gate of the light-emitting control transistor M4 of the pixel driving circuit 300 to provide an enable signal.

[0126] The following is combined with Figures 5-9 The structure of shift register 100 is illustrated schematically.

[0127] In some embodiments, such as Figures 5-9 As shown, the shift register 100 includes: a first input circuit 1, a first control circuit 2, a first output circuit 3, a second input circuit 4, a second control circuit 5, and a second output circuit 6.

[0128] In some examples, such as Figures 5-9As shown, the first input circuit 1 is electrically connected to the first voltage signal terminal V1, the first clock signal terminal CKA, and the first node N1. The first input circuit 1 is configured to transmit the first voltage signal received at the first voltage signal terminal V1 to the first node N1 under the control of the first clock signal transmitted at the first clock signal terminal CKA.

[0129] For example, when the first clock signal is high, the first input circuit 1 can receive and transmit the first voltage signal to the first node N1 under the control of the first clock signal.

[0130] Optionally, the first voltage signal terminal V1 is configured to transmit a first DC high-level signal (e.g., a portion of the clock signal that is higher than or equal to the high level of the clock signal). Here, this first DC high-level signal is referred to as the first voltage signal.

[0131] In some examples, such as Figures 5-9 As shown, the first control circuit 2 is electrically connected to at least the first node N1, the second clock signal terminal CKB, and the second node N2. The first control circuit 2 is configured to transmit the second clock signal or an electrical signal from the first node N1 to the second node N2 under the control of the second clock signal transmitted at least at the second clock signal terminal CKB.

[0132] Here, the first control circuit 2 has multiple configuration options, which can be selected according to actual needs.

[0133] For example, such as Figures 5-7 As shown, the first control circuit 2 is electrically connected to the first node N1, the second clock signal terminal CKB, and the second node N2. The first control circuit 2 is configured to transmit the second clock signal to the second node N2 under the control of the voltage at the first node N1 and the second clock signal.

[0134] For example, when the voltage at the first node N1 is high and the level of the second clock signal is high, the first control circuit 2 can receive and transmit the second clock signal to the second node N2 under the joint control of the voltage at the first node N1 and the second clock signal.

[0135] For example, such as Figure 8 and Figure 9 As shown, the first control circuit 2 is electrically connected to the first node N1, the second clock signal terminal CKB, the second node N2, and the second voltage signal terminal V2. The first control circuit 2 is configured to transmit the electrical signal from the first node N1 to the second node N2 under the control of the second clock signal.

[0136] For example, when the level of the second clock signal is high, the first control circuit 2 can be turned on under the control of the second clock signal to receive and transmit the above-mentioned electrical signal to the second node N2.

[0137] It is understood that when the first node N1 is not electrically connected to other circuits, the voltage of the first node N1 is controlled by the first voltage signal transmitted by the first input circuit 1. Accordingly, the electrical signal from the first node N1 is the first voltage signal. When the first node N1 is electrically connected to other circuits (such as the third control circuit mentioned below), the voltage of the first node N1 is jointly determined by the first voltage signal transmitted by the first input circuit 1 and the electrical signal transmitted by the other circuit. Accordingly, the electrical signal from the first node N1 can be either the first voltage signal or the electrical signal transmitted by the other circuit.

[0138] In some examples, such as Figures 5-9 As shown, the first output circuit 3 is electrically connected to the second voltage signal terminal V2, the second node N2, and the first output signal terminal OUT1. The first output circuit 3 is configured to transmit the second voltage signal received at the second voltage signal terminal V2 to the first output signal terminal OUT1 under the control of the voltage of the second node N2, so that the first output signal terminal OUT1 outputs the first output signal.

[0139] For example, when the voltage of the second node N2 is high, the first output circuit 3 can be turned on under the control of the voltage of the second node N2 to receive and transmit the second voltage signal to the first output signal terminal OUT1.

[0140] Optionally, the second voltage signal terminal V2 is configured to transmit a first DC low-level signal (e.g., a portion of the clock signal that is lower than or equal to the low level of the clock signal). This first DC low-voltage signal is referred to here as the second voltage signal.

[0141] It should be noted that the terms "high level" and "low level" mentioned in this article are only relative and do not limit the relationship between the voltage value of a high-level signal and 0V, nor do they limit the relationship between the voltage value of a low-level signal and 0V.

[0142] In some examples, such as Figures 5-9 As shown, the second input circuit 4 is electrically connected to the input signal terminal INPUT, the first clock signal terminal CKA, and the third node N3. The second input circuit 4 is configured to transmit the input signal received at the input signal terminal INPUT to the third node N3 under the control of the first clock signal.

[0143] For example, when the level of the first clock signal is high, the second input circuit 4 can be turned on under the control of the first clock signal to receive and transmit the input signal to the third node N3.

[0144] In some examples, such as Figures 5-9 As shown, the second control circuit 5 is electrically connected to the third node N3, the first control signal terminal E1, and the control node Q. The second control circuit 5 is configured to transmit the first control signal received at the first control signal terminal E1 to the control node Q under the control of the voltage of the third node N3. The control node Q includes either the first node N1 or the second node N2.

[0145] For example, when the voltage of the third node N3 is high, the second control circuit 5 can be turned on under the control of the voltage of the third node N3 to receive and transmit the first control signal to the control node Q.

[0146] Here, there are several ways to configure the first control signal terminal E1, which can be selected according to actual needs. Among them, the above configuration method is related to the control node Q.

[0147] For example, such as Figure 6 and Figure 7 As shown, the control node Q is the second node N2.

[0148] For example, the first control signal terminal E1 can be the fourth voltage signal terminal V4.

[0149] Optionally, the fourth voltage signal terminal V4 is configured to transmit a second DC low-level signal (e.g., a portion of the clock signal that is lower than or equal to the low level of the clock signal). This second DC low-voltage signal is referred to here as the fourth voltage signal.

[0150] At this time, when the voltage of the third node N3 is high, the second control circuit 5 can be turned on under the control of the voltage of the third node N3, receive and transmit the fourth voltage signal to the second node N2, discharge and reset the second node N2, so that the first output circuit 3 is turned off.

[0151] This ensures that the first output circuit 3 is off while the voltage at the third node N3 is high, thus turning on the second output circuit 6, thereby avoiding affecting the accuracy of the electrical signal output from the first output signal terminal OUT1.

[0152] For example, such as Figure 9 As shown, the control node Q is the first node N1.

[0153] For example, the first control signal terminal E1 can be the first clock signal terminal CKA or the fourth voltage signal terminal V4.

[0154] It should be noted that the high-level periods of the first clock signal and the second clock signal do not overlap. That is, when the first clock signal is high, the second clock signal is low; and when the second clock signal is high, the first clock signal is low.

[0155] At this time, when the voltage of the third node N3 is high, the second control circuit 5 can be turned on under the control of the voltage of the third node N3, receiving and transmitting the first clock signal or the fourth voltage signal to the first node N1. This can discharge and reset the first node N1, so that the first control circuit 2 is in the off state, or when the first control circuit 2 is in the on state, the first clock signal or the fourth voltage signal is transmitted to the second node N2.

[0156] This ensures that the first output circuit 3 is off while the voltage at the third node N3 is high, thus turning on the second output circuit 6, thereby avoiding affecting the accuracy of the electrical signal output from the first output signal terminal OUT1.

[0157] In some examples, such as Figures 5-9 As shown, the second output circuit 6 is electrically connected to the first voltage signal terminal V1, the third node N3, and the first output signal terminal OUT1. The second output circuit 6 is configured to transmit the first voltage signal to the first output signal terminal OUT1 under the control of the voltage of the third node N3.

[0158] For example, when the voltage of the third node N3 is high, the second output circuit 6 can be turned on under the control of the voltage of the third node N3, receive and transmit the first voltage signal to the first output signal terminal OUT1, so that the first output signal terminal OUT1 outputs the first output signal.

[0159] It is understandable that, based on the electrical connections of the circuits in the shift register 100, the first output circuit 3 and the second output circuit 6 can be turned on at different times. When the first output circuit 3 is turned on, the second voltage signal can be output as the first output signal from the first output signal terminal OUT1; when the second output circuit 6 is turned on, the first voltage signal can be output as the first output signal from the first output signal terminal OUT1.

[0160] In an image frame, the conduction state of the first output circuit 3 and the second output circuit 6 can be achieved by utilizing the cooperation between the signal terminals.

[0161] For example, during the display phase t2 of an image frame, the first output circuit 3 can be continuously turned on, so that the second voltage signal output by the first output circuit 3 constitutes the first output signal. This first output signal can be transmitted as an enable signal to the gate of the light-emitting control transistor M4 in the sub-pixel P, so that the light-emitting control transistor M4 remains in the off state during the display phase t2, causing the light-emitting device L to stop emitting light, thereby causing the display device 1000 to display a black screen.

[0162] For example, during the display phase t2 of an image frame, the second output circuit 6 can be continuously turned on, so that the first voltage signal output by the second output circuit 6 constitutes the first output signal. This first output signal can be transmitted as an enable signal to the gate of the light-emitting control transistor M4 in the sub-pixel P, so that the light-emitting control transistor M4 remains turned on during the display phase t2, causing the light-emitting device L to continuously emit light, thereby enabling the display device 1000 to display an image.

[0163] For example, in the display phase t2 of an image frame, the first output circuit 3 and the second output circuit 6 can be turned on at different time periods, so that the second voltage signal output by the first output circuit 3 and the first voltage signal output by the second output circuit 6 together constitute the first output signal. This first output signal can be transmitted as an enable signal to the gate of the light-emitting control transistor M4 in the sub-pixel P, so that the light-emitting control transistor M4 alternately turns on and off in the display phase t2, so that the light-emitting device L alternately emits light and stops emitting light, thereby alternating between the light-emitting phase ③ and the black-insertion phase ④, reducing the light-emitting duration of the light-emitting device L in an image frame, enhancing the dynamic image response time, and achieving black-insertion with a shorter time interval and a higher frequency, thus preventing the black screen from being captured by the human eye, and thus preventing the human eye from seeing a flickering display.

[0164] In some examples, the first input circuit 1, the first control circuit 2, the first output circuit 3, the second input circuit 4, the second control circuit 5, and the second output circuit 6 each include at least one transistor. All transistors are oxide transistors.

[0165] This disclosure does not limit the number of transistors included in any one of the first input circuit 1, the first control circuit 2, the first output circuit 3, the second input circuit 4, the second control circuit 5, and the second output circuit 6, and the specific selection and setting can be made according to actual needs.

[0166] For example, the number of transistors included in any one of the first input circuit 1, the first control circuit 2, the first output circuit 3, the second input circuit 4, the second control circuit 5, and the second output circuit 6 can be 1, 2, 3, 5, etc.

[0167] By setting the transistors included in the above circuits as oxide transistors, it can be ensured that the initial threshold voltages of each transistor are similar or equal. In this way, after the electrical signal flows through the corresponding transistor, there will be basically no significant difference. This makes the transmission of each electrical signal between the first input circuit 1, the first control circuit 2, the first output circuit 3, the second input circuit 4, the second control circuit 5, and the second output circuit 6 relatively stable. Consequently, the first output signal output from the first output signal terminal OUT1 is relatively stable. Then, after providing the first output signal as an enable signal to the light-emitting control transistor M4, it is beneficial to improve the uniformity of the brightness of the light emitted by different light-emitting devices L, thereby improving the uniformity of the display screen of the display device 1000.

[0168] The following is a schematic description of the structure of the first input circuit 1, the first control circuit 2, the first output circuit 3, the second input circuit 4, the second control circuit 5, and the second output circuit 6 included in the shift register 100, with reference to the accompanying drawings.

[0169] In some examples, such as Figure 6 As shown, the first input circuit 1 includes a first transistor T1. The gate of the first transistor T1 is electrically connected to the first clock signal terminal CKA, the first terminal of the first transistor T1 is electrically connected to the first voltage signal terminal V1, and the second terminal of the first transistor T1 is electrically connected to the first node N1.

[0170] For example, when the level of the first clock signal is high, the first transistor T1 can be turned on under the control of the first clock signal to receive and transmit the first voltage signal to the first node N1 and charge the first node N1.

[0171] It is understandable that the structure of the first control circuit 2 can change according to the setting method.

[0172] In some examples, such as Figure 6 and Figure 7 As shown, the first control circuit 2 is electrically connected to the first node N1, the second clock signal terminal CKB, and the second node N2. The first control circuit 2 is configured to transmit the second clock signal to the second node N2 under the control of the voltage at the first node N1 and the second clock signal.

[0173] In this case, the first control circuit 2 includes, for example, a seventh transistor T7, an eighth transistor T8, and a third capacitor C3.

[0174] For example, the gate of the seventh transistor T7 is electrically connected to the first node N1, the first terminal of the seventh transistor T7 is electrically connected to the second clock signal terminal, and the second terminal of the seventh transistor T7 is electrically connected to the fourth node N4. The gate of the eighth transistor T8 is electrically connected to the second clock signal terminal CKB, the first terminal of the eighth transistor T8 is electrically connected to the fourth node N4, and the second terminal of the eighth transistor T8 is electrically connected to the second node N2. The first terminal of the third capacitor C3 is electrically connected to the first node N1, and the second terminal of the third capacitor C3 is electrically connected to either the second clock signal terminal CKB or the fourth node N4.

[0175] For example, when the voltage level of the first node N1 is high, the seventh transistor T7 can be turned on under the control of the voltage of the first node N1 to receive and transmit the second clock signal to the fourth node N4. When the voltage level of the second clock signal is high, the eighth transistor T8 can be controlled by the second clock signal to transmit the second clock signal at the fourth node N4 to the second node N2.

[0176] Understandably, during the process of transmitting the first voltage signal to the first node N1 by the first transistor T1 in the first input circuit 1, the third capacitor C3 will also be charged. When the first transistor T1 is turned off, the third capacitor C3 can discharge, maintaining the voltage of the first node N1 at a high voltage, thus keeping the seventh transistor T7 in the conducting state.

[0177] It should be noted that when the second terminal of the third capacitor C3 is electrically connected to the second clock signal terminal CKB, due to the coupling effect of the third capacitor C3, the voltage of the first node N1 will also rise after the level of the second clock signal jumps from low to high. This helps to ensure that the seventh transistor T7 is fully turned on, avoiding loss to the second clock signal it transmits.

[0178] In other examples, such as Figure 9 As shown, the first control circuit 2 is electrically connected to the first node N1, the second clock signal terminal CKB, the second node N2, and the second voltage signal terminal V2. The first control circuit 2 is configured to transmit the first voltage signal from the first node N1 to the second node N2 under the control of the second clock signal.

[0179] In this case, the first control circuit 2 includes, for example, a ninth transistor T9 and a fourth capacitor C4.

[0180] For example, the gate of the ninth transistor T9 is electrically connected to the second clock signal terminal CKB, the first terminal of the ninth transistor T9 is electrically connected to the first node N1, and the second terminal of the ninth transistor is electrically connected to the second node N2. The first terminal of the fourth capacitor C4 is electrically connected to the first node N1, and the second terminal of the fourth capacitor C4 is electrically connected to the second voltage signal terminal V2.

[0181] For example, when the level of the second clock signal is high, the ninth transistor T9 can be turned on under the control of the second clock signal to transmit the electrical signal at the first node N1 to the second node N2.

[0182] It is understandable that during the process of the first transistor T1 transmitting the first voltage signal to the first node N1 in the first input circuit 1, the fourth capacitor C4 will also be charged. When the first transistor T1 is turned off, the fourth capacitor C4 can discharge, maintaining the voltage of the first node N1 at a high voltage.

[0183] In some examples, such as Figure 6 , Figure 7 and Figure 9 As shown, the first output circuit 3 includes a second transistor T2 and a first capacitor C1.

[0184] For example, the gate of the second transistor T2 is electrically connected to the second node N2, the first terminal of the second transistor T2 is electrically connected to the second voltage signal terminal V2, and the second terminal of the second transistor T2 is electrically connected to the first output signal terminal OUT1. The first terminal of the first capacitor C1 is electrically connected to the second node N2, and the second terminal of the first capacitor C1 is electrically connected to the second voltage signal terminal V2.

[0185] For example, when the level of the second node N2 is high, the second transistor T2 can be turned on under the control of the voltage of the second node N2, and receive and transmit the second voltage signal to the first output signal terminal OUT1.

[0186] Understandably, during the process of transmitting the second clock signal to the second node N2 using the seventh transistor T7 and the eighth transistor T8 in the first control circuit 2, the first capacitor C1 is also charged. When the first control circuit 2 is turned off, the first capacitor C1 can discharge, maintaining the voltage of the second node N2 at a high voltage, thus keeping the second transistor T2 in a conducting state.

[0187] Alternatively, during the process of transmitting the electrical signal from the first node N1 to the second node N2, the ninth transistor T9 in the first control circuit 2 also charges the first capacitor C1. When the first control circuit 2 is turned off, the first capacitor C1 can discharge, maintaining the voltage of the second node N2 at a high voltage, thus keeping the second transistor T2 in a conducting state.

[0188] In some examples, such as Figure 6 , Figure 7 and Figure 9 As shown, the second input circuit 4 includes a third transistor T3.

[0189] For example, the gate of the third transistor T3 is electrically connected to the first clock signal terminal CKA, the first terminal of the third transistor T3 is electrically connected to the input signal terminal INPUT, and the second terminal of the third transistor T3 is electrically connected to the third node N3.

[0190] For example, when the level of the first clock signal is high, the third transistor T3 can be turned on under the control of the first clock signal to receive and transmit the input signal to the third node N3.

[0191] In some examples, such as Figure 6 , Figure 7 and Figure 9 As shown, the second control circuit 5 includes: a fourth transistor T4.

[0192] For example, the gate of the fourth transistor T4 is electrically connected to the third node N3, the first terminal of the fourth transistor T4 is electrically connected to the first control signal terminal E1, and the second terminal of the fourth transistor T4 is electrically connected to the control node Q.

[0193] For example, when the voltage of the third node N3 is high, the fourth transistor T4 can be turned on under the control of the voltage of the third node N3, and receive and transmit the first control signal to the control node Q.

[0194] In some examples, such as Figure 6 , Figure 7 and Figure 9 As shown, the second output circuit 6 includes: a fifth transistor T5 and a second capacitor C2.

[0195] For example, the gate of the fifth transistor T5 is electrically connected to the third node N3, the first terminal of the fifth transistor T5 is electrically connected to the first voltage signal terminal V1, and the second terminal of the fifth transistor T5 is electrically connected to the first output signal terminal OUT1. The first terminal of the second capacitor C2 is electrically connected to the third node N3, and the second terminal of the second capacitor C2 is electrically connected to the first output signal terminal OUT1.

[0196] For example, when the voltage of the third node N3 is high, the fifth transistor T5 can be turned on under the control of the voltage of the third node N3, and receive and transmit the first voltage signal to the first output signal terminal OUT1.

[0197] Understandably, the second capacitor C2 serves to store and discharge charge. For example, the second capacitor C2 can discharge to maintain a high voltage at the third node N3, thus keeping the fifth transistor T5 in a conducting state.

[0198] In some embodiments, such as Figure 10 and Figure 11 As shown, the shift register 100 also includes a voltage regulator circuit 7.

[0199] In some examples, the voltage regulator circuit 7 is electrically connected to the first voltage signal terminal V1, the third node N3, and the fifth node N5. The second input circuit 4 is also electrically connected to the fifth node N5 and, through the voltage regulator circuit 7, to the third node N3. The second input circuit 4 is configured to transmit the first input signal to the fifth node N5 under the control of the first clock signal. The voltage regulator circuit 7 is configured to transmit the electrical signal from the fifth node N5 to the third node N3 under the control of the first voltage signal.

[0200] For example, when both the second input circuit 4 and the voltage regulator circuit 7 are on, the input signal transmitted by the second input circuit 4 can be transmitted sequentially to the third node N3 via the fifth node N5 and the voltage regulator circuit 7. When the voltage regulator circuit 7 is off, the conductive path between the third node N3 and the fifth node N5 is cut off, and the input signal transmitted by the second input circuit 4 cannot be transmitted to the third node N3, nor can the electrical signal at the third node N3 be transmitted to the fifth node N5.

[0201] This helps improve the stability of the voltage at the third node N3.

[0202] Understandably, when the fifth node N5 is not electrically connected to other circuits, its voltage is controlled by the input signal transmitted by the second input circuit 4. Accordingly, the electrical signal from the fifth node N5 is the input signal. When the fifth node N5 is electrically connected to other circuits (such as the fourth control circuit mentioned below), its voltage is determined by both the input signal transmitted by the second input circuit 4 and the electrical signal transmitted by the other circuit. Accordingly, the electrical signal from the fifth node N5 can be either the input signal or the electrical signal transmitted by the other circuit.

[0203] It is worth mentioning that when the shift register 100 also includes a voltage regulator circuit 7, the control node Q in the second control circuit 5 is the second node N2. In this case, the second control circuit 5 is electrically connected to the third node N3, the first control signal terminal E1, and the second node N2. Correspondingly, the first control signal terminal E1 can be the fourth voltage signal terminal V4.

[0204] In this example, such as Figure 11 As shown, in the second input circuit 4, the second terminal of the third transistor T3 is electrically connected to the fifth node N5. In the second control circuit 5, the second terminal of the fourth transistor T4 is electrically connected to the second node N2.

[0205] In some examples, such as Figure 11 As shown, the voltage regulator circuit 7 includes a tenth transistor T10. The gate of the tenth transistor T10 is electrically connected to the first voltage signal terminal V1, the first terminal of the tenth transistor T10 is electrically connected to the fifth node N5, and the second terminal of the tenth transistor T10 is electrically connected to the third node N3.

[0206] Since the first voltage signal is a high-level signal, the tenth transistor T10 can remain in the conducting state under the control of the first voltage signal, receiving and transmitting electrical signals from the fifth node N5 to the third node N3.

[0207] When the second output circuit 6 is on and the first output circuit 3 is off, the level of the first output signal jumps from low to high. Based on the coupling effect (or bootstrapping effect) of the second capacitor C2, the voltage at the third node N3 can be further increased, which in turn makes the voltage at the second terminal of the tenth transistor T10 slightly higher than the voltage at the gate of the tenth transistor T10, thus turning off the tenth transistor T10. In this way, when the threshold voltage of the third transistor T3 included in the second input circuit 4 is negatively biased, leakage current from the second output circuit 6 through the third transistor T3 can be prevented, thereby ensuring that the voltage at the third node N3 can be maintained at a relatively high and stable voltage. This, in turn, ensures that the fifth transistor T5 is in a stable and relatively complete conducting state, so that the first voltage signal transmitted to the first output signal terminal OUT1 can be maintained at a relatively high and stable voltage.

[0208] For example, the tenth transistor T10 can be an oxide transistor.

[0209] In some embodiments, the shift register 100 further includes at least one of the third control circuit 8, the fourth control circuit 9, and the reset circuit 10. That is, the shift register 100 may include one or more of the third control circuit 8, the fourth control circuit 9, and the reset circuit 10.

[0210] For example, such as Figures 12-16As shown, the shift register 100 also includes a third control circuit 8 and a fourth control circuit 9.

[0211] For example, such as Figures 17-20 As shown, the shift register 100 also includes a third control circuit 8, a fourth control circuit 9, and a reset circuit 10.

[0212] In some examples, such as Figures 12-20 As shown, the third control circuit 8 is electrically connected to the fifth node N5, the second control signal terminal E2, and the first node N1. The third control circuit 8 is configured to transmit the second control signal received at the second control signal terminal E2 to the first node N1 under the control of the voltage of the fifth node N5. The second control signal terminal E2 includes a fourth voltage signal terminal V4 or a first clock signal terminal CKA.

[0213] For example, when the voltage of the fifth node N5 is high, the third control circuit 8 can receive and transmit the second control signal to the first node N1 under the control of the voltage of the fifth node N5.

[0214] When the second control signal terminal E2 is the fourth voltage signal terminal V4, the third control circuit 8 can use the fourth voltage signal to discharge and reset the first node N1, so that the first control circuit 2 is in the off state, or transmit the fourth clock signal to the second node N2 when the first control circuit 2 is in the on state.

[0215] When the second control signal terminal E2 is the first clock signal terminal CKA, and the level of the first clock signal is low and the level of the second clock signal is high, the third control circuit 8 can use the first clock signal to discharge and reset the first node N1, so that the first control circuit 2 is in the off state, or transmit the fourth clock signal to the second node N2 when the first control circuit 2 is in the on state.

[0216] This ensures that the first output circuit 3 is off while the voltage at the third node N3 is high, thus turning on the second output circuit 6, thereby avoiding affecting the accuracy of the electrical signal output from the first output signal terminal OUT1.

[0217] In some examples, such as Figures 12-20 As shown, the fourth control circuit 9 is electrically connected to the first node N1, the fourth voltage signal terminal V4, the second clock signal terminal CKB, and the fifth node N5. The third control circuit 120 is configured to transmit the fourth voltage signal to the fifth node N5 under the control of the voltage of the first node N1 and the second clock signal.

[0218] For example, when both the voltage of the first node N1 and the level of the second clock signal are high, the fourth control circuit 9 can receive and transmit the fourth voltage signal to the fifth node N5 under the joint control of the voltage of the first node N1 and the second clock signal.

[0219] This allows the fourth control circuit 9 to be turned on when the first input circuit 1 is turned on to transmit a high-level first voltage signal to the first node N1 and the second clock signal is at a high level. The fourth voltage signal is then transmitted to the fifth node N5 to discharge and reset the fifth node N5, thereby preventing the second output circuit 6 from being turned on.

[0220] In some examples, such as Figures 17-20 As shown, the reset circuit 10 is electrically connected to the reset signal terminal TRST, the first voltage signal terminal V1, and the reset node I. The reset circuit 10 is configured to transmit the first voltage signal to the reset node I under the control of the reset signal transmitted at the reset signal terminal TRST. The reset node I includes either a third node N3 or a fifth node N5.

[0221] For example, when the reset signal is at a high level, the reset circuit 10 can receive and transmit a first voltage signal to the reset node I under the control of the reset signal, and reset the reset node I.

[0222] Since the first voltage signal is a DC high-level signal, after the first reset signal is transmitted to the reset node I, the second output circuit 6 can be turned on and the first voltage signal can be output as the first output signal.

[0223] It should be noted that the reset signal transmitted at the TRST terminal is a global reset signal. After multiple shift registers 100 are cascaded to form a scan drive circuit, the aforementioned scan signal can be simultaneously transmitted to the multiple shift registers 100, simultaneously driving the reset circuits 10 in the multiple shift registers to conduct, and simultaneously resetting the reset nodes I in the multiple shift registers 100. In this way, the multiple shift registers 100 can simultaneously output the first voltage signal as the first output signal, so that the light-emitting control transistors M4 in the multiple pixel drive circuits 300 included in the display device 1000 are simultaneously reset, thereby achieving a global reset.

[0224] The structure of the third control circuit 8, the fourth control circuit 9, and the reset circuit 10 will be schematically described below with reference to the accompanying drawings.

[0225] In some examples, such as Figure 13 , Figure 14 , Figure 16 , Figure 18 and Figure 20As shown, the third control circuit 8 includes: the thirteenth transistor T13.

[0226] For example, the gate of the thirteenth transistor T13 is electrically connected to the fifth node N5, the first terminal of the thirteenth transistor T13 is electrically connected to the second control signal terminal E2, and the second terminal of the thirteenth transistor T13 is electrically connected to the first node N1.

[0227] For example, when the voltage of the fifth node N5 is high, the thirteenth transistor T13 can be turned on under the control of the voltage of the fifth node N5 to receive and transmit the second control signal to the first node N1.

[0228] It should be noted that when the second control signal terminal E2 is the first clock signal terminal CKA, when the level of the first clock signal is high, the first transistor T1 is turned on and transmits the first voltage signal to the first node N1; when the thirteenth transistor T13 is turned on and the level of the first clock signal is low, the thirteenth transistor T13 can transmit the first clock signal to the first node N1 to discharge and reset the first node N1. By transmitting the first clock signal to the first node N1, the transmission of the fourth voltage signal to the first node N1 to discharge and reset the first node N1 can be avoided. This prevents the first voltage signal and the fourth voltage signal from being directly connected, thereby avoiding excessive current.

[0229] For example, the thirteenth transistor T13 can be an oxide transistor.

[0230] In some examples, such as Figure 13 , Figure 14 , Figure 16 , Figure 18 and Figure 20 As shown, the fourth control circuit 9 includes: the fourteenth transistor T14 and the fifteenth transistor T15.

[0231] For example, the gate of the fourteenth transistor T14 is electrically connected to the first node N1, the first terminal of the fourteenth transistor T14 is electrically connected to the fourth voltage signal terminal V4, and the second terminal of the fourteenth transistor T14 is electrically connected to the first terminal of the fifteenth transistor T15. The gate of the fifteenth transistor T15 is electrically connected to the second clock signal terminal CKB, and the second terminal of the fifteenth transistor T15 is electrically connected to the fifth node N5.

[0232] For example, when the voltage at the first node N1 is high and the second clock signal is high, the fourteenth transistor T14 can be turned on under the control of the first voltage signal, and the fifteenth transistor T15 can be turned on under the control of the second clock signal. The fourteenth transistor T14 receives and transmits the fourth voltage signal to the first terminal of the fifteenth transistor T15, and the fifteenth transistor T15 transmits the fourth voltage signal to the fifth node N5 to discharge and reset the fifth node.

[0233] For example, the fourteenth transistor T14 and the fifteenth transistor T15 can be oxide transistors.

[0234] In some examples, such as Figure 18 and Figure 20 As shown, the reset circuit 10 includes: a sixteenth transistor T16.

[0235] For example, the gate of the sixteenth transistor T16 is electrically connected to the reset signal terminal TRST, the first terminal of the sixteenth transistor T16 is electrically connected to the first voltage signal terminal V1, and the second terminal of the sixteenth transistor T16 is electrically connected to the reset node I.

[0236] For example, when the reset signal is at a high level, the sixteenth transistor T16 can be turned on under the control of the reset signal, receive and transmit the first voltage signal to the reset node I, and reset the reset node I.

[0237] For example, the sixteenth transistor T16 can be an oxide transistor.

[0238] In some embodiments, such as Figures 21-23 As shown, the shift register 100 also includes a third output circuit 11 and a fourth output circuit 12.

[0239] In some examples, such as Figures 21-23 As shown, the third output circuit 11 is electrically connected to the second node N2, the fourth voltage signal terminal V4, and the second output signal terminal OUT2. The third output circuit 11 is configured to transmit the fourth voltage signal received at the fourth voltage signal terminal V4 to the second output signal terminal OUT2 under the control of the voltage at the second node N2.

[0240] For example, when the voltage of the second node N2 is high, the third output circuit 11 can receive and transmit the fourth voltage signal to the second output signal terminal OUT2 under the control of the voltage of the second node N2.

[0241] In some examples, such as Figures 21-23As shown, the fourth output circuit 12 is electrically connected to the third node N3, the first voltage signal terminal V1, and the second output signal terminal OUT2. The fourth output circuit 12 is configured to transmit the first voltage signal to the second output signal terminal OUT2 under the control of the voltage of the third node N3.

[0242] For example, when the voltage of the third node N3 is high, the fourth output circuit 12 can receive and transmit the first voltage signal to the second output signal terminal OUT2 under the control of the voltage of the third node N3.

[0243] It is understood that the shift register 100 in this application can, through cooperation with various signal terminals, control the third output circuit 11 and the fourth output circuit 12 in the shift register 100 to be turned on at different time periods, thereby obtaining a second output signal with the desired waveform. For example, the waveform can be a continuous high level, a continuous low level, a period of low level followed by a period of high level, or a period of high level followed by a period of low level, etc.

[0244] It should be noted that there are multiple settings for the second voltage signal terminal V2 and the fourth voltage signal terminal V4, which can be selected according to actual needs.

[0245] In some examples, the second voltage signal terminal V2 and the fourth voltage signal terminal V4 are the same signal terminal. Accordingly, the second voltage signal transmitted by the second voltage signal terminal V2 and the fourth voltage signal transmitted by the fourth voltage signal terminal V4 are the same electrical signal.

[0246] This helps to reduce the number of signal terminals connected to the shift register 100, and simplifies the structure of the shift register 100, the scan drive circuit 400, and the display device 1000.

[0247] In other examples, the second voltage signal terminal V2 and the fourth voltage signal terminal V4 are signal terminals that transmit different voltage signals, and the voltage of the second voltage signal is higher than the voltage of the third voltage signal.

[0248] When the voltage of the second node N2 is low and the first output circuit 3 and the third output circuit 11 are turned off, a large voltage difference can be made between the second node N2 and the second voltage signal terminal V2. In this way, when the transistor included in the first output circuit 3 is negatively biased, leakage current can be avoided through the first output signal terminal OUT1 through the first output circuit 3.

[0249] The structures of the third output circuit 11 and the fourth output circuit 12 are schematically described below with reference to the accompanying drawings. The structures of the third output circuit 11 and the fourth output circuit 12 are related to the structures of the first output circuit 3 and the second output circuit 6.

[0250] In some examples, such as Figure 23 As shown, when the first output circuit 3 includes the second transistor T2 and the first capacitor C1, the second output circuit 6 includes the fifth transistor T5 and the second capacitor C2, the third output circuit 11 includes the seventeenth transistor T17, and the fourth output circuit 12 includes the eighteenth transistor T18.

[0251] For example, the gate of the seventeenth transistor T17 is electrically connected to the second node N2, the first terminal of the seventeenth transistor T17 is electrically connected to the fourth voltage signal terminal V4, and the second terminal of the seventeenth transistor T17 is electrically connected to the second output signal terminal OUT2.

[0252] For example, when the voltage of the second node N2 is high, the third output circuit 11 can be turned on under the control of the voltage of the second node N2 to receive and transmit the fourth voltage signal to the second output signal terminal OUT2.

[0253] For example, such as Figure 23 As shown, the gate of the eighteenth transistor T18 is electrically connected to the third node N3, the first terminal of the eighteenth transistor T18 is electrically connected to the first voltage signal terminal V1, and the second terminal of the eighteenth transistor T18 is electrically connected to the second output signal terminal OUT2.

[0254] For example, when the voltage of the third node N3 is high, the fourth output circuit 12 can be turned on under the control of the voltage of the third node N3 to receive and transmit the first voltage signal to the second output signal terminal OUT2.

[0255] It is understandable that when the voltage of the third node N3 is raised under the coupling effect (or bootstrapping effect) of the second capacitor C2, the eighteenth transistor T18 will also be fully turned on, ensuring the accuracy of the second output signal.

[0256] For example, the seventeenth transistor T17 and the eighteenth transistor T18 can be oxide transistors.

[0257] In other examples, such as Figure 22 As shown, when the first output circuit 3 includes the second transistor T2 and the second output circuit 6 includes the fifth transistor T5, the third output circuit 11 includes the seventeenth transistor T17 and the fifth capacitor C5, and the fourth output circuit 12 includes the eighteenth transistor T18 and the sixth capacitor C6.

[0258] For example, such as Figure 22 As shown, the first terminal of the fifth capacitor C5 is electrically connected to the second node N2, and the second terminal of the fifth capacitor C5 is electrically connected to the fourth voltage signal terminal V4.

[0259] Understandably, during the process of the first control circuit 2 transmitting the first voltage signal or the high-level second clock signal to the second node N2, the fifth capacitor C5 will also be charged. When the first control circuit 2 is turned off, the fifth capacitor C5 can discharge, maintaining the voltage of the second node N2 at a higher voltage, so that the second transistor T2 and the seventeenth transistor T17 remain in the conducting state.

[0260] For example, such as Figure 22 As shown, the first terminal of the sixth capacitor C6 is electrically connected to the third node N3, and the second terminal of the sixth capacitor C6 is electrically connected to the second output signal terminal OUT2.

[0261] Understandably, during the process of the second input circuit 4 transmitting the high-level input signal to the third node N3, the sixth capacitor C6 is also charged. When the second input circuit 4 is turned off, the sixth capacitor C6 can discharge, maintaining the voltage of the third node N3 at a higher voltage, thus keeping the eighteenth transistor T18 and the fifth transistor T5 in a conducting state.

[0262] In some embodiments, such as Figures 24-26 As shown, the shift register 100 also includes a first leakage protection circuit 13.

[0263] In some examples, the first leakage protection circuit 13 is electrically connected to the first leakage protection signal terminal D1, the first leakage protection node OFF1, and the first output signal terminal OUT1. The first leakage protection circuit 13 is configured to transmit the first leakage protection signal received at the first leakage protection signal terminal D1 to the first leakage protection node OFF1 under the control of the first output signal transmitted at the first output signal terminal OUT1. The first leakage protection signal terminal D1 includes either a first voltage signal terminal V1 or a first output signal terminal OUT1.

[0264] For example, when the first output signal is high, the first leakage protection circuit 13 can be turned on under the control of the first output signal to receive and transmit the first leakage protection signal to the first leakage protection node OFF1.

[0265] It is understood that the first leakage protection signal is either a first voltage signal or a first output signal. The first voltage signal is a DC high-level signal, and when the first leakage protection circuit 13 is turned on, the level of the first output signal is high. Therefore, the level of the first leakage protection signal transmitted from the first leakage protection circuit 13 to the first leakage protection node OFF1 is high.

[0266] Based on this, such as Figures 24-26 As shown, the first output circuit 3 is also electrically connected to the first leakage protection node OFF1.

[0267] When the second output circuit 6 is turned on and the first voltage signal is output from the first output signal terminal OUT1 as the first output signal, the first leakage protection circuit 13 can be turned on and send the first leakage protection signal to the first leakage protection node OFF1, thereby increasing the voltage of the first leakage protection node OFF1, reducing the voltage difference between the first leakage protection node OFF1 and the first output signal terminal OUT1, and increasing the voltage difference between the first leakage protection node OFF1 and the second node N2, thus preventing the first output circuit 3 from being turned on by mistake, and thus preventing the first output signal terminal OUT1 from leaking current through the first output circuit 3.

[0268] In some examples, such as Figure 25 and Figure 26 As shown, the first leakage protection circuit 13 includes: a sixth transistor T6.

[0269] For example, the gate of the sixth transistor T6 is electrically connected to the first output signal terminal OUT1, the first terminal of the sixth transistor T6 is electrically connected to the first leakage protection signal terminal D1, and the second terminal of the sixth transistor T6 is electrically connected to the first leakage protection node OFF1.

[0270] For example, when the level of the first output signal is high, the sixth transistor T6 can be turned on under the control of the first output signal to receive and transmit the first leakage protection signal to the first leakage protection node OFF1.

[0271] For example, the sixth transistor T6 can be an oxide transistor.

[0272] In some examples, such as Figure 25 and Figure 26 As shown, when the first output circuit 3 is also electrically connected to the first leakage protection node OFF1, the second transistor T2 includes: a first sub-transistor T2a and a second sub-transistor T2b.

[0273] For example, the gate of the first sub-transistor T2a is electrically connected to the second node N2, the first terminal of the first sub-transistor T2a is electrically connected to the second voltage signal terminal V2, and the second terminal of the first sub-transistor T2a is electrically connected to the first leakage protection node OFF1. The gate of the second sub-transistor T2b is electrically connected to the second node N2, the first terminal of the second sub-transistor T2b is electrically connected to the first leakage protection node OFF1, and the second terminal of the second sub-transistor T2b is electrically connected to the first output signal terminal OUT1.

[0274] For example, when the level of the second node N2 is high, the first sub-transistor T2a and the second sub-transistor T2b can be turned on simultaneously under the control of the second node N2. The first sub-transistor T2a can receive and transmit the second voltage signal to the first anti-leakage node OFF1, and the second sub-transistor T2b can transmit the second voltage signal from the first anti-leakage node OFF1 to the first output signal terminal OUT1.

[0275] Here, when the voltage at the second node N2 is low and the second output circuit 6 is on, the first leakage protection circuit 13 can transmit the first voltage signal or the high-level first output signal to the first leakage protection node OFF1, reducing the voltage difference between the first leakage protection node OFF1 and the first output signal terminal OUT1, and increasing the voltage difference between the first leakage protection node OFF1 and the second node N2, making the voltage difference between the gate of the first sub-transistor T2a and the second terminal of the first sub-transistor T2a larger. For example, even when the threshold voltage of the first sub-transistor T2a is significantly negatively biased, this voltage difference is still less than the threshold voltage of the first sub-transistor T2a, thus ensuring that the first sub-transistor T2a is completely or relatively completely turned off. This prevents leakage through the first output signal terminal OUT1 through the first output circuit 3, allowing the first output signal output from the first output signal terminal OUT1 to maintain a relatively high and stable voltage.

[0276] In some embodiments, such as Figures 27-29 As shown, when the shift register 100 includes the voltage regulator circuit 7, the shift register 100 also includes a second leakage protection circuit 14.

[0277] In some examples, the second leakage protection circuit 14 is electrically connected to the third node N3, the third voltage signal terminal V3, and the second leakage protection node OFF2. The second leakage protection circuit 14 is configured to transmit the third voltage signal received at the third voltage signal terminal V3 to the second leakage protection node OFF2 under the control of the voltage of the third node N3.

[0278] For example, when the voltage of the third node N3 is high, the second leakage protection circuit 14 can be turned on under the control of the voltage of the third node N3 to receive and transmit the third voltage signal to the second leakage protection node OFF2.

[0279] Optionally, the third voltage signal terminal V3 is configured to transmit a second DC high-level signal (e.g., a portion of the clock signal that is higher than or equal to the high level of the clock signal). This second DC low-voltage signal is referred to here as the third voltage signal.

[0280] Based on this, such as Figures 27-29As shown, the voltage regulator circuit 7 is also electrically connected to the second leakage protection node OFF2, wherein the voltage of the third voltage signal is higher than the voltage of the first voltage signal.

[0281] In this way, when the second leakage protection circuit 14 is turned on and the third voltage signal is sent to the second leakage protection node OFF2, the voltage of the second leakage protection node OFF2 can be increased, the voltage difference between the second leakage protection node OFF2 and the first voltage signal terminal V1 can be increased, the voltage regulator circuit 7 can be prevented from being turned on by mistake, and thus the second output circuit 6 can be prevented from leaking through the voltage regulator circuit 7.

[0282] In some examples, such as Figure 28 and Figure 29 As shown, the second leakage protection circuit 14 includes: an eleventh transistor T11.

[0283] For example, the gate of the eleventh transistor T11 is electrically connected to the third node N3, the first terminal of the eleventh transistor T11 is electrically connected to the third voltage signal terminal V3, and the second terminal of the eleventh transistor T11 is electrically connected to the second leakage protection node OFF2.

[0284] For example, when the voltage of the third node N3 is high, the second leakage protection circuit 14 can receive and transmit the third voltage signal to the second leakage protection node OFF2 under the control of the voltage of the third node N3.

[0285] For example, the eleventh transistor T11 can be an oxide transistor.

[0286] In some examples, such as Figure 28 and Figure 29 As shown, the tenth transistor T10 in the voltage regulator circuit 7 includes: a third sub-transistor T10a and a fourth sub-transistor T10b.

[0287] For example, the gate of the third sub-transistor T10a is electrically connected to the first voltage signal terminal V1, the first terminal of the third sub-transistor T10a is electrically connected to the fifth node N5, and the second terminal of the third sub-transistor T10a is electrically connected to the second leakage protection node OFF2. The gate of the fourth sub-transistor T10b is electrically connected to the first voltage signal terminal V1, the first terminal of the fourth sub-transistor T10b is electrically connected to the second leakage protection node OFF2, and the second terminal of the fourth sub-transistor T10b is electrically connected to the third node N3.

[0288] For example, the first voltage signal is a DC high-level signal. Therefore, the third sub-transistor T10a and the fourth sub-transistor T10b can be turned on simultaneously under the control of the first voltage signal. The third sub-transistor T10a can receive and transmit the electrical signal from the fifth node N5 to the second leakage protection node OFF2, and the fourth sub-transistor T10b can transmit the electrical signal from the first leakage protection node OFF1 to the third node N3.

[0289] Here, with the second output circuit 6 turned on and the voltage of the third node N3 further increased, the second leakage protection circuit 14 can transmit the third voltage signal to the second leakage protection node OFF2, increasing the voltage difference between the second leakage protection node OFF2 and the first voltage signal terminal V1. This results in a larger voltage difference between the gate of the third sub-transistor T10a and the second terminal of the third sub-transistor T10a. For example, even when the threshold voltage of the third sub-transistor T10a is significantly negatively biased, this voltage difference remains less than the threshold voltage of the third sub-transistor T10a, ensuring that the third sub-transistor T10a is completely or relatively completely turned off. This further prevents leakage from the second output circuit 6 through the voltage regulator circuit 7, allowing the first output signal output from the first output signal terminal OUT1 to maintain a relatively high and stable voltage.

[0290] It is understandable that with the use of oxide transistors, their threshold voltage will exhibit a negative drift phenomenon and become negative. Figure 30 and Figure 31 For example, a timing diagram showing the case where the threshold voltages of the multiple transistors included in shift register 100 all drift negatively to -2.5V.

[0291] For example, in Figure 29 Without the first leakage protection circuit 13 and the second leakage protection circuit 14 in the shift register 100 shown, the first output signal output by the shift register 100 is as follows: Figure 30 As shown. Figure 31 for Figure 20 The first output signal of the shift register 100 shown is N3. <2> OUT1 is the voltage at the third node N3 of the second shift register 100 in a cascaded array of shift registers 100; <1> OUT1 is the first output signal output by the first shift register 100 in a cascaded series of shift registers 100. <2> OUT1 is the first output signal output by the second shift register 100 in a cascaded series of shift registers 100. <20> The first output signal is output by the twentieth shift register 100 in a cascaded set of multiple shift registers 100.

[0292] Depend on Figure 30It can be seen that during the operation of shift register 100, leakage will occur in the third node N3, resulting in a decrease in voltage and poor stability of the third node N3, which in turn leads to poor stability of the first output signal output by the first output signal terminal OUT1.

[0293] Depend on Figure 31 It can be seen that after setting the first anti-leakage circuit 13 and the second anti-leakage circuit 14, the voltage of the third node N3 is relatively stable, which can effectively improve the leakage phenomenon of the third node N3, thereby making the first output signal output by the first output signal terminal OUT1 more stable.

[0294] In some embodiments, such as Figures 32-34 As shown, when the shift register 100 includes the voltage regulator circuit 7, the shift register 100 also includes a third leakage protection circuit 15.

[0295] In some examples, the third leakage protection circuit 15 is electrically connected to the second node N2, the first voltage signal terminal V1, and the third leakage protection node OFF3. The third leakage protection circuit 15 is configured to transmit the first voltage signal to the third leakage protection node OFF3 under the control of the voltage of the second node N2.

[0296] For example, when the voltage of the second node N2 is high, the third leakage protection circuit 15 can be turned on under the control of the voltage of the second node N2, and receive and transmit the first voltage signal to the third leakage protection node OFF3.

[0297] Based on this, such as Figures 32-34 As shown, the second control circuit 5 is also electrically connected to the third leakage protection node OFF3.

[0298] In this way, when the third leakage protection circuit 15 is turned on and transmits the first voltage signal to the third leakage protection node OFF3, the voltage of the third leakage protection node OFF3 can be increased, the voltage difference between the third leakage protection node OFF3 and the third node N3 can be increased, the second control circuit 5 can be prevented from being turned on by mistake, and thus the second node N2 can be prevented from leaking current through the second control circuit 5.

[0299] In some examples, such as Figure 33 and Figure 34 As shown, the third leakage protection circuit 15 includes: the twelfth transistor T12.

[0300] For example, the gate of the twelfth transistor T12 is electrically connected to the second node N2, the first terminal of the twelfth transistor T12 is electrically connected to the first voltage signal terminal V1, and the second terminal of the twelfth transistor T12 is electrically connected to the third leakage protection node OFF3.

[0301] For example, when the voltage of the second node N2 is high, the twelfth transistor T12 can be turned on under the control of the voltage of the second node N2 to receive and transmit the first voltage signal to the third leakage protection node OFF3.

[0302] For example, the twelfth transistor T12 can be an oxide transistor.

[0303] In some examples, such as Figure 33 and Figure 34 As shown, the fourth transistor T4 in the second control circuit 5 includes a fifth sub-transistor T4a and a sixth sub-transistor T4b.

[0304] For example, the gate of the fifth sub-transistor T4a is electrically connected to the third node N3, the first terminal of the fifth sub-transistor T4a is electrically connected to the first control signal terminal E1, and the second terminal of the fifth sub-transistor T4a is electrically connected to the third leakage protection node OFF3. The gate of the sixth sub-transistor T4b is electrically connected to the third node N3, the first terminal of the sixth sub-transistor T4b is electrically connected to the third leakage protection node OFF3, and the second terminal of the sixth sub-transistor T4b is electrically connected to the second node N2.

[0305] For example, when the voltage of the third node N3 is high, the fifth sub-transistor T4a and the sixth sub-transistor T4b can be turned on simultaneously under the control of the voltage of the third node N3. The fifth sub-transistor T4a can receive and transmit the first control signal to the third leakage protection node OFF3, and the sixth sub-transistor T4b can transmit the first control signal from the third leakage protection node OFF3 to the second node N2.

[0306] Here, when the voltage at the second node N2 is high, the third leakage protection circuit 15 can transmit the first voltage signal to the third leakage protection node OFF3, increasing the voltage difference between the third leakage protection node OFF3 and the third node N3. This results in a larger voltage difference between the gate and the second terminal of the fifth sub-transistor T4a. For example, even when the threshold voltage of the fifth sub-transistor T4a is significantly negatively biased, this voltage difference remains less than the threshold voltage of the fifth sub-transistor T4a, thus ensuring that the fifth sub-transistor T4a is completely or relatively completely turned off. This further prevents leakage through the second control circuit 5 at the second node N2, thereby ensuring that the first output circuit 3 is in a stable and relatively complete conduction state, allowing the second voltage signal transmitted to the first output signal terminal OUT1 to be maintained at a lower and more stable voltage.

[0307] In some embodiments, such as Figure 35 and Figure 36As shown, when the shift register 100 also includes a third output circuit 11 and a fourth output circuit 12, the shift register 100 also includes a fourth leakage protection circuit 16.

[0308] In some examples, the fourth leakage protection circuit 16 is electrically connected to the second leakage protection signal terminal D2, the first voltage signal terminal V1, and the fourth leakage protection node OFF4. The fourth leakage protection circuit 16 is configured to transmit the first voltage signal to the fourth leakage protection node OFF4 under the control of the second leakage protection signal transmitted through the second leakage protection signal terminal D2. The second leakage protection signal terminal D2 includes either a first output signal terminal OUT1 or a second output signal terminal OUT2.

[0309] For example, when the level of the second leakage protection signal (i.e., the level of the first output signal or the level of the second output signal) is high, the fourth leakage protection circuit 16 can be turned on under the control of the second leakage protection signal to receive and transmit the first voltage signal to the fourth leakage protection node OFF4.

[0310] Based on this, such as Figure 36 As shown, the third output circuit 11 is also electrically connected to the fourth leakage protection node OFF4.

[0311] In this way, when the fourth leakage protection circuit 16 is turned on and the first voltage signal is transmitted to the fourth leakage protection node OFF4, the voltage of the fourth leakage protection node OFF4 can be increased, the voltage difference between the fourth leakage protection node OFF4 and the second node N2 can be increased, the third output circuit 11 can be prevented from being turned on by mistake, and the second output signal terminal OUT1 can be prevented from leaking through the third output circuit 11.

[0312] In some examples, such as Figure 36 As shown, the fourth leakage protection circuit 16 includes: the nineteenth transistor T19.

[0313] For example, the gate of the nineteenth transistor T19 is electrically connected to the second leakage protection signal terminal D2, the first terminal of the nineteenth transistor T19 is electrically connected to the first voltage signal terminal V1, and the second terminal of the nineteenth transistor T19 is electrically connected to the fourth leakage protection node OFF4.

[0314] For example, when the level of the second leakage protection signal is high, the fourth leakage protection circuit 16 can be turned on under the control of the second leakage protection signal to receive and transmit the first voltage signal to the fourth leakage protection node OFF4.

[0315] For example, the nineteenth transistor T19 can be an oxide transistor.

[0316] In some examples, such as Figure 36As shown, the seventeenth transistor T17 in the third output circuit 11 includes: a seventh sub-transistor T17a and an eighth sub-transistor T17b.

[0317] For example, the gate of the seventh sub-transistor T17a is electrically connected to the second node N2, the first terminal of the seventh sub-transistor T17a is electrically connected to the fourth voltage signal terminal V4, and the second terminal of the seventh sub-transistor T17a is electrically connected to the fourth leakage protection node OFF4. The gate of the eighth sub-transistor T17b is electrically connected to the second node N2, the first terminal of the eighth sub-transistor T17b is electrically connected to the fourth leakage protection node OFF4, and the second terminal of the eighth sub-transistor T17b is electrically connected to the second output signal terminal OUT2.

[0318] For example, when the voltage of the second node N2 is high, the seventh sub-transistor T17a and the eighth sub-transistor T17b can be turned on simultaneously under the control of the voltage of the second node N2. The seventh sub-transistor T17a can receive and transmit the fourth voltage signal to the fourth leakage protection node OFF4, and the eighth sub-transistor T17b can transmit the fourth voltage signal from the fourth leakage protection node OFF4 to the second output signal terminal OUT2.

[0319] Here, when the voltage at the second node N2 is low and the fourth output circuit 12 is on, the fourth leakage protection circuit 16 can transmit the first voltage signal to the fourth leakage protection node OFF4, increasing the voltage difference between the fourth leakage protection node OFF4 and the second node N2. This results in a larger voltage difference between the gate and the second terminal of the seventh sub-transistor T17a. For example, even when the threshold voltage of the seventh sub-transistor T17a is significantly negatively biased, this voltage difference remains less than the threshold voltage of the seventh sub-transistor T17a, thus ensuring that the seventh sub-transistor T17a is completely or relatively completely turned off. This prevents leakage through the third output circuit 11 at the second output signal terminal OUT2, allowing the first voltage signal output from the second output signal terminal OUT2 to maintain a relatively high and stable voltage.

[0320] In some embodiments, such as Figure 38 and Figure 39 As shown, the scan drive circuit 400 includes a plurality of shift registers 100 as described in any of the embodiments above.

[0321] In some examples, the scan drive circuit 400 also includes a first clock signal line CLA and a second clock signal line CLB.

[0322] For example, the first clock signal line CLA can be electrically connected to the first clock signal terminal CKA of the (2n-1)th shift register 100 and the second clock signal terminal CKB of the 2nth shift register 100.

[0323] For example, the second clock signal line CLB can be electrically connected to the second clock signal terminal CKB of the (2n-1)th shift register 100 and the first clock signal terminal CKA of the 2nth shift register 100. Here, n is a positive integer.

[0324] For example, such as Figure 38 As shown, when shift register 100 does not include the third output circuit 11 and the fourth output circuit 12, the first output signal terminal OUT1 of the Nth shift register is electrically connected to the input signal terminal INPUT of the (N+1)th shift register, where N is a positive integer. That is, the first output signal of the Nth shift register can be used as the input signal of the (N+1)th shift register.

[0325] For example, such as Figure 39 As shown, when shift register 100 includes a third output circuit 11 and a fourth output circuit 12, the second output signal terminal OUT2 of the Nth shift register is electrically connected to the input signal terminal INPUT of the (N+1)th shift register, where N is a positive integer. That is, the second output signal of the Nth shift register can be used as the input signal of the (N+1)th shift register.

[0326] Thus, on the one hand, since the first output signal terminal OUT1 needs to be electrically connected to the gate of the light-emitting control transistor M4 of the pixel driving circuit 300 through a relatively long trace (e.g., an enable signal line EL), the load electrically connected to the first output signal terminal OUT1 is relatively large. By connecting the second output signal terminal OUT2 of the Nth shift register 100 to the input signal terminal INPUT of the (N+1)th shift register 100, the length of the trace required between the second output signal terminal OUT2 and the input signal terminal INPUT can be reduced, thereby reducing the load electrically connected to the second output signal terminal OUT2, and consequently making the waveform of the signal transmitted from the second output signal terminal OUT2 to the input signal terminal INPUT more stable.

[0327] On the other hand, since the first output signal output from the first output signal terminal OUT1 and the second output signal output from the second output signal terminal OUT2 are independent of each other, they can each play their own role. Therefore, the shift register 100 has good fault tolerance and stability.

[0328] It should be noted that, Figure 38 and Figure 39 OUT1 <1> OUT1 <2> OUT1 <3> OUT1 <4> OUT1 <n>OUT1<N+1> These represent the first output signal terminals of the first shift register 100, the second shift register 100, the third shift register 100, the fourth shift register 100, ..., the Nth shift register 100 and the N+1th shift register 100 in the scan drive circuit 400, respectively.

[0329] It should also be noted that, Figure 39 OUT2 <1> OUT2 <2> OUT2 <3> OUT2 <4> OUT2 <n>OUT2<N+1> These represent the second output signal terminals of the first shift register 100, the second shift register 100, the third shift register 100, the fourth shift register 100, ..., the Nth shift register 100, and the (N+1)th shift register 100 in the scan drive circuit 400, respectively.

[0330] For example, such as Figure 38 and Figure 39 As shown, the scan drive circuit 400 may further include a start signal line STL.

[0331] For example, the input signal terminal INPUT of the first shift register in the scan drive circuit 400 is electrically connected to the start signal line STL so that the start signal transmitted by the start signal line STL is used as the input signal.

[0332] The shift register 100 included in the scan drive circuit 400 described above has the same structure and beneficial technical effects as the shift register 100 provided in some of the above embodiments, and will not be described again here.

[0333] In some embodiments, a driving method for a shift register 100 is provided, the driving method comprising: a first stage a, a second stage b, a third stage c, and a fourth stage d.

[0334] In the first stage a, in response to the first clock signal received at the first clock signal terminal CKA, the first input circuit 1 is turned on, transmitting the first voltage signal received at the first voltage signal terminal V1 to the first node N1. In response to the first clock signal, the second input circuit 4 is turned on, transmitting the input signal received at the input signal terminal INPUT to the third node N3.

[0335] In the second stage b, at least in response to the second clock signal received at the second clock signal terminal CKB, the first control circuit 2 is turned on to transmit the second clock signal or the electrical signal from the first node N1 to the second node N2.

[0336] In the third stage c, in response to the voltage at the second node N2, the first output circuit 3 is turned on, and the second voltage signal received at the second voltage signal terminal V2 is transmitted to the first output signal terminal OUT1.

[0337] In the fourth stage d, in response to the first clock signal, the second input circuit 4 is turned on, transmitting the input signal to the third node N3. In response to the voltage at the third node N3, the second control circuit 5 is turned on, transmitting the first control signal received at the first control signal terminal E1 to the control node Q. In response to the voltage at the third node N3, the second output circuit 6 is turned on, transmitting the first voltage signal to the first output signal terminal OUT1.

[0338] It should be noted that the various configurations of the first control circuit 2 and the second control circuit 5 can be found in the descriptions of some of the above embodiments, and will not be repeated here.

[0339] Therefore, the driving method of the shift register 100 provided in some embodiments of this disclosure, by applying the driving methods in the first stage a, the second stage b, and the third stage c, can enable the first output circuit 3 to conduct, thereby transmitting the second voltage signal to the first output signal terminal OUT1. That is, the first output signal output by the first output signal terminal is the second voltage signal. By applying the driving method in the fourth stage d, the second output circuit can be enabled, thereby transmitting the first voltage signal to the first output signal terminal OUT1. That is, the first output signal output by the first output signal terminal is the first voltage signal. In this way, the second voltage signal output by the first output circuit and the first voltage signal output by the second output circuit can cooperate to form a first output signal with alternating low and high levels. The waveform of this first output signal is the same as the waveform of the enable signal required by the pixel driving circuit 300 in the display device 1000, thereby achieving the beneficial effects of the shift register 100 mentioned in the above embodiments.

[0340] The following is combined with Figure 37 The timing diagram shown and Figure 38 The scan drive circuit shown is for Figure 13 The driving method of the shift register 100 shown is illustrated schematically.

[0341] like Figure 37 As shown, the driving method of shift register 100 includes: first stage a, second stage b, third stage c and fourth stage d.

[0342] In the first stage a, the level of the first clock signal is divided into two stages: a high-level stage and a low-level stage. The input signal level is low. The level of the second clock signal is low.

[0343] When the first clock signal is high, in response to the first clock signal, the first transistor T1 turns on, transmitting the first voltage signal to the first node N1 and charging the third capacitor C3. Under the control of the voltage at the first node N1, the seventh transistor T7 turns on, transmitting the second clock signal to the fourth node N4. Since the eighth transistor T8 is turned off under the control of the second clock signal, the electrical signal at the fourth node N4 cannot be transmitted to the second node N2. The voltage at the second node N2 remains at the voltage of the previous stage, i.e., low level.

[0344] In response to the first clock signal, the third transistor T3 turns on, transmitting the input signal to the third node N3 via the tenth transistor T10, and charging the second capacitor C2. Therefore, the voltage at the third node N3 is low. The fifth transistor T5 turns off.

[0345] When the first clock signal is at a low level, the eighth transistor T8 remains off, and the voltage at the second node N2 remains the same as in the previous stage, i.e., low. The second capacitor C2 discharges, and the voltage at the third node N3 remains low.

[0346] Therefore, in the first stage a, the first output signal OUT1 output from the first output signal terminal OUT1 is... <n>The voltage is maintained at the voltage of the previous stage, that is, the high level.

[0347] In the second stage b, the level of the first clock signal is low. The level of the input signal is low. The level of the second clock signal is divided into two stages: a high-level stage and a low-level stage.

[0348] When the second clock signal is at a high level, the first transistor T1 is turned off under the control of the first clock signal, and the third capacitor C3 begins to discharge, maintaining the voltage of the first node N1 at a high level. The seventh transistor T7 is turned on under the control of the voltage of the first node N1, transmitting the second clock signal to the fourth node N4. The eighth transistor T8 is turned on under the control of the second clock signal, transmitting the second clock signal to the second node N2, meaning the voltage of the second node N2 is at a high level, and charging the first capacitor C1. The second transistor T2 is turned on under the control of the voltage of the second node N2, transmitting the second voltage signal to the first output signal terminal OUT1.

[0349] It should be noted that when the second clock signal is transmitted to the fourth node N4, the potential of the fourth node N4 is raised. Due to the bootstrap effect of the third capacitor C3, the potential of the first node N1 is further raised, which allows the seventh transistor T7 to be turned on more fully.

[0350] The third transistor T3 is turned off under the control of the first clock signal, therefore, the voltage of the third node N3 remains low.

[0351] When the second clock signal is at a low level, the eighth transistor T8 is turned off under the control of the second clock signal, and the first capacitor C1 begins to discharge, keeping the voltage of the second node N2 at a high level. The voltage of the third node N3 remains at a low level.

[0352] Therefore, in the second stage b, the second transistor T2 is always in the on state, the fifth transistor T5 is always in the off state, and the first output signal OUT1 is output from the first output signal terminal OUT1. <n>The level is low.

[0353] In the third stage c, the level of the first clock signal is divided into multiple alternating high-level and low-level stages. The level of the second clock signal is divided into multiple alternating low-level and high-level stages.

[0354] When the level of the second clock signal is at any high level, the level of the first clock signal is at a low level. Correspondingly, when the level of the second clock signal is at any high level, the operation of each transistor in the shift register 100 can refer to the corresponding operation in the second stage b; when the level of the second clock signal is at any low level, the operation of each transistor in the shift register 100 can refer to the corresponding operation in the second stage b.

[0355] Therefore, in the third stage c, the second node N2 is always at a high level, thus the second transistor T2 is always on, and the level of the third node N3 is always at a low level, thus the fifth transistor T5 is always off, thereby the first output signal terminal OUT is turned off. <1> The first output signal OUT1 <n>The voltage level remains low.

[0356] In stage d, the input signal level is high. The first clock signal level consists of multiple alternating high and low levels. The second clock signal level consists of multiple alternating low and high levels.

[0357] When the first clock signal is at its first high level, the third transistor T3 is turned on under the control of the first clock signal, transmitting the input signal to the third node N3 and charging the second capacitor C2. Therefore, the voltage of the third node N3 is high. The fourth transistor T4 is turned on under the control of the voltage of the third node N3, transmitting the first control signal (i.e., the fourth voltage signal) to the second node N2, pulling the voltage of the second node N2 low.

[0358] When the level of the first clock signal is in the first low level phase, the third transistor T3 is turned off under the control of the first clock signal, the second capacitor C2 begins to discharge, so that the voltage of the third node N3 remains at a high level, and the fourth transistor T4 remains on under the control of the voltage of the third node N3, continuously pulling the voltage of the second node N2 down to a low level.

[0359] Therefore, in the fourth stage d, regardless of whether the level of the first clock signal is in the high level stage or the low level stage, the voltage of the third node N3 always remains at the high level, thereby causing the voltage of the second node N2 to be continuously pulled down to the low level.

[0360] Therefore, in the fourth stage d, the voltage of the second node N2 remains at a low level, thus the second transistor T2 remains off; the voltage of the third node N3 remains at a high level, thus the fifth transistor T5 remains on, and consequently the first output signal OUT1 is output from the first output signal terminal OUT1. <n>The voltage level is high.

[0361] Therefore, based on the driving method of shift register 100 in this example, the waveform output by shift register 100 is a waveform in which high and low levels alternate sequentially, that is, and Figure 4 The waveform of the enable signal EM required by the pixel driving circuit 300 in the display device 1000 shown is the same. That is, by using the shift register 100 described above, the enable signal EM required by the pixel driving circuit 300 in the display device 1000 can be obtained.

[0362] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.< / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A shift register, characterized in that, The shift register includes: The first input circuit is electrically connected to the first voltage signal terminal, the first clock signal terminal, and the first node; the first input circuit is configured to transmit the first voltage signal received at the first voltage signal terminal to the first node under the control of the first clock signal transmitted at the first clock signal terminal. A first control circuit is electrically connected to at least the first node, the second clock signal terminal, and the second node; the first control circuit is configured to transmit the second clock signal or an electrical signal from the first node to the second node under the control of the second clock signal transmitted at the second clock signal terminal. A first output circuit is electrically connected to a second voltage signal terminal, a second node, and a first output signal terminal. The first output circuit is configured to transmit a second voltage signal received at the second voltage signal terminal to the first output signal terminal under the control of the voltage of the second node. The second input circuit is electrically connected to the input signal terminal, the first clock signal terminal, and the third node; the second input circuit is configured to transmit the input signal received at the input signal terminal to the third node under the control of the first clock signal. A second control circuit is electrically connected to the third node, the first control signal terminal, and the control node; the second control circuit is configured to, under the control of the voltage of the third node, transmit a first control signal received at the first control signal terminal to the control node; the control node includes either the first node or the second node; and, The second output circuit is electrically connected to the first voltage signal terminal, the third node, and the first output signal terminal; the second output circuit is configured to transmit the first voltage signal to the first output signal terminal under the control of the voltage of the third node. The first input circuit, the first control circuit, the first output circuit, the second input circuit, the second control circuit, and the second output circuit each include at least one transistor; the at least one transistor is an oxide transistor.

2. The shift register according to claim 1, characterized in that, The first input circuit includes: a first transistor; The gate of the first transistor is electrically connected to the first clock signal terminal, the first terminal of the first transistor is electrically connected to the first voltage signal terminal, and the second terminal of the first transistor is electrically connected to the first node. The first output circuit includes: a second transistor and a first capacitor; or, the first output circuit includes: a second transistor; The gate of the second transistor is electrically connected to the second node, the first terminal of the second transistor is electrically connected to the second voltage signal terminal, and the second terminal of the second transistor is electrically connected to the first output signal terminal. The first terminal of the first capacitor is electrically connected to the second node, and the second terminal of the first capacitor is electrically connected to the second voltage signal terminal; The second input circuit includes: a third transistor; The gate of the third transistor is electrically connected to the first clock signal terminal, the first terminal of the third transistor is electrically connected to the input signal terminal, and the second terminal of the third transistor is electrically connected to the third node. The second control circuit includes: a fourth transistor; The gate of the fourth transistor is electrically connected to the third node, the first terminal of the fourth transistor is electrically connected to the first control signal terminal, and the second terminal of the fourth transistor is electrically connected to the control node. The second output circuit includes: a fifth transistor and a second capacitor; or, the second output circuit includes: a fifth transistor; The gate of the fifth transistor is electrically connected to the third node, the first terminal of the fifth transistor is electrically connected to the first voltage signal terminal, and the second terminal of the fifth transistor is electrically connected to the first output signal terminal. The first terminal of the second capacitor is electrically connected to the third node, and the second terminal of the second capacitor is electrically connected to the first output signal terminal.

3. The shift register according to claim 2, characterized in that, The shift register further includes: a first leakage protection circuit; The first leakage protection circuit is electrically connected to the first leakage protection signal terminal, the first leakage protection node, and the first output signal terminal; the first leakage protection circuit is configured to transmit the first leakage protection signal received at the first leakage protection signal terminal to the first leakage protection node under the control of the first output signal transmitted at the first output signal terminal. Wherein, the first leakage protection signal terminal includes the first voltage signal terminal or the first output signal terminal; The first output circuit is also electrically connected to the first leakage protection node.

4. The shift register according to claim 3, characterized in that, The first leakage protection circuit includes: a sixth transistor; The gate of the sixth transistor is electrically connected to the first output signal terminal, the first terminal of the sixth transistor is electrically connected to the first leakage protection signal terminal, and the second terminal of the sixth transistor is electrically connected to the first leakage protection node. The second transistor includes: a first sub-transistor and a second sub-transistor; The gate of the first sub-transistor is electrically connected to the second node, the first terminal of the first sub-transistor is electrically connected to the second voltage signal terminal, and the second terminal of the first sub-transistor is electrically connected to the first leakage protection node. The gate of the second sub-transistor is electrically connected to the second node, the first terminal of the second sub-transistor is electrically connected to the first leakage protection node, and the second terminal of the second sub-transistor is electrically connected to the first output signal terminal.

5. The shift register according to claim 1, characterized in that, The first control circuit is electrically connected to the first node, the second clock signal terminal, and the second node; the first control circuit is configured to transmit the second clock signal to the second node under the control of the voltage at the first node and the second clock signal. The first control circuit includes: a seventh transistor, an eighth transistor, and a third capacitor; The gate of the seventh transistor is electrically connected to the first node, the first terminal of the seventh transistor is electrically connected to the second clock signal terminal, and the second terminal of the seventh transistor is electrically connected to the fourth node; The gate of the eighth transistor is electrically connected to the second clock signal terminal, the first terminal of the eighth transistor is electrically connected to the fourth node, and the second terminal of the eighth transistor is electrically connected to the second node. The first terminal of the third capacitor is electrically connected to the first node, and the second terminal of the third capacitor is electrically connected to the second clock signal terminal or the fourth node.

6. The shift register according to claim 1, characterized in that, The first control circuit is electrically connected to the first node, the second clock signal terminal, the second node, and the second voltage signal terminal; the first control circuit is configured to transmit an electrical signal from the first node to the second node under the control of the second clock signal. The first control circuit includes: a ninth transistor and a fourth capacitor; The gate of the ninth transistor is electrically connected to the second clock signal terminal, the first terminal of the ninth transistor is electrically connected to the first node, and the second terminal of the ninth transistor is electrically connected to the second node; The first terminal of the fourth capacitor is electrically connected to the first node, and the second terminal of the fourth capacitor is electrically connected to the second voltage signal terminal.

7. The shift register according to claim 1, characterized in that, The shift register further includes: a voltage regulator circuit; The voltage regulator circuit is electrically connected to the first voltage signal terminal, the third node, and the fifth node. The second input circuit is also electrically connected to the fifth node and to the third node through the voltage regulator circuit; the second input circuit is configured to transmit the input signal to the fifth node under the control of the first clock signal; the voltage regulator circuit is configured to transmit the electrical signal from the fifth node to the third node under the control of the first voltage signal. The control node is the second node, and the second control circuit is electrically connected to the third node, the first control signal terminal, and the second node.

8. The shift register according to claim 7, characterized in that, The voltage regulator circuit includes: a tenth transistor; The gate of the tenth transistor is electrically connected to the first voltage signal terminal, the first terminal of the tenth transistor is electrically connected to the fifth node, and the second terminal of the tenth transistor is electrically connected to the third node. In the second input circuit, the second terminal of the third transistor is electrically connected to the fifth node; In the second control circuit, the second terminal of the fourth transistor is electrically connected to the second node.

9. The shift register according to claim 8, characterized in that, The shift register also includes: a second leakage protection circuit; The second leakage protection circuit is electrically connected to the third node, the third voltage signal terminal, and the second leakage protection node; the second leakage protection circuit is configured to transmit the third voltage signal received at the third voltage signal terminal to the second leakage protection node under the control of the voltage of the third node. The voltage regulator circuit is also electrically connected to the second leakage protection node; the voltage of the third voltage signal is higher than the voltage of the first voltage signal.

10. The shift register according to claim 9, characterized in that, The second leakage protection circuit includes: an eleventh transistor; The gate of the eleventh transistor is electrically connected to the third node, the first terminal of the eleventh transistor is electrically connected to the third voltage signal terminal, and the second terminal of the eleventh transistor is electrically connected to the second leakage protection node. The tenth transistor includes: a third sub-transistor and a fourth sub-transistor; The gate of the third sub-transistor is electrically connected to the first voltage signal terminal, the first terminal of the third sub-transistor is electrically connected to the fifth node, and the second terminal of the third sub-transistor is electrically connected to the second leakage protection node. The gate of the fourth sub-transistor is electrically connected to the first voltage signal terminal, the first terminal of the fourth sub-transistor is electrically connected to the second leakage protection node, and the second terminal of the fourth sub-transistor is electrically connected to the third node.

11. The shift register according to claim 8, characterized in that, The shift register also includes: a third leakage protection circuit; The third leakage protection circuit is electrically connected to the second node, the first voltage signal terminal, and the third leakage protection node; the third leakage protection circuit is configured to transmit the first voltage signal to the third leakage protection node under the control of the voltage of the second node. The second control circuit is also electrically connected to the third leakage protection node.

12. The shift register according to claim 11, characterized in that, The third leakage protection circuit includes: a twelfth transistor; The gate of the twelfth transistor is electrically connected to the second node, the first terminal of the twelfth transistor is electrically connected to the first voltage signal terminal, and the second terminal of the twelfth transistor is electrically connected to the third leakage protection node. The fourth transistor includes: a fifth sub-transistor and a sixth sub-transistor; The gate of the fifth sub-transistor is electrically connected to the third node, the first terminal of the fifth sub-transistor is electrically connected to the first control signal terminal, and the second terminal of the fifth sub-transistor is electrically connected to the third leakage protection node. The gate of the sixth sub-transistor is electrically connected to the third node, the first terminal of the sixth sub-transistor is electrically connected to the third leakage protection node, and the second terminal of the sixth sub-transistor is electrically connected to the second node.

13. The shift register according to claim 7, characterized in that, The shift register further includes at least one of a third control circuit, a fourth control circuit, and a reset circuit; The third control circuit is electrically connected to the fifth node, the second control signal terminal, and the first node; the third control circuit is configured to transmit the second control signal received at the second control signal terminal to the first node under the control of the voltage of the fifth node. The fourth control circuit is electrically connected to the first node, the fourth voltage signal terminal, the second clock signal terminal, and the fifth node; the fourth control circuit is configured to transmit the fourth voltage signal received at the fourth voltage signal terminal to the fifth node under the control of the voltage of the first node and the second clock signal. The reset circuit is electrically connected to the reset signal terminal, the first voltage signal terminal, and the reset node; the reset circuit is configured to transmit the first voltage signal to the reset node under the control of the reset signal transmitted at the reset signal terminal; the reset node includes the third node or the fifth node.

14. The shift register according to claim 13, characterized in that, The third control circuit includes: a thirteenth transistor; The gate of the thirteenth transistor is electrically connected to the fifth node, the first terminal of the thirteenth transistor is electrically connected to the second control signal terminal, and the second terminal of the thirteenth transistor is electrically connected to the first node; The fourth control circuit includes: a fourteenth transistor and a fifteenth transistor; The gate of the fourteenth transistor is electrically connected to the first node, the first terminal of the fourteenth transistor is electrically connected to the fourth voltage signal terminal, and the second terminal of the fourteenth transistor is electrically connected to the first terminal of the fifteenth transistor. The gate of the fifteenth transistor is electrically connected to the second clock signal terminal, and the second terminal of the fifteenth transistor is electrically connected to the fifth node; The reset circuit includes: a sixteenth transistor; The gate of the sixteenth transistor is electrically connected to the reset signal terminal, the first terminal of the sixteenth transistor is electrically connected to the first voltage signal terminal, and the second terminal of the sixteenth transistor is electrically connected to the reset node.

15. The shift register according to claim 2, characterized in that, The shift register further includes: a third output circuit and a fourth output circuit; The third output circuit is electrically connected to the second node, the fourth voltage signal terminal, and the second output signal terminal; the third output circuit is configured to transmit the fourth voltage signal received at the fourth voltage signal terminal to the second output signal terminal under the control of the voltage of the second node. The fourth output circuit is electrically connected to the third node, the first voltage signal terminal, and the second output signal terminal; the fourth output circuit is configured to transmit the first voltage signal to the second output signal terminal under the control of the voltage of the third node.

16. The shift register according to claim 15, characterized in that, The second voltage signal terminal and the fourth voltage signal terminal are the same signal terminal; or, The second voltage signal terminal and the fourth voltage signal terminal are signal terminals that transmit different voltage signals, and the voltage of the second voltage signal is higher than the voltage of the fourth voltage signal.

17. The shift register according to claim 15, characterized in that, The first output circuit includes a second transistor and a first capacitor; the second output circuit includes a fifth transistor and a second capacitor. The third output circuit includes: a seventeenth transistor; The gate of the seventeenth transistor is electrically connected to the second node, the first terminal of the seventeenth transistor is electrically connected to the fourth voltage signal terminal, and the second terminal of the seventeenth transistor is electrically connected to the second output signal terminal. The fourth output circuit includes: an eighteenth transistor; The gate of the eighteenth transistor is electrically connected to the third node, the first terminal of the eighteenth transistor is electrically connected to the first voltage signal terminal, and the second terminal of the eighteenth transistor is electrically connected to the second output signal terminal.

18. The shift register according to claim 15, characterized in that, The first output circuit includes a second transistor, and the second output circuit includes a fifth transistor; The third output circuit includes: a seventeenth transistor and a fifth capacitor; The gate of the seventeenth transistor is electrically connected to the second node, the first terminal of the seventeenth transistor is electrically connected to the fourth voltage signal terminal, and the second terminal of the seventeenth transistor is electrically connected to the second output signal terminal. The first terminal of the fifth capacitor is electrically connected to the second node, and the second terminal of the fifth capacitor is electrically connected to the fourth voltage signal terminal. The fourth output circuit includes: an eighteenth transistor and a sixth capacitor; The gate of the eighteenth transistor is electrically connected to the third node, the first terminal of the eighteenth transistor is electrically connected to the first voltage signal terminal, and the second terminal of the eighteenth transistor is electrically connected to the second output signal terminal. The first terminal of the sixth capacitor is electrically connected to the third node, and the second terminal of the sixth capacitor is electrically connected to the second output signal terminal.

19. The shift register according to claim 17 or 18, characterized in that, The shift register also includes: a fourth leakage protection circuit; The fourth leakage protection circuit is electrically connected to the second leakage protection signal terminal, the first voltage signal terminal, and the fourth leakage protection node; the fourth leakage protection circuit is configured to transmit the first voltage signal to the fourth leakage protection node under the control of the second leakage protection signal transmitted at the second leakage protection signal terminal. The second leakage protection signal terminal includes either the first output signal terminal or the second output signal terminal; The third output circuit is also electrically connected to the fourth leakage protection node.

20. The shift register according to claim 19, characterized in that, The fourth leakage protection circuit includes: a nineteenth transistor; The gate of the nineteenth transistor is electrically connected to the second anti-leakage signal terminal, the first terminal of the nineteenth transistor is electrically connected to the first voltage signal terminal, and the second terminal of the nineteenth transistor is electrically connected to the fourth anti-leakage node. The seventeenth transistor includes: a seventh sub-transistor and an eighth sub-transistor; The gate of the seventh sub-transistor is electrically connected to the second node, the first terminal of the seventh sub-transistor is electrically connected to the fourth voltage signal terminal, and the second terminal of the seventh sub-transistor is electrically connected to the fourth leakage protection node. The gate of the eighth sub-transistor is electrically connected to the second node, the first terminal of the eighth sub-transistor is electrically connected to the fourth leakage protection node, and the second terminal of the eighth sub-transistor is electrically connected to the second output signal terminal.

21. A method for driving a shift register, characterized in that, The driving method is applied to the shift register as described in any one of claims 1 to 20; the driving method includes: a first stage, a second stage, a third stage, and a fourth stage; In the first stage, in response to the first clock signal received at the first clock signal terminal, the first input circuit is turned on and transmits the first voltage signal received at the first voltage signal terminal to the first node; in response to the first clock signal, the second input circuit is turned on and transmits the input signal received at the input signal terminal to the third node; In the second stage, at least in response to the second clock signal received at the second clock signal terminal, the first control circuit is turned on to transmit the second clock signal or an electrical signal from the first node to the second node. In the third stage, in response to the voltage at the second node, the first output circuit is turned on and transmits the second voltage signal received at the second voltage signal terminal to the first output signal terminal. In the fourth stage, in response to the first clock signal, the second input circuit is turned on to transmit the input signal to the third node; in response to the voltage at the third node, the second control circuit is turned on to transmit the first control signal received at the first control signal terminal to the control node; in response to the voltage at the third node, the second output circuit is turned on to transmit the first voltage signal to the first output signal terminal.

22. A scanning drive circuit, characterized in that, The scan driving circuit includes: a plurality of shift registers as described in any one of claims 1 to 14; The first output signal terminal of the Nth shift register is electrically connected to the input signal terminal of the (N+1)th shift register, where N is a positive integer.

23. A scanning drive circuit, characterized in that, The scan driving circuit includes: a plurality of shift registers as described in any one of claims 15 to 20; The second output signal terminal of the Mth shift register is electrically connected to the input signal terminal of the (M+1)th shift register, where M is a positive integer.

24. A display device, characterized in that, The display device includes: the scanning driving circuit as described in claim 22 or 23, and a plurality of pixel driving circuits; The pixel driving circuit includes: a switching transistor, a sensing transistor, a driving transistor, a light-emitting control transistor, and a storage capacitor; The shift register in the scanning drive circuit is electrically connected to the gate of the light-emitting control transistor.

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