Time-to-digital circuit system with error protection scheme

Abstract

The present application relates to a time-to-digital circuit system with an error protection scheme. The time-to-digital circuit can provide a time measurement of an event, or a time measurement of the duration between multiple events. Various electronic devices may include one or more time-to-digital circuits. The time-to-digital circuit may include circuitry for measuring the duration of time using a thermometer code. For example, the time-to-digital circuit may generate an alternating signal using a ring oscillator upon receiving an indication of an event. Furthermore, the time-to-digital circuit may convert the alternating signal into a consistent signal having only one transition between a high signal and a low signal in multiple consecutive signals. Furthermore, the time-to-digital circuit may correct erroneous signal values ​​of the consistent signal when multiple transitions between a high signal and a low signal in the multiple consecutive signals occur.

Description

Technical Field

[0001] The present application relates to electronic devices, and more particularly to time-to-digital circuitry with error protection schemes. Background Art

[0002] This section is intended to introduce the reader to various aspects of the technology that may be related to various aspects of the present technology described and / or claimed below. It is believed that this discussion will help provide the reader with background information to facilitate a better understanding of various aspects of the present disclosure. Therefore, it should be understood that these statements should be read in this light and not as admissions of prior art.

[0003] The following generally relates to electronic devices, and more specifically to time-to-digital conversion schemes used in various electronic devices. Such electronic devices may include memory devices, processing devices, routing circuitry, and the like. In some cases, a time-to-digital converter circuit may use a clock signal to provide a digital representation of the time of an event. Alternatively or in addition, the time-to-digital converter circuit may use the clock signal to provide a digital representation of the time difference between multiple events. For example, an electronic device may use the time-to-digital converter circuit to provide an event signal, provide a redundant signal, convert a clock signal frequency, provide a time measurement of received data (e.g., sensor data), and other applications. Summary of the Invention

[0004] One aspect of the present disclosure provides an electronic device comprising: a ring oscillator configured to provide an alternating signal using an alternating code when the ring oscillator receives an indication of an event, wherein the alternating signal indicates a duration of the event; a converter configured to: receive the alternating signal provided using the alternating code; and convert the alternating signal into a consistent signal based on a thermometer code, wherein the consistent signal indicates the duration of the event; and an encoder configured to: receive the consistent signal; and provide the duration of the event based on decoding the consistent signal provided using the thermometer code.

[0005] Another aspect of the present disclosure provides a time-to-digital circuit comprising: a ring oscillator configured to provide an alternating signal using an alternating code that is an incremental count indicating a duration of an event, wherein continuous signals of the alternating signal include one or more transitions between a high value and a low value; a converter configured to receive the alternating signal, wherein the converter is configured to convert the alternating signal into a consistent signal based on a thermometer code, wherein continuous signals of the consistent signal include only one transition between a high value and a low value; a code protection circuit configured to receive the consistent signal, wherein the code protection circuit is configured to correct inconsistent signals in the consistent signal based on determining more than one transition between a high value and a low value of continuous signals in the consistent signal; and a counter configured to receive the corrected consistent signal and determine the duration of the event based on receiving the corrected consistent signal.

[0006] Another aspect of the present disclosure provides a method comprising: receiving, by a time-to-digital circuit, an indication of a start of a duration of time to be measured; providing, by the time-to-digital circuit, a coincidence signal provided by a thermometer code that is based on an incremental count indicating the duration of the time; correcting, by the time-to-digital circuit, an erroneous signal value of the coincidence signal provided based on the thermometer code; and counting, by the time-to-digital circuit, the duration of the time based on the incremental count of the corrected coincidence signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure may be better understood after reading the following detailed description and referring to the accompanying drawings, in which:

[0008] Figure 1 is a block diagram illustrating certain features of a memory device according to an embodiment of the present disclosure;

[0009] Figure 2 is a functional block diagram of a time-to-digital circuit according to an embodiment of the present disclosure;

[0010] Figure 3 According to an embodiment of the present disclosure Figure 2 The time to digital circuit schematic;

[0011] Figure 4 is an example signal according to an embodiment of the present disclosure including when a high trigger signal (EN) is received Figure 3 Schematic diagram of an embodiment;

[0012] Figure 5 According to the embodiment of the present disclosure Figure 3 A schematic diagram of a phase splitter half including three inverter circuits associated with an embodiment of the present invention;

[0013] Figure 6 According to the embodiments of the present disclosure Figure 3 A schematic diagram of a phase splitter half including two inverting circuits associated with an embodiment of the present invention; and

[0014] Figure 7 According to an embodiment of the present disclosure Figure 3 Schematic diagram of a portion of the code protection circuit for the time-to-digital circuit. DETAILED DESCRIPTION

[0015] When introducing the elements of various embodiments of the present disclosure, the words "a", "an" and "said" are intended to indicate that there are one or more of these elements. The terms "comprising", "including" and "having" are intended to be inclusive and mean that there may be additional elements in addition to the listed elements. One or more specific embodiments of the present embodiment described herein will be described below. In an effort to provide a concise description of these embodiments, not all features of the actual implementation scheme may be described in the specification. It should be understood that in the development of any such actual implementation scheme, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the specific goals of the developer, such as consistency with machine-related, system-related and enterprise-related constraints, which may vary from one implementation scheme to another. In addition, it should be understood that such development efforts may be complex and time-consuming, but will be a routine of design, construction and manufacture for those skilled in the art who benefit from this disclosure.

[0016] An electronic device may include one or more time-to-digital circuits. The electronic device may use the time-to-digital circuits to measure the time of an event, the time difference between multiple events, and other time measurements. For example, an event may include an internal or external event to the electronic device based on receipt of one or more trigger signals. The time-to-digital circuits may include ring oscillators, converters, encoders, and counters.

[0017] The ring oscillator can provide an odd number of alternating signals using an odd number of inverting circuits (e.g., NAND logic gates, inverter logic gates, etc.) coupled in series. For example, each of the alternating signals can switch between a high value (e.g., a logic 1, high) and a low value (e.g., a logic 0, low). Furthermore, the ring oscillator can provide an odd number of alternating signals in parallel with the converter.

[0018] Examples of alternating signals are presented below in Table 1. For example, a ring oscillator may provide an alternating signal to a converter based on using the alternating code shown in Table 1.

[0019]

[0020] Table 1

[0021] Furthermore, the ring oscillator may receive a trigger signal associated with an event. In some cases, the trigger signal may remain high (e.g., a logical 1) for a duration associated with the event. For example, a first event may set the trigger signal high (e.g., a high value, a logical 1), and a subsequent second event may set the trigger signal low (e.g., a low value, a logical 0). In some cases, the ring oscillator may receive a first trigger signal (e.g., a start trigger signal) indicating the start of an event and, after receiving the first trigger signal, receive a second trigger signal (e.g., a stop trigger signal) indicating the end of the event. The ring oscillator may facilitate determining a digital time representation of the duration of the event based on the trigger signal.

[0022] In some cases, a ring oscillator may provide an alternating signal having a changing pattern in response to receiving a high trigger signal. For example, the ring oscillator may provide an alternating signal having a first pattern when the trigger signal is low, and may provide an alternating signal having a second pattern when the trigger signal is high. However, when using an alternating signal, determining a first transition between the first pattern and the second pattern, or determining a second transition between the second pattern and the first pattern, may be difficult.

[0023] In some cases, using alternating signals to determine a trigger signal based on the first transition and / or the second transition can make the time-to-digital circuit susceptible to various circuit faults. Such circuit errors can result in incorrect time measurements by the time-to-digital circuit. For example, violations of the setup times of the rising and / or falling edges of one of the alternating signals can lead to metastable conditions in either a latch circuit or an encoder, among other things, which can cause such incorrect time measurements when using alternating signals.

[0024] Therefore, the time-to-digital circuit can use a converter to provide a consistent signal to the encoder based on the alternating signal received from the ring oscillator. The consistent signal can include a consistently high or low value continuous signal with one (e.g., only one) transition between high and low values ​​across multiple (e.g., one word length) continuous signals. For example, the converter can use a thermometer code to provide the consistent signal. In some cases, using a thermometer code to provide the consistent signal can increase the resolution of the time measurement. An example of a consistent signal using a thermometer code is shown in Table 2.

[0025]

[0026] Table 2

[0027] As shown in Table 2, the thermometer code may include only one transition between a high signal and a low signal after several high and / or low signals. In one example, the converter may provide a consistently high signal (e.g., only high signals) when receiving an alternating signal having a first pattern. As mentioned above, the ring oscillator may provide an alternating signal having a first pattern when the trigger signal is low.

[0028] Furthermore, based on a first transition between the first and second patterns of the alternating signal, the converter may transition to providing a consistently low signal using a thermometer code. For example, the converter may provide an odd number of consecutive low signals when receiving an odd number of alternating signals having the second pattern from an odd number of inverter circuits. As mentioned above, the ring oscillator may provide an alternating signal having the second pattern when the trigger signal is high.

[0029] Subsequently, upon continuously receiving an alternating signal having a second pattern, the converter may transition between providing an odd number of consistently low signals and an odd number of consistently high signals using a thermometer code. Thus, the converter may switch between providing consistently high and / or low signals after providing every odd number of consistently high and / or low signals, with one transition between the consistently high and / or low signals. The converter may provide consistently high signals (e.g., only high signals) in response to a second transition between the second pattern and the first pattern of the alternating signal.

[0030] In any case, the converter can provide a consistent signal using a thermometer code to the encoder when receiving the alternating code. As mentioned above, a thermometer code may include only one transition between several consecutive high or low signals. Therefore, the encoder can correct for an error signal based on comparing consecutive signals with the consistent signal provided using the thermometer code. For example, the encoder can correct for an error signal when a consecutive consistent signal provided using the thermometer code includes multiple consecutive transitions between high and low values.

[0031] In some cases, the encoder can correct the determined error signal by flipping the value of the inconsistency signal (e.g., an error signal). The encoder can then provide the corrected signal to a counter for measuring time. The counter can provide a digital time representation of the duration of receiving a consistent signal transitioning between an odd number of consistent low signals and an odd number of consistent high signals. Thus, the time-to-digital circuit can measure the time of an event, the time difference between multiple events, and other time measurements based on the duration of the trigger signal.

[0032] Time-to-digital circuits can use a consistent signal (e.g., a thermometer code) to provide accurate time measurements based on detecting and correcting erroneous signals. For example, an encoder can correct erroneous signals caused by metastable conditions when providing the consistent signal to a counter. As a result, the time-to-digital circuit can become more reliable. In some cases, using such a time-to-digital circuit can reduce the test time and / or number of operations used for time measurement based on the improved reliability.

[0033] Turning now to the accompanying drawings, Figure 1 A simplified block diagram illustrating certain features of a memory device 100 (e.g., a memory subsystem of a device) is depicted. Specifically, Figure 1 The block diagram depicts a functional block diagram of certain functionalities of the memory device 100. According to one embodiment, the memory device 100 may include a random access memory (RAM) device, a ferroelectric RAM (FeRAM) device, a dynamic RAM (DRAM) device, a static RAM (SRAM) device (including a double data rate SRAM device), a flash memory, and / or a 3D memory array including a phase change (PC) memory and / or other chalcogenide-based memory such as a select-by-slave memory (SSM). Furthermore, each memory cell of such a 3D memory array may include a corresponding logical storage device (e.g., a capacitor, a resistor, or a resistor of a chalcogenide material).

[0034] The memory device 100 may include several memory banks 102, each memory bank including one or more memory arrays. Various configurations, organizations, and sizes of the memory banks 102 on the memory device 100 may be used based on the application and / or design of the memory device 100 within the power system. For example, in different embodiments, the memory banks 102 may include different numbers of rows and / or columns of memory cells. Furthermore, the memory banks 102 may each include several pins for communicating with other blocks of the memory device 100. For example, each memory bank 102 may receive one data bit per pin per clock cycle.

[0035] Memory device 100 may also include a command interface 104 and an input / output (I / O) interface 106. Command interface 104 is configured to provide a number of signals received from a processor (e.g., a processor subsystem of a device) or a controller such as memory controller 108. In various embodiments, memory controller 108, hereinafter referred to as controller 108, may include one or more processors (e.g., memory processors), one or more programmable logic fabrics, or any other suitable processing component.

[0036] In some embodiments, bus 110 may provide a signal path or a set of signal paths to allow bidirectional communication between controller 108, command interface 104, and I / O interface 106. For example, controller 108 may receive memory access requests from I / O interface 106 via command interface 104 and bus 110. Furthermore, controller 108 may provide access commands and / or access instructions for performing memory operations to command interface 104 via bus 110.

[0037] Similarly, the external bus 112 may provide another signal path or set of signal paths to allow bidirectional transmission of signals such as data signals and access commands (e.g., read / write requests) between the I / O interface 106, the controller 108, the command decoder 120, and / or other components. Thus, the controller 108 may provide various signals (e.g., access commands, access instructions, or other signals) to different components of the memory device 100 to facilitate the transmission and reception of data to be written to or read from the memory banks 102.

[0038] Nonetheless, command interface 104 may still receive various signals from controller 108. For example, a reset command may be used during power-up to reset command interface 104, status registers, state machines, and the like. Various test signals may also be provided to memory device 100. For example, controller 108 may use such test signals to test the connectivity of different components of memory device 100. In some embodiments, command interface 104 may also provide an alert signal to controller 108 upon detecting an error in memory device 100. Furthermore, I / O interface 106 may additionally or alternatively be used to provide such alert signals, for example, to other system components electrically connected to memory device 100.

[0039] The command interface 104 may also receive one or more clock signals (e.g., an external clock signal) from an external device. Furthermore, the command interface 104 may include a clock input circuit 114 (CIC) and a command address input circuit 116 (CAIC). The command interface 104 may use the clock input circuit 114 and the command address input circuit 116 to receive input signals, including access commands, to facilitate communication with the memory banks 102 and other components of the memory device 100.

[0040] Furthermore, the clock input circuit 114 can receive the one or more clock signals (e.g., external clock signals) and can generate an internal clock signal (CLK) therefrom. In some embodiments, the command interface 104 can provide the CLK to the command decoder 120 and an internal clock generator, such as a delay-locked loop (DLL) 118 circuit. The DLL 118 can generate a phase-controlled internal clock signal (LCLK) based on the received CLK. For example, the DLL 118 can provide the LCLK to the I / O interface 106. The I / O interface 106 can then use the received LCLK as a clock signal for transmitting read data using the external bus 112.

[0041] The command interface 104 may also provide an internal clock signal CLK to various other memory components. As mentioned above, the command decoder 120 may receive the internal clock signal CLK. In some cases, the command decoder 120 may also receive access commands received via the external bus 112 via the bus 122 and / or via the I / O interface 106. For example, the command decoder 120 may receive access commands transmitted by one or more external devices via the I / O interface 106. In some cases, the processor may transmit the access commands.

[0042] The command decoder 120 can decode the access command and / or the memory access request to provide a corresponding access instruction for accessing the target memory unit. For example, the command decoder 120 can provide the access instruction to one or more control blocks 132 associated with the memory bank 102 via the bus path 126. In some cases, the command decoder 120 can provide the access instruction to the control block 132 in coordination with the DLL 118 via the bus 124. For example, the command decoder 120 can coordinate the generation of the access instruction in parallel (e.g., synchronously) with the CLK and / or LCLK.

[0043] In some embodiments, each memory bank 102 may include a corresponding control block 132. In some cases, each of the control blocks 132 may also provide row decoding and column decoding capabilities based on received access instructions. Thus, the control blocks 132 may facilitate accessing the memory cells of the corresponding memory bank 102. For example, the control blocks 132 may include circuitry (e.g., logic circuitry) to facilitate accessing the memory cells of the corresponding memory bank 102 based on received access instructions.

[0044] In some cases, the control block 132 may receive the access instruction and determine the target memory bank 102 associated with the target memory cell. In certain cases, the command decoder 120 may include the control block 132. In addition, the control block 132 may also provide timing control and data control functions to facilitate the execution of different commands with respect to the corresponding memory bank 102.

[0045] Furthermore, the command decoder 120 may provide register commands to the one or more registers 128 to facilitate operation of one or more of the memory banks 102, the control block 132, etc. For example, one of the one or more registers 128 may provide instructions for configuring various modes of programmable operation and / or configuration of the memory device 100. The one or more registers 128 may be included in various semiconductor devices to provide and / or define the operation of various components of the memory device 100.

[0046] In some embodiments, the one or more registers 128 may provide configuration information to define the operation of the memory device 100. For example, the one or more registers 128 may include operating instructions for DRAM, synchronous DRAM, FeRAM, chalcogenide memory (e.g., SSM memory, PC memory), or other types of memory. As discussed above, the one or more registers 128 may receive various signals from the command decoder 120 or other components via the one or more global wires 130.

[0047] In some embodiments, the one or more global wires 130 may include a common data path, a common address path, a common write command path, and a common read command path. The one or more global wires 130 may traverse the memory device 100 so that each of the one or more registers 128 may be coupled to the global wire 130. Additional registers may involve additional wiring across a semiconductor device (e.g., a die) so that the registers are communicatively coupled to corresponding memory components.

[0048] The I / O interface 106 may include several pins (e.g., 7 pins) to facilitate data communication with external components (e.g., processing components such as a processor). Specifically, the I / O interface 106 may receive access commands via the pins. Furthermore, data stored on the memory cells of the memory banks 102 may be transmitted to and / or retrieved from the memory banks 102 via data paths 134. The data paths 134 may include multiple bidirectional data buses that pass through the I / O interface 106 to one or more external devices. For some memory devices, such as DDR5 SDRAM memory devices, the I / O signals may be divided into upper and lower bytes; however, such segmentation is not used with other memory device types.

[0049] Nevertheless, in different embodiments, the memory device 100 may also include additional or alternative components. That is, the memory device 100 may include additional or alternative components, such as a power supply circuit (for receiving external VDD and VSS signals), a read / write amplifier (for amplifying signals during read / write operations), a temperature sensor (for sensing the temperature of the memory device 100), etc. Therefore, it should be understood that only the following examples are provided. Figure 1 The block diagram is used to highlight certain functional features of the memory device 100 to facilitate the subsequent detailed description.

[0050] Figure 2 A functional block diagram of a time-to-digital circuit 200 is depicted. Various electronic devices may include the time-to-digital circuit 200. The time-to-digital circuit 200 can measure the time of an event and / or the time difference between multiple events, as well as other time measurements. In some cases, the memory device 100 may include the time-to-digital circuit 200. For example, the DLL 118 of the memory device 100 may include the time-to-digital circuit 200. In certain cases, the DLL 118 of the memory device 100 may use the time-to-digital circuit 200 to provide an LCLK using a similar or different operating frequency based on the received CLK. The time-to-digital circuit can also be used to measure other timing parameters, such as transistor toggle speed or other timing intervals of interest.

[0051] In any case, time-to-digital circuit 200 may include ring oscillator 202, converter 204, and encoder 206. Encoder 206 may include latch circuit 208, code protection circuit 210, and counter 212. However, it should be understood that in different embodiments, time-to-digital circuit 200 may include additional or different functional blocks.

[0052] Ring oscillator 202 can provide (e.g., output) an odd number of parallel alternating signals to converter 204 using an odd number of inverter circuits coupled in series. The signal can propagate through the odd number of inverter circuits coupled in series (e.g., cascaded) to provide an odd number of parallel alternating signals. Furthermore, the signal can be looped through ring oscillator 202. For example, the first inverter circuit in the odd number of inverter circuits can receive the output of the last inverter circuit to form a feedback loop. While passing through each of the inverter circuits, the value of the signal can switch between a logic 1 and a logic 0 value. The signal can propagate through ring oscillator 202 using a first mode based on the odd number of inverter circuits.

[0053] The first inverting circuit of ring oscillator 202 may also receive a trigger signal. The trigger signal may be generated and / or provided based on a trigger event. In some cases, ring oscillator 202 may change the mode of providing an odd number of parallel alternating signals based on receiving a high trigger signal. In certain cases, a high trigger signal may indicate a time-measured duration of the event. For example, the trigger signal may remain high for the time-measured duration. In other cases, ring oscillator 202 may change the mode of providing an odd number of parallel alternating signals based on receiving a low trigger signal.

[0054] As mentioned above, the value of the signal can switch between a logic 1 and a logic 0 value when passing through each of the inverting circuits. For example, ring oscillator 202 can use an alternating code to provide a parallel alternating signal. In some cases, ring oscillator 202 can indicate the duration of an event by changing the pattern in which the alternating signal is provided. For example, ring oscillator 202 can use a first pattern to provide the alternating signal when a low trigger signal is received and a second pattern to provide the alternating signal when a high trigger signal is received. Furthermore, a downstream block can determine the duration of the event based on detecting a switch in the pattern in which the alternating signal is provided to the downstream block.

[0055] In some cases, when using an alternating signal, the time-to-digital circuit 200 may become susceptible to errors and incorrect time measurements. For example, a metastable condition of a circuit component, a setup timing violation of a signal that continuously (e.g., repeatedly) switches between high and low values, etc. may result in providing an erroneous alternating signal that may cause incorrect time measurements.

[0056] Thus, as will be appreciated, converter 204 can convert alternating signals into uniform signals to facilitate error correction for downstream blocks. For example, converter 204 can include circuitry to receive a set of parallel alternating signals from ring oscillator 202, convert the alternating signals into uniform signals, and provide the parallel uniform signals to latch circuit 208 of encoder 206. In some cases, converter 204 can provide the uniform signals using a thermometer code.

[0057] In some cases, converter 204 may provide a consistent signal having a consistently high signal when receiving an alternating signal having a first pattern (e.g., when the ring oscillator receives a low trigger signal). Furthermore, converter 204 may provide a consistent signal that switches between high and low values ​​based on the length (e.g., number) of the received parallel alternating signals when receiving an alternating signal having a second pattern (e.g., when the ring oscillator receives a high trigger signal). For example, converter 204 may switch between providing an odd number of low signals followed by an odd number of high signals, and so on, based on using a thermometer code to indicate the time associated with the high trigger signal.

[0058] The latch circuit 208 can latch the value of the parallel consensus signal received at each clock cycle. In some cases, the consensus signal (e.g., parallel consensus signal) latched at each clock cycle can include a number of consistent low signals followed by a number of consistent high signals (e.g., 000001111, 000011111, 000111111, etc.), a number of consistent high signals followed by a number of consistent low signals (e.g., 111000000, 111100000, 111110000, etc.), an odd number of consistent low signals (e.g., 000000000), or an odd number of consistent high signals (e.g., 111111111). In any case, the parallel consensus signal latched at each clock cycle can include zero or one transitions between high and low signals.

[0059] In one example, each row of the thermometer code in Table 2 above depicts the value of the parallel consensus signal at a different clock cycle. As depicted in Table 2, the parallel consensus signal may include zero or one transitions between a high signal and a low signal for each corresponding clock cycle. As will be appreciated, code protection circuit 210 may identify an erroneous signal by identifying more than one transition between a high signal and a low signal. Thus, converter 204 may provide a consensus signal to facilitate error correction in downstream blocks.

[0060] In one embodiment, a clock cycle may correspond to a Figure 1 DLL 118. In other embodiments, latch circuit 208 may use clock cycles of different clock signals. In any case, latch circuit 208 may provide the latched value of the coincidence signal on subsequent clock cycles to code protection circuit 210.

[0061] As mentioned above, code protection circuit 210 can identify and correct erroneous signals in received parallel consensus signals. Code protection circuit 210 can include circuitry to identify erroneous signals in the consensus signal based on comparing consecutive signals in the received parallel consensus signal. For example, multiple toggles in the consensus signal between high and low values ​​can indicate inconsistency according to the thermometer code specification. Therefore, when the received parallel consensus signal includes multiple consecutive toggles between high and low values, code protection circuit 210 can correct the erroneous signals in the consensus signal.

[0062] Furthermore, the code protection circuit 210 may include circuitry for correcting the identified error signal. The code protection circuit 210 may then provide the corrected coincidence signal to the counter 212. Thus, the counter 212 may determine the duration of the signal based on receipt of the corrected coincidence signal. In one example, the counter 212 may provide a final count of the duration when the trigger signal goes low. In another example, the counter 212 may continuously provide a count of the duration until the trigger signal goes low. The converter 204 and the code protection circuit 210 may improve the operational efficiency of the time-to-digital circuit 200 by measuring the duration of time based on the use of the coincidence signal.

[0063] With the above ideas, Figure 3 A schematic diagram 300 depicts one embodiment of the time-to-digital circuit 200. Specifically, Figure 3 The depicted portion of the time-to-digital circuit 200 may include a schematic diagram of a ring oscillator 202, a schematic diagram of a converter 204, a schematic diagram of a latch circuit 208, a block diagram of a code protection circuit 210, and a block diagram of a counter 212. The ring oscillator 202 may include an odd number of inverter circuits coupled in series. In the depicted embodiment, the ring oscillator 202 may include a NAND gate 302 and eight inverters 304-1, 304-2, 304-3, 304-4, 304-5, 304-6, 304-7, and 304-8.

[0064] NAND gate 302 and inverters 304-1, 304-2, 304-3, 304-4, 304-5, 304-5, 304-6, 304-7, and 304-8 may be coupled in series. Each of NAND gate 302 and inverters 304-1, 304-2, 304-3, 304-4, 304-5, 304-5, 304-6, 304-7, and 304-8 may receive an output signal from the corresponding inverting circuit coupled thereto, such that NAND gate 302 may receive (e.g., input) the output of inverter 304-8.

[0065] NAND gate 302 may also receive a trigger signal (EN) 306. Time-to-digital circuit 200 may measure the time associated with receiving a high trigger signal (EN) 306. For example, a ring oscillator may provide alternating signals (R0-R8) 308-1, 308-2, 308-3, 308-4, 308-5, 308-6, 308-7, 308-8, and 308-9 in parallel to converter 204 at each clock cycle (e.g., T0, T1, T2, etc.). Example embodiments of trigger signal (EN) 306 and alternating signals (R0-R8) 308-1, 308-2, 308-3, 308-4, 308-5, 308-6, 308-7, 308-8, and 308-9 are provided below in Table 3.

[0066] Table 3 depicts successive steps in time (e.g., T1, T2, T3, T4, T5, T6, T7, T8, and T9) when the ring oscillator 202 is operating. For example, in the successive steps in time shown in Table 3 below, a high or low signal may continuously propagate through the NAND gate 302 and the inverters 304-1, 304-2, 304-3, 304-4, 304-5, 304-5, 304-6, 304-7, and 304-8. However, each of the AND gate 302 and the inverters 304-1, 304-2, 304-3, 304-4, 304-5, 304-5, 304-6, 304-7, and 304-8 may use a different amount of time for the signal to propagate to subsequent circuits.

[0067] In Table 3 below, the ring oscillator 202 may provide alternating signals (R0-R8) 308-1, 308-2, 308-3, 308-4, 308-5, 308-6, 308-7, 308-8, and 308-9 using a first mode when the NAND gate 302 receives a low trigger signal (EN) 306 (e.g., at T0, T1, T2, T8, and T9 in Table 3). Furthermore, the ring oscillator 202 may provide alternating signals (R0-R8) 308-1, 308-2, 308-3, 308-4, 308-5, 308-6, 308-7, 308-8, and 308-9 using a second mode when the ring oscillator 202 receives a high trigger signal (EN) 306 (e.g., at T3, T4, T5, T6, and T7 in Table 3). The transition between the first mode and the second mode may indicate a change in the value of the trigger signal (EN) 306. Such transitions are shown with respect to the signal in different steps in time in Table 3 below.

[0068] As mentioned above, the duration of the high trigger signal (EN) 306 can indicate the duration of the event. NAND gates 302 and 304-2, 304-3, 304-4, 304-5, 304-5, 304-6, 304-7, and 304-8 can provide alternating signals (R0-R8) 308-1, 308-2, 308-3, 308-4, 308-5, 308-6, 308-7, 308-8, and 308-9 at times T1, T2, T3, T4, T5, T6, T7, T8, and T9, respectively. In the example embodiment of Table 3, NAND gate 302 can receive the high trigger signal (EN) 306 and the alternating signal 308-9 at time T4 (e.g., the step in time when the logic level propagates around the ring oscillator 202). As mentioned above, each of times T1 , T2, T3, T4, T5, T6, T7, T8, and T9 may be a step in time depicting the propagation of alternating logic levels through and around ring oscillator 202 .

[0069] Therefore, the ring oscillator 202 may change the mode of providing the alternating signals (R0-R8) 308-1, 308-2, 308-3, 308-4, 308-5, 308-6, 308-7, 308-8, and 308-9 based on receiving the high trigger signal (EN) 306. The NAND gate 302 and the inverters 304-1, 304-2, 304-3, 304-4, 304-5, 304-5, 304-6, 304-7, and 304-8 of the ring oscillator 202 may use the second mode to provide the alternating signals (R0-R8) 308-1, 308-2, 308-3, 308-4, 308-5, 308-6, 308-7, 308-8, and 308-9.

[0070] For example, when the first mode is used to provide the R0 signal based on receiving the low trigger signal (EN) 306, the NAND gate 302 may provide a high R0 signal at each time step (e.g., T0, T1, T2, T8, and T9). However, when the second mode is used to provide the R0 signal based on receiving the high trigger signal (EN) 306, the NAND gate 302 may provide a low R0 signal at each time step (e.g., T3-T7).

[0071]

[0072] Table 3

[0073] In any case, the converter 204 can receive the alternating signals (R0-R8) 308-1, 308-2, 308-3, 308-4, 308-5, 308-6, 308-7, 308-8, and 308-9. In some cases, the phase splitter circuit can include a first circuit portion including an inverting delay path and a second circuit portion including a non-inverting delay path. Figure 3 In the depicted embodiment, the converter 204 may include inverting and non-inverting delay paths with matched propagation delays. Thus, the depicted inverting and non-inverting delay paths may be referred to hereinafter as phase splitter halves.

[0074] Converter 204 may convert received alternating signals (R0-R8) 308-1, 308-2, 308-3, 308-4, 308-5, 308-6, 308-7, 308-8, and 308-9 into consistent signals using phase splitter halves 310-1, 310-2, 310-3, 310-4, 310-5, 312-1, 312-2, 312-3, and 312-4. Thus, the phase splitter halves 310-1, 310-2, 310-3, 310-4, 310-5, 312-1, 312-2, 312-3, and 312-4 can provide the coincidence signals (D0-D8) 314-1, 314-2, 314-3, 314-4, 314-5, 314-6, 314-7, 314-8, and 314-9. However, in alternative or additional cases, the converter 204 can include other circuitry to provide the coincidence signals (D0-D8) 314-1, 314-2, 314-3, 314-4, 314-5, 314-6, 314-7, 314-8, and 314-9.

[0075] Referring back to Table 3 above, the ring oscillator 202 can use an alternating code to provide alternating signals (R0-R8) 308-1, 308-2, 308-3, 308-4, 308-5, 308-6, 308-7, 308-8, and 308-9. As shown in the example embodiment of Table 3, the consecutive alternating signals (R0-R8) 308-1, 308-2, 308-3, 308-4, 308-5, 308-6, 308-7, 308-8, and 308-9 can switch between high and low values ​​(e.g., using a first mode or a second mode). Thus, in one embodiment, the phase splitter halves 310-1, 310-2, 310-3, 310-4, and 310-5 may include two inverting circuits (e.g., inverters), and the phase splitter halves 312-1, 312-2, 312-3, and 312-4 may include three inverting circuits (e.g., inverters) to convert the alternating signals (R0-R8) 308-1, 308-2, 308-3, 308-4, 308-5, 308-6, 308-7, 308-8, and 308-9 into coincident signals (D0-D8) 314-1, 314-2, 314-3, 314-4, 314-5, 314-6, 314-7, 314-8, and 314-9.

[0076] Table 4 below contains examples of coincidence signals (D0-D8) 314-1, 314-2, 314-3, 314-4, 314-5, 314-6, 314-7, 314-8, and 314-9 at successive steps in time, T0, T1, T2, T3, T4, T5, T6, T7, T8, and T9. When NAND gate 302 receives a low trigger signal (EN) 306, converter 204 may provide high coincidence signals (D0-D8) 314-1, 314-2, 314-3, 314-4, 314-5, 314-6, 314-7, 314-8, and 314-9. As mentioned above, when the NAND gate 302 receives the low trigger signal (EN) 306 , the ring oscillator 202 may provide alternating signals ( R0 - R8 ) 308 - 1 , 308 - 2 , 308 - 3 , 308 - 4 , 308 - 5 , 308 - 6 , 308 - 7 , 308 - 8 , and 308 - 9 using the first mode. Thus, when receiving the alternating signals (R0-R8) 308-1, 308-2, 308-3, 308-4, 308-5, 308-6, 308-7, 308-8, and 308-9 using the first pattern, the converter 204 may use the phase splitter halves 310-1, 310-2, 310-3, 310-4, 310-5, 312-1, 312-2, 312-3, and 312-4 to provide high coincident signals (D0-D8) 314-1, 314-2, 314-3, 314-4, 314-5, 314-6, 314-7, 314-8, and 314-9.

[0077] When the NAND gate 302 receives a high trigger signal (EN) 306 , the converter 204 may switch to provide coincident signals ( D0 - D8 ) 314 - 1 , 314 - 2 , 314 - 3 , 314 - 4 , 314 - 5 , 314 - 6 , 314 - 7 , 314 - 8 , and 314 - 9 having low values. In some cases, the converter 204 may provide a number of low consistent signals (D0-D8) 314-1, 314-2, 314-3, 314-4, 314-5, 314-6, 314-7, 314-8, and 314-9 based on the length (e.g., number) of the received parallel alternating signals (R0-R8) 308-1, 308-2, 308-3, 308-4, 308-5, 308-6, 308-7, 308-8, and 308-9 in response to the NAND gate 302 receiving the sustained high trigger signal (EN) 306. For example, based on a time measurement using a thermometer code to indicate a high trigger signal, the converter 204 may switch between providing an odd number of low signals followed by an odd number of high signals, and so on.

[0078] With the foregoing in mind, the ring oscillator 202 may switch from providing alternating signals (R0-R8) 308-1, 308-2, 308-3, 308-4, 308-5, 308-6, 308-7, 308-8, and 308-9 using the first mode to the second mode based on receipt of the trigger signal 306. Consequently, the converter 204 may transition from providing high coincidence signals (D0-D8) 314-1, 314-2, 314-3, 314-4, 314-5, 314-6, 314-7, 314-8, and 314-9 to low coincidence signals (D0-D8) 314-1, 314-2, 314-3, 314-4, 314-5, 314-6, 314-7, 314-8, and 314-9 based on the switching. As will be appreciated, the transitions between high and low signals may be propagated through coincident signals (D0-D8) 314-1, 314-2, 314-3, 314-4, 314-5, 314-6, 314-7, 314-8, and 314-9 in successive steps in time, T0, T1, T2, T3, T4, T5, T6, T7, T8, and T9.

[0079] For example, as shown in the example embodiment of Table 4 below, the phase splitter half 310-1 may receive an alternating signal (R0) 308-1 having a second pattern. The phase splitter half 310-1 may provide a low coincident signal (D0) 314-1 at a first step in time (e.g., T3) based on receiving the alternating signal (R0) 308-1 having the second pattern. Subsequently, the phase splitter half 312-2 may receive an alternating signal (R1) 308-2 having a second pattern. The phase splitter half 312-1 may provide a low coincident signal (D1) 314-2 at a subsequent step in time (e.g., T4) based on receiving the alternating signal (R1) 308-2 having the second pattern.

[0080] Similarly, in subsequent steps in time (e.g., T5, T6, T7, T8, T9, T10), the phase splitter halves 310-2, 312-2, 310-3, 312-3, 310-4, 312-4, and 310-5 of the converter 204 may receive alternating signals (R2-R8) 308-3, 308-4, 308-5, 308-6, 308-7, 308-8, and 308-9 having a second pattern. Thus, based on receiving the alternating signals (R2-R8) 308-3, 308-4, 308-5, 308-6, 308-7, 308-8, and 308-9 having the second pattern, the phase splitter halves 310-2, 312-2, 310-3, 312-3, 310-4, 312-4, and 310-5 may each provide low consistent signals (D2-D8) 314-3, 314-4, 314-5, 314-6, 314-7, 314-8, and 314-9 at corresponding subsequent steps in time (e.g., T5, T6, T7, T8, T9, and T10).

[0081] Thus, at each step in time (e.g., T0, T1, T2, T3, T4, T5, T6, T7, T8, T9, or T10), the phase splitter halves 310-1, 310-2, 310-3, 310-4, 310-5, 312-1, 312-2, 312-3, and 312-4 may provide consistent signals (D0-D8) 314-1, 314-2, 314-3, 314-4, 314-5, 314-6, 314-7, 314-8, and 314-9 having only high signals, only low signals, or only one transition between high and low signals. Such transitions between high and low signals are illustrated in Table 4 below, which are propagated via the coincidence signals (D0-D8) 314-1, 314-2, 314-3, 314-4, 314-5, 314-6, 314-7, 314-8, and 314-9 when the alternating signals (R0-R8) 308-1, 308-2, 308-3, 308-4, 308-5, 308-6, 308-7, 308-8, and 308-9 using the second pattern are received at each step in time. As will be appreciated, providing the coincidence signals (D0-D8) 314-1, 314-2, 314-3, 314-4, 314-5, 314-6, 314-7, 314-8, and 314-9 using a thermometer code can facilitate error correction by the code protection circuit 210.

[0082]

[0083]

[0084] Table 4

[0085] In any case, converter 204 may provide coincidence signals (D0-D8) 314-1, 314-2, 314-3, 314-4, 314-5, 314-6, 314-7, 314-8, and 314-9 in parallel to latch circuit 208 of encoder 206. Latch circuit 208 may include latches 316-1, 316-2, 316-3, 316-4, 316-5, 316-6, 316-7, 316-8, and 316-9. Thus, latches 316-1, 316-2, 316-3, 316-4, 316-5, 316-5, 316-6, 316-7, 316-8, and 316-9 can receive (e.g., latch) coincidence signals (D0-D8) 314-1, 314-2, 314-3, 314-4, 314-5, 314-6, 314-7, 314-8, and 314-9 in parallel. In the depicted embodiment, latches 316-1, 316-2, 316-3, 316-4, 316-5, 316-5, 316-6, 316-7, 316-8, and 316-9 can also receive clock signal 318. In different cases, the clock signal can be the same as described above. Figure 1 CLK or LCLK as described in , or any other feasible clock signal.

[0086] For example, latches 316-1, 316-2, 316-3, 316-4, 316-5, 316-5, 316-6, 316-7, 316-8, and 316-9 may clock (e.g., latch) parallel coincidence signals (D0-D8) 314-1, 314-2, 314-3, 314-4, 314-5, 314-6, 314-7, 314-8, and 314-9 based on clock signal 318. Subsequently, latches 316-1, 316-2, 316-3, 316-4, 316-5, 316-5, 316-6, 316-7, 316-8, and 316-9 may provide latched signals (Q0-Q8) 320-1, 320-2, 320-3, 320-4, 320-5, 320-6, 320-7, 320-8, and 320-9 to the code protection circuit 210 in parallel.

[0087] The latches 316-1, 316-2, 316-3, 316-4, 316-5, 316-5, 316-6, 316-7, 316-8, and 316-9 may provide latched signals (Q0-Q8) 320-1, 320-2, 320-3, 320-4, 320-5, 320-6, 320-7, 320-8, and 320-9, for example, using an increasing integer value that indicates the duration of time associated with an event using a thermometer code. However, in some cases, the latched signals (Q0-Q8) 320-1, 320-2, 320-3, 320-4, 320-5, 320-6, 320-7, 320-8, and 320-9 may include one or more error signals. In these cases, the code protection circuit 210 can correct the one or more error signals by correcting the thermometer code. Figure 7 An example embodiment of the code protection circuit 210 is described.

[0088] In any case, code protection circuit 210 may provide corrected signals (QA0-QA8) 322-1, 322-2, 322-3, 322-4, 322-5, 322-6, 322-7, 322-8, and 322-9 to counter 212. In some cases, counter 212 may determine an integer value for the duration of time associated with the event based on receiving corrected signals (QA0-QA8) 322-1, 322-2, 322-3, 322-4, 322-5, 322-6, 322-7, 322-8, and 322-9. For example, counter 212 may determine the duration of time associated with the event based on decoding a thermometer code. Thus, the time-to-digital circuit 200 may provide a corrected duration measurement of an event by correcting the coincidence signals (D0-D8) 314-1, 314-2, 314-3, 314-4, 314-5, 314-6, 314-7, 314-8, and 314-9 provided using a thermometer code.

[0089] Figure 4 An example embodiment of a schematic diagram 300 including example signals is depicted. The example embodiment of schematic diagram 300 depicts example signals when ring oscillator 202 receives a high trigger signal (EN) 306. The example signals are depicted to illustrate the parallel flow of alternating signals (R0-R8) 308-1, 308-2, 308-3, 308-4, 308-5, 308-6, 308-7, 308-8, and 308-9 through converter 204, latch circuit 208, and code protection circuit 210 in response to receiving the high trigger signal.

[0090] Strobe 400 is depicted to indicate the propagation of a transition between a first mode and a second mode for providing alternating signals (R0-R8) 308-1, 308-2, 308-3, 308-4, 308-5, 308-6, 308-7, 308-8, and 308-9 in response to receiving a high trigger signal by NAND gate 302. For example, inverters 304-4, 304-5, 304-6, 304-7, and 304-8 can provide alternating signals (R4-R8) 308-5, 308-6, 308-7, 308-8, and 308-9 using the first mode. Additionally, NAND gate 302 and inverters 304-1, 304-2, and 304-3 can provide alternating signals (R0-R3) 308-1, 308-2, 308-3, and 308-4 using the second mode.

[0091] In the depicted embodiment, the converter 204 can provide low coincidence signals (D0-D3) 314-1, 314-2, 314-3, and 314-4 using the phase splitter halves 310-1, 312-1, 310-2, and 312-2. The converter 204 can provide low coincidence signals (D0-D3) 314-1, 314-2, 314-3, and 314-4 in response to receiving the alternating signals (R0-R3) 308-1, 308-2, 308-3, and 308-4 using the second mode.

[0092] In addition, the converter 204 can provide high coincident signals (D4-D8) 314-5, 314-6, 314-7, 314-8, and 314-9 using the phase splitter halves 310-3, 312-3, 310-4, 312-4, and 310-5. The converter 204 can provide high coincident signals (D4-D8) 314-5, 314-6, 314-7, 314-8, and 314-9 in response to receiving the alternating signals (R4-R8) 308-5, 308-6, 308-7, 308-8, and 308-9 using the first mode.

[0093] A strobe signal 402 is also depicted to illustrate transitions at the output of the latch circuit 208 based on the parallel streams of alternating signals (R0-R8) 308-1, 308-2, 308-3, 308-4, 308-5, 308-6, 308-7, 308-8, and 308-9 through the converter 204 and the latch circuit 208. Accordingly, the latches 316-1, 316-2, 316-3, and 316-4 may provide low latched signals (Q0-Q3) 320-1, 320-2, 320-3, and 320-4 based on receiving the low coincidence signals (D0-D3) 314-1, 314-2, 314-3, and 314-4. Furthermore, latches 316-5, 316-6, 316-7, 316-8, and 316-9 may provide high latched signals (Q4-Q8) 320-5, 320-6, 320-7, 320-8, and 320-9 based on receiving high coincidence signals (D4-D8) 314-5, 314-6, 314-7, 314-8, and 314-9.

[0094] However, in the depicted example, latched signal (Q5) 320-6 is erroneously low. For example, a metastable condition in latch 316-7, a timing violation in coincidence signal 314-7, and the like can cause latched signal (Q5) 320-6 to be erroneously low. As mentioned above, a thermometer code can use a transition between high and low values ​​in a continuous signal. Therefore, code protection circuit 210 can correct the erroneous signal (e.g., latched signal (Q5) 320-6 erroneously low) based on comparing continuous parallel signals. Subsequently, code protection circuit 210 can provide the corrected signal (e.g., a high latched signal (Q5) 320-6) to downstream components (e.g., counter 212).

[0095] In some cases, the code protection circuit 210 can correct an erroneous latched signal (Q5) 320-6 by comparing the latched signals (Q4-6) 320-5, 320-6, and 320-7. For example, the code protection circuit 210 can correct an erroneous latched signal (Q5) 320-6 based on determining multiple transitions between high and low values ​​when comparing the latched signals (Q4-6) 320-5, 320-6, and 320-7. Subsequently, the code protection circuit 210 can provide corrected signals (QA0-QA8) 322-1, 322-2, 322-3, 322-4, 322-5, 322-6, 322-7, 322-8, and 322-9, including a high corrected signal (QA5) 322-6. Thus, counter 212 may provide a correct time measurement of the duration of an event based on receiving corrected signals (QA0-QA8) 322-1, 322-2, 322-3, 322-4, 322-5, 322-6, 322-7, 322-8, and 322-9.

[0096] Figure 5 A schematic diagram 500 depicts the phase splitter halves 312 (e.g., phase splitter halves 312-1, 312-2, 312-3, and 312-4) and latches 316 (e.g., latches 316-2, 316-4, 316-6, and 316-8). As mentioned above, in some cases, the phase splitter halves 312 may include three inverters. In the depicted embodiment, the phase splitter halves 312 may include inverter circuits 502, 504, and 506 coupled in series.

[0097] Inverting circuit 502 may include switches 508 and 510, inverting circuit 504 may include switches 512 and 514, and inverting circuit 506 may include switches 516 and 518. In various embodiments, switches 508, 510, 512, 514, 516, and 518 may be variable resistance transistors, MOSFETs, combinations thereof, or any other feasible switching elements.

[0098] In any case, each of the inverting circuits 502, 504, and 506 can invert the alternating signal 308 by applying a peripheral voltage (VPERI) or a ground voltage to flip the polarity of the alternating signal 308. Furthermore, each of the inverting circuits 502, 504, and 506 can flip the value or polarity of the alternating signal 308 based on a corresponding delay. The phase splitter half 312 can flip the alternating signal 308 (e.g., by flipping the alternating signal 308 three times) to provide the coincidence signal 314.

[0099] However, in alternative or additional embodiments, the time-to-digital circuit 200 may utilize different inverter circuits and / or phase splitter halves 312. Furthermore, in alternative or additional embodiments, the phase splitter halves 312 may include different odd numbers of inverter circuits. In any case, the phase splitter halves 312 may invert the alternating signal 308 to provide the coincidence signal 314. Furthermore, the latch 316 may provide a latched signal 320 based on receiving the coincidence signal 314 and the clock signal 318.

[0100] Figure 6 A schematic diagram 600 depicts the phase splitter halves 310 (e.g., phase splitter halves 310-1, 310-2, 310-3, 310-4, and 310-5) and latches 316 (e.g., latches 316-1, 316-3, 316-5, 316-7, and 316-9). As mentioned above, in some cases, the phase splitter halves 310 may include two inverters. In the depicted embodiment, the phase splitter halves 310 may include inverter circuits 602 and 604 coupled in series.

[0101] Inverting circuit 602 may include switches 606 and 608, and inverting circuit 604 may include switches 610 and 612. In various embodiments, switches 606, 608, 610, and 612 may be variable resistance transistors, MOSFETs, combinations thereof, or any other feasible switches. In the depicted embodiment, each of inverting circuits 602 and 604 may invert alternating signal 308 by inverting the polarity or value of the alternating signal by providing a peripheral voltage (VPERI) or a ground voltage. Phase splitter half 312 may provide alternating signal 308 (e.g., by inverting alternating signal 308 twice) to provide coincidence signal 314.

[0102] Furthermore, similar to the inverting circuits 502, 504, and 506, each of the inverting circuits 602 and 604 can flip the value of the alternating signal 308 based on a corresponding delay. However, in some cases, the two inverting circuits 602 and 604 of the phase splitter half 310 can provide a smaller delay than the three inverting circuits 502, 504, and 506 of the phase splitter half 312. Therefore, in these cases, the phase splitter half 312 can include a delay circuit 614 to adjust the delay of the phase splitter half 312 based on the delay of the phase splitter half 310. For example, the delay circuit 614 can include a load circuit including switches 616 and 618 to provide the delay.

[0103] Nevertheless, in alternative or additional embodiments, the time-to-digital circuit 200 may use different delay circuits, inverter circuits, and / or phase splitter halves 310. Furthermore, in alternative or additional embodiments, the phase splitter halves 310 may include any other even number of inverter circuits. However, such an even number of inverter circuits of the phase splitter halves 310 may correspond to an odd number of inverter circuits of the phase splitter halves 312. Furthermore, the inverting phase splitter halves 312 and the non-inverting phase splitter halves 310 may provide a consistent signal 314 based on similar time delays. Thus, the inverting phase splitter halves 312 and the non-inverting phase splitter halves 310 may facilitate providing the consistent signal 314 in parallel with downstream components.

[0104] Furthermore, latch 316 can provide a latched signal 320 based on receiving the coincidence signal 314 and the clock signal 318. Thus, the phase splitter half 310 and the phase splitter half 312 can convert the alternating signal 308 into the coincidence signal 314. The phase splitter half 310 and the phase splitter half 312 can output the coincidence signal 314 to provide a thermometer code.

[0105] Figure 7Schematic diagram 700 depicts a portion of the code protection circuit 210 of the time-to-digital circuit 200. As mentioned above, the code protection circuit 210 can correct erroneous input signals (e.g., the erroneous latched signal 320) according to a thermometer code. The code protection circuit 210 can include comparison circuitry (e.g., redundancy check circuitry) to correct for erroneous consistency signals provided using the thermometer code. For example, a thermometer code can use a single transition between multiple consecutive signals. Thus, the code protection circuit 210 can correct for inconsistent input signals associated with multiple transitions between high and low values. An example of a thermometer code is provided in Table 2 above.

[0106] With the foregoing in mind, the schematic diagram 700 may include XOR gates 702-1, 702-2, 702-3, 702-4, 702-5, 702-6, and 702-7. Each of the XOR gates 702-1, 702-2, 702-3, 702-4, 702-5, 702-6, and 702-7 may receive two consecutive latched signals 320. The latch 316 of the latch circuit 208 may provide the same latching signal as described above with respect to FIG. Figure 3 Described and Figure 4 The latched signal 320 is depicted in .

[0107] Specifically, XOR gate 702-1 may receive latched signals (Q0) 320-1 and (Q1) 320-2. XOR gate 702-2 may receive latched signals (Q1) 320-2 and (Q2) 320-3. XOR gate 702-3 may receive latched signals (Q3) 320-3 and (Q3) 320-4. XOR gate 702-4 may receive latched signals (Q3) 320-4 and (Q4) 320-5. XOR gate 702-5 may receive latched signals (Q4) 320-5 and (Q5) 320-6. XOR gate 702 - 6 may receive latched signals ( Q5 ) 320 - 6 and ( Q6 ) 320 - 7 , and XOR gate 702 - 7 may receive latched signals ( Q6 ) 320 - 7 and ( Q7 ) 320 - 8 .

[0108] Each of the XOR gates 702-1, 702-2, 702-3, 702-4, 702-5, 702-6, and 702-7 may provide a corresponding XOR output signal 704-1, 704-2, 704-3, 704-4, 704-5, 704-6, and 704-7. The XOR gates 702-1, 702-2, 702-3, 702-4, 702-5, 702-6, and 702-7 may provide a corresponding high XOR output signal 704-1, 704-2, 704-3, 704-4, 704-5, and 704-6 upon receiving a high value and a low value of the corresponding input signal. Thus, XOR gates 702 - 1 , 702 - 2 , 702 - 3 , 702 - 4 , 702 - 5 , 702 - 6 , and 702 - 7 may provide corresponding high XOR output signals 704 - 1 , 704 - 2 , 704 - 3 , 704 - 4 , 704 - 5 , and 704 - 6 when determining transitions between a plurality of consecutive latched signals 320 .

[0109] In the depicted embodiment, XOR gates 702-4, 702-5, and 702-6 can provide high XOR output signals 704-4, 704-5, and 704-6. XOR gate 702-4 can provide a high XOR output signal 704-4 based on a transition between the values ​​of latched signals (Q3) 320-4 and (Q4) 320-5. Additionally, XOR gate 702-5 can provide a high XOR output signal 704-5 based on a transition between the values ​​of latched signals (Q4) 320-5 and (Q5) 320-6. Additionally, XOR gate 702-6 can provide a high XOR output signal 704-6 based on a transition between the values ​​of latched signals (Q5) 320-6 and (Q6) 320-7. Specifically, in the depicted embodiment, high XOR output signals 704-5 and 704-6 are generated based on the erroneously low latched signal (Q5) 320-6. Furthermore, the code protection circuit 210 can use the high XOR output signals 704-5 and 704-6 to correct the erroneously low latched signal (Q5) 320-6 and instead provide a corrected signal (QA5) 322-6.

[0110] Each of the OR gates 706-1, 706-2, 706-3, 706-4, 706-5, 706-6, and 706-7 may receive the corresponding XOR output signal 704-1, 704-2, 704-3, 704-4, 704-5, 704-6, and 704-7 and the output of the previous OR gate 706 (e.g., the select signal (S)). In the depicted embodiment, the OR gate 706-1 may receive the XOR output signal 704-1 and the low value signal. In other embodiments, the OR gate 706-1 may receive Figure 7 The output of the previous OR gate 706 not shown in FIG.

[0111] In any case, OR gate 706-2 may receive the XOR output signal 704-2 and the select signal (S1) 708-1 from OR gate 706-1. OR gate 706-3 may receive the XOR output signal 704-3 and the select signal (S2) 708-2 from OR gate 706-2. OR gate 706-4 may receive the XOR output signal 704-4 and the select signal (S3) 708-3 from OR gate 706-3.

[0112] Additionally, OR gate 706-5 may receive the XOR output signal 704-5 and a select signal (S4) 708-4 from OR gate 706-4. OR gate 706-6 may receive the XOR output signal 704-6 and a select signal (S5) 708-5 from OR gate 706-5. Additionally, OR gate 706-7 may receive the XOR output signal 704-7 and a select signal (S6) 708-6 from OR gate 706-6.

[0113] With the foregoing in mind, each of the OR gates 706-1, 706-2, 706-3, 706-4, 706-5, 706-6, and 706-7 can provide a corresponding high select signal (S1-S7) 708-1, 708-2, 708-3, 708-4, 708-5, 708-6, and 708-7 based on transitions between high and low values ​​of the latched signal 320. In the depicted embodiment, the OR gates 706-1, 706-2, and 706-3 can provide low select signals (S1-S3) 708-1, 708-2, and 708-3. Subsequently, the OR gate 706-4 can provide a high select signal (S4) 708-4 after receiving the high XOR output signal 704-4 of the XOR gate 702-4. As will be appreciated, the high select signal ( S4 ) 708 - 4 may cause the high corrected signal ( QA4 ) 322 - 5 to be used in place of the erroneous latched signal ( Q5 ) 320 - 6 to provide the corrected signal ( QA5 ) 322 - 6 .

[0114] As mentioned above, XOR gate 702-4 can provide a high XOR output signal 704-4 based on a transition between a low latched signal (Q3) 320-4 and a high latched signal (Q4) 320-5. Furthermore, OR gate 706-5 can provide a high select signal (S5) 708-5 based on receiving a high select signal (S4) 708-4 and / or a high XOR output signal 704-5. Furthermore, OR gate 706-6 can provide a high select signal (S6) 708-6 based on receiving a high select signal (S5) 708-5, and OR gate 706-7 can provide a high select signal (S7) 708-7 based on receiving a high select signal (S6) 708-6.

[0115] exist Figure 7, the code protection circuit 210 may further include multiplexers (MUXs) 710-1, 710-2, 710-3, 710-4, 710-5, 710-6, 710-7, 710-8, and 710-9. For simplicity, MUXs 710-1 and 710-2 are not shown. Each of MUXs 710-3, 710-4, 710-5, 710-6, 710-7, 710-8, and 710-9 may receive a corresponding latched signal 320 and a corresponding corrected signal 322 received from an adjacent MUX. Each of the MUXs 710-3, 710-4, 710-5, 710-6, 710-7, 710-8, and 710-9 may also receive a corresponding select signal (S1-S7) 708-1, 708-2, 708-3, 708-4, 708-5, 708-6, and 708-7.

[0116] Each of MUXes 710-3, 710-4, 710-5, 710-6, 710-7, 710-8, and 710-9 may receive two corresponding input signals. MUXes 710-3, 710-4, 710-5, 710-6, 710-7, 710-8, and 710-9 may also receive a corresponding input select signal (S). Furthermore, each of MUXes 710-1, 710-2, 710-3, 710-4, 710-5, 710-6, 710-7, 710-8, and 710-9 may provide one of the input signals based on the select signal (S). For example, each of MUXs 710-3, 710-4, 710-5, 710-6, 710-7, 710-8, and 710-9 may provide a first input signal as an output signal when receiving a low select signal, and may provide a second input signal as an output signal when receiving a high select signal.

[0117] In the depicted embodiment, MUX 710-3 may receive the latched signal (Q2) 320-3 and the corrected signal (QA1) 322-1. For example, MUX 710-3 may receive the latched signal (Q2) 320-3 and the corrected signal (QA1) 322-1 from the adjacent MUX 710-2 ( Figure 7 The MUX 710-3 may also receive a low select signal (S1) 708-1.

[0118] MUX 710-3 may provide latched signal (Q2) 320-3 as corrected signal (QA2) 322-3 based on receiving low select signal (S1) 708-1. MUX 710-3 may provide corrected signal (QA2) 322-3 to adjacent MUX 710-4 and counter 212 of time-to-digital circuit 200.

[0119] MUX 710-4 may receive the latched signal (Q3) 320-4 and the corrected signal (QA2) 322-3 from MUX 710-3. MUX 710-4 may also receive the low select signal (S2) 708-2. MUX 710-4 may provide the latched signal (Q3) 320-4 as the corrected signal (QA3) 322-4 based on receiving the low select signal (S2) 708-2. MUX 710-4 may provide the corrected signal (QA3) 322-4 to MUX 710-5 and to the counter 212 of the time-to-digital circuit 200.

[0120] Furthermore, MUX 710-5 may receive the latched signal (Q4) 320-5 and the corrected signal (QA3) 322-4 from MUX 710-4. MUX 710-5 may also receive the low select signal (S3) 708-3. MUX 710-5 may provide the latched signal (Q4) 320-5 as the corrected signal (QA4) 322-5 based on receiving the low select signal (S3) 708-3. MUX 710-5 may provide the corrected signal (QA4) 322-5 to MUX 710-6 and to the counter 212 of the time-to-digital circuit 200.

[0121] MUX 710-6 may receive the latched signal (Q5) 320-6 and the corrected signal (QA4) 322-5 from MUX 710-5. MUX 710-6 may also receive the high select signal (S4) 708-4. MUX 710-6 may provide the corrected signal (QA4) 322-5 as the corrected signal (QA5) 322-6 based on receiving the high select signal (S4) 708-4. Thus, MUX 710-6 provides a high output signal instead of the erroneous latched signal (Q5) 320-6. MUX 710-6 may provide the corrected signal (QA5) 322-6 to MUX 710-7 and to the counter 212 of the time-to-digital circuit 200.

[0122] As mentioned above and shown above in Table 2, the parallel signals provided using the thermometer code may include only one transition between a high value and a low value for a plurality of consecutive signals. Furthermore, as discussed above, the XOR gate 702-4 may cause the high select signal (S4) 708-4 to be provided based on the first transition between the low latched signal (Q3) 320-4 and the high latched signal (Q4) 320-5.

[0123] Therefore, MUXs 710-7, 710-8, and 710-9 may also provide corrected signals (QA5-7) 322-6, 322-7, and 322-8, respectively. MUXs 710-7, 710-8, and 710-9 may also provide corrected signals (QA5-7) 322-6, 322-7, and 322-8 received from corresponding adjacent MUXs 710-6, 710-7, and 710-8 based on receiving high select signals (S5-7) 708-5, 708-6, and 708-7. As discussed above, each of the OR gates 706-4, 706-5, 706-6, and 706-7 may provide a high select signal (S5-7) 708-5, 708-6, and 708-7 based at least in part on receiving a high select signal (S4-6) 708-4, 708-5, and 708-6 and / or a high XOR output signal 704-4, 704-5, and 704-6 provided by a previous OR gate 706-4, 706-5, and 706-6, respectively.

[0124] Thus, in the depicted embodiment, MUX 710-7 may provide the high corrected signal (QA5) 322-6, rather than the latched signal (Q6) 320-7, to MUX 710-8 and the counter 212 of the time-to-digital circuit 200. Thus, the code protection circuit 210 may include circuitry according to schematic 700 to provide the corrected signal 322. However, in alternative or additional embodiments, the code protection circuit 210 may also use a different schematic to provide the corrected signal 322.

[0125] By understanding these technical effects, using thermometer codes for time-to-digital circuits can improve the consistency of time-to-digital circuits. For example, using thermometer codes for time-to-digital circuits can reduce the time required to debug and test the time-to-digital circuits, and / or reduce the number of redundant time measurements. Furthermore, time-to-digital circuits incorporating the described converter and code protection circuits can provide reliable time measurements based on reduced error probabilities. As described above, such time-to-digital circuits can correct erroneous signals to mitigate the effects of metastable conditions and / or violations of signal value setup times in different parts of the circuit.

[0126] The specific embodiments described above have been shown by way of example, and it should be understood that these embodiments are susceptible to various modifications and alternative forms. It should be further understood that the claims are not intended to be limited to the specific forms disclosed, but rather to cover all modifications, equivalents, and alternatives that fall within the spirit and scope of the present disclosure.

[0127] The technology presented and claimed herein is presented with reference to and applied to substantial objects and specific examples of a practical nature that advance the art in a demonstrable manner and are therefore not abstract, intangible, or purely theoretical. Furthermore, if any claim appended to the end of this specification contains one or more elements that are referred to as "means for [performing] [the function] ..." or "a step for [performing] [the function] ...", then it is intended that such elements be construed under 35 U.S.C. § 112(f). However, for any claim containing elements specified in any other manner, it is intended that such elements not be construed under 35 U.S.C. § 112(f).

Claims

1. An electronic device comprising: a ring oscillator configured to provide an alternating signal using an alternating code when the ring oscillator receives an indication of an event, wherein the alternating signal indicates a duration of the event; A converter configured to: receiving the alternating signal provided using the alternating code; as well as converting the alternating signal into a consistent signal based on a thermometer code, wherein the consistent signal indicates the duration of the event; as well as An encoder configured to: receiving the coincidence signal; and A duration of the event is provided based on decoding the coincidence signal provided using the thermometer code. 2 . The electronic device of claim 1 , wherein the ring oscillator is configured to provide the alternating signal in parallel at each clock cycle of a clock signal of the electronic device. The electronic device of claim 1 , wherein the alternating signal indicates an incremental count of the duration of the event. 4 . The electronic device of claim 1 , wherein the ring oscillator is configured to receive a trigger signal indicative of the event, and wherein the ring oscillator is configured to provide an indication of the start of the event based on receiving the trigger signal. 5 . The electronic device of claim 4 , wherein the ring oscillator is configured to provide an indication of an end of the event based on receiving a stop trigger signal after receiving the trigger signal. The electronic device of claim 1 , wherein the coincident signal comprises several high signals followed by several low signals, several low signals followed by several high signals, only high signals, or only low signals.

7. The electronic device of claim 1, wherein the converter comprises phase splitter halves to convert the alternating signal into the uniform signal, wherein each of the phase splitter halves comprises a number of inverter circuits, delay circuits, or both.

8. The electronic device of claim 1, wherein the encoder comprises a code protection circuit, wherein the code protection is configured to correct the coincidence signal having an erroneous value provided by using the temperature code.

9. The electronic device of claim 8, wherein the code protection circuit comprises comparison circuitry configured to correct the coincidence signal having an erroneous value provided by using the temperature code based on comparing successive signal values ​​of the coincidence signal.

10. A time-to-digital circuit comprising: a ring oscillator configured to provide an alternating signal using an alternating code indicating an incremental count of a duration of an event, wherein a continuous signal of the alternating signal includes one or more transitions between a high value and a low value; a converter configured to receive the alternating signal, wherein the converter is configured to convert the alternating signal into a consistent signal based on a thermometer code, wherein a continuous signal of the consistent signal includes only one transition between a high value and a low value; a code protection circuit configured to receive the consistency signal, wherein the code protection circuit is configured to correct inconsistent signals in the consistency signal based on determining more than one transition between high and low values ​​of consecutive signals in the consistency signal; as well as A counter is configured to receive the corrected agreement signal and determine a duration of the event based on receiving the corrected agreement signal.

11. The time-to-digital circuit of claim 10, wherein the ring oscillator is configured to receive a trigger signal within the duration of the event, wherein the ring oscillator is configured to provide the alternating signal upon receiving the trigger signal.

12. The time-to-digital circuit of claim 10, wherein the ring oscillator is configured to provide the alternating signal in parallel within a clock cycle of a clock signal associated with the time-to-digital circuit.

13. The time-to-digital circuit of claim 10, wherein the converter comprises a phase splitter half to convert the alternating signal to the coincident signal.

14. The time-to-digital circuit of claim 13, wherein the phase splitter half includes an inverting circuit to convert the alternating signal into the coincident signal.

15. The time-to-digital circuit of claim 10, wherein the converter is configured to provide the coincidence signal in parallel within a clock cycle of a clock signal associated with the time-to-digital circuit. 16 . The time-to-digital circuit of claim 10 , wherein the code protection circuit is configured to compare the consecutive ones of the coincidence signals to determine more than one transition between the high and low values ​​of the consecutive ones of the coincidence signals.

17. The time-to-digital circuit of claim 16, wherein the code protection circuit includes comparison circuitry to compare the consecutive ones of the coincidence signals.

18. The time-to-digital circuit of claim 10, wherein the time-to-digital circuit comprises a latch circuit configured to receive the coincidence signal from the converter and provide the received coincidence signal to the code protection circuit.

19. A method comprising: receiving, by the time-to-digital circuit, an indication of the beginning of a duration of time to be measured; providing, by said time-to-digital circuit, a coincidence signal provided by a thermometer code based on an incremental count indicating said duration of said time; Correcting, by the time-to-digital circuit, an erroneous signal value of the coincidence signal provided based on the thermometer code; The duration of the time is counted by the time-to-digital circuit based on the incremental count of the corrected coincidence signal.

20. The method according to claim 19, comprising: providing, by the time-to-digital circuit in response to receiving the indication of the start of the duration of the time, an alternating signal provided based on an alternating code; providing the coincidence signal by the time-to-digital circuit by converting the alternating signal into the coincidence signal, wherein a continuous coincidence signal provided based on the thermometer code includes only one transition between a high signal value and a low signal value; as well as Correcting erroneous signal values ​​of the coincidence signal by the time-to-digital circuit is based on determining more than one transition between high and low signal values ​​of the consecutive coincidence signals provided based on the thermometer code.

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