Method for forming silicon substrate with native nuclei having reduced number of extrinsic epitaxial defects and method for forming epitaxial wafer

Abstract

Disclosed are methods for preparing single crystal silicon substrates for epitaxial growth. The methods can involve controlling (i) the growth velocity v and / or (ii) the axial temperature gradient G during growth of an ingot segment such that v / G is less than a critical v / G and / or less than a v / G value dependent on the boron concentration of the ingot. Also disclosed are methods for preparing epitaxial wafers.

Description

[0001] Cross-reference of related applications

[0002] This application claims the rights of U.S. Provisional Patent Application No. 63 / 112,424, filed November 11, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the preparation of single-crystal silicon substrates for epitaxial growth and to methods for forming epitaxial wafers. Background Technology

[0004] An epitaxial wafer comprises a monocrystalline silicon substrate having an epitaxial layer deposited on the front surface of the substrate. Epitaxial wafers can be used to form electronic devices suitable for microelectronic (integrated circuit or power supply applications) or photovoltaic applications.

[0005] Epitaxial wafers can have surface defects that degrade their performance. Some defects formed in the silicon substrate do not dissolve during the epitaxial process and are believed to lead to native defect sites in the epitaxial layer after epitaxial deposition (e.g., epitaxial stacking failures or "hillocks"). Defect propagation through the epitaxial layer is believed to cause the formation of these native defects. <111> In the planar silicon epitaxial growth mode, a thicker epitaxial layer rather than covering substrate defects amplifies the size of the initial substrate surface defects, thereby causing larger and more pronounced epitaxial defects to form as the epitaxial layer thickness increases.

[0006] A method is needed to reduce the number of native nuclei causing epitaxial defects in a substrate wafer, and a related method for forming an epitaxial wafer.

[0007] This section is intended to introduce the reader to various technical aspects that may relate to the various aspects of this disclosure described and / or claimed below. It is believed that this discussion helps to provide the reader with background information to facilitate a better understanding of the various aspects of this disclosure. Therefore, it should be understood that these statements should be taken into account and not as an endorsement of prior art. Summary of the Invention

[0008] One aspect of this disclosure relates to a method for forming a silicon substrate having a native core with reduction-induced epitaxial defects. The silicon substrate has a core size of at least 2.8 x 10⁻⁶. 18 atoms / cm 3Boron doping is performed at a concentration of [missing information]. An initial charge of polycrystalline silicon is added to a crucible. The crucible containing the initial charge of polycrystalline silicon is heated to induce the formation of a silicon melt in the crucible. Boron is added to the crucible to produce a doped silicon melt. A seed crystal is brought into contact with the doped silicon melt. The seed crystal is removed to grow a single-crystal silicon ingot with a constant diameter portion. The constant diameter portion of the ingot has a diameter of at least approximately 2.8 x 10 [missing information]. 18 atoms / cm 3 The boron concentration. When the fragment has a boron concentration of 2.8 x 10⁻⁶. 18 atoms / cm 3 Up to 5.4x10 18 atoms / cm 3 At a boron concentration of [specific value], during the growth of the fragment, (i) the growth rate v and / or (ii) the axial temperature gradient G are controlled such that v / G is less than 0.20 mm. 2 / (minutes*K). When the segment has a value from 5.4x10 18 atoms / cm 3 Up to 8.0x10 18 atoms / cm 3 At a boron concentration of [specific value], during the growth of the fragment, (i) the growth rate v and / or (ii) the axial temperature gradient G are controlled such that v / G is less than 0.25 mm. 2 / (minutes*K). When the segment has a value greater than 8.0x10 18 atoms / cm 3 At a boron concentration of [value missing], operate (i) the growth rate v and / or (ii) the axial temperature gradient G at any v / G value. Cool the segment of the constant diameter portion of the ingot from its solidification temperature to 950°C or less. The dwell time of the segment of the constant diameter portion of the ingot in the temperature range from 1150°C to 950°C is less than 160 minutes.

[0009] Another aspect of the invention relates to a method for forming a silicon substrate having a primary nucleus with reduced epitaxial defects. An initial charge of polycrystalline silicon is added to a crucible. The crucible comprising the initial charge of polycrystalline silicon is heated to induce the formation of a silicon melt in the crucible. Boron is added to the crucible to prepare a substrate having a core with a diameter of at least 3.8 x 10⁻⁶. 18 atoms / cm 3A boron-doped silicon melt is prepared. A silicon seed crystal is brought into contact with the doped silicon melt. The silicon seed crystal is then removed to grow a single-crystal silicon ingot. The ingot has a constant diameter portion. The method further includes controlling (i) the growth rate v and / or (ii) the axial temperature gradient G during the growth of a segment of the constant diameter portion of the ingot, such that the ratio v / G is less than a critical v / G. The segment of the constant diameter portion of the ingot is cooled from its solidification temperature to 950°C or less. The residence time of the segment of the constant diameter portion of the ingot in the temperature range from 1150°C to 950°C is less than 160 minutes.

[0010] Various modifications exist to the features mentioned in the foregoing aspects of this disclosure. Similarly, further features may be incorporated into the foregoing aspects of this disclosure. These modifications and additional features may exist individually or in any combination. For example, various features discussed below in any of the illustrated embodiments of this disclosure may be incorporated individually or in any combination into any of the foregoing aspects of this disclosure. Attached Figure Description

[0011] Figure 1 This is the cross-section of the ingot pulling equipment before silicon ingot growth;

[0012] Figure 2 It is during the silicon ingot growth process. Figure 1 The cross-section of the ingot pulling equipment;

[0013] Figure 3 It is a schematic cross-sectional view of a single-crystal silicon ingot showing the axial trends of vacancy-rich and interstitial-rich regions for three boron doping levels (from (a) to (c)).

[0014] Figure 4 This is a graph showing the epitaxial defect counts that vary depending on the axial position of the substrate wafer in a single crystal ingot over a relatively long period of time within a temperature range of 1150°C to 950°C.

[0015] Figure 5 It is a graph showing the epitaxial defect counts that vary according to the axial position of the substrate wafer in a single crystal ingot over a relatively short period of time within a temperature range of 1150°C to 950°C.

[0016] Figure 6 It is a chart showing the defect counts based on the residence time of ingot segments within a temperature range from 1150°C to 950°C; and

[0017] Figure 7 It is a chart showing the residence time of various single-crystal silicon ingots along the crystal length.

[0018] The corresponding reference symbols indicate the corresponding parts in all drawings. Detailed Implementation

[0019] This disclosure relates to a method for forming a silicon substrate with primary nuclei that reduce epitaxial defects (i.e., defects that occur after epitaxial silicon growth on a silicon substrate). According to embodiments of the invention, the ratio (v / G) of the growth rate (v) to the axial temperature gradient (G) can be controlled during a segment or the entire growth period of a constant diameter portion of the ingot, and the time the segment is in the temperature range of 1150°C to 950°C is controlled to 160 minutes or less, so as to reduce the number of nuclei that cause defects during epitaxial growth. The resulting substrate is suitable for epitaxial silicon growth, wherein the epitaxial layer grown on the substrate has reduced primary defects or is substantially free of primary defects.

[0020] The method disclosed herein can be implemented substantially in any ingot puller equipment configured to pull monocrystalline silicon ingots. Figure 1 The exemplary ingot puller apparatus (or more simply, "ingot puller") is generally designated as "100". Ingot puller apparatus 100 includes a crucible 102 supported by a susceptor 106 for holding a molten material 104 of semiconductor or solar-grade material (e.g., silicon). Ingot puller apparatus 100 includes a section defining a silicon ingot 113 for pulling from the molten material 104 along a pulling axis A. Figure 2 The growth chamber 152 and the crystal puller shell 108.

[0021] The crucible 102 includes a base plate 129 and a sidewall 131 extending upward from the base plate 129. The sidewall 131 is generally vertical. The base plate 129 includes a curved portion of the crucible 102 extending below the sidewall 131. A silicon melt 104 having a melt surface 111 (i.e., a melt-ingot interface) is contained within the crucible 102.

[0022] In some embodiments, crucible 102 is layered. For example, crucible 102 may be made of a quartz base layer and a synthetic quartz liner disposed on the quartz base layer.

[0023] The base 106 is supported by the shaft 105. The base 106, crucible 102, shaft 105, and ingot 113 ( Figure 2 They have a common longitudinal axis A or "pull axis" A.

[0024] A pulling mechanism 114 is provided within the ingot pulling apparatus 100 for growing and pulling ingot 113 from melt 104. The pulling mechanism 114 includes a pulling cable 118, a seed holder or chuck 120 coupled to one end of the pulling cable 118, and a silicon seed crystal 122 coupled to the seed holder or chuck 120 for initiating crystal growth. One end of the pulling cable 118 is connected to a pulley (not shown) or roller (not shown) or any other suitable type of lifting mechanism (e.g., a shaft), and the other end is connected to the chuck 120 holding the seed crystal 122. In operation, the seed crystal 122 is lowered to contact the melt 104. The pulling mechanism 114 is operated to cause the seed crystal 122 to rise. This causes the single crystal ingot 113 to be pulled out from the melt 104. Figure 2 ).

[0025] During heating and crystal pulling, the crucible drive unit 107 (e.g., a motor) rotates the crucible 102 and the base 106. The lifting mechanism 112 raises and lowers the crucible 102 along the pulling axis A during the growth process. For example, as... Figure 1 As shown, crucible 102 is located at its lowest position (near the bottom heater 126), where the initial charge of solid polycrystalline silicon previously added to crucible 102 melts. Crystal growth is initiated by bringing the melt 104 into contact with the seed crystal 122 and lifting the seed crystal 122 using a pulling mechanism 114. As the ingot grows, the silicon melt 104 is consumed and the height of the melt in crucible 102 decreases. The crucible 102 and base 106 can be raised to maintain the surface 111 of the melt at or near the same position relative to the ingot pulling device 100. Figure 2 ).

[0026] The crystal drive unit (not shown) can also pull the cable 118 and the ingot 113 ( Figure 2 The crystal drive unit rotates in the opposite direction to the direction in which the crucible 102 is rotated by the crucible drive unit 107 (e.g., in the opposite direction). In embodiments using iso-rotation, the crystal drive unit can rotate the pull cable 118 in the same direction in which the crucible 102 is rotated by the crucible drive unit 107. Additionally, the crystal drive unit optionally raises and lowers the ingot 113 relative to the molten surface 111 during the growth process.

[0027] The puller apparatus 100 may include an inert gas system for introducing an inert gas (e.g., argon) and extracting the inert gas from the growth chamber 152. The puller apparatus 100 may also include a dopant feeding system (not shown) for introducing dopant into the melt 104.

[0028] According to the Czochralski single crystal growth process, a certain amount of polycrystalline silicon is loaded into crucible 102. Heat from one or more heating elements melts the initial semiconductor or solar-grade material introduced into the crucible to form a silicon melt within the crucible. The puller apparatus 100 includes a bottom insulation 110 and side insulation 124 for maintaining heat within the puller apparatus. In the illustrated embodiment, the puller apparatus 100 includes a bottom heater 126 disposed below the crucible base plate 129. The crucible 102 can be moved relatively closely to the bottom heater 126 to melt the polycrystalline silicon loaded into the crucible 102.

[0029] To form an ingot, the seed crystal 122 is brought into contact with the surface 111 of the molten material 104. The pulling mechanism 114 is operated to pull the seed crystal 122 from the molten material 104. (See now for reference.) Figure 2 Ingot 113 includes a crown-shaped portion 142 in which the ingot transforms and tapers outward from the seed crystal 122 to reach a target diameter. Ingot 113 includes a constant-diameter portion 145 or a cylindrical "body" of a crystal grown by increasing the pulling rate. The body 145 of ingot 113 has a relatively constant diameter. Ingot 113 includes a tail or end cone (not shown) in which the diameter of the ingot tapers after the body 145. When the diameter becomes sufficiently small, ingot 113 is then separated from melt 104.

[0030] The puller apparatus 100 includes a side heater 135 and a base 106 surrounding the crucible 102 to maintain the temperature of the melt 104 during crystal growth. As the crucible 102 moves up and down along the pull axis A, the side heater 135 is positioned radially outward of the crucible sidewall 131. The side heater 135 and the bottom heater 126 can be any type of heater that allows the side heater 135 and the bottom heater 126 to operate as described herein. In some embodiments, heaters 135 and 126 are resistance heaters. The side heater 135 and the bottom heater 126 can be controlled by a control system (not shown) such that the temperature of the melt 104 is controlled throughout the pulling process.

[0031] The ingot pulling apparatus 100 may include a heat shield 151. During crystal growth, the heat shield 151 can protect the ingot 113 and can be placed inside the crucible 102. Figure 2 ).

[0032] In some embodiments, the silicon substrate produced by the methods described herein is doped with boron (e.g., relatively heavily doped). For example, silicon melt can be boron doped to produce a substrate with a silicon content of at least 2.8 x 10⁻⁶. 18 atoms / cm 3 The boron concentration of the doped silicon ingot is at least 3.8 x 10⁻⁶.18 atoms / cm 3 A boron doping concentration of [specific value] can be used to achieve a seed crystal with a density of at least 2.8 x 10⁻⁶. 18 atoms / cm 3 The concentration of the ingot is [specific value]. The resulting ingot (and sliced ​​wafer) can have a concentration of at least 2.8 x 10 [units]. 18 atoms / cm 3 The boron concentration. In some embodiments, the melt is not doped with carbon (and in some embodiments, no dopants other than boron are used).

[0033] According to embodiments of the present disclosure, a silicon substrate having a primary nucleus with reduced epitaxial defects or even a substrate substantially without such a primary nucleus can be produced by the following steps: (1) controlling the ratio of the crystal pulling rate (v) to the magnitude of the axial temperature gradient (G) near the melt-crystal interface; and (2) controlling the time period (i.e., dwell time) of the fragment in the temperature range of 1150°C to 950°C to 160 minutes or less.

[0034] The type of dominant defect can be controlled by adjusting the v / G ratio during silicon growth. At higher v / G ratios, convection of point defects dominates their diffusion, and vacancies remain incorporated into the dominant point defect because the vacancy concentration at the interface is higher than the interstitial concentration. At lower v / G ratios, diffusion dominates convection, allowing rapidly diffusing interstitials to be incorporated as dominant point defects. At v / G ratios close to their critical value (i.e., the transition between vacancy-dominant and interstitial-dominant materials), both types of point defects are incorporated at very low and comparable concentrations.

[0035] According to embodiments of the present disclosure, (i) the growth rate v and / or (ii) the axial temperature gradient G can be controlled during the growth of an axial segment of a constant diameter portion of the ingot, such that the ratio v / G is below a critical value of v / G that causes a decrease in the vacancy concentration in the ingot (or even controlled to be less than or slightly above the critical value of v / G).

[0036] The critical v / G is largely based on changes in the amount of boron doping. Boron shifts the equilibrium to the interstitial system. As the boron concentration increases (i.e., resistivity decreases), the vacancy-dominated region shrinks until it completely disappears at the crystal center. Figure 3 C). In doped boron ingots, it is believed that a value greater than 8.0 x 10⁻⁶ can be achieved across the entire v / G ratio. 18 atoms / cm 3 Boron doping (e.g., resistivity less than 10 mΩ*cm) eliminates vacancy-dominated regions.

[0037] For 8.0x10 18 atoms / cm 3Or even lower boron concentrations can control the v / G below the critical v / G (or even below a value slightly above the critical v / G). According to some embodiments of this disclosure, when a segment of the constant diameter portion of the ingot has a value from 2.8 x 10⁻⁶, 18 atoms / cm 3 Up to 5.4x10 18 atoms / cm 3 At a boron concentration of [value missing], control (i) the growth rate v and / or (ii) the axial temperature gradient G such that v / G is less than 0.20 mm. 2 / (minutes*K). When the constant diameter portion of the ingot has a segment with a diameter of 5.4x10 18 atoms / cm 3 Up to 8.0x10 18 atoms / cm 3 At a boron concentration of [value missing], during fragment growth, (i) the growth rate v and / or (ii) the axial temperature gradient G are controlled such that v / G is less than 0.25 mm. 2 / (minutes*K).

[0038] As mentioned above, when it is greater than 8.0x10 18 atoms / cm 3 When doping fragments at a concentration of , it is not necessary to control v / G because the gaps are the dominant point defects throughout the entire fragment range (i.e., any technically feasible v / G can be used).

[0039] Since v / G is generally highest at the center of the ingot, the v / G range provided in this paper is generally measured at the center of the ingot to ensure that v / G is below the upper limit across the entire radius of the ingot.

[0040] When the ingot is drawn from the melt, it is cooled from solidification (approximately 1412°C) to room temperature. According to embodiments of this disclosure, the growth of the ingot and the control of v / G (for an ingot with a growth rate of 8.0 x 10⁻⁶) are... 18 atoms / cm 3 During the control of boron doping (or even lower boron doping, i.e., resistivity above 10 mΩ*cm) and v / G), the cooling rate of the ingot is controlled such that the residence time of the segments (e.g., each portion of the segment) in the temperature range from 1150°C to 950°C is minimized. In this respect, the entire ingot can be controlled in this way regardless of the boron doping concentration. According to some embodiments, the cooling rate of the ingot is controlled such that the period during which the segments are in the temperature range from 1150°C to 950°C is less than 160 minutes.

[0041] The hot zone of the ingot puller can be arranged and / or modified to achieve this cooling rate over this temperature range (e.g., at least 1.25°C / min, at least 1.5°C / min, at least 2.0°C / min, at least 2.5°C / min, at least 3.0°C / min, or at least 3.5°C / min over a temperature range of 1150°C to 950°C). The hot zone that achieves this cooling may include any combination of one or more of the following: (1) active cooling elements (e.g., water cooling) near the ingot surface, (2) increasing insulation between the crystal surface and the melt to reduce thermal radiation from the melt to the crystal, (3) applying a jet of cold inert gas near the melt-ingot interface, and (4) using a conical thermal shield (e.g., a reflective material, such as molybdenum) surrounding the ingot to reflect the heat radiated by the ingot toward the wall of the ingot puller equipment. In other embodiments, the cooling rate of the ingot is controlled such that the time period during which the fragment is in the temperature range of 1150°C to 950°C is less than 120 minutes, less than 90 minutes, or less than 60 minutes.

[0042] As mentioned above, v / G can be controlled such that the gap is the dominant inherent point defect, and wherein, for at least one segment of the ingot (e.g., an axial segment), the cooling rate is controlled such that the ingot segment is subjected to a temperature range from 1150°C to 950°C for less than 160 minutes. This segment of the ingot may have a length at least 0.5 times (0.5*D) the length of the constant diameter portion of the ingot. In other embodiments, the length of the segment is at least 0.75*D or at least 0.9*D. In some embodiments, the segment is the entire constant diameter portion of the ingot.

[0043] Once the ingot has been grown, it is sliced ​​into a substrate (i.e., a wafer). The resulting wafer has a native core containing depletion-induced epitaxial defects formed during epitaxial growth.

[0044] Once the wafer has been sliced ​​from the ingot and processed (e.g., various smoothing and / or surface roughness reduction), an epitaxial layer can be deposited on the front surface of the substrate by contacting the front surface of the substrate with a silicon-containing gas (which decomposes and forms an epitaxial silicon layer on the substrate). Generally, any method available to those skilled in the art for depositing silicon epitaxial layers on a silicon substrate can be used, unless otherwise specified. Depending on the device application, silicon can be deposited to any suitable thickness via epitaxy. For example, silicon can be deposited using metal-organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or molecular beam epitaxy (MBE). Silicon precursors (i.e., silicon-containing gases) used for LPCVD or PECVD include methylsilane, silicon tetrahydrodeionide (silane), trisilane, disilane, pentasilane, neopentyl silane, tetrasilane, dichlorosilane (SiH₂Cl₂), trichlorosilane (SiHCl₃), silicon tetrachloride (SiCl₄), etc. For example, silicon can be deposited onto a surface by pyrolyzing silane (SiH₄) in a temperature range between about 550°C and about 690°C (e.g., between about 580°C and about 650°C). Chamber pressures can range from 70 mTorr to about 400 mTorr.

[0045] Boron-containing gas can be introduced into the epitaxial reactor to dope the epitaxial layer with boron. In some embodiments, the resulting epitaxial structure (i.e., substrate and epitaxial layer) is doped with boron at a concentration sufficient to achieve a p / p+ epitaxial wafer. The epitaxial layer may have a reduced number of primary defects or may be substantially free of primary defects.

[0046] Compared with other methods for forming substrates for silicon epitaxial growth and methods for forming epitaxial wafers, the method disclosed herein has several advantages. It has been found that using boron-doped substrates (e.g., 2.8 x 10⁻⁶) offers several advantages. 18 atoms / cm 3(or higher boron concentrations) suppress the formation of interstitial dislocation loops. It has also been found that boron-doped substrates enhance oxygen deposition. In vacancy-rich regions, oxygen deposition is further enhanced (i.e., larger precipitates form). This enhancement increases with higher vacancy concentrations. It is believed that native defects in epitaxial layers deposited on boron-doped substrates are largely caused by larger oxygen precipitates at the surface of the monocrystalline silicon substrate on which the epitaxial layers are grown. These larger oxygen precipitates, which may be associated with dislocation loops or entanglements, are insoluble during the epitaxial process and are believed to lead to defect sites in the epitaxial layer (e.g., epitaxial stacking failures or “hills”) after epitaxial deposition. By keeping v / G below (or slightly above) a critical value in relatively heavily doped substrates, vacancies are eliminated or reduced, respectively, thus suppressing the formation of relatively large oxygen precipitates that are insoluble during epitaxial deposition. Therefore, it is evident that relatively high boron doping with v / G controlled below a threshold reduces defects due to interstitial and vacancy factors.

[0047] The ingot fragment has a size greater than 8.0 x 10. 18 atoms / cm 3 In examples with boron concentrations, the fragments are fully interstitial and any v / G ratio can be used. By controlling the v / G ratio rather than just the pull rate v, process productivity can be maintained (e.g., by using hot zones configured to provide high values ​​of the thermal gradient G).

[0048] By minimizing the time that ingot segments are exposed to temperatures ranging from 1150°C to 950°C (e.g., a residence time of 160 minutes or less), defects can be further reduced or eliminated, regardless of the v / G value, even if vacancies exist.

[0049] Example

[0050] The process of this disclosure is further illustrated by the following examples. These examples should not be considered limiting.

[0051] Example 1: Axial trends of vacancy-rich and interstitial-rich regions in silicon ingots at different boron doping levels

[0052] Figure 3 This is a cross-sectional schematic diagram of a single-crystal silicon ingot showing the axial trends of vacancy-rich and interstitial-rich regions for three boron doping levels. Figure 3 (a) Demonstrates a boron-doped silicon substrate with a target resistivity of 2.8 x 10⁻⁶ at the seed end, corresponding to 22 mΩ*cm (a typical specification for heavily boron-doped silicon substrates). 18 atoms / cm 3 The axial trend of vacancy-rich and interstitial-rich regions in silicon crystals that have undergone relatively light doping. Figure 3In crystal (a), at the seed end, the vacancy-rich region extends across the entire crystal radius from the center to the edge, and gradually shrinks along the crystal length as the boron concentration increases axially due to dopant segregation. The location of the OISF ring is also shown at the V / I boundary. The OISF ring disappears where the vacancy-rich region completely shrinks.

[0053] Figure 3 (b) Demonstrates a boron-doped substrate to an intermediate concentration (e.g., at the seed end, a target resistivity of 16 mΩ*cm corresponding to the seed end, which is a typical intermediate resistivity specification for heavily boron-doped silicon substrates) of 4.5 x 10⁻⁶. 18 atoms / cm 3 The axial trends of vacancy-rich and interstitial-rich regions in a silicon crystal (with relatively intermediate doping) are shown. In this example, the vacancy-rich region extends only to a specific distance from the center (even at the seed end). The vacancy-rich region gradually shrinks along the crystal length as the boron concentration increases due to dopant isolation, and disappears completely at a certain axial location. The location of the OISF ring is also shown at the V / I boundary. The OISF ring disappears where the vacancy-rich region completely shrinks.

[0054] Figure 3 (c) Demonstrating an 8.0x10⁸ boron-doped crystal (e.g., a target resistivity of approximately 10 mΩ*cm at the seed end, corresponding to the seed end; this is a typical resistivity specification for heavily boron-doped crystals covering the common p++ range of 5 mΩ*cm to 10 mΩ*cm). 18 atoms / cm 3 The axial trend of vacancy-rich and interstitial-rich regions in silicon crystals that have undergone relatively high doping. Figure 3 The defect pattern in (c) remains unchanged even at lower resistivities (e.g., 5 mΩ*cm). There are no vacancy-rich regions and the crystal is completely interstitial. No OISF rings are formed. At this high doping level, no effect of the v / G ratio is observed, and it can be concluded that the defect properties are entirely determined by the dopant concentration alone.

[0055] Example 2: Situations involving relatively long and relatively short periods within a temperature range from 1150℃ to 950℃. Comparison of epitaxial defect counts between wafers from ingot fragments

[0056] Figure 4 This is a graph showing the epitaxial defect counts, measured by a laser inspection tool, varying according to the axial position of the substrate wafer in a single crystal ingot over a relatively long period of time within a temperature range from 1150°C to 950°C (labeled "Example 1"). Figure 4 The data points on the left are for those with relatively light doping (e.g., 2.8 x 10⁻⁶). 18 atoms / cm 3Crystals heavily doped with boron, such as Figure 3 As shown in (a). In Figure 4 The data points on the right are for relatively intermediate doping (e.g., 4.5x10). 18 atoms / cm 3 Crystals heavily doped with boron, such as Figure 3 As shown in (b).

[0057] Figure 5 This is a graph showing the epitaxial defect counts, measured by a laser inspection tool, varying according to the axial position of the substrate wafer in a single crystal ingot, over a relatively short period of time within a temperature range from 1150°C to 950°C (labeled "Example 2"). Figure 5 The data points on the left are for those with relatively light doping (e.g., 2.8 x 10⁻⁶). 18 atoms / cm 3 Crystals heavily doped with boron, such as Figure 3 As shown in (a). In Figure 5 The data points on the right are for relatively intermediate doping, such as (e.g., 4.5x10). 18 atoms / cm 3 Crystals heavily doped with boron, such as Figure 3 As shown in (b).

[0058] like Figure 4 and 5 As demonstrated, especially for lighter doped substrates, shortening the time period in the temperature range from 1150°C to 950°C reduces the number of defects.

[0059] exist Figure 6 The diagram shows the variation based on the residence time of the ingot fragment within a temperature range from 1150°C to 950°C. Figure 4 and 5 Defect counts. Ingot fragments with excessive vacancy concentration are displayed in a diamond shape, and fragments grown at relatively low vacancy concentrations are displayed by crossing over. (Example) Figure 6 As shown in the figure, epitaxial defects depend on the residence time of the ingot fragment in the temperature range of 1150°C to 950°C.

[0060] Figure 7 This displays the residence time of various ingot fragments within a temperature range between 1150°C and 950°C. Relatively low cooling is indicated as "Example 1" and relatively rapid cooling as "Example 2". Select an ingot with a diameter of 4.32 x 10 mm. 18 atoms / cm 3 Up to 4.61x10 18 atoms / cm 3 The boron concentration and 6.25 x 10 17 atoms / cm3 The oxygen concentration of the ingot fragment. The v / G at the center of the fragment is approximately 0.25 mm. 2 / (minutes*K), which is more than the 0.20mm boron concentration specified above for the fragment. 2 / (minutes*K) range. A segment with a dwell time of 180 minutes between 1150°C and 950°C is selected. The segment is sliced ​​into wafers and a silicon epitaxial layer is grown on the positive surface of each substrate. The epitaxial wafers are measured using a laser inspection tool to determine the defect count. The average epitaxial defect count is 16 per wafer, which is significantly higher than the 3 defect count per wafer achieved by embodiments of this disclosure (e.g., see...). Figure 5 and 6 (and Table 1 below).

[0061] Figure 7 Also demonstrated is the preparation Figure 4 (“Example 1”) and Figure 5 ("Example 2") data.

[0062] Example 3: Defect count varying according to v / G

[0063] Table 1 shows the target boron and oxygen concentrations in the crystal fragments for various test batches, along with the dwell time spent in the temperature range from 1150°C to 950°C. Epitaxial silicon layers were deposited on each substrate, and epitaxial defect counts were measured using a laser inspection tool. In Table 1, "High" excess vacancy indicates a v / G higher than the v / G range specified above (for values ​​from 2.8 x 10⁻⁶). 18 atoms / cm 3 Up to 5.4x10 18 atoms / cm 3 The boron concentration, v / G greater than 0.20 mm 2 / (minutes*K), and for 5.4x10 18 atoms / cm 3 Up to 8.0x10 18 atoms / cm 3 The boron concentration is greater than 0.25 (v / G). "Low" excess vacancy indicates a v / G less than the range specified above (for values ​​from 2.8 x 10⁻⁶). 18 atoms / cm 3 Up to 5.4x10 18 atoms / cm 3 The boron concentration, v / G less than 0.20 mm 2 / (minutes*K), and for 5.4x10 18 atoms / cm 3 Up to 8.0x10 18 atoms / cm 3 (Boron concentration, v / G less than 0.25).

[0064]

[0065]

[0066] Table 1: Defect counts varying according to v / G (i.e., excess vacancy concentration)

[0067] As shown in Table 1, low defect counts can be achieved when the excess vacancy concentration is low or when the residence time in the temperature range of 1150°C to 950°C is low (or a combination of these conditions).

[0068] As used herein, the terms “about,” “substantially,” and “approximately” when used in conjunction with a range of size, concentration, temperature, or other physical or chemical properties or characteristics mean that variations may exist in the upper and / or lower limits of the range of properties or characteristics, including variations such as those due to rounding, measurement methodology, or other statistical variations.

[0069] When describing elements of this disclosure or embodiments thereof, the articles “a” and “described” are intended to mean that one or more elements are present. The terms “comprising,” “including,” “containing,” and “having” are intended to be inclusive and mean that additional elements besides those listed are present. Terms indicating a particular orientation (e.g., “top,” “bottom,” “side,” etc.) are used for convenience of description and do not require any particular orientation of the described items.

[0070] Because various changes can be made to the above construction and methods without departing from the scope of this disclosure, all matters contained in the above description and shown in the accompanying drawings should be interpreted as illustrative and non-limiting.

Claims

1. A method for forming a silicon substrate having a primary core with depletion-induced epitaxial defects, wherein the silicon substrate is boron doped, the method comprising: Add the initial charge of polycrystalline silicon to the crucible; The crucible containing the initial charge of polycrystalline silicon is heated to cause a silicon melt to form in the crucible; Boron is added to the crucible to produce a doped silicon melt; The silicon seed crystal is brought into contact with the doped silicon molten material; The silicon seed crystal is extracted to grow a single-crystal silicon ingot, the ingot having a constant diameter portion having a length D, wherein a segment is a portion of the constant diameter portion of the ingot, the segment having a length from 2.8 x 10⁻⁶. 18 atoms / cm 3 Up to 5.4 x 10 18 atoms / cm 3 The boron concentration is specified, and the fragment has a length of at least 0.5*D; During the growth of the segment, (i) the growth rate v and / or (ii) the axial temperature gradient G are controlled such that v / G is less than 0.20 mm. 2 / (minutes*K); and The fragment is cooled from its solidification temperature to 950°C or less, wherein the residence time of the fragment in the temperature range of 1150°C to 950°C is less than 160 minutes.

2. The method according to claim 1, wherein the length of the segment is at least 0.75*D.

3. The method of claim 1, wherein the residence time of the segment of the constant diameter portion of the ingot within the temperature range of 1150°C to 950°C is less than 120 minutes.

4. The method of claim 1, wherein the melt is not doped with carbon.

5. The method of claim 1, further comprising slicing the single-crystal silicon ingot into a substrate.

6. A method for preparing an epitaxial structure, the method comprising: A silicon substrate is formed by the method according to claim 1; and The front surface of the silicon substrate is brought into contact with a silicon-containing gas, which decomposes to form an epitaxial silicon layer on the silicon substrate.

7. A method for forming a silicon substrate having a primary core with reduction-induced epitaxial defects, the method comprising: Add the initial charge of polycrystalline silicon to the crucible; The crucible containing the initial charge of polycrystalline silicon is heated to cause a silicon melt to form in the crucible; Boron is added to the crucible to prepare a sample with a diameter of at least 3.8 x 10⁻⁶. 18 atoms / cm 3 Boron concentration in doped silicon melt; The silicon seed crystal is brought into contact with the doped silicon molten material; The silicon seed crystal is extracted to grow a single-crystal silicon ingot, the ingot having a constant diameter portion and the constant diameter portion having a length D; During fragment growth, (i) the growth rate v and / or (ii) the axial temperature gradient G are controlled such that the ratio v / G is less than a critical v / G and the gap is the dominant inherent point defect in the fragment, wherein the fragment is part of the constant diameter portion of the ingot, and the fragment has a length of at least 0.5*D; and The fragment is cooled from its solidification temperature to 950°C or less, wherein the residence time of the fragment in the temperature range of 1150°C to 950°C is less than 160 minutes.

8. The method of claim 7, wherein the length of said segment is at least 0.75*D.

9. The method of claim 7, wherein the residence time of the segment of the constant diameter portion of the ingot within the temperature range of 1150°C to 950°C is less than 120 minutes.

10. The method according to claim 7, wherein: The boron concentration in the fragment is from 2.8 x 10⁻⁶. 18 atoms / cm 3 Up to 5.4 x 10 18 atoms / cm 3 Control (i) the growth rate v and / or (ii) the axial temperature gradient G so that v / G is less than 0.20 mm. 2 / (minutes*K).

11. The method according to claim 7, wherein: The boron concentration in the fragment is from 5.4 x 10⁻⁶. 18 atoms / cm 3 Up to 8.0 x 10 18 atoms / cm 3 Control (i) the growth rate v and / or (ii) the axial temperature gradient G so that v / G is less than 0.25 mm. 2 / (minutes*K).

12. The method of claim 7, wherein the melt is not doped with carbon.

13. The method of claim 7, further comprising slicing the single-crystal silicon ingot into a substrate.

14. A method for preparing an epitaxial structure, the method comprising: A silicon substrate is formed by the method according to claim 7; and The front surface of the silicon substrate is brought into contact with a silicon-containing gas, which decomposes to form an epitaxial silicon layer on the silicon substrate.

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