Backlight control chip, driving method, backlight control system and near-eye display device

Abstract

A backlight control chip (001), a driving method and a backlight control system, and a near-eye display device. The backlight control chip (001) is used for driving a backlight module, comprising: a boost circuit (101), the boost circuit (101) is configured to receive and boost a variable frequency clock signal (EXT_CLK) into a synchronization signal (HVSYNC_IN), wherein the variable frequency clock signal (EXT_CLK) and the synchronization signal (HVSYNC_IN) both have the same refresh rate as variable frequency display; a gating circuit (102), the gating circuit (102) is configured to receive the synchronization signal (HVSYNC_IN), a fixed frequency signal (VSYNC), a variable frequency signal (512xVSYNC), a first frame frequency control signal (HVSYNC_EN) and a second frame frequency control signal (DPLL_ENB), and after controlling the switching output of the synchronization signal (HVSYNC_IN) and the variable frequency signal (512xVSYNC) in response to the first frame frequency control signal (HVSYNC_EN), then controlling the switching output of the synchronization signal (HVSYNC_IN) or the variable frequency signal (512xVSYNC) and the fixed frequency signal (VSYNC) in response to the second frame frequency control signal (DPLL_ENB), wherein the fixed frequency signal (VSYNC) is used to complete the generation of the internal main clock signal of the backlight control chip (001), the variable frequency signal (512xVSYNC) is irrelevant to the refresh rate of variable frequency display, and the frame frequency control signal includes the first frame frequency control signal (HVSYNC_EN) and the second frame frequency control signal (DPLL_ENB).

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a backlight control chip, driving method and backlight control system, and near-eye display device. Background Technology

[0002] Near-eye displays are currently a hot research topic, including helmet-style virtual reality displays and smart glasses-style augmented reality displays. Near-eye displays can provide people with an unprecedented level of interactivity and have significant application value in many fields such as telemedicine, industrial design, education, military virtual training, and entertainment. Summary of the Invention

[0003] The backlight control chip, driving method, backlight control system, and near-eye display device disclosed herein are specifically designed as follows:

[0004] On one hand, embodiments of this disclosure provide a backlight control chip for driving a backlight module, including:

[0005] A boost circuit is configured to receive and boost a frequency-converted clock signal into a synchronization signal, wherein both the frequency-converted clock signal and the synchronization signal have the same refresh rate as the frequency-converted display.

[0006] A gating circuit is configured to receive at least the synchronization signal and the frame rate control signal, and to control the output of the synchronization signal in response to the frame rate control signal.

[0007] In some embodiments, in the backlight control chip provided in the present disclosure, the gating circuit is specifically configured to receive the synchronization signal, the fixed-frequency signal, the variable-frequency signal, the first frame frequency control signal, and the second frame frequency control signal. After controlling the switching output of the synchronization signal and the variable-frequency signal in response to the first frame frequency control signal, it then controls the switching output of the synchronization signal or the variable-frequency signal and the fixed-frequency signal in response to the second frame frequency control signal. The fixed-frequency signal is used to generate the internal master clock signal of the backlight control chip. The variable-frequency signal is independent of the refresh rate of the variable-frequency display. The frame frequency control signal includes the first frame frequency control signal and the second frame frequency control signal.

[0008] In some embodiments, in the backlight control chip provided in the present disclosure, the gating circuit includes a first gating unit and a second gating unit, wherein the control terminal of the first gating unit is connected to the first frame frequency control signal, the first input terminal of the first gating unit is connected to the frequency conversion signal, the second input terminal of the first gating unit is connected to the synchronization signal, the control terminal of the second gating unit is connected to the second frame frequency control signal, the first input terminal of the second gating unit is electrically connected to the output terminal of the first gating unit, and the second input terminal of the second gating unit is connected to the fixed frequency signal.

[0009] In some embodiments, the backlight control chip provided in this disclosure further includes a first voltage regulation and filtering circuit, which is configured to perform voltage regulation and filtering on the frequency conversion clock signal provided by the clock signal terminal, and provide the frequency conversion clock signal after voltage regulation and filtering to the boost circuit.

[0010] In some embodiments, in the backlight control chip provided in the present disclosure, the first voltage stabilizing filter circuit includes an even number of cascaded first NOT gates.

[0011] In some embodiments, the backlight control chip provided in the present disclosure further includes a protection circuit, which is configured to provide the effective level of the frequency conversion clock signal to the first voltage regulator and filter circuit, and prevent the effective level in the first voltage regulator and filter circuit from flowing back to the clock signal terminal.

[0012] In some embodiments, in the backlight control chip provided in this disclosure, the protection circuit includes: a first resistor, a second resistor, a third resistor, a diode, a switching transistor, a second NOT gate, a third NOT gate, and a first AND gate. The first resistor is connected between the clock signal terminal and the first voltage regulator / filter circuit. The first end of the second resistor is electrically connected to the first voltage regulator / filter circuit. The second end of the second resistor is electrically connected to the first end of the third resistor. The second end of the third resistor is grounded. The anode of the diode is grounded. The cathode of the diode is electrically connected to the clock signal terminal. The control terminal of the switching transistor is electrically connected to the output terminal of the first AND gate. The first electrode of the switching transistor is electrically connected to the second end of the second resistor. The second electrode of the switching transistor is grounded. The input terminal of the second NOT gate is electrically connected to the second end of the second resistor. The output terminal of the second NOT gate is electrically connected to the input terminal of the third NOT gate. The first input terminal of the first AND gate is electrically connected to the output terminal of the second NOT gate. The second input terminal of the first AND gate is connected to a first frame rate control signal.

[0013] In some embodiments, the backlight control chip provided in the present disclosure further includes a second voltage-stabilizing filter circuit, which is configured to perform voltage-stabilizing filter processing on the synchronization signal and provide the voltage-stabilized and filtered synchronization signal to the gating circuit.

[0014] In some embodiments, in the backlight control chip provided in the present disclosure, the second voltage stabilizing filter circuit includes an even number of cascaded fourth NOT gates.

[0015] In some embodiments, the backlight control chip provided in the present disclosure further includes a noise reduction circuit, which is configured to perform noise reduction processing on the synchronization signal after voltage regulation and filtering, and then provide it to the gating circuit.

[0016] In some embodiments, in the backlight control chip provided in the present disclosure, the noise reduction circuit includes a fourth resistor and a capacitor, wherein the fourth resistor is connected between the second voltage stabilizing filter circuit and the gating circuit, and the capacitor is connected between the gating circuit and ground.

[0017] In some embodiments, the backlight control chip provided in this disclosure further includes an analog phase-locked loop (PLL), which is configured to generate a backlight driving timing sequence with the same refresh rate as the output signal of the gating circuit in response to the output signal of the gating circuit.

[0018] In some embodiments, the backlight control chip provided in this disclosure further includes a digital phase-locked loop (PLL), which is configured to receive a fixed-frequency signal and generate a variable-frequency signal based on the fixed-frequency signal.

[0019] In some embodiments, the backlight control chip provided in this disclosure further includes a third voltage stabilizing filter circuit, which is configured to provide a stable analog enable signal to the analog phase-locked loop and a stable digital enable signal to the digital phase-locked loop.

[0020] In some embodiments, in the backlight control chip provided in this disclosure, the third voltage regulator filter circuit includes: a fifth NOT gate, a sixth NOT gate, a seventh NOT gate, a second AND gate, a third AND gate, a fourth AND gate, and an OR gate; wherein, the input terminal of the fifth NOT gate is connected to the second frame frequency control signal, the output terminal of the fifth NOT gate is electrically connected to the first input terminal of the second AND gate, the second input terminal of the second AND gate is connected to a trigger signal, the output terminal of the second AND gate is electrically connected to the enable input terminal of the digital phase-locked loop (PLL), the input terminal of the sixth NOT gate is electrically connected to the first output terminal of the digital PLL, and the output terminal of the sixth NOT gate is electrically connected to the... The first input terminal of the seventh NOT gate is electrically connected, the second input terminal of the seventh NOT gate is electrically connected to the output terminal of the fifth NOT gate, the output terminal of the seventh NOT gate is electrically connected to the first input terminal of the third AND gate, the second input terminal of the third AND gate is connected to the trigger signal, the output terminal of the third AND gate is electrically connected to the enable input terminal of the analog phase-locked loop, the first input terminal of the fourth AND gate is connected to the analog enable signal, the first input terminal of the fourth AND gate is connected to the first frame frequency control signal, the output terminal of the fourth AND gate is electrically connected to the first input terminal of the OR gate, and the second input terminal of the OR gate is electrically connected to the second output terminal of the digital phase-locked loop.

[0021] On the other hand, this disclosure provides a driving method for the aforementioned backlight control chip, including:

[0022] The system receives and boosts a frequency conversion clock signal into a synchronization signal, wherein both the frequency conversion clock signal and the synchronization signal have the same refresh rate as the frequency conversion display.

[0023] The system receives at least the synchronization signal and the frame rate control signal, and in response to the frame rate control signal, controls the output of the synchronization signal to drive the backlight module according to the output synchronization signal.

[0024] On the other hand, embodiments of this disclosure provide a backlight control system, including: a backlight control chip, a power supply chip, a logic control chip, a backlight power supply chip, and a display driver chip; wherein,

[0025] The backlight control chip is the backlight control chip provided in the embodiments of this disclosure;

[0026] The power supply chip is configured to provide operating voltage to the backlight control chip, the logic control chip, the backlight power chip, and the display driver chip;

[0027] The logic control chip is configured to control the enabling and logic operation of the backlight control chip, the backlight power chip, and the display driver chip;

[0028] The backlight power chip is configured to provide a driving voltage to the backlight module;

[0029] The display driver chip is configured to provide a driving voltage to the display module and a fixed-frequency signal to the backlight control chip.

[0030] On the other hand, embodiments of this disclosure provide a near-eye display device, including a display module, a backlight module, and a backlight control system, wherein the backlight control system is the aforementioned backlight control system. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the backlight control chip provided in an embodiment of the present disclosure;

[0032] Figure 2 This is a schematic diagram of the circuit structure in the backlight control chip provided in the embodiments of this disclosure;

[0033] Figure 3 A schematic diagram of the specific structure of the circuit in the backlight control chip provided in the embodiments of this disclosure;

[0034] Figure 4 This is a schematic diagram of the backlight control system provided in an embodiment of the present disclosure;

[0035] Figure 5 A timing diagram for backlight frequency conversion control provided in an embodiment of this disclosure. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that the dimensions and shapes of the figures in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout the drawings.

[0037] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0038] In near-eye display systems (such as virtual reality (VR), augmented reality (AR), and mixed reality (MR), binocular stereoscopic vision plays a significant role. The user's two eyes see different images, which are generated and displayed separately on different screens. When a user wears a near-eye display device, one eye sees only odd-numbered frames, and the other eye sees only even-numbered frames. The human eye perceives these differing images and generates a sense of depth in the brain.

[0039] When a display shows a moving object, the eye perceives the object's trajectory as a line as its position changes. Since the image on the screen jumps to the next point after a short period at each point, the best and simplest way to make the image appear to move more continuously is to increase the refresh rate. However, considering that a higher refresh rate increases power consumption, a variable refresh rate design can be used to balance display quality and power consumption. Specifically, the refresh rate is reduced when displaying static images to lower power consumption; the refresh rate is increased when displaying dynamic video images, especially in fast-paced games, to achieve the best display effect. When designing a variable refresh rate display, the backlight also needs to be designed with a variable refresh rate, ensuring that the backlight frequency changes synchronously with the video content. However, simply adjusting the backlight frequency requires powering on and off the backlight control chip and updating the driver code, which causes the backlight to flicker and then relight, affecting the user experience.

[0040] To address the aforementioned technical problems in related technologies, this disclosure provides a backlight control chip 001 for driving a backlight module, such as... Figures 1 to 3 As shown, it includes:

[0041] A boost circuit 101 is configured to receive and boost the frequency conversion clock signal EXT_CLK into a synchronization signal HVSYNC_IN, for example, boosting it into a square wave signal with an amplitude of 3.3V, wherein both the frequency conversion clock signal EXT_CLK and the synchronization signal HVSYNC_IN have the same refresh rate as the frequency conversion display.

[0042] The gating circuit 102 is configured to receive at least the synchronization signal HVSYNC_IN and the frame rate control signal (e.g., HVSYNC_EN and DPLL_ENB), and to control the output of the synchronization signal HVSYNC_IN in response to the frame rate control signal (e.g., HVSYNC_EN and DPLL_ENB).

[0043] In the backlight control chip 001 provided in this embodiment, the external frequency conversion clock signal EXT_CLK is boosted by the boost circuit 101 into a synchronization signal HVSYNC_IN that can be used by the backlight control chip 001. Under the action of the frame frequency control signal (e.g., HVSYNC_EN and DPLL_ENB) by the gating circuit 102, the synchronization signal HVSYNC_IN is output, so that the backlight module can work based on the synchronization signal HVSYNC_IN that is synchronized with the frequency conversion display. Therefore, the backlight control chip 001 does not need to be re-powered, so the backlight module will not flicker and then light up again, thus improving the user experience.

[0044] In some embodiments, the backlight control chip 001 provided in this disclosure is designed with a working voltage region, a multiplexed channel region, and a logic control input region. The working voltage region is used to receive power signals, the multiplexed channel region is used to connect to the LED drive channel of the backlight module via a multiplexed switch MUX, and the logic control input region is used to receive control signals. This disclosure does not improve the working voltage region and the multiplexed channel region; in other words, the circuit structures described in this disclosure are all improvements to the logic control input region. Furthermore, since this application adds a frequency conversion clock signal EXT_CLK (see [link to relevant technology]) compared to related technologies... Figure 1 The remaining signals were unchanged; therefore, this disclosure does not imply any alteration of the signals. Figure 1 The functions of each existing signal will be introduced in detail.

[0045] In some embodiments, in the backlight control chip provided in the present disclosure, such as Figure 2 and Figure 3 As shown, the gating circuit 102 is specifically configured to receive the synchronization signal HVSYNC_IN, the fixed-frequency signal VSYNC, the variable-frequency signal 512xVSYNC, the first frame frequency control signal HVSYNC_EN, and the second frame frequency control signal DPLL_ENB. After controlling the switching output of the synchronization signal HVSYNC_IN and the variable-frequency signal 512xVSYNC in response to the first frame frequency control signal HVSYNC_EN, it then controls the switching output of the synchronization signal HVSYNC_IN or the variable-frequency signal 512xVSYNC and the fixed-frequency signal VSYNC in response to the second frame frequency control signal DPLL_ENB. The fixed-frequency signal VSYNC is used to generate the main clock signal inside the backlight control chip 001. The variable-frequency signal 512xVSYNC is independent of the refresh rate of the variable-frequency display. The frame frequency control signals include the first frame frequency control signal HVSYNC_EN and the second frame frequency control signal DPLL_ENB.

[0046] Since related technologies use a variable frequency signal 512xVSYNC and a fixed frequency signal VSYNC to drive the backlight module and the display screen to work synchronously, the gating circuit 102 in this disclosure can control the selective output of the synchronization signal HVSYNC_IN, the variable frequency signal 512xVSYNC, or the fixed frequency signal VSYNC, making the backlight control chip 001 compatible with related technologies and facilitating product upgrades. In specific implementations, the fixed frequency signal VSYNC can still be used to generate the internal master clock of the backlight control chip 001 during display. When it is necessary to synchronize the frequency with the display frequency, the synchronization signal HVSYNC_IN generated by the variable frequency clock signal EXT_CLK can be used to achieve synchronous frequency conversion control of the backlight module.

[0047] In some embodiments, in the backlight control chip provided in the present disclosure, such as Figure 2 and Figure 3 As shown, the gating circuit 102 may include a first gating unit 1021 and a second gating unit 1022. The control terminal of the first gating unit 1021 is connected to the first frame frequency control signal HVSYNC_EN, the first input terminal of the first gating unit 1021 is connected to the frequency conversion signal 512xVSYNC, the second input terminal of the first gating unit 1021 is connected to the synchronization signal HVSYNC_IN, the control terminal of the second gating unit 1022 is connected to the second frame frequency control signal DPLL_ENB, the first input terminal of the second gating unit 1022 is electrically connected to the output terminal of the first gating unit 1021, and the second input terminal of the second gating unit 1022 is connected to the fixed frequency signal VSYNC.

[0048] Specifically, the first selector 1021 can respond to the first frame frequency control signal HVSYNC_EN to switch the output of the synchronization signal HVSYNC_IN and the frequency conversion signal 512xVSYNC. Furthermore, when the first selector 1021 outputs the synchronization signal HVSYNC_IN, the second selector 1022 can respond to the second frame frequency control signal DPLL_ENB to switch the output of the synchronization signal HVSYNC_IN and the fixed-frequency signal VSYNC; when the first selector 1021 outputs the frequency conversion signal 512xVSYNC, the second selector 1022 can respond to the second frame frequency control signal DPLL_ENB to switch the output of the frequency conversion signal 512xVSYNC and the fixed-frequency signal VSYNC.

[0049] In some embodiments, in the backlight control chip provided in the present disclosure, such as Figure 2 and Figure 3As shown, it may also include a first voltage-regulating filter circuit 103, which is configured to perform voltage regulation and filtering on the frequency-changing clock signal EXT_CLK provided by the clock signal terminal TM, and provide the voltage-regulating and filtered frequency-changing clock signal EXT_CLK to the boost circuit 101. Optionally, the first voltage-regulating filter circuit 103 may include an even number (e.g., 2) of cascaded first NOT gates (also called inverters) N1. Specifically, the frequency-changing clock signal EXT_CLK changes with the refresh rate of the frequency-changing display. After being connected to the backlight control chip 001, it passes through the first voltage-regulating filter circuit 103, which includes two first NOT gates N1, to form a stable periodic signal that follows the refresh rate change of the frequency-changing display.

[0050] In some embodiments, in the backlight control chip provided in the present disclosure, such as Figure 2 and Figure 3 As shown, it may also include a protection circuit 104, which is configured to provide the effective level (e.g., high level) of the frequency conversion clock signal EXT_CLK to the first voltage regulator filter circuit 103 and prevent the effective level (e.g., high level) in the first voltage regulator filter circuit 103 from flowing back to the clock signal terminal TM. Optionally, the protection circuit 104 may include: a first resistor R1, a second resistor R2, a third resistor R3, a diode D, a switching transistor Q, a second NOT gate N2, a third NOT gate N3, and a first AND gate A. The first resistor R1 is connected between the clock signal terminal TM and the first voltage regulator / filter circuit 103. The first end of the second resistor R2 is electrically connected to the first voltage regulator / filter circuit 103. The second end of the second resistor R2 is electrically connected to the first end of the third resistor R3. The second end of the third resistor R3 is grounded. The anode of the diode D is grounded. The cathode of the diode D is electrically connected to the clock signal terminal TM. The control terminal of the switching transistor Q is electrically connected to the output terminal of the first AND gate A1. The first electrode of the switching transistor Q is electrically connected to the second end of the second resistor R2. The second electrode of the switching transistor Q is grounded. The input terminal of the second NOT gate N2 is electrically connected to the second end of the second resistor R2. The output terminal of the second NOT gate N2 is electrically connected to the input terminal of the third NOT gate N3. The first input terminal of the first AND gate A is electrically connected to the output terminal of the second NOT gate N1. The second input terminal of the first AND gate A is connected to the first frame rate control signal HVSYNC_EN.

[0051] In some embodiments, in the backlight control chip provided in the present disclosure, such as Figure 2 and Figure 3As shown, it may further include a second voltage-regulating filter circuit 105, which is configured to perform voltage-regulating filtering on the synchronization signal HVSYNC_IN and provide the voltage-regulating filtered synchronization signal HVSYNC_IN to the gating circuit 102, specifically to the first gating circuit 1021. Optionally, the second voltage-regulating filter circuit 105 includes an even number (e.g., 2) of cascaded fourth NOT gates N4.

[0052] In some embodiments, in the backlight control chip provided in the present disclosure, such as Figure 2 and Figure 3 As shown, it may also include a noise reduction circuit 106, which is configured to reduce the noise of the regulated and filtered synchronization signal HVSYNC_IN before providing it to the gating circuit 102, specifically to the first gating circuit 1021. Optionally, the noise reduction circuit 106 may include a fourth resistor R4 and a capacitor C, wherein the fourth resistor R4 is connected between the second regulated and filtered circuit 105 and the gating circuit 102 (specifically the first gating circuit 1021), and the capacitor C is connected between the gating circuit 102 (specifically the first gating circuit 1021) and ground.

[0053] In some embodiments, in the backlight control chip provided in the present disclosure, such as Figure 2 and Figure 3 As shown, it may also include an analog phase-locked loop (APLL) 107, which is configured to generate a backlight drive timing with the same refresh rate as the output signal of the gating circuit 102 (specifically the second gating circuit 1022) in response to the output signal of the gating circuit 102 (specifically the second gating circuit 1022).

[0054] In some embodiments, in the backlight control chip provided in the present disclosure, such as Figure 2 and Figure 3 As shown, it may also include a digital phase-locked loop (AFC) 108, which is configured to receive a fixed-frequency signal VSYNC and generate a variable-frequency signal 512xVSYNC based on the fixed-frequency signal VSYNC.

[0055] In some embodiments, in the backlight control chip provided in the present disclosure, such as Figure 2 and Figure 3As shown, it may also include a third voltage regulator and filter circuit 109, which is configured to provide a stable analog enable signal APLL_EN to the analog phase-locked loop 107 and a stable digital enable signal AFC_EN to the digital phase-locked loop 108. Optionally, the third voltage regulator filter circuit 109 includes: a fifth NOT gate N5, a sixth NOT gate N6, a seventh NOT gate N7, a second AND gate A2, a third AND gate A3, a fourth AND gate A4, and an OR gate O; wherein, the input terminal of the fifth NOT gate N5 is connected to the second frame frequency control signal DPLL_ENB, the output terminal of the fifth NOT gate N5 is electrically connected to the first input terminal of the second AND gate A2, the second input terminal of the second AND gate A2 is connected to the trigger signal PLL_START, the output terminal of the second AND gate A2 is electrically connected to the enable input terminal of the digital phase-locked loop 108 (i.e., the pin used to connect the digital enable signal AFC_EN), the input terminal of the sixth NOT gate N6 is electrically connected to the first output terminal APLL_RUN of the digital phase-locked loop 108, and the output terminal of the sixth NOT gate N6 is electrically connected to the fourth AND gate A4 of the seventh NOT gate N7. One input terminal is electrically connected. The second input terminal of the seventh NOT gate N7 is electrically connected to the output terminal of the fifth NOT gate N5. The output terminal of the seventh NOT gate N7 is electrically connected to the first input terminal of the third AND gate A3. The second input terminal of the third AND gate A3 is connected to the trigger signal PLL_START. The output terminal of the third AND gate A3 is electrically connected to the enable input terminal of the analog phase-locked loop 107 (i.e., the pin used to connect the analog enable signal APLL_EN). The first input terminal of the fourth AND gate A4 is connected to the analog enable signal APLL_EN. The first input terminal of the fourth AND gate A4 is connected to the first frame frequency control signal HVSYNC_EN. The output terminal of the fourth AND gate A4 is electrically connected to the first input terminal of the OR gate O. The second input terminal of the OR gate O is electrically connected to the second output terminal AFCOK of the digital phase-locked loop 108.

[0056] It should be noted that, Figure 3 This is merely an example illustrating the specific structure of each circuit in the backlight driver chip 001 provided in the embodiments of this disclosure. In specific implementation, the specific structure of each circuit is not limited to the structure provided in the embodiments of this disclosure, and may also be other structures known to those skilled in the art, which are not limited here.

[0057] Based on the same inventive concept, this disclosure provides a driving method for the aforementioned backlight control chip, which may include the following steps:

[0058] It receives and boosts the frequency conversion clock signal into a synchronization signal, wherein both the frequency conversion clock signal and the synchronization signal have the same refresh rate as the frequency conversion display;

[0059] It receives at least a synchronization signal and a frame rate control signal, and in response to the frame rate control signal, controls the output of the synchronization signal to drive the backlight module according to the output synchronization signal.

[0060] Since the principle of this driving method in solving the problem is similar to that of the backlight control chip described above, the implementation of the driving method provided in this disclosure embodiment can refer to the implementation of the backlight control chip provided in this disclosure embodiment, and the repeated parts will not be described again.

[0061] Based on the same inventive concept, embodiments of this disclosure provide a backlight control system, such as... Figure 4 As shown, it may include: a backlight control chip (BLU IC) 001, a power supply chip (PMIC) 002, a logic control chip (AP) 003, a backlight power supply chip (BLU Power Supply) 004, and a display driver chip (DDIC) 005; wherein,

[0062] The backlight control chip 001 is the backlight control chip 001 provided in the embodiments of this disclosure;

[0063] The power supply chip 002 is configured to provide operating voltage to the backlight control chip 001, the logic control chip 003, the backlight power chip 004, and the display driver chip 005;

[0064] The logic control chip 003 is configured to control the enabling and logic operation of the backlight control chip 001, the backlight power supply chip 004, and the display driver chip 005.

[0065] Backlight power chip 004 is configured to provide driving voltage to the backlight module;

[0066] The display driver chip 005 is configured to provide a driving voltage to the display module and a fixed-frequency signal VSYNC to the backlight control chip 001.

[0067] Optionally, such as Figure 5 As shown, within one frame: triggered by the display data signal MIPI, the liquid crystal stabilization period is entered first, and then the backlight starts working; the frequency conversion clock signal ECT_CLK is input to the backlight control chip 001 as an external dynamic clock signal; the backlight drive timing BLU_PWM is a square wave signal that specifically drives the backlight to light up, which runs through the lighting process of the backlight modules in each area; at the same time, the fixed frequency signal VSYNC, as an external input signal, can make the backlight control chip 001 work in a fixed frequency state. In some embodiments, the backlight control chip 001 can also work in a frequency conversion state based on the synchronization signal HVSYNC_IN generated by the external frequency conversion clock signal EXT_CLK.

[0068] Based on the same inventive concept, this disclosure provides a near-eye display device, including a display module, a backlight module, and a backlight control system, wherein the backlight control system is the aforementioned backlight control system. Since the principle by which this near-eye display device solves the problem is similar to that of the aforementioned backlight control chip, the implementation of this near-eye display device can refer to the embodiments of the aforementioned backlight control chip, and repeated details will not be elaborated further.

[0069] In some embodiments, the near-eye display device provided in the present disclosure may also include, but is not limited to, components such as a radio frequency unit, a network module, an audio output & input unit, a user input unit, an interface unit, and a memory. Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the near-eye display device provided in the present disclosure; in other words, the near-eye display device provided in the present disclosure may include more or fewer of the above components, or combine certain components, or have different component arrangements.

[0070] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A backlight control chip for driving a backlight module, wherein, include: A boost circuit is configured to receive and boost a frequency-converted clock signal into a synchronization signal, wherein both the frequency-converted clock signal and the synchronization signal have the same refresh rate as the frequency-converted display. A gating circuit configured to receive at least the synchronization signal and the frame rate control signal, and in response to the frame rate control signal, control the output of the synchronization signal; The gating circuit is specifically configured to receive the synchronization signal, the fixed-frequency signal, the variable-frequency signal, the first frame frequency control signal, and the second frame frequency control signal, and after controlling the switching output of the synchronization signal and the variable-frequency signal in response to the first frame frequency control signal, it further controls the switching output of the synchronization signal or the variable-frequency signal and the fixed-frequency signal in response to the second frame frequency control signal.

2. The backlight control chip of claim 1, wherein, The fixed-frequency signal is used to generate the main clock signal inside the backlight control chip. The variable-frequency signal is independent of the refresh rate of the variable-frequency display. The frame rate control signal includes the first frame rate control signal and the second frame rate control signal.

3. The backlight control chip of claim 2, wherein, The gating circuit includes a first gating unit and a second gating unit. The control terminal of the first gating unit is connected to the first frame frequency control signal, the first input terminal of the first gating unit is connected to the frequency conversion signal, the second input terminal of the first gating unit is connected to the synchronization signal, the control terminal of the second gating unit is connected to the second frame frequency control signal, the first input terminal of the second gating unit is electrically connected to the output terminal of the first gating unit, and the second input terminal of the second gating unit is connected to the fixed frequency signal.

4. The backlight control chip according to any one of claims 1 to 3, wherein, It also includes a first voltage regulator and filter circuit, which is configured to perform voltage regulation and filtering on the frequency conversion clock signal provided by the clock signal terminal, and provide the frequency conversion clock signal after voltage regulation and filtering to the boost circuit.

5. The backlight control chip of claim 4, wherein, The first voltage regulator filter circuit includes an even number of cascaded first NOT gates.

6. The backlight control chip of claim 4, wherein, It also includes a protection circuit, which is configured to provide the effective level of the frequency conversion clock signal to the first voltage regulator and filter circuit, and prevent the effective level in the first voltage regulator and filter circuit from flowing back to the clock signal terminal.

7. The backlight control chip of claim 6, wherein, The protection circuit comprises a first resistor, a second resistor, a third resistor, a diode, a switching transistor, a second NOT gate, a third NOT gate and a first AND gate, wherein the first resistor is connected between the clock signal end and the first voltage stabilizing filter circuit, a first end of the second resistor is electrically connected with the first voltage stabilizing filter circuit, a second end of the second resistor is electrically connected with a first end of the third resistor, a second end of the third resistor is grounded, an anode of the diode is grounded, a cathode of the diode is electrically connected with the clock signal end, a control end of the switching transistor is electrically connected with an output end of the first AND gate, a first pole of the switching transistor is electrically connected with the second end of the second resistor, a second pole of the switching transistor is grounded, an input end of the second NOT gate is electrically connected with the second end of the second resistor, an output end of the second NOT gate is electrically connected with an input end of the third NOT gate, a first input end of the first AND gate is electrically connected with the output end of the second NOT gate, and a second input end of the first AND gate is connected with a first frame frequency control signal.

8. The backlight control chip according to any one of claims 1-3, 5-7, wherein, The protection circuit further comprises a second voltage stabilizing filter circuit configured to perform voltage stabilizing filtering on the synchronization signal and provide the voltage stabilizing filtered synchronization signal to the gating circuit.

9. The backlight control chip of claim 8, wherein, The second voltage stabilizing filter circuit comprises an even number of fourth NOT gates connected in cascade.

10. The backlight control chip of claim 8, wherein, The protection circuit further comprises a noise reduction circuit configured to perform noise reduction on the voltage stabilizing filtered synchronization signal and provide the noise reduced synchronization signal to the gating circuit.

11. The backlight control chip of claim 10, wherein, The noise reduction circuit comprises a fourth resistor and a capacitor, wherein the fourth resistor is connected between the second voltage stabilizing filter circuit and the gating circuit, and the capacitor is connected between the gating circuit and the ground.

12. The backlight control chip of any of claims 1-3, 5-7, 9-11, wherein, The protection circuit further comprises an analog phase-locked loop configured to generate a backlight driving timing with the same refresh rate as an output signal of the gating circuit in response to the output signal of the gating circuit.

13. The backlight control chip of claim 12, wherein, The protection circuit further comprises a digital phase-locked loop configured to receive a fixed frequency signal and generate a variable frequency signal according to the fixed frequency signal.

14. The backlight control chip of claim 13, wherein, The protection circuit further comprises a third voltage stabilizing filter circuit configured to provide a stable analog enable signal to the analog phase-locked loop and a stable digital enable signal to the digital phase-locked loop.

15. The backlight control chip of claim 14, wherein, The third voltage stabilizing filter circuit comprises a fifth NOT gate, a sixth NOT gate, a seventh NOT gate, a second AND gate, a third AND gate, a fourth AND gate and an OR gate; wherein the input end of the fifth NOT gate is connected to the second frame frequency control signal, the output end of the fifth NOT gate is electrically connected to the first input end of the second AND gate, the second input end of the second AND gate is connected to a trigger signal, the output end of the second AND gate is electrically connected to the enable input end of the digital phase-locked loop, the input end of the sixth NOT gate is electrically connected to the first output end of the digital phase-locked loop, the output end of the sixth NOT gate is electrically connected to the first input end of the seventh NOT gate, the second input end of the seventh NOT gate is electrically connected to the output end of the fifth NOT gate, the output end of the seventh NOT gate is electrically connected to the first input end of the third AND gate, the second input end of the third AND gate is connected to the trigger signal, the output end of the third AND gate is electrically connected to the enable input end of the analog phase-locked loop, the first input end of the fourth AND gate is connected to the analog enable signal, the first input end of the fourth AND gate is connected to the first frame frequency control signal, and the output end of the fourth AND gate is electrically connected to the first input end of the OR gate, and the second input end of the OR gate is electrically connected to the second output end of the digital phase-locked loop.

16. A method of driving a backlight control chip as claimed in any one of claims 1 to 15, wherein, Comprise: Receive and boost the variable frequency clock signal to a synchronization signal, wherein the variable frequency clock signal and the synchronization signal both have the same refresh rate as the variable frequency display; At least receive the synchronization signal and a frame frequency control signal, and in response to the frame frequency control signal, control the output of the synchronization signal to drive the backlight module according to the output synchronization signal.

17. A backlight control system, wherein, Comprise: A backlight control chip, a power supply chip, a logic control chip, a backlight power supply chip and a display driving chip; wherein The backlight control chip is the backlight control chip of any one of claims 1-15; The power supply chip is configured to provide operating voltage for the backlight control chip, the logic control chip, the backlight power supply chip and the display driving chip; The logic control chip is configured to control the enablement and logic operation of the backlight control chip, the backlight power supply chip and the display driving chip; The backlight power supply chip is configured to provide driving voltage for the backlight module; The display driving chip is configured to provide driving voltage for the display module and provide a fixed frequency signal for the backlight control chip.

18. A near-eye display device, wherein, Comprise a display module, a backlight module and a backlight control system, wherein the backlight control system is the backlight control system of claim 17.

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