Method of preparing a TEM sample

Abstract

The application discloses a TEM sample preparation method, comprising the following steps: step one, providing a chip sample with a metal protective layer formed on a first surface; step two, fixing the chip sample on a sample stage of a FIB system; step three, performing first FIB cutting on the metal protective layer along a first direction to form a groove; the first direction is a width direction of the TEM sample, a second direction is perpendicular to the first direction; the groove extends along the first direction; on a section along the second direction, an inner side surface of the groove is arc-shaped, so that the thickness of the metal protective layer in the groove area gradually changes; step four, performing second FIB cutting along a third direction to thin the chip sample and form a TEM sample; the third direction points from the metal protective layer to the chip sample; the thickness of the metal protective layer is used to adjust a cutting speed, so that the width of the TEM sample gradually changes and an optimal observation area is obtained. The application can realize accurate control on the thickness of the TEM sample, thereby improving the TEM analysis quality.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor integrated circuit manufacturing method, in particular to a transmission electron microscope (TEM) sample preparation method. BACKGROUND

[0002] Transmission electron microscope has a very wide and increasingly important application in various fields including integrated circuit analysis, and double-beam focused ion beam (FIB) sample preparation is the most important TEM sample preparation method in the semiconductor field.

[0003] According to the sample process node and the analysis target structure, the thickness requirement of the TEM sample to be prepared is also different, for example, at the 55nm technology node, the thickness of most TEM samples is required to be about 60nm-80nm; and at the 14nm FinFET technology node, the TEM sample thickness is 30nm, or even 10nm.

[0004] The current TEM sample preparation method is to thin the whole chip sample to the required thickness, and the thickness is mainly determined according to the experience of the sample preparation personnel, so that the analysis quality is often affected due to inaccurate judgment. SUMMARY

[0005] The technical problem to be solved by the present application is to provide a TEM sample preparation method, which can realize accurate control of the thickness of the TEM sample, thereby improving the TEM analysis quality.

[0006] To solve the above technical problems, the TEM sample preparation method provided by the present application comprises the following steps:

[0007] Step one, providing a chip sample formed with a metal protective layer, the metal protective layer is formed on a first surface of the chip sample.

[0008] Step two, fixing the chip sample on a sample stage of a FIB system.

[0009] Step three, using FIB to perform first FIB cutting on the metal protective layer to form a groove; the first direction is the width direction of the TEM sample, and the second direction is the direction perpendicular to the first direction in the first surface.

[0010] The direction of the first FIB cutting is the first direction, and the groove extends along the first direction.

[0011] On the section along the second direction, the inner side surface of the groove is arc-shaped.

[0012] In the second direction, the groove is located in a forming area of the TEM sample, and the thickness of the metal protective layer at each position of the inner side surface of the groove gradually changes.

[0013] Step four, performing a second FIB cutting on the chip sample by using FIB, the second FIB cutting thins the chip sample and forms the TEM sample.

[0014] The direction of the second FIB cutting is a third direction, and the third direction is a direction from the metal protective layer to the chip sample; in the second FIB cutting, the thickness of the metal protective layer is used to adjust the cutting speed at the corresponding position and thereby adjust the width of the TEM sample; the thicker the thickness of the metal protective layer, the slower the cutting speed of the second FIB cutting, and the thinner the thickness of the metal protective layer, the faster the cutting speed of the second FIB cutting; in the groove forming area, the gradually changing thickness of the metal protective layer is used to make the width of the TEM sample gradually change, and the optimal observation area is obtained in the gradually changing width of the TEM sample for TEM analysis, and the optimal observation area is flanked by an over-thick area and an over-thin area.

[0015] Further improvement is that the chip sample is obtained by cutting or thinning process on a wafer composed of a semiconductor substrate.

[0016] Further improvement is that the metal protective layer is formed before or after the wafer is cut or thinned.

[0017] Further improvement is that a semiconductor device layer is formed on the semiconductor substrate, and the top surface of the semiconductor device layer is the first surface.

[0018] Further improvement is that the material of the metal protective layer includes platinum or tungsten.

[0019] Further improvement is that in step one, the thickness of the chip sample is 300nm-1000nm.

[0020] Further improvement is that the thickness of the metal protective layer is 2μm-5μm.

[0021] Further improvement is that in step two, the chip sample is fixed on the sample stage of the FIB system by being welded on the TEM copper ring.

[0022] Further improvement is that in step three, in the cross section along the second direction, the arc shape of the inner side surface of the groove includes a circular arc shape.

[0023] Further improvement is that the diameter of the circle corresponding to the circular arc shape is 3μm-10μm.

[0024] Further improvement is that the third direction is perpendicular to the first surface.

[0025] Further improvement is that the second FIB cutting forms a first side surface and a second side surface of the TEM sample in sequence; the first side surface and the second side surface of the TEM sample are parallel and perpendicular to the width direction of the TEM sample outside the groove.

[0026] Further improvement is that the thickness of the metal protective layer is lost during the second FIB cutting.

[0027] The second FIB cutting is ended when the metal protective layer in the over-thin area is completely removed and the material of the bottom chip sample is damaged.

[0028] Further improvement is that the semiconductor device layer is formed with a FinFET.

[0029] Further improvement is that the minimum width of the optimal observation area of the TEM sample in step four is 30 nm or less than 10 nm.

[0030] The present application forms a metal protective layer on a chip sample, and then performs FIB cutting on the metal protective layer before performing FIB cutting on the chip sample, i.e. first FIB cutting. The first FIB cutting forms a groove extending along the width direction of the TEM sample in the metal protective layer. The inner side of the groove is arc-shaped, and the groove is located in the forming area of the TEM sample. The groove causes the thickness of the metal protective layer to continuously change. Then, the FIB cutting on the chip sample is performed, i.e. second FIB cutting. In the second FIB cutting, the thickness of the metal protective layer in the forming area of the TEM sample continuously changes, and the cutting rate of the second FIB cutting is different when the thickness of the metal protective layer is different. As a result, the width of the finally formed TEM sample continuously changes. In the continuously changing width, the optimal observation area for TEM analysis can be easily obtained. In the present application, the width of the TEM sample is used as the thickness. Therefore, in the second FIB cutting of the present application, even if there is a certain deviation in the cutting, the deviation only moves the optimal observation area to the over-thick area side or the over-thin area side, but the corresponding optimal observation area can always be obtained. Thus, the defect that the thickness of the TEM sample is either too thick or too thin in the prior art is eliminated. Therefore, the present application can accurately control the thickness of the TEM sample, thereby improving the quality of TEM analysis. BRIEF DESCRIPTION OF DRAWINGS

[0031] The present application will be further described in detail below in combination with the drawings and specific embodiments:

[0032] Figure 1This is a flowchart of the method for preparing TEM samples according to an embodiment of the present invention;

[0033] Figure 2A This is a side view of the chip sample in step one of the TEM sample preparation method according to an embodiment of the present invention;

[0034] Figure 2B This is a top view of the chip sample in step one of the TEM sample preparation method of this embodiment of the invention;

[0035] Figure 3A This is a side view of the chip sample after step three of the TEM sample preparation method according to an embodiment of the present invention.

[0036] Figure 3B This is a top view of the chip sample after step three of the TEM sample preparation method according to an embodiment of the present invention.

[0037] Figure 4A This is a side view of the TEM sample after step four of the TEM sample preparation method according to an embodiment of the present invention is completed;

[0038] Figure 4B This is a top view of the TEM sample after step four of the TEM sample preparation method in this embodiment of the invention has been completed;

[0039] Figures 5A-5E These are photographs of the samples taken in each step of the TEM sample preparation method according to the embodiments of the present invention.

[0040] Figure 6A The TEM image is obtained by performing TEM analysis on the optimal observation area of ​​the TEM sample prepared by the TEM sample preparation method of the present invention.

[0041] Figure 6A The TEM image is obtained by performing TEM analysis on the optimal observation area of ​​the TEM sample prepared by the TEM sample preparation method of the present invention.

[0042] Figure 6B The TEM image is obtained by performing TEM analysis on the excessively thick area of ​​the TEM sample formed by the TEM sample preparation method of the present invention.

[0043] Figure 6C The TEM image is obtained by performing TEM analysis on the overly thin region of the TEM sample prepared by the TEM sample preparation method of the present invention. Detailed Implementation

[0044] like Figure 1 The diagram shown is a flowchart of the preparation method of TEM sample 106 according to an embodiment of the present invention; the preparation method of TEM sample 106 according to an embodiment of the present invention includes the following steps:

[0045] Step one, as shown in Figure 2A provides a chip sample 101 formed with a metal protective layer 104, which is formed on a first surface of the chip sample 101.

[0046] Figure 2A is a side view of the yz plane. Figure 2B is Figure 2A is a top view of the xy plane.

[0047] In the embodiment of the present application, the chip sample 101 is obtained by cutting or thinning a wafer composed of a semiconductor substrate 102.

[0048] In some embodiments, the cutting or thinning of the wafer can be achieved by mechanical cutting or thinning. After the cutting or thinning of the wafer, the thickness of the chip sample 101 is 300nm-1000nm.

[0049] The semiconductor device layer 103 is formed on the semiconductor substrate 102, and the top surface of the semiconductor device layer 103 is the first surface.

[0050] In some embodiments, the semiconductor device layer 103 is formed with a FinFET. The FinFET is formed on a fin body (Fin), which is formed by patterned etching of the semiconductor substrate 102. FinFET is usually applied to 14nm technology node and below.

[0051] The metal protective layer 104 is formed before or after the cutting or thinning of the wafer.

[0052] The material of the metal protective layer 104 includes platinum or tungsten.

[0053] The thickness of the metal protective layer 104 is 2μm-5μm.

[0054] Step two, the chip sample 101 is fixed on the sample stage of the FIB system.

[0055] In some embodiments, the chip sample 101 is fixed on the sample stage of the FIB system by being welded on the TEM copper ring.

[0056] Step three, as shown in Figure 3A , a first FIB cutting is performed on the metal protective layer 104 by FIB to form a groove 105; the first direction is the width direction of the TEM sample 106, and the second direction is perpendicular to the first direction in the first surface.

[0057] Figure 3A is a side view of the yz plane. Figure 3B isFigure 3A A top view of the corresponding xy plane. The first direction is the x direction, and the second direction is the y direction. Figure 3B In the middle, the dashed box 201 represents the formation region of the groove 105.

[0058] The first direction of the first FIB cutting is the first direction, and the groove 105 extends along the first direction.

[0059] In the cross section along the second direction, i.e. in the Figure 3A On the corresponding yz plane, the inner side surface of the groove 105 is arc-shaped.

[0060] In the second direction, the groove 105 is located in the formation region of the TEM sample 106, and the thickness of the metal protective layer 104 at each position of the inner side surface of the groove 105 gradually changes.

[0061] In some preferred embodiments, in the cross section along the second direction, the arc shape of the inner side surface of the groove 105 is a circular arc shape. The diameter of the corresponding circle of the circular arc shape is 3 μm to 10 μm.

[0062] Step four, as shown in the figure, the chip sample 101 is subjected to a second FIB cutting by using a FIB. The second FIB cutting thins the chip sample 101 and forms the TEM sample 106. Figure 4A

[0063] A side view of the yz plane. Figure 4A A top view of the corresponding xy plane. Figure 4B Figure 4A Since the TEM sample 106 is formed by thinning the chip sample 101, the superposed film layer of the TEM sample 106 is also the same as that of the chip sample 101, i.e. the superposed film layer of the TEM sample 106 includes the semiconductor substrate 102 and the semiconductor device layer 103.

[0064] Since the TEM sample 106 is formed by thinning the chip sample 101, the superposed film layer of the TEM sample 106 is also the same as that of the chip sample 101, i.e. the superposed film layer of the TEM sample 106 includes the semiconductor substrate 102 and the semiconductor device layer 103.

[0065] ​The direction of the second FIB cut is a third direction, which is the direction from the metal protective layer 104 to the chip sample 101. In the second FIB cut, the cutting rate at the corresponding position is adjusted by the thickness of the metal protective layer 104, thereby adjusting the width of the TEM sample 106. The thicker the metal protective layer 104, the slower the cutting rate of the second FIB cut, and the thinner the metal protective layer 104, the faster the cutting rate of the second FIB cut. In the region where the groove 105 is formed, the width of the TEM sample 106 is gradually changed by utilizing the gradually changing thickness of the metal protective layer 104. The optimal observation area 106b is obtained in the gradually changing width of the TEM sample 106 for TEM analysis. The two sides of the optimal observation area 106b are the overly thick area 106c and the overly thin area 106a, respectively.

[0066] In this embodiment of the invention, the third direction is perpendicular to the first surface, thus, the third direction is... Figure 4A The -z direction. In other embodiments, the third direction may also be at an angle to the -z direction.

[0067] like Figure 4B As shown, the second FIB cut sequentially forms the first and second sides of the TEM sample 106. Outside the groove, the first and second sides of the TEM sample 106 are parallel and perpendicular to the width direction of the TEM sample 106. The dashed box 202 indicates the region of the chip sample 101. The second FIB cut causes the first and second sides of the chip sample 101 to move inward and form the first and second sides of the TEM sample 106.

[0068] In the region where the groove 105 is formed, the first and second sides of the TEM sample 106 will be concave, causing the width of the TEM sample 106 to change gradually. This makes it easy to obtain the optimal observation area 106b in the TEM sample 106. That is, even if there is a certain control deviation in the second FIB cutting process, this deviation will only cause the optimal observation area 106b to move towards the overly thick area 106c or the overly thin area 106a, but the corresponding optimal observation area 106b can always be obtained.

[0069] In this embodiment of the invention, the thickness of the metal protective layer 104 will be reduced during the second FIB cutting process. (Comparison) Figure 3A and Figure 4A As shown, Figure 4A The thickness of the metal protective layer 104 in the middle becomes thinner.

[0070] The second FIB dicing ends when the metal protective layer 104 in the overthin region 106a is completely removed and the material of the bottom chip sample 101 is damaged. This also makes it easy to determine the endpoint of the second FIB dicing in this embodiment of the invention.

[0071] In some embodiments, the minimum width of the optimal observation region 106b of the TEM sample 106 is 30 nm or less. This is readily applicable to FinFET TEM analysis that requires a thinner TEM sample 106.

[0072] In this embodiment of the invention, after the metal protective layer 104 is formed on the chip sample 101, before performing FIB dicing on the chip sample 101, the metal protective layer 104 is first diced using FIB, i.e., a first FIB dicing is performed. The first FIB dicing forms a groove 105 extending along the width direction of the TEM sample 106 within the metal protective layer 104. The inner surface of the groove 105 has an arc-shaped structure, and the groove 105 is located in the formation area of ​​the TEM sample 106. The groove 105 causes the thickness of the metal protective layer 104 to continuously change. Then, the chip sample 101 is diced using FIB, i.e., a second FIB dicing is performed. In the second FIB dicing, the thickness of the metal protective layer 104 in the formation area of ​​the TEM sample 106 continuously changes, and the thickness of the metal protective layer 104 is also considered. The different cutting rates of the second FIB cut result in a continuously varying width of the final TEM sample 106. Within this continuously varying width, the optimal observation region 106b for TEM analysis is easily obtained. In this invention, the width of the TEM sample 106 is considered its thickness. Therefore, in the second FIB cut of this embodiment, even if there is a certain deviation in the cutting, this deviation only causes the optimal observation region 106b to shift towards either the excessively thick region 106c or the excessively thin region 106a. However, the corresponding optimal observation region 106b can always be obtained, thus eliminating the defect in existing methods where the thickness of the TEM sample 106 is either too thick or too thin. Therefore, this embodiment of the invention can achieve precise control of the thickness of the TEM sample 106, thereby improving the quality of TEM analysis.

[0073] The following description, in conjunction with actual photographs, further illustrates the method of this invention:

[0074] like Figures 5A to 5E The images shown are sample photographs corresponding to each step of the TEM sample preparation method in an embodiment of the present invention.

[0075] Figure 5AFigure 2 shows the chip sample 301 after step one, in which the metal protective layer 304, i.e. metal plating layer, is formed on the first surface of the chip sample 301. After step two, the chip sample 301 is welded on the TEM copper ring 401.

[0076] Figure 5B Figure 3 shows the processing area 305a defined before the first FIB cutting in step three. The processing area 305a is used to define the forming area of the groove 305.

[0077] Figure 5C Figure 4 shows the groove 305 formed after the first FIB cutting.

[0078] Figure 5D Figure 5 shows the chip sample 301 after step three and before step four, in which the chip sample 301 is flipped to change the FIB cutting direction. Figure 5D Figure 6 also shows the superimposed layers of the chip sample 301, i.e. the semiconductor substrate 302 and the semiconductor device layer 303.

[0079] Figure 5E Figure 7 shows the chip sample 301 thinned into the TEM sample 306 after the second FIB cutting in step four. The TEM sample 306 is divided into the best observation area 306b, the too thin area 306a and the too thick area 306c according to the width.

[0080] When TEM analysis is performed, the best observation area 306b can obtain the best TEM photo. As shown in Figure 6A Figure 8, the TEM photo 501 obtained by performing TEM analysis on the best observation area 306b in Figure 6 can be seen to be very clear. Figure 5E As shown in

[0081] Figure 9, the TEM photo 502 obtained by performing TEM analysis on the too thick area 306c in Figure 6 can be seen to be not as good as the TEM photo 501 in Figure 8. Figure 6B Figure 5E As shown in Figure 6A Figure 10, the TEM photo 503 obtained by performing TEM analysis on the too thin area 306a in Figure 6 can be seen to be not as good as the TEM photo 501 in Figure 8. It can also be seen in the TEM photo 503 that the material of the chip sample 101 is slightly damaged.

[0082] As shown in Figure 6C Figure 11, the TEM photo 504 obtained by performing TEM analysis on the chip sample 101 in Figure 1 can be seen to be not as good as the TEM photo 501 in Figure 8. Figure 5E Figure 6A

[0083] ​​​The application is described in detail above with specific embodiments, but these do not constitute a limitation on the application. Those skilled in the art can make many modifications and improvements without departing from the principles of the application, and these should also be considered as within the scope of protection of the application.

Claims

1. A method of preparing a TEM sample, characterized by, The method comprises the following steps: Step one, providing a chip sample formed with a metal protective layer, the metal protective layer being formed on a first surface of the chip sample; Step two, fixing the chip sample on a sample stage of a FIB system; Step three, using FIB to perform a first FIB cutting on the metal protective layer to form a groove; a first direction is a width direction of a TEM sample to be formed subsequently, and a second direction is a direction perpendicular to the first direction within the first surface; The first FIB cutting is performed in the first direction, and the groove extends in the first direction; On a cross section along the second direction, an inner side surface of the groove is arc-shaped; In the groove, a thickness of the metal protective layer at each position of the inner side surface gradually changes along the second direction; Step four, using FIB to perform a second FIB cutting on the chip sample, the second FIB cutting thinning the chip sample and forming the TEM sample; The second FIB cutting is performed in a third direction, the third direction being a direction from the metal protective layer to the chip sample; in the second FIB cutting, a cutting speed at a corresponding position is adjusted by using the thickness of the metal protective layer to adjust a width of the TEM sample; the thicker the thickness of the metal protective layer, the slower the cutting speed of the second FIB cutting, and the thinner the thickness of the metal protective layer, the faster the cutting speed of the second FIB cutting; in the groove formation area, the width of the TEM sample gradually changes by using the gradually changing thickness of the metal protective layer, and an optimal observation area is obtained in the gradually changing width of the TEM sample for TEM analysis, the optimal observation area being flanked by an over-thick area and an over-thin area.

2. The method of preparing a TEM sample of claim 1, wherein: The chip sample is obtained by cutting or thinning a wafer composed of a semiconductor substrate.

3. The method of preparing a TEM sample of claim 2, wherein: The metal protective layer is formed before or after the wafer is cut or thinned.

4. The method of preparing a TEM sample of claim 2, wherein: A semiconductor device layer is formed on the semiconductor substrate, a top surface of the semiconductor device layer being the first surface.

5. The method of preparing a TEM sample of claim 1, wherein: The metal protective layer is made of platinum or tungsten.

6. The method of preparing a TEM sample of claim 1, wherein: In step one, the thickness of the chip sample is 300 nm to 1000 nm.

7. The method of preparing a TEM sample of claim 2, wherein: The thickness of the metal protective layer is 2 μm to 5 μm.

8. The method of preparing a TEM sample of claim 1, wherein: In step two, the chip sample is fixed on the sample stage of the FIB system by being welded on a TEM copper ring.

9. The method of preparing a TEM sample of claim 7, wherein: In step three, on a cross section along the second direction, the arc shape of the inner side surface of the groove comprises a circular arc shape.

10. The method of preparing a TEM sample of claim 9, wherein: The diameter of a circle corresponding to the circular arc shape is 3 μm to 10 μm.

11. The method of preparing a TEM sample of claim 1, wherein: The third direction is perpendicular to the first surface.

12. The method of preparing a TEM sample of claim 1, wherein: The second FIB cutting sequentially forms a first side surface and a second side surface of the TEM sample, and the first side surface and the second side surface of the TEM sample are parallel and perpendicular to the width direction of the TEM sample outside the groove.

13. The method of preparing a TEM sample of claim 1, wherein: In the second FIB cutting, the thickness of the metal protective layer is lost. The second FIB cut ends when the metal protective layer in the over-thin area is completely removed and causes material of the bottom chip sample to be damaged.

14. The method of preparing a TEM sample of claim 4, wherein: The semiconductor device layer has a FinFET formed therein.

15. The method of preparing a TEM sample of claim 14, wherein: In step four, the minimum width of the optimal observation area of the TEM sample is 30 nm or less, or 10 nm or less.

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