Fib and tem based finfet structure slice analysis method

Abstract

The application discloses a FinFET structure slicing analysis method based on FIB and TEM, and relates to the technical field of semiconductor process detection and analysis. In order to solve the problem of the deficiency of traditional detection technology in resolution and accuracy caused by the complexity of the three-dimensional nano structure of the FinFET device, the application realizes high-precision analysis of the FinFET device by optimizing the whole process of sample pretreatment, FIB processing and TEM analysis. The application utilizes the combination of FIB accurate processing and TEM high-resolution imaging to accurately measure the fin structure morphology, multi-layer film thickness and composition distribution. The application reduces sample damage through processes such as PI conductive adhesive treatment and low-energy ion cleaning, and combines a dynamic parameter optimization mechanism to ensure the sample integrity in the processing and detection process. The application introduces three-dimensional reconstruction and structure-performance correlation analysis, which not only can stereoscopically present the structure characteristics of the FinFET, but also can simulate the influence of parameters such as fin pitch and gate coverage length on the device performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor process inspection and analysis technology, and in particular to a FinFET structure slice analysis method based on FIB and TEM. Background Technology

[0002] With the advancement of integrated circuit technology to nodes of 7nm and below, FinFET has become the mainstream device structure. In FinFET devices, the accurate control of the multilayer film structure and the intricate three-dimensional structure directly determines the device's performance and reliability. However, the complexity of this three-dimensional nanostructure poses a significant challenge to traditional detection techniques, especially when analyzing the morphology, size, thickness, and compositional distribution of the fin structure. Existing methods still fall short in terms of resolution and accuracy. Particularly in processes below 7nm, issues such as ion beam processing damage, positioning deviations caused by multilayer film obstruction, and incomplete three-dimensional structure characterization make accurate analysis of FinFET structures difficult. Summary of the Invention

[0003] The purpose of this invention is to provide a FinFET structure slicing analysis method based on FIB and TEM. By combining FIB and TEM techniques and optimizing the sample preparation process, high-precision detection of the thickness, morphology and composition of multilayer films in the three-dimensional structure of FinFET is achieved, meeting the nanoscale analysis requirements of 7nm and below process devices, and solving the problems mentioned in the background art.

[0004] To achieve the above objectives, the present invention provides the following technical solution:

[0005] FinFET structure slicing analysis methods based on FIB and TEM include:

[0006] Sample pretreatment: The FinFET chip is coated with adhesive, and the uneven surface of the FinFET chip is potted with adhesive. At the same time, the target area is calibrated using a marking machine.

[0007] FIB processing: The pre-processed FinFET chip is placed in the FIB device, and the FinFET chip is initially positioned based on the range calibration results of the target area to determine the target FinFET area. The target cross section is then cut and thinned to prepare a thin film sample for TEM analysis.

[0008] TEM analysis: The prepared thin film sample was placed in a TEM to obtain a high-resolution image of the FinFET structure. The boundaries and morphology of the fin structure and its multilayer films were analyzed. Based on the analysis results, the structural features of the FinFET were extracted, the elemental distribution map inside the FinFET was drawn, and the constituent materials of the FinFET structure were determined.

[0009] Furthermore, the sample pretreatment also includes:

[0010] For FinFET chips that are highly sensitive to fin structures, PI conductive adhesive is used to coat the surface of the FinFET chip. After coating, a low-temperature curing process is performed to form a smooth conductive layer.

[0011] Before the slicing operation, a low-energy ion cleaning process is used on the surface of the FinFET chip. The surface of the FinFET chip is cleaned by an inert gas ion beam at an inclined angle to remove contaminants and oxide layers.

[0012] Furthermore, using a marking machine to define the range of the target area also includes:

[0013] Scanning electron microscopes were used to verify the marked points of the FinFET chip after range calibration, and the positional relationship between the marked points and the actual FinFET structure was compared. The offset between the center of the marked points and the key features of the actual FinFET structure was calculated.

[0014] If the offset between the marker point and the actual FinFET structure exceeds a preset threshold, the positioning fails, and the range is recalibrated to adjust the coordinates of the marker point selection position.

[0015] If the offset is within the preset threshold range, the actual coordinate deviation between the marker point and the actual FinFET structure is recorded.

[0016] Based on the actual coordinate deviation between the marked point and the actual FinFET structure, a mapping relationship between the marking machine coordinates and the FIB coordinate system is established in the FIB device.

[0017] Furthermore, the FIB processing, which determines the target FinFET region, specifically includes:

[0018] The pre-processed FinFET chip is fixed on the sample stage of the FIB equipment, the marking machine marks are identified, and the target position of the target FinFET region in the FIB coordinate system is calculated by combining the mapping relationship between the marking machine coordinates and the FIB coordinate system.

[0019] A grid scan is performed on the target location to obtain an ion image of the target location. The actual position of the marker point in the ion image is extracted, and the deviation parameter between the actual position of the marker point and the FIB coordinate system is calculated. The position of the marker point and the mapped coordinates are calibrated to determine the target FinFET region.

[0020] Furthermore, the FIB processing, which involves cutting and thinning the target cross-section, specifically includes:

[0021] A protective film is deposited on the surface of the designated target area to construct a processing protection barrier;

[0022] A low-energy ion beam is used to perform rough processing by gradually reducing the ion beam energy and beam current intensity, and the target cross section is cut in layers to gradually thin the FinFET chip;

[0023] In the final stage of processing, the target cross-section is polished. After polishing, the key areas of the target cross-section are locally polished.

[0024] The FIB processing involves cutting and thinning the target cross-section, specifically including:

[0025] A protective film is deposited on the surface of the designated target area to construct a processing protection barrier;

[0026] A low-energy ion beam is used to perform rough processing by gradually reducing the ion beam energy and beam current intensity, and the target cross section is cut in layers to gradually thin the FinFET chip;

[0027] In the final stage of processing, the target cross-section is polished. After polishing, the key areas of the target cross-section are locally polished.

[0028] Furthermore, a low-energy ion beam is used for rough processing by progressively reducing the ion beam energy and beam current intensity, and the target cross-section is cut into layers to gradually thin the FinFET chip. Specifically, this includes:

[0029] Load the FinFET chip material property library to obtain the initial cutting energy E0 and the minimum allowable polishing energy E. min And the total number of layers N to be cut; wherein, the initial cutting energy E0 is used to cut the first layer;

[0030] Based on the initial cutting energy E0 and the minimum permissible polishing energy E min And set the energy attenuation coefficient ξ=ln(E0 / E) to the total number of layers N to be cut. min ) / N 1.5 ;

[0031] Configure a piezoelectric sensor to collect the current depth acoustic impedance of the material corresponding to the target cross section in real time, and determine the rate of change Z of the acoustic impedance of the material corresponding to the current target cross section by real-time monitoring of the depth acoustic impedance.

[0032] An infrared thermal imager is configured, and the temperature of the processing area during the current target section cutting process is monitored in real time using an infrared camera;

[0033] The rate of temperature change T of the processing area during the processing process is obtained based on the real-time monitoring of the processing area temperature.

[0034] The ion beam energy and beam intensity for each layer cutting process are set according to the acoustic impedance change rate Z of the target cross-section corresponding to the start time of each layer cutting and the temperature change rate T of the processing area.

[0035] Furthermore, based on the acoustic impedance change rate Z of the target cross-section corresponding to the start time of each layer cutting and the temperature change rate T of the processing area, the ion beam energy and beam current intensity during each layer cutting process are set, specifically including:

[0036] Detect the current depth acoustic impedance value of the material corresponding to the target cross section of the current layer;

[0037] Retrieve the theoretical depth acoustic impedance value corresponding to the current layer's depth;

[0038] The depth acoustic impedance coefficient Z is obtained by using the current depth acoustic impedance value of the material corresponding to the target cross section of the current layer and the theoretical depth acoustic impedance value corresponding to the depth of the current layer. x =(Z s -Z t ) / Z t Among them, Z s Z represents the current depth acoustic impedance value; t This represents the theoretical depth acoustic impedance value;

[0039] Obtain the energy attenuation coefficient ξ;

[0040] The energy attenuation coefficient ξ and the depth acoustic impedance coefficient Z are compared. x The energy attenuation coefficient ξ is compared with the depth acoustic impedance coefficient Z. x The larger of the median values ​​is taken as the energy regulation coefficient max(ξ, Z). x );

[0041] Determine the initial cutting energy E0;

[0042] The ion beam energy for each layer cutting process is set by combining the energy adjustment coefficient with the acoustic impedance change rate Z corresponding to the current layer cutting start time.

[0043] Retrieve the cutting energy E corresponding to the previous layer when performing layered cutting. x ;

[0044] Using the cutting energy E x The cutting beam intensity corresponding to the current layer cutting is set by combining the ratio of the initial cutting energy E0 with the temperature change rate T of the processing area and the initial beam intensity I0; wherein, the initial beam intensity I0 is used to cut the first layer.

[0045] Furthermore, the TEM analysis determines the constituent materials of the FinFET structure, including: fin structure material: semiconductor material constituting the three-dimensional fin structure of the FinFET chip; multilayer film material: thin film material of each functional layer in the FinFET chip;

[0046] Among them, the multilayer film material also includes: obtaining the diffraction pattern of the multilayer film material, automatically identifying and calibrating the diffraction spots, classifying the material crystal form based on the constructed material classification and identification model, calculating the lattice constant and distortion parameters based on the position of the diffraction spots, and analyzing the crystal quality and interface stress state of the gate material.

[0047] Furthermore, the TEM analysis also includes:

[0048] The thin film sample was photographed from multiple angles to obtain projection images from different angles. Based on the image sequence of the projection images from different angles, a three-dimensional reconstruction was performed to construct a three-dimensional structure of the FinFET structure.

[0049] Three-dimensional measurements of key parameters of a three-dimensional structure based on FinFET structure are performed, and the three-dimensional features of the fin structure are analyzed based on the measurement results.

[0050] By mapping the three-dimensional features of the fin structure to the cross-sectional images of the FIB fabrication process, a three-dimensional coordinate system for the FinFET structure is established. The influence of key parameters of different three-dimensional features on the electrical performance of the device is simulated, and a quantitative correlation analysis of structure and performance is carried out.

[0051] Furthermore, it also includes:

[0052] During sample pretreatment, FIB processing and TEM analysis, the FinFET chip status and analysis data are acquired in real time, and key parameters are dynamically adjusted based on the real-time monitoring data.

[0053] The surface roughness of the FinFET chip after coating is monitored in real time during the sample pretreatment stage. When the roughness exceeds the preset roughness threshold, an early warning is triggered, prompting the coating process to be repeated.

[0054] During the FIB processing stage, cross-sectional images are acquired in real time to determine whether ion beam-induced damage occurs in the fin structure. Simultaneously, processing parameters such as ion beam energy and beam current intensity are acquired. If a pattern effect is detected on the cross-section, the ion beam energy and beam current intensity are reduced until the cross-sectional flatness meets the standard.

[0055] During the TEM analysis stage, it is determined whether the FinFET chip has been irradiated and damaged. At the same time, the stability of elemental signals in the energy dispersive spectroscopy analysis is monitored. The accelerating voltage is adjusted according to the thickness of the thin film sample, and the focal length shift caused by the uneven thickness of the thin film sample is corrected in real time.

[0056] Compared with the prior art, the beneficial effects of the present invention are:

[0057] This invention proposes a FinFET structure slicing analysis method based on FIB and TEM. By optimizing the entire process of sample pretreatment, FIB processing, and TEM analysis, it achieves high-precision analysis of FinFET devices. By combining precise FIB processing with high-resolution TEM imaging, it can accurately measure the morphology of fin structures, multilayer film thickness, and composition distribution with a resolution below 0.2 nm. Sample damage is reduced through processes such as PI conductive adhesive treatment and low-energy ion cleaning, and the integrity of samples is ensured during processing and testing by combining a dynamic parameter optimization mechanism. In addition, the introduction of three-dimensional reconstruction and structure-performance correlation analysis can not only present the structural characteristics of FinFETs in three dimensions, but also simulate the impact of parameters such as fin spacing and gate coverage length on device performance. This provides a systematic technical solution for the research and development, process optimization, and failure analysis of FinFETs with 7nm and below processes, significantly improving the quality control capabilities of advanced integrated circuit manufacturing. Attached Figure Description

[0058] Figure 1 This is a flowchart of the FinFET structure slice analysis method based on FIB and TEM according to the present invention. Detailed Implementation

[0059] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0060] To address the limitations of traditional detection techniques in terms of resolution and accuracy due to the complexity of the three-dimensional nanostructure of FinFET devices, as well as the technical problems of ion beam processing damage, multilayer film positioning errors, and incomplete three-dimensional structure characterization, please refer to [link to relevant documentation]. Figure 1 This embodiment provides the following technical solution:

[0061] FinFET structure slicing analysis methods based on FIB and TEM include:

[0062] Sample pretreatment: The FinFET chip is coated with adhesive, and uneven FinFET chip surfaces are potted with adhesive to improve surface smoothness and reduce ion beam energy loss due to unevenness, thus preventing cross-sectional patterning effects. Simultaneously, a marking machine is used to calibrate the target area. Other procedures include:

[0063] For FinFET chips that are highly sensitive to fin structures, a specific conductive adhesive (PI) is used to coat the surface of the FinFET chip. After coating, a low-temperature curing process is performed. The uniform distribution of the adhesive layer fills the micro-unevenness of the FinFET chip surface, forming a flat conductive layer to ensure surface flatness. This ensures that the adhesive layer is tightly bonded to the FinFET chip surface without introducing additional stress, reducing ion beam energy loss and FinFET chip cross-sectional pattern effect caused by flatness issues.

[0064] Before the slicing operation, a low-energy ion cleaning process is used on the surface of the FinFET chip. The surface of the FinFET chip is cleaned by an inert gas ion beam at a 45° tilt angle to remove contaminants and oxide layers. The oxide layer and adsorbed contaminant particles are peeled off layer by layer through the ion sputtering effect, thereby improving the surface quality of the FinFET chip.

[0065] FIB processing: The pre-processed FinFET chip is placed in the FIB device. Based on the range calibration results of the target area, the FinFET chip is initially positioned to determine the accurate target FinFET area. The target cross-section is then cut and thinned to prepare a thin film sample for TEM analysis.

[0066] TEM analysis: The prepared thin film sample was placed in a TEM to obtain a high-resolution image of the FinFET structure. Bright field and dark field imaging modes were used to analyze the boundaries and morphology of the fin structure and its multilayer films. Based on the analysis results, the structural features of the FinFET were extracted, the elemental distribution map inside the FinFET was drawn, and the constituent materials of the FinFET structure were determined.

[0067] In this embodiment, during sample pretreatment, PI conductive adhesive treatment and low-energy ion cleaning can improve surface smoothness and remove contaminants, reduce ion beam damage, and improve slice quality. FIB processing uses gradient energy ion beams and protective film deposition to precisely cut and thin to below 50nm, and polishing further improves cross-sectional smoothness, laying the foundation for high-resolution TEM imaging. TEM analysis, combined with EDS and SAED, enables accurate characterization of composition and crystal structure. Three-dimensional reconstruction technology can also measure key parameters in three dimensions and analyze the impact of structure on electrical performance. Dynamic parameter optimization throughout the process ensures sample integrity and analytical accuracy, solving the problems of insufficient resolution and large damage in existing technologies, and providing strong support for the research and development and process optimization of FinFET for 7nm and below processes.

[0068] In this embodiment, the marking machine is used to define the range of the target area, and the method further includes:

[0069] Scanning electron microscopy (SEM) was used to verify the marked points on the FinFET chip after range calibration. The positional relationship between the marked points and the actual FinFET structure was compared, and the offset between the center of the marked point and the key feature of the actual FinFET structure was calculated, including: lateral offset: the distance deviation between the center of the marked point and the target key feature in the X-axis direction of the chip's global coordinate system; longitudinal offset: the distance deviation between the center of the marked point and the target key feature in the Y-axis direction of the chip's global coordinate system.

[0070] If the offset between the marker point and the actual FinFET structure exceeds the preset threshold ±10μm, the positioning fails, and the range is recalibrated to adjust the coordinates of the marker point selection position.

[0071] If the offset is within the preset threshold range (≤±10μm), then record the actual coordinate deviation between the marker point and the actual FinFET structure;

[0072] Based on the actual coordinate deviation between the marked point and the actual FinFET structure, a mapping relationship between the marking machine coordinates and the FIB coordinate system is established in the FIB equipment. This is used for positioning correction during subsequent FIB processing, ensuring that the ion beam is accurately aligned with the target area and avoiding positioning deviations caused by coordinate system errors between the marking machine and the FIB equipment.

[0073] In this embodiment, by observing the positional relationship between the marker points and the actual FinFET structure using SEM and calculating the offset, positioning failures caused by coordinate system errors between the marking machine and the FIB equipment can be effectively avoided. When the offset exceeds a preset threshold, the range is recalibrated to ensure that the ion beam can be accurately aligned with the target area. The actual coordinate deviation between the marker points and the actual FinFET structure is recorded, and a mapping relationship between the marking machine coordinates and the FIB coordinate system is established. This can improve the positioning accuracy to within ±10μm, reduce repetitive operations caused by positioning deviations, and thus improve analysis efficiency.

[0074] In this embodiment, the FIB processing, which determines the target FinFET region, specifically includes:

[0075] The pre-processed FinFET chip is fixed on the sample stage of the FIB equipment, the marking machine marks are identified, and the target position of the target FinFET region in the FIB coordinate system is calculated by combining the mapping relationship between the marking machine coordinates and the FIB coordinate system.

[0076] A grid scan is performed on the target location to obtain an ion image of the target location. The actual position of the marker point in the ion image is extracted, and the deviation parameter between the actual position of the marker point and the FIB coordinate system is calculated. The position of the marker point and the mapped coordinates are calibrated to determine the target FinFET region.

[0077] In this embodiment, the FIB processing, which involves cutting and thinning the target cross-section, specifically includes:

[0078] A protective film of 50-200nm thickness, made of materials such as platinum or carbon, is deposited on the surface of the calibrated target area to build a processing protection barrier and prevent the FinFET chip from being damaged during the ion beam processing.

[0079] A low-energy ion beam is used to perform rough processing by gradually reducing the ion beam energy and beam current intensity. The target cross section is cut into layers to gradually thin the FinFET chip to a thickness of less than 50nm, ensuring the uniformity of the FinFET chip film.

[0080] Specifically, a low-energy ion beam is used for rough processing by gradually reducing the ion beam energy and beam current intensity, and the target cross-section is cut into layers to gradually thin the FinFET chip. This includes:

[0081] Load the FinFET chip material property library to obtain the initial cutting energy E0 and the minimum allowable polishing energy E. min And the total number of layers N to be cut; wherein, the initial cutting energy E0 is used to cut the first layer;

[0082] Based on the initial cutting energy E0 and the minimum permissible polishing energy E min And set the energy attenuation coefficient ξ=ln(E0 / E) to the total number of layers N to be cut. min ) / N 1.5 ;

[0083] Configure a piezoelectric sensor to collect the current depth acoustic impedance of the material corresponding to the target cross section in real time, and determine the rate of change Z of the acoustic impedance of the material corresponding to the current target cross section by real-time monitoring of the depth acoustic impedance.

[0084] An infrared thermal imager is configured, and the temperature of the processing area during the current target section cutting process is monitored in real time using an infrared camera;

[0085] The rate of temperature change T of the processing area during the processing process is obtained based on the real-time monitoring of the processing area temperature.

[0086] The ion beam energy and beam intensity for each layer of cutting are set according to the acoustic impedance change rate Z of the target cross-section corresponding to the start time of each layer cutting and the temperature change rate T of the processing area.

[0087] In this embodiment, by loading a FinFET chip material property library, the initial cutting energy, minimum allowable polishing energy, and total number of cutting layers are obtained. Based on material properties and processing requirements, a reasonable energy attenuation coefficient can be set, enabling precise control of the ion beam energy and beam current intensity. Layered cutting, with progressively decreasing ion beam energy and beam current intensity, allows the chip to be gradually thinned according to predetermined thickness requirements, helping to achieve precise thinning dimensions and meeting the stringent thickness accuracy requirements in FinFET chip manufacturing. A piezoelectric sensor is used to collect the depth acoustic impedance of the material corresponding to the target cross-section in real time, and the rate of change of acoustic impedance is determined. Changes in acoustic impedance reflect changes in material properties and structural characteristics. By monitoring this parameter, the state of the material during cutting can be understood in real time, such as whether the interlayer interface of different materials has been cut, providing a basis for adjusting ion beam parameters and avoiding over-cutting or under-cutting. An infrared thermal imager is used to monitor the temperature of the processing area in real time and obtain the temperature change rate. Temperature changes during cutting affect the performance of the chip material and the ion beam processing effect; excessively high temperatures may lead to material deformation, damage, and other problems. Real-time monitoring of temperature change rate allows for timely detection of temperature anomalies. By adjusting ion beam energy and beam current intensity, heat generation is controlled, ensuring the processing occurs within a suitable temperature range and minimizing the adverse effects of thermal effects on the chip. Real-time setting of ion beam energy and beam current intensity for each layer cut based on acoustic impedance and temperature change rates ensures that ion beam processing parameters are matched to the chip material state and processing conditions. When encountering different materials or structures, the ion beam can be adjusted promptly to cut with appropriate energy and intensity, thereby reducing chip damage and improving the quality and performance of the processed chip. This benefits subsequent chip manufacturing processes and overall chip performance. This technical solution, through precise control and real-time monitoring, avoids problems such as repeated processing and chip damage caused by improper processing parameters. It reduces debugging time and scrap rate during processing, comprehensively improving the efficiency of FinFET chip thinning, helping to reduce production costs and increase production efficiency.

[0088] Specifically, the ion beam energy and beam intensity during each layer cutting process are set according to the acoustic impedance change rate Z of the target cross-section corresponding to the start time of each layer cutting and the temperature change rate T of the processing area. This includes:

[0089] Detect the current depth acoustic impedance value of the material corresponding to the target cross section of the current layer;

[0090] Retrieve the theoretical depth acoustic impedance value corresponding to the current layer's depth;

[0091] The depth acoustic impedance coefficient Z is obtained by using the current depth acoustic impedance value of the material corresponding to the target cross section of the current layer and the theoretical depth acoustic impedance value corresponding to the depth of the current layer. x =(Zs -Z t ) / Z t Among them, Z s Z represents the current depth acoustic impedance value; t This represents the theoretical depth acoustic impedance value;

[0092] Obtain the energy attenuation coefficient ξ;

[0093] The energy attenuation coefficient ξ and the depth acoustic impedance coefficient Z are compared. x The energy attenuation coefficient ξ is compared with the depth acoustic impedance coefficient Z. x The larger of the median values ​​is taken as the energy regulation coefficient max(ξ, Z). x );

[0094] Determine the initial cutting energy E0;

[0095] The ion beam energy for each layer cutting process is set by combining the energy adjustment coefficient with the acoustic impedance change rate Z corresponding to the current layer cutting start time.

[0096] The cutting ion beam energy corresponding to the current layer cutting is obtained by the following formula:

[0097]

[0098] Among them, E k E represents the cutting ion beam energy corresponding to the current layer cutting; x This represents the cutting ion beam energy corresponding to the layer-by-layer cutting, when E x When E = 0, then let min(E) x E0) = E0; max(ξ, Z) x ) represents the energy regulation coefficient; d k D represents the cumulative cutting depth corresponding to the completion of the previous layer's layered cutting; total This represents the overall target thinning depth of the layered cutting; π is taken as 3.14; specifically, max(ξ, Z) x The maximum value between the two is taken, allowing the more critical factor among "process planning" and "material anomalies" to dominate energy regulation—if the material is uniform (Z... x If the energy is small, the energy will be slowly adjusted according to the preset attenuation (ξ); if a sudden change in material (Z) occurs... x If the energy level is high, the material anomaly will be responded to first, and energy will be rapidly reduced to avoid damage. d k It represents the depth of machining, D. total The total target depth is the starting point, and the ratio of these two values ​​represents the current processing progress (0 to 1 corresponds to the depth from the surface to the target depth). The sin² function causes the adjustment weight to fluctuate periodically with depth, but generally decreases; that is, the surface (d...)... kWhen the depth is small (d), the sin² value is small, indicating that the energy regulation is weak and a higher energy is needed for roughing; when approaching the target depth (d), the sin² value is small. k When the value approaches D_total, the sin² value is large, indicating strong surface energy regulation. This necessitates rapid energy reduction to prevent chip breakdown. This processing section simulates the "rough machining to fine polishing" process. The denominator 1+Z is used for dynamic compensation of the above calculations. Specifically, when the chip's internal structure is unstable (Z is large, such as due to uneven material or defects), the denominator increases, reducing the overall adjustment amplitude. This prevents severe energy fluctuations caused by over-responding to local anomalies, ensuring the robustness of the processing.

[0099] Retrieve the cutting energy E corresponding to the previous layer when performing layered cutting. x ;

[0100] Using the cutting energy E x The cutting beam intensity corresponding to the current layer cutting is set by combining the ratio of the initial cutting energy E0 with the temperature change rate T of the processing area and the initial beam intensity I0; wherein, the initial beam intensity I0 is used to cut the first layer.

[0101] Meanwhile, the cutting beam intensity corresponding to the current layer cutting is obtained by the following formula:

[0102]

[0103] Among them, I k I0 represents the cutting beam intensity corresponding to the current layer cutting; I0 represents the initial beam intensity; I0 represents the cutting beam intensity. x This represents the cutting beam intensity corresponding to the layered cutting of the previous layer. When I x When I = 0, then let min(I) x I0) = I0; T represents the temperature change rate of the processing area; f represents the synergistic decay index, which is obtained by the following formula:

[0104]

[0105] Where f represents the co-decay exponent; d k D represents the cumulative cutting depth corresponding to the completion of the previous layer's layered cutting; total This indicates the overall target thinning depth of the layered cutting process.

[0106] Specifically, the cutting beam intensity corresponding to the current layered cutting is determined by... This ratio reflects the current processing energy intensity relative to the initial state: a larger ratio (higher energy) indicates a more "aggressive" processing; a smaller ratio (lower energy) indicates a more "conservative" processing. In engineering, energy and beam current are strongly correlated processing parameters. High energy usually requires high beam current, but excessively high current can lead to overheating; low energy requires reduced beam current to maintain stability. This ratio allows beam current adjustment to follow the energy state. Simultaneously, the co-attenuation index f is used for shallow depths d. k Less than 0.3*D total At this time, the amplified energy's effect on beam regulation indicates the processing stage, allowing the beam to rapidly follow energy changes; high energy paired with a large beam for efficient material removal; when the depth d is shallow... k Greater than 0.3*D total When the energy is adjusted to regulate the beam current, it indicates that in the fine processing stage, the beam current regulation is more conservative to avoid overheating and damaging the chip due to high energy and high beam current.

[0107] Finally, temperature overload protection is achieved by multiplying the product with the temperature change rate T. In engineering, this is active temperature control using beam current regulation. That is, the higher the temperature and the more aggressive the energy, the more the beam current needs to be reduced to prevent the chip from deforming or burning due to overheating.

[0108] In this embodiment, the depth acoustic impedance coefficient Z is calculated by detecting the actual depth acoustic impedance value of the current layer and comparing it with the theoretical value. x And in combination with the energy attenuation coefficient ξ, the energy regulation coefficient max(ξ,Z) is determined. x Using this coefficient and the cumulative cutting depth d of each layer. k Total thinning depth D total The parameters, such as the ion beam energy E, are dynamically adjusted using the formula described above. k This allows the ion beam energy to be adapted to the characteristics of the chip material due to factors such as depth and material composition, avoiding over-etching or under-etching caused by inappropriate energy. This ensures the uniformity and precision of material removal during FinFET chip thinning, improving the surface quality and structural integrity of the thinned chip. Based on the temperature change rate T of the processing area, combined with the initial beam current intensity I0 and the beam current intensity I of the previous layer... x The beam intensity I is controlled by the above formula. kFurthermore, the synergistic attenuation index f allows for flexible adjustment of beam intensity based on processing progress and temperature conditions. This reduces the risk of chip damage due to excessive heat from an overly strong beam or reduced processing efficiency due to an underlying beam, ensuring a stable thermal environment and further guaranteeing chip quality. During chip layer-by-layer thinning, the material properties (such as acoustic impedance) and processing environment (such as temperature changes) differ at different depths. This solution dynamically adjusts the ion beam energy and beam intensity by real-time monitoring of parameters such as depth acoustic impedance and temperature, adapting to the layer-by-layer thinning requirements from roughing to progressively finer processing. Whether it's roughing with higher energy and beam intensity for the initial layer or finer processing with reduced energy and beam intensity for subsequent layers based on material and environmental changes, a coherent and adaptable processing flow can be achieved. This enhances the adaptability to the complex thinning process of FinFET chips, helping to obtain chip products that meet high-precision manufacturing requirements. Simultaneously, in this embodiment, multiple parameters such as depth acoustic impedance, temperature change rate, cumulative cutting depth, and total thinning depth collaboratively participate in the control of energy and beam intensity. Multi-parameter coordination can form a mutually constraining and compensating control mechanism, reducing the adverse effects of single parameter fluctuations on processing and making the processing more stable. For example, when abnormal depth acoustic impedance may lead to inappropriate energy changes, parameters such as the rate of temperature change can be adjusted by beam intensity to help correct the thermal environment and ensure continuous and stable processing. At the same time, due to the improved parameter adaptability, processing interruptions and repeated adjustments are reduced, which helps to improve overall processing efficiency while ensuring quality.

[0109] Existing technologies for chip thinning lack adaptability to varying material properties and processing environments at different depths. Their coarse control of ion beam energy and current intensity easily leads to problems such as uneven etching and thermal damage on the chip surface. This embodiment addresses this by finely controlling energy and current intensity through multiple parameters, including depth acoustic impedance coefficient and temperature change rate. This allows for more precise adaptation to the needs of each stage of chip thinning, significantly improving dimensional accuracy and surface quality after thinning, reducing the risk of damage to the internal chip structure, and ensuring high performance and reliability of FinFET chips. Furthermore, traditional technologies have limited ability to handle complex chip thinning scenarios, making it difficult to flexibly adjust processing parameters to adapt to different depths and processing conditions. This embodiment, based on real-time monitoring and dynamic multi-parameter control, can flexibly adapt to the FinFET chip thinning process from rough to fine processing, as well as the thinning of different batches and specifications of chips. This enhances processing adaptability and flexibility, expanding the application scope and scenarios of the technology. On the other hand, in existing technologies, unreasonable parameter control can easily cause processing fluctuations (such as excessive energy leading to a sudden temperature rise, or unstable beam current affecting the etching rate), thereby reducing processing stability and efficiency. The multi-parameter collaborative control mechanism in this embodiment can effectively mitigate the impact of fluctuations in a single parameter and ensure the stability of the processing. At the same time, due to the precise parameter adaptation, it reduces the waste of time and resources caused by processing anomalies, and achieves synergistic optimization of processing stability and efficiency, which is more in line with the needs of industrial-scale, high-quality production of FinFET chips.

[0110] In the final stage of processing, the target cross section is polished to further improve the flatness of the cross section and lay the foundation for subsequent high-resolution imaging. After the polishing process is completed, the key areas of the target cross section, such as the edges of the fin structure, are locally polished to further optimize the surface state of the FinFET chip and improve the resolution of the TEM image to below 0.2nm.

[0111] In this embodiment, rough processing is first performed with an accelerating voltage of 30kV and a beam current of 1-5nA. The ion beam energy is gradually reduced to 10kV by decreasing by 10% in each step, while the beam current intensity is simultaneously reduced to 50pA, thinning the target cross section to below 50nm. A spiral scanning path is used to ensure that the film thickness uniformity error is ≤5%. In the final processing stage, the process switches to a low-energy ion beam of 1-2kV and performs plasma polishing on the cross section at an angle of 10-15°. The surface roughness after polishing is ≤1nm.

[0112] In this embodiment, by identifying the marking machine's marker points and combining the mapping relationship between the marking machine coordinates and the FIB coordinate system, the position of the target FinFET region in the FIB coordinate system can be accurately calculated. Gradient scanning and ion image extraction further refine the positioning, ensuring the ion beam is precisely aligned with the target region. Depositing a protective film prevents damage to the FinFET chip during ion beam processing, extending the sample's lifespan. Gradually reducing ion beam energy and current intensity for rough processing ensures the uniformity of the FinFET chip film, avoiding sample damage and morphological changes caused by excessive processing speed. Polishing improves the flatness of the cross-section, and local polishing further optimizes the FinFET chip surface condition, laying the foundation for subsequent high-resolution imaging. Ultimately, high-quality TEM images with resolutions below 0.2 nm are achieved, improving the imaging quality and efficiency of FinFET structure analysis and enhancing the practicality and reliability of this technology.

[0113] In this embodiment, the TEM analysis determines the constituent materials of the FinFET structure, including: fin structure material: semiconductor material constituting the three-dimensional fin structure of the FinFET chip; multilayer film material: thin film material of each functional layer in the FinFET chip, such as gate oxide layer, gate material, insulating layer, conductive layer, etc. The composition and crystal structure of these multilayer films directly affect the electrical performance and reliability of the device.

[0114] Among them, the multilayer film material also includes: obtaining the diffraction pattern of the multilayer film material through selected area electron diffraction and high-resolution electron diffraction techniques, automatically identifying and calibrating the diffraction spots, classifying the material crystal form (single crystal, polycrystalline, amorphous) based on the constructed material classification and identification model, with an accuracy of ≥98%; and calculating the lattice constant and distortion parameters based on the position of the diffraction spots, analyzing the crystal quality and interface stress state of the gate material, and providing quantitative data for device reliability assessment.

[0115] In this embodiment, the TEM analysis further includes:

[0116] Multi-angle tilting images of the thin film sample were captured to obtain projection images at different angles. Based on the image sequence of the projection images at different angles, three-dimensional reconstruction was performed to construct a three-dimensional structure of the FinFET structure, which intuitively presents the three-dimensional morphological features of the fin structure.

[0117] Based on the FinFET structure, the key parameters such as fin height, fin width, and gate coverage length were measured in three dimensions with a measurement error of ≤2nm. Based on the measurement results, the three-dimensional characteristics of the fin structure, such as the sidewall steepness and gate oxide layer thickness uniformity, were analyzed.

[0118] By mapping the three-dimensional features of the fin structure to the cross-sectional images of the FIB fabrication process, a three-dimensional coordinate system for the FinFET structure is established. The influence of key parameters of different three-dimensional features on the electrical performance of the device is simulated, such as the suppression effect of fin spacing on short-channel effect, the correlation between fin height and source / drain capacitance, and the influence of gate cover length on threshold voltage. Quantitative correlation analysis of structure and performance is then performed.

[0119] In this embodiment, energy dispersive spectroscopy (EDS) is used to analyze the elemental composition and distribution in the multilayer film, which can determine the elemental composition and distribution of the multilayer film material. Electron diffraction (EDS) is used to analyze the diffraction pattern to confirm its crystal structure, such as single crystal, polycrystalline or amorphous state, thereby providing key data support for process optimization and failure analysis of FinFET devices. Through structure-performance correlation analysis, parameter adjustments in FinFET manufacturing can be directly guided, such as optimizing the fin etching process to improve the sidewall steepness. This upgrades TEM analysis from passive detection to an active process optimization tool, avoiding the limitations of traditional TEM analysis that only focuses on structural observation and lacks performance correlation.

[0120] In this embodiment, it also includes:

[0121] During sample pretreatment, FIB processing and TEM analysis, the FinFET chip status and analysis data are acquired in real time, and based on the real-time monitoring data, key parameters such as FIB beam intensity and TEM accelerating voltage are dynamically adjusted to optimize processing and detection conditions.

[0122] During the sample pretreatment stage, the surface roughness of the FinFET chip after the coating process is monitored in real time. When the roughness is greater than the preset roughness threshold > 2nm, an early warning is triggered, prompting the coating process to be repeated.

[0123] During the FIB processing stage, cross-sectional images are acquired in real time to determine whether ion beam-induced damage occurs in the fin structure, such as edge blurring caused by lattice distortion. Simultaneously, processing parameters such as ion beam energy and beam current intensity are acquired. If a pattern effect is detected on the cross-section, the ion beam energy and beam current intensity are reduced until the cross-sectional flatness meets the standard.

[0124] During the TEM analysis stage, it is determined whether the FinFET chip has been irradiated and damaged. At the same time, the stability of elemental signals in the energy dispersive spectroscopy analysis is monitored. The accelerating voltage is adjusted according to the thickness of the thin film sample, and the focal length shift caused by the uneven thickness of the thin film sample is corrected in real time.

[0125] In this embodiment, by dynamically optimizing the parameters, an energy reduction gradient threshold is set in the roughing and finishing stages of FIB processing, which effectively reduces the damage to the FinFET chip during processing and detection, improves the accuracy and reliability of the analysis results, and ensures image quality while reducing electron beam damage, thus ensuring the effectiveness and stability of the entire analysis method.

[0126] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A method for FinFET structure slicing analysis based on FIB and TEM, characterized in that, include: Sample pretreatment: The FinFET chip is coated with adhesive, and the uneven surface of the FinFET chip is potted with adhesive. At the same time, the target area is calibrated using a marking machine. FIB processing: The pre-processed FinFET chip is placed in the FIB device, and the FinFET chip is initially positioned based on the range calibration results of the target area to determine the target FinFET area. The target cross section is then cut and thinned to prepare a thin film sample for TEM analysis. TEM analysis: The prepared thin film sample was placed in a TEM to obtain a high-resolution image of the FinFET structure. The boundaries and morphology of the fin structure and its multilayer films were analyzed. Based on the analysis results, the structural features of the FinFET were extracted, the elemental distribution map inside the FinFET was drawn, and the constituent materials of the FinFET structure were determined. The FIB processing involves cutting and thinning the target cross-section, specifically including: A protective film is deposited on the surface of the designated target area to construct a processing protection barrier; A low-energy ion beam is used to perform rough processing by gradually reducing the ion beam energy and beam current intensity, and the target cross section is cut in layers to gradually thin the FinFET chip; In the final stage of processing, the target cross section is polished. After the polishing is completed, the key areas of the target cross section are locally polished. A low-energy ion beam is used for roughing by progressively reducing the ion beam energy and beam current intensity. The target cross-section is then cut in layers to gradually thin the FinFET chip. Specifically, this includes: Load the FinFET chip material property library to obtain the initial cutting energy E0 and the minimum allowable polishing energy E. min And the total number of layers N to be cut; wherein, the initial cutting energy E0 is used to cut the first layer; Based on the initial cutting energy E0 and the minimum permissible polishing energy E min And set the energy attenuation coefficient ξ=ln(E0 / E) to the total number of layers N to be cut. min ) / N 1.5 ; Configure a piezoelectric sensor to collect the current depth acoustic impedance of the material corresponding to the target cross section in real time, and determine the rate of change Z of the acoustic impedance of the material corresponding to the current target cross section by real-time monitoring of the depth acoustic impedance. An infrared thermal imager is configured, and the temperature of the processing area during the current target section cutting process is monitored in real time using an infrared camera; The rate of temperature change T of the processing area during the processing process is obtained based on the real-time monitoring of the processing area temperature. The ion beam energy and beam intensity during the cutting process of each layer are set according to the acoustic impedance change rate Z of the target cross section corresponding to the starting time of each layer cutting and the temperature change rate T of the processing area. Based on the acoustic impedance change rate Z of the target cross-section corresponding to the start time of each layer cutting and the temperature change rate T of the processing area, the ion beam energy and beam current intensity during the cutting process of each layer are set, specifically including: Detect the current depth acoustic impedance value of the material corresponding to the target cross section of the current layer; Retrieve the theoretical depth acoustic impedance value corresponding to the current layer's depth; The depth acoustic impedance coefficient Z is obtained by using the current depth acoustic impedance value of the material corresponding to the target cross section of the current layer and the theoretical depth acoustic impedance value corresponding to the depth of the current layer. x =(Z s -Z t ) / Z t Among them, Z s Z represents the current depth acoustic impedance value; t This represents the theoretical depth acoustic impedance value; Obtain the energy attenuation coefficient ξ; The energy attenuation coefficient ξ and the depth acoustic impedance coefficient Z are compared. x The energy attenuation coefficient ξ is compared with the depth acoustic impedance coefficient Z. x The larger of the median values ​​is taken as the energy regulation coefficient max(ξ, Z). x ); Determine the initial cutting energy E0; The ion beam energy for each layer cutting process is set by combining the energy adjustment coefficient with the acoustic impedance change rate Z corresponding to the current layer cutting start time. The cutting ion beam energy corresponding to the current layer cutting is obtained by the following formula: Among them, E k E represents the cutting ion beam energy corresponding to the current layer cutting; x This represents the cutting ion beam energy corresponding to the layer-by-layer cutting, when E x When E = 0, then let min(E) x E0) = E0; max(ξ, Z) x ) represents the energy regulation coefficient; d k D represents the cumulative cutting depth corresponding to the completion of the previous layer's layered cutting; total This represents the total target thinning depth for the layered cutting; π is taken as 3.

14. Retrieve the cutting energy E corresponding to the previous layer when performing layered cutting. x ; Using the cutting energy E x The cutting beam intensity corresponding to the current layer cutting is set by combining the ratio of the initial cutting energy E0 with the temperature change rate T of the processing area and the initial beam intensity I0; wherein, the initial beam intensity I0 is used to cut the first layer; Meanwhile, the cutting beam intensity corresponding to the current layer cutting is obtained by the following formula: Among them, I k I0 represents the cutting beam intensity corresponding to the current layer cutting; I0 represents the initial beam intensity; I0 represents the cutting beam intensity. x This represents the cutting beam intensity corresponding to the layered cutting of the previous layer. When I x When I = 0, then let min(I) x I0) = I0; T represents the temperature change rate of the processing area; f represents the synergistic decay index, which is obtained by the following formula: Where f represents the co-decay exponent; d k D represents the cumulative cutting depth corresponding to the completion of the previous layer's layered cutting; total This indicates the overall target thinning depth of the layered cutting process.

2. The FinFET structure slice analysis method based on FIB and TEM as described in claim 1, characterized in that, The sample pretreatment also includes: For FinFET chips that are highly sensitive to fin structures, PI conductive adhesive is used to coat the surface of the FinFET chip. After coating, a low-temperature curing process is performed to form a smooth conductive layer. Before the slicing operation, a low-energy ion cleaning process is used on the surface of the FinFET chip. The surface of the FinFET chip is cleaned by an inert gas ion beam at an inclined angle to remove contaminants and oxide layers.

3. The FinFET structure slice analysis method based on FIB and TEM as described in claim 2, characterized in that, The use of a marking machine to define the range of a target area also includes: Scanning electron microscopes were used to verify the marked points of the FinFET chip after range calibration, and the positional relationship between the marked points and the actual FinFET structure was compared. The offset between the center of the marked points and the key features of the actual FinFET structure was calculated. If the offset between the marker point and the actual FinFET structure exceeds a preset threshold, the positioning fails, and the range is recalibrated to adjust the coordinates of the marker point selection position. If the offset is within the preset threshold range, the actual coordinate deviation between the marker point and the actual FinFET structure is recorded. Based on the actual coordinate deviation between the marked point and the actual FinFET structure, a mapping relationship between the marking machine coordinates and the FIB coordinate system is established in the FIB device.

4. The FinFET structure slice analysis method based on FIB and TEM as described in claim 3, characterized in that, The FIB processing, which determines the target FinFET region, specifically includes: The pre-processed FinFET chip is fixed on the sample stage of the FIB equipment, the marking machine marks are identified, and the target position of the target FinFET region in the FIB coordinate system is calculated by combining the mapping relationship between the marking machine coordinates and the FIB coordinate system. A grid scan is performed on the target location to obtain an ion image of the target location. The actual position of the marker point in the ion image is extracted, and the deviation parameter between the actual position of the marker point and the FIB coordinate system is calculated. The position of the marker point and the mapped coordinates are calibrated to determine the target FinFET region.

5. The FinFET structure slice analysis method based on FIB and TEM as described in claim 1, characterized in that, The TEM analysis determined the constituent materials of the FinFET structure, including: fin structure material: semiconductor material constituting the three-dimensional fin structure of the FinFET chip; multilayer film material: thin film material of each functional layer in the FinFET chip; Among them, the multilayer film material also includes: obtaining the diffraction pattern of the multilayer film material, automatically identifying and calibrating the diffraction spots, classifying the material crystal form based on the constructed material classification and identification model, calculating the lattice constant and distortion parameters based on the position of the diffraction spots, and analyzing the crystal quality and interface stress state of the gate material.

6. The FinFET structure slice analysis method based on FIB and TEM as described in claim 1, characterized in that, The TEM analysis also includes: The thin film sample was photographed from multiple angles to obtain projection images from different angles. Based on the image sequence of the projection images from different angles, a three-dimensional reconstruction was performed to construct a three-dimensional structure of the FinFET structure. Three-dimensional measurements of key parameters of a three-dimensional structure based on FinFET structure are performed, and the three-dimensional features of the fin structure are analyzed based on the measurement results. By mapping the three-dimensional features of the fin structure to the cross-sectional images of the FIB fabrication process, a three-dimensional coordinate system for the FinFET structure is established. The influence of key parameters of different three-dimensional features on the electrical performance of the device is simulated, and a quantitative correlation analysis of structure and performance is carried out.

7. The FinFET structure slice analysis method based on FIB and TEM as described in claim 1, characterized in that, Also includes: During sample pretreatment, FIB processing and TEM analysis, the FinFET chip status and analysis data are acquired in real time, and key parameters are dynamically adjusted based on the real-time monitoring data. The surface roughness of the FinFET chip after coating is monitored in real time during the sample pretreatment stage. When the roughness exceeds the preset roughness threshold, an early warning is triggered, prompting the coating process to be repeated. During the FIB processing stage, cross-sectional images are acquired in real time to determine whether ion beam-induced damage occurs in the fin structure. Simultaneously, processing parameters such as ion beam energy and beam current intensity are acquired. If a pattern effect is detected on the cross-section, the ion beam energy and beam current intensity are reduced until the cross-sectional flatness meets the standard. During the TEM analysis stage, it is determined whether the FinFET chip has been irradiated and damaged. At the same time, the stability of elemental signals in the energy dispersive spectroscopy analysis is monitored. The accelerating voltage is adjusted according to the thickness of the thin film sample, and the focal length shift caused by the uneven thickness of the thin film sample is corrected in real time.

Images