Array substrate and display device

Abstract

An array substrate and a display device. The array substrate includes a base substrate, and gate lines, a metal layer, pixel electrodes, and thin-film transistors located on the base substrate. The metal layer includes a data line, a first connection portion, and a first electrode and a second electrode of the thin-film transistor, wherein the first electrode is electrically connected to the pixel electrode via the first connection portion. The gate line includes a gate line pad, which includes a protrusion protruding into the pixel region relative to a position on the gate line other than the gate line pad. The metal layer located in the pixel region includes multiple routing segments extending along at least a portion of the outline of the pixel region; the multiple routing segments include multiple first routing segments surrounding the protrusion, the multiple first routing segments being connected end to end to form a stepped structure, and the ratio of the orthographic projection area of the first connection portions on the base substrate in different pixel regions is 0.8 to 1.2. Providing the first routing segments surrounding the protrusion of the gate line pad with a stepped structure is beneficial for improving the consistency of the capacitance generated by the metal layer and the pixel electrode in different pixel regions.

Description

[0001] This application is a divisional application of Chinese patent application No. 202210148521.6 filed on February 18, 2022, with the invention name of "Array substrate and display device". Technical Field

[0002] At least one embodiment of the present disclosure relates to an array substrate and a display device. Background Art

[0003] Currently, liquid crystal display devices including thin film transistors are widely used, and more and more liquid crystal display devices are developing towards wide viewing angles and high image quality to provide users with better usage experience. Summary of the Invention

[0004] Embodiments of the present disclosure provide an array substrate and a display device.

[0005] At least one embodiment of the present disclosure provides an array substrate, comprising: a base substrate; a plurality of gate lines located on the base substrate; a metal layer located on a side of the plurality of gate lines away from the base substrate, the metal layer comprising a plurality of data lines, the plurality of data lines extending along a first direction and arranged along a second direction, the plurality of gate lines extending along the second direction and arranged along the first direction, the first direction and the second direction intersecting, the plurality of data lines intersecting with the plurality of gate lines to define a plurality of pixel regions. At least one gate line comprises a gate line pad, the gate line pad comprising a protrusion protruding into the pixel region relative to a position on the gate line other than the gate line pad, the metal layer located in the pixel region comprising a plurality of routing segments extending along at least a portion of the outline of the pixel region; the plurality of routing segments comprising a plurality of first routing segments surrounding at least a portion of the edge of the protrusion, each first routing segment extending along the first direction or the second direction, the plurality of first routing segments being connected end to end to form a step structure. The array substrate also includes a pixel electrode and a thin film transistor, wherein the thin film transistor includes a first electrode, a gate electrode and a second electrode, the first electrode and the second electrode both overlap with the film layer where the gate line is located, the first electrode is electrically connected to the pixel electrode through a first connecting portion, and the second electrode is electrically connected to the data line; the first electrode, the second electrode and the first connecting portion are all structures in the metal layer; the multiple pixel areas include at least one first pixel area and at least one second pixel area, the first pixel area is a pixel area corresponding to the gate line pad, and the second pixel area is a pixel area corresponding to a position on the gate line other than the gate line pad; the first connecting portion includes at least part of the multiple sections of the first routing lines, and the ratio of the area of the orthographic projection of the first connecting portion in the first pixel area on the substrate to the area of the orthographic projection of the first connecting portion in the second pixel area on the substrate is 0.8 to 1.2.

[0006] For example, according to an embodiment of the present disclosure, along a direction perpendicular to the base substrate, the first connection portion overlaps with the pixel electrode.

[0007] For example, according to an embodiment of the present disclosure, the metal layer also includes a common electrode located in the pixel area; along a direction perpendicular to the base substrate, the common electrode overlaps with the pixel electrode, and the first electrode and the second electrode of the thin film transistor are both insulated from the common electrode.

[0008] For example, according to an embodiment of the present disclosure, the common electrode includes at least a portion of the plurality of first wiring segments.

[0009] For example, according to an embodiment of the present disclosure, the ratio of the length of the common electrode in the first pixel region to the length of the common electrode in the second pixel region is 0.8 to 1.2.

[0010] For example, according to an embodiment of the present disclosure, the ratio of the length of the first connection portion in the first pixel region to the length of the first connection portion in the second pixel region is 0.8 to 1.2.

[0011] For example, according to an embodiment of the present disclosure, the edge of the protrusion includes an edge of the protrusion whose extension direction is not parallel to the first direction and the second direction, the number of the multiple first traces is greater than or equal to 2, and the length of each first trace is L i The orthographic projection of each first trace on the substrate is a first orthographic projection, and the orthographic projection of the edge of the protrusion on the substrate is a second orthographic projection. The first orthographic projection includes a long side extending along its extension direction and close to the second orthographic projection. The minimum distance between the long side and the second orthographic projection is d i , the angle between the long side and the second orthographic projection is θ i , a first parameter C in the capacitance between the first trace and the edge of the protrusion pad satisfy N is the number of the multiple first routing segments, i is a positive integer not less than 1, and N is a positive integer not less than 2.

[0012] For example, according to an embodiment of the present disclosure, the first parameter C pad Satisfy 0.035≤C pad ≤5.

[0013] For example, according to an embodiment of the present disclosure, the multiple routing segments in the second pixel region include a second routing segment parallel to the second direction, and the edge of the gate line closest to the second routing segment, which is close to the second routing segment, is an inclined edge that is not parallel to the second direction; and the minimum distance between the orthographic projection of the second routing segment on the substrate and the orthographic projection of the inclined edge on the substrate is d. h , the length of the second trace is L h The angle between the orthographic projection of the second line on the substrate and the orthographic projection of the inclined edge on the substrate is θ h , a second parameter C of the capacitance between the second trace and the inclined edge tft Satisfy C tft =ln[(L h / d h )×sinθ h +1].

[0014] For example, according to an embodiment of the present disclosure, the second parameter C tft Satisfy 0.01≤C tft ≤2.5.

[0015] For example, according to an embodiment of the present disclosure, the ratio of the first parameter to the second parameter satisfies 1≤C pad / C tft ≤7.

[0016] For example, according to an embodiment of the present disclosure, each of the multiple routing segments extends along the first direction or the second direction.

[0017] For example, according to an embodiment of the present disclosure, in a direction perpendicular to the base substrate, the gate line pad is configured to be disposed opposite to the support portion.

[0018] For example, according to an embodiment of the present disclosure, the first connection portion extends along the first direction to be electrically connected to the pixel electrode.

[0019] For example, according to an embodiment of the present disclosure, the gate line pad includes the gate.

[0020] For example, according to an embodiment of the present disclosure, the plurality of first trace segments include two parts, one of the two parts is the common electrode, and the other of the two parts is the first connecting portion.

[0021] For example, according to an embodiment of the present disclosure, the two gate lines located on both sides of at least one first pixel area include the gate line pad protruding into the first pixel area, the common electrode includes the first routing surrounding the protruding portion of the gate line pad on one of the two gate lines, and the first connecting portion includes the first routing surrounding the protruding portion of the gate line pad on the other of the two gate lines.

[0022] For example, according to an embodiment of the present disclosure, the gate is located at a position on the gate line other than the gate line pad.

[0023] For example, according to an embodiment of the present disclosure, the first connecting portion includes a sub-portion extending along the first direction and a sub-portion extending along the second direction.

[0024] For example, according to an embodiment of the present disclosure, the array substrate further includes: a common electrode line, which is provided in the same layer as the plurality of gate lines, and the common electrode is electrically connected to the common electrode line.

[0025] For example, according to an embodiment of the present disclosure, the common electrode line extends along the second direction, and along a direction perpendicular to the base substrate, the first connection portion overlaps the common electrode line.

[0026] For example, according to an embodiment of the present disclosure, an insulating layer is provided between the pixel electrode and the metal layer, the first connecting portion is electrically connected to the pixel electrode through a via in the insulating layer, and a straight line parallel to the first direction passes through the via and the gate line pad's positive projection on the base substrate.

[0027] For example, according to an embodiment of the present disclosure, the edge of the protrusion includes a broken line or a curved line.

[0028] For example, according to an embodiment of the present disclosure, the first connecting portion and the first electrode of the thin film transistor are integrated into one structure.

[0029] Another embodiment of the present disclosure provides a display device, comprising the array substrate provided by any of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0031] Figure 1 A schematic diagram of a partial planar structure of an array substrate provided according to an example of an embodiment of the present disclosure;

[0032] Figure 2 for Figure 1A schematic diagram of a partial planar structure of pixel electrodes provided on an array substrate is shown;

[0033] Figure 3 For the Figure 2 A cross-sectional view of the metal layer, the insulating layer, and the pixel electrode taken along line AA' is shown;

[0034] Figure 4 for Figure 1 A schematic diagram of another pixel area on the array substrate shown;

[0035] Figure 5 for Figure 1 A schematic diagram of a portion of the protrusion and a first trace located at an edge of the portion of the protrusion;

[0036] Figure 6 A schematic diagram of a partial planar structure of an array substrate provided according to another example of implementation of the present disclosure;

[0037] Figure 7 for Figure 6 A schematic diagram of another pixel area on the array substrate shown;

[0038] Figure 8A A schematic diagram of a partial planar structure of an array substrate provided according to another example of implementation of the present disclosure;

[0039] Figure 8B A schematic diagram of a partial planar structure of an array substrate provided according to another example of implementation of the present disclosure;

[0040] Figure 9 A schematic diagram of a partial planar structure of an array substrate provided according to another example of implementation of the present disclosure;

[0041] Figure 10 A schematic diagram of a partial planar structure of an array substrate provided according to another example of implementation of the present disclosure;

[0042] Figure 11 A schematic diagram of a partial planar structure of an array substrate provided according to another example of implementation of the present disclosure;

[0043] Figure 12 A schematic diagram of a partial planar structure of an array substrate provided according to another example of implementation of the present disclosure;

[0044] Figure 13 A schematic diagram of a partial planar structure of an array substrate provided according to another example of implementation of the present disclosure;

[0045] Figure 14 A schematic diagram of a partial planar structure of an array substrate provided according to another example of implementation of the present disclosure;

[0046] Figure 15A schematic diagram of a partial planar structure of an array substrate provided according to another example of implementation of the present disclosure;

[0047] Figure 16 A schematic diagram of a partial planar structure of an array substrate provided according to another example of implementation of the present disclosure;

[0048] Figure 17 A schematic diagram of a partial planar structure of an array substrate provided in another embodiment of the present disclosure;

[0049] Figure 18 A schematic diagram of a partial planar structure of an array substrate provided in another embodiment of the present disclosure.

[0050] Figure markings: 01-support part; 010-first pixel area; 020-second pixel area; 10-pixel area; 11-via; 12-via; 13-insulating layer; 30-routing; 31-first routing; 32-second routing; 33-routing sub-part; 100-substrate substrate; 200-gate line; 201-hollow pattern; 210-gate line pad; 211-protrusion; 2110-protrusion edge; 300-metal layer; 310-data line; 320-common electrode; 321-first sub-common electrode; 322-second sub-common electrode; 323-third sub-common electrode; 324-fourth sub-common electrode; 330-first connecting part; 340-second connecting part; 400-pixel electrode; 500-thin film transistor; 510-first pole; 520-second pole; 530-gate; 600-common electrode line. DETAILED DESCRIPTION

[0051] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0052] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are simply used to distinguish different components. The words "include" or "comprising" and similar terms mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0053] The embodiments of the present disclosure provide an array substrate and a display device. The array substrate includes a base substrate, and a plurality of gate lines and a metal layer located on the base substrate. The metal layer is located on a side of the plurality of gate lines away from the base substrate, and the metal layer includes a plurality of data lines, the plurality of data lines extending along a first direction and arranged along a second direction, the plurality of gate lines extending along a second direction and arranged along the first direction, the first direction and the second direction intersect, and the plurality of data lines intersect with the plurality of gate lines to define a plurality of pixel areas. At least one gate line includes a gate line pad, the gate line pad includes a protrusion protruding into the pixel area relative to a position on the gate line other than the gate line pad, the metal layer located in the pixel area includes a plurality of routing segments extending along at least a portion of the outline of the pixel area; the plurality of routing segments include a plurality of first routing segments surrounding at least a portion of the edge of the protrusion, each first routing segment extending along the first direction or the second direction, and the plurality of first routing segments are connected end to end to form a step structure. The array substrate also includes a pixel electrode and a thin film transistor, wherein the thin film transistor includes a first electrode, a gate electrode and a second electrode, the first electrode and the second electrode both overlap with the film layer where the gate line is located, the first electrode is electrically connected to the pixel electrode through a first connecting portion, and the second electrode is electrically connected to the data line; the first electrode, the second electrode and the first connecting portion are all structures in the metal layer; the multiple pixel areas include at least one first pixel area and at least one second pixel area, the first pixel area is a pixel area corresponding to the gate line pad, and the second pixel area is a pixel area corresponding to the position on the gate line other than the gate line pad; the first connecting portion includes at least part of the routing of multiple sections of first wiring, and the ratio of the area of the orthographic projection of the first connecting portion in the first pixel area on the substrate to the area of the orthographic projection of the first connecting portion in the second pixel area on the substrate is 0.8 to 1.2. In the embodiment of the present disclosure, the first routing line surrounding the protruding portion of the gate line pad is set to a step structure, and the ratio of the orthographic projection area of the first connecting portion in the first pixel area and the second pixel area on the substrate is 0.8 to 1.2. This is beneficial for improving the consistency of the capacitance generated by the metal layer and the pixel electrode in different pixel areas while reducing the influence of the metal layer on the aperture ratio in the pixel area.

[0054] The array substrate and the display device provided by the embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0055] Figure 1 FIG. 1 is a schematic diagram of a partial planar structure of an array substrate provided according to an example of an embodiment of the present disclosure. Figure 1 As shown, the array substrate includes a base substrate 100, and a plurality of gate lines 200 and a metal layer 300 located on the base substrate 100. The metal layer 300 is located on a side of the plurality of gate lines 200 away from the base substrate 100. The metal layer 300 includes a plurality of data lines 310. The plurality of data lines 310 extend along a first direction and are arranged along a second direction. The plurality of gate lines 200 extend along the second direction and are arranged along the first direction. The first direction and the second direction intersect. The plurality of data lines 310 intersect with the plurality of gate lines 200 to define a plurality of pixel areas 10. Figure 1 A pixel area 10 is schematically shown.

[0056] For example, Figure 1 As shown, a plurality of data lines 310 extend along the X direction and are arranged along the Y direction; a plurality of gate lines 200 extend along the Y direction and are arranged along the X direction. Figure 1 In the schematic diagram, the first direction is the X direction, the second direction is the Y direction, and the first direction is perpendicular to the second direction. However, the present invention is not limited thereto. The first direction and the second direction may not be perpendicular to each other. For example, the angle between the first direction and the second direction may be 30 to 60 degrees. For example, the first direction and the second direction may be interchangeable.

[0057] For example, Figure 1 The schematic diagram shows that the planar shape of each data line 310 (e.g., the planar shape parallel to the XY plane) is a straight strip extending along the first direction, but the present invention is not limited thereto. The planar shape of the data line 310 may also be a non-linear strip with the overall extension direction along the first direction, such as a broken line. For example, Figure 1 The schematic diagram shows that the planar shape of each data line 310 is a straight strip with uniform width at all locations, but is not limited to this. The planar shape of the data line 310 can also be a strip with uneven widths. The specific shape of the data line can be set according to product requirements. For example, the overall extension direction of each gate line 200 is the second direction. For example, the planar shape of the gate line 200 can be a strip with uneven widths, but is not limited to this. The specific shape of the gate line can be set according to product requirements.

[0058] For example, Figure 1 As shown, two adjacent data lines 310 and two adjacent gate lines 200 are arranged to cross to define a pixel area 10. For example, a pixel area 10 is a sub-pixel. For example, the array substrate includes a plurality of sub-pixels (a plurality of pixel areas 10), and the plurality of sub-pixels include sub-pixels configured to display different colors of light. For example, the plurality of sub-pixels may include a red sub-pixel configured to display red light, a green sub-pixel configured to display green light, and a blue sub-pixel configured to display blue light. For example, two adjacent sub-pixels arranged in at least one of the first direction and the second direction are respectively sub-pixels configured to display different colors of light.

[0059] For example, the shape of the pixel area 10 can be a polygon. For example, the shape of the pixel area 10 can be a quadrilateral. For example, the shape of the pixel area 10 can be a rectangle. The present disclosure does not limit this. The shape of the pixel area 10 is related to the shape of the edge of the data line 310 and the edge of the gate line 200.

[0060] For example, each pixel region 10 includes a display area for display, and the area of the display area may be smaller than that of the pixel region 10. For example, the shape of the display area may be the same as that of the pixel region 10, or the shape of the display area may be different from that of the pixel region 10.

[0061] For example, Figure 1 As shown, the metal layer 300 further includes a common electrode 320 located in the pixel area 10. For example, the common electrode 320 can be a film layer provided in the same layer and made of the same material as the data line 310. Of course, the embodiments of the present disclosure are not limited thereto, and the common electrode can also be provided in a different layer from the metal layer.

[0062] like Figure 1 As shown, at least one gate line 200 includes a gate line pad 210 , and the gate line pad 210 includes a protrusion 211 protruding into the pixel area 10 relative to a position on the gate line 200 except the gate line pad 210 .

[0063] For example, Figure 1 As shown, the gate line pad 210 is a portion of the gate line 200. For example, along the X direction, the width of the gate line pad 210 is greater than the width of the gate line 200 other than the gate line pad 210. For example, in the width direction, the portion of the gate line pad 210 that protrudes relative to the portion of the gate line 200 other than the gate line pad 210 is a protrusion 211.

[0064] For example, Figure 1 As shown, the gate line pad 210 may include a protrusion 211 protruding relative to one side of the gate line 200. For example, a plurality of gate line pads 210 may be provided on one gate line 200, each of the plurality of gate line pads 210 including a protrusion 211 protruding toward the same side of the gate line 200.

[0065] For example, the pixel region 10 does not include the protrusion 211 .

[0066] For example, Figure 1 As shown, the gate line pad 210 is configured to be arranged opposite to the support portion 01. For example, in a direction perpendicular to the base substrate 100, the gate line pad 210 overlaps with the support portion 01. For example, the orthographic projection of the gate line pad 210 on the base substrate 100 can overlap with the orthographic projection of the support portion 01 on the base substrate 100. For example, the orthographic projection of the support portion 01 on the base substrate 100 can completely fall within the orthographic projection of the gate line pad 210 on the base substrate 100. For example, Figure 1 The support portion 01 is schematically shown as having a circular shape in a plane parallel to the XY plane, but is not limited thereto and may also be a regular shape such as a polygon, or an irregular shape.

[0067] The above-mentioned “direction perpendicular to the base substrate 100 ” refers to a direction perpendicular to a main surface of the base substrate 100 for arranging structures such as gate lines, such as a direction perpendicular to an XY plane.

[0068] For example, the array substrate may be an array substrate in a liquid crystal display panel, and the liquid crystal display panel further includes an opposing substrate, a liquid crystal layer located between the array substrate and the opposing substrate, and a frame sealant that encapsulates the liquid crystal layer. For example, the opposing substrate may be a color filter substrate. For example, the support portion 01 (also referred to as a spacer) is located in the liquid crystal layer between the array substrate and the opposing substrate to maintain the uniformity of the thickness of the display panel. For example, the support portion 01 may be a photosensitive spacer, that is, a spacer with high positional accuracy is formed by photolithography using a photosensitive composition, and the support portion 01 includes a resin, a polymerizable compound, a photopolymerization initiator, etc., but the embodiments of the present disclosure are not limited thereto.

[0069] For example, the liquid crystal display panel further includes a first polarizing layer disposed on a side of the array substrate away from the opposing substrate and a second polarizing layer disposed on a side of the opposing substrate away from the array substrate. For example, a backlight source may be disposed on the non-display side of the display panel, the backlight source being configured to provide backlight to the display panel.

[0070] For example, the array substrate includes a support portion 01, which overlaps the gate line pad 210 in a direction perpendicular to the base substrate 100. However, the support portion may be provided on the opposing substrate, and its position may be set according to product requirements.

[0071] For example, the position of the gate line pad 210 can be set according to the position of the support part 01. For example, the number of the support parts 01 is K, the number of the gate line pad 210 is also K, and the support parts 01 and the gate line pads 210 are arranged in a one-to-one correspondence.

[0072] like Figure 1 As shown, the metal layer 300 located in the pixel area 10 includes a plurality of routing segments 30 extending along at least a portion of the outline of the pixel area 10. For example, at least some of the routing segments 30 are electrically connected routing segments. For example, the electrically connected routing segments 30 are integrated routing segments. The "integrated routing segments" may refer to routing segments formed by performing the same patterning process on the same metal material layer. The "multiple routing segments 30 extending along at least a portion of the outline of the pixel area 10" may refer to the plurality of routing segments extending along the edge of the data line 310 and the edge of the gate line 200. The plurality of routing segments extending along at least a portion of the outline of the pixel area may be parallel to the edge extension direction of the data line or the gate line, but is not limited thereto. Part of the routing segments may also be non-parallel to a portion of the edge of the gate line or the data line. Whether the routing segments are parallel to the edge of the signal line (including the gate line and the data line) adjacent thereto (in a plan view) may be set according to product requirements.

[0073] For example, Figure 1 As shown, the edge of the protrusion 211 of the gate line pad 210 includes a fold line or a curve.

[0074] like Figure 1 As shown, the multiple traces 30 include multiple first traces 31 surrounding at least a portion of the edge of the protrusion 211. Each first trace 31 extends in the first direction or the second direction, and the multiple first traces 31 are connected end to end to form a stepped structure. The "multiple first traces 31 surrounding at least a portion of the edge of the protrusion 211" mentioned above may refer to the orthographic projections of the multiple first traces 31 on the substrate 100 surrounding at least a portion of the edge of the protrusion 211.

[0075] The embodiment of the present disclosure provides a step structure for the first routing line surrounding the protruding portion of the gate line pad, which helps to improve the consistency of the capacitance generated by the metal layer and the pixel electrode in different pixel areas while reducing the impact of the metal layer on the aperture ratio in the pixel area.

[0076] For example, two first traces 31 connected end to end among the multiple first traces 31 are electrically connected. For example, the multiple first traces 31 can be an integrated structure. For example, the distance between the orthographic projection of the multiple first traces 31 on the base substrate 100 and the orthographic projection of the edge of the protrusion 211 it surrounds on the base substrate is smaller than the distance between the orthographic projection of other traces on the base substrate 100 and the edge of the protrusion 211. For example, the distances between different first traces 31 and the edges of the protrusion 211 they surround can be the same or different. For example, the extension direction of the first trace 31 can be parallel to the edge of the protrusion 211 it surrounds; the extension direction of the first trace 31 can also intersect with the edge of the protrusion 211 it surrounds.

[0077] For example, Figure 1 As shown, the extension direction of the routing lines 30 other than the first routing line 31 in the multi-segment routing line 30 can be parallel to the extension direction of the adjacent data line 310 or gate line 200. For example, the extension direction of the routing lines 30 other than the first routing line 31 in the multi-segment routing line 30 can be parallel to the extension direction of the adjacent data line 310 or gate line 200 near the edge of the routing line 30.

[0078] For example, Figure 1As shown, the two segments of the first trace 31 located at the outermost ends of the plurality of segments of the first trace 31 can extend along the second direction. For example, the two segments of the first trace 31 located at the outermost ends of the plurality of segments of the first trace 31 can both be electrically connected to the first trace 31. For example, the two segments of the first trace 31 located at the outermost ends of the plurality of segments of the first trace 31 can both be integrated with the first trace 31. However, this is not limiting. One of the two segments of the first trace 31 located at the outermost ends of the plurality of segments of the first trace can also be spaced apart from the first trace.

[0079] For example, Figure 1 As shown, any one of the multiple routing segments 31 can extend along the first direction or along the second direction.

[0080] For example, Figure 1 As shown, the protrusion 211 may be in the shape of a trapezoid, the upper base of the trapezoid protruding into the pixel area 10 relative to the rest of the gate line 200 , and the lower base of the trapezoid flush with at least part of the edge of the rest of the gate line 200 .

[0081] For example, Figure 1 As shown, the gate line 200 is provided with a protrusion 211 only on one side, and the edge of the other side of the gate line 200 at the position opposite to the protrusion 211 extends along the Y direction. At this time, the multiple segments of the first routing lines 31 in the multiple segments of routing lines 30 in each pixel area are concentrated in one place in the multiple segments of routing lines 30 to surround a protrusion 211.

[0082] In the array substrate provided by the embodiment of the present disclosure, regardless of whether the edge of the protrusion is parallel to the first direction and the second direction, the influence of multiple routing segments on the aperture ratio of the pixel area can be minimized by setting the first routing line surrounding the edge of the protrusion to extend along the first direction or along the second direction.

[0083] Figure 2 for Figure 1 The schematic diagram of the local planar structure of the pixel electrodes arranged on the array substrate is shown in FIG. Figure 1 and Figure 2 As shown, the array substrate further includes a plurality of pixel electrodes 400 and a plurality of thin film transistors 500. For example, in a direction perpendicular to the base substrate 100, the pixel electrodes 400 overlap with the metal layer 300. For example, each pixel region 10 includes a pixel electrode 400. The pixel electrode 400 included in each pixel region 10 can be a single electrode, but is not limited thereto. The pixel electrodes included in each pixel region can also be a plurality of strip-shaped structures. For example, the pixel electrode 400 can be made of a transparent conductive material, and the pixel electrode 400 covers the light-emitting area of the pixel region 10.

[0084] For example, Figure 1As shown, the embodiment of the present disclosure schematically shows that the pixel electrode 400 is located on the side of the metal layer 300 away from the base substrate 100, but is not limited to this. The pixel electrode can be located between the metal layer and the base substrate, and the positions of the pixel electrode and the metal layer can be set according to product requirements.

[0085] For example, Figure 1 and Figure 2 As shown, each pixel region 10 may include a thin film transistor 500, but is not limited thereto. The number of thin film transistors included in each pixel region may be set according to the performance of the required pixel circuit. For example, the number of thin film transistors in each pixel region may be two or more.

[0086] For example, Figure 1 and Figure 2 As shown, each thin film transistor 500 includes a first electrode 510, a gate electrode 530, and a second electrode 520. The first electrode 510 and the second electrode 520 overlap with the film layer where the gate line 200 is located. For example, the thin film transistor 500 also includes an active layer, the first electrode 510 and the second electrode 520 overlap with the active layer, and the gate electrode 530 overlaps with the active layer.

[0087] For example, Figure 1 and Figure 2 As shown, the first electrode 510 of the thin film transistor 500 is electrically connected to the pixel electrode 400 through the first connecting portion 330 , and the second electrode 520 of the thin film transistor 500 is electrically connected to the data line 310 .

[0088] Figure 3 For the Figure 2 The cross-sectional view of the metal layer, the insulating layer and the pixel electrode taken along line AA' is shown. Figures 1 to 3 As shown, an insulating layer 13 is provided between the pixel electrode 400 and the metal layer 300 , and the first connecting portion 330 is electrically connected to the pixel electrode 400 through a via hole 12 in the insulating layer 13 .

[0089] For example, Figure 1 and Figure 2 As shown, the first electrode 510 of the thin film transistor 500, the second electrode 520 of the thin film transistor 500, and the first connecting portion 330 are all structures in the metal layer 300. For example, the first electrode 510 of the thin film transistor 500 and the second electrode 520 of the thin film transistor 500 are both insulated from the common electrode 320. For example, the first electrode 510 of the thin film transistor 500 and the second electrode 520 of the thin film transistor 500 are both spaced apart from the common electrode 320. For example, the first connecting portion 330 is spaced apart from the common electrode 320.

[0090] For example, Figure 1 and Figure 2As shown, the first electrode 510 and the first connecting portion 330 of the thin film transistor 500 can be an integrated structure, but are not limited thereto. The first electrode 510 and the first connecting portion 330 of the thin film transistor 500 can also be a structure in which two parts are electrically connected. For example, the first electrode 510 of the thin film transistor 500 can be the portion where the metal layer 300 overlaps with the active layer, and the first connecting portion 330 can be the portion where the metal layer 300 does not overlap with the active layer.

[0091] For example, Figure 1 and Figure 2 As shown, along a direction perpendicular to the base substrate 100, both the first connection portion 330 and the common electrode 320 overlap with the pixel electrode 400. For example, along a direction perpendicular to the base substrate 100, a portion of the first connection portion 330 overlaps with the pixel electrode 400. For example, along a direction perpendicular to the base substrate 100, a portion of the common electrode 320 overlaps with the pixel electrode 400.

[0092] For example, Figure 1 As shown, a straight line extending along the first direction passes through the orthographic projection of the first electrode 510 of the thin film transistor 500 on the substrate 100 and the orthographic projection of the via 12 on the substrate 100. For example, the first connecting portion 330 includes at least a sub-portion extending along the first direction. For example, the first connecting portion 330 includes only a sub-portion extending along the first direction. For example, the sub-portion extending along the first direction of the first connecting portion 330 is electrically connected to the pixel electrode 400.

[0093] For example, Figure 1 As shown, the metal layer 300 further includes a second connecting portion 340 connecting the data line 310 and the second electrode 520 of the thin film transistor 500 .

[0094] For example, Figure 1 As shown, the second connecting portion 340 overlaps the gate line 200 in a direction perpendicular to the base substrate 100. For example, the second connecting portion 340 can be an integrated structure with the second electrode 520 of the thin film transistor 500. For example, the second connecting portion 340 can be an integrated structure with the data line 310. For example, the second electrode 520 of the thin film transistor 500, the second connecting portion 340, and the data line 310 can be an integrated structure. However, the present invention is not limited to this. The second connecting portion and the second electrode of the thin film transistor can also be a structure in which two parts are electrically connected, or the second connecting portion and the data line can also be a structure in which two parts are electrically connected.

[0095] For example, the second connection portion 340 may extend along the second direction. For example, the second connection portion 340 is spaced apart from the common electrode 320. For example, the second connection portion 340 is a portion that does not overlap the metal layer 300 and the active layer of the thin film transistor 500. For example, the second connection portion 340 does not overlap the pixel electrode 400 in a direction perpendicular to the base substrate 100.

[0096] Figure 4 for Figure 1 Schematic diagram of another pixel area on the array substrate shown in FIG. Figures 1 to 4 As shown, the multiple pixel areas 10 include at least one first pixel area 010 and at least one second pixel area 020. The first pixel area 010 is the pixel area 10 corresponding to the gate line pad 210, and the second pixel area 020 is the pixel area 10 corresponding to the position on the gate line 200 except the gate line pad 210.

[0097] For example, Figures 1 to 4 As shown, the first pixel region 010 and the second pixel region 020 are different pixel regions, that is, the first pixel region 010 and the second pixel region 020 are regions defined by the intersection of different data lines 310 and different gate lines 200. For example, the number of the second pixel regions 020 can be greater than the number of the first pixel regions 010, but is not limited thereto. The number of the second pixel regions 020 can also be less than the number of the first pixel regions 010, or the number of the second pixel regions 020 can also be equal to the number of the first pixel regions 010.

[0098] For example, Figure 4 As shown, the second pixel area 020 is opposite to the position of the non-gate line pad of the gate line 200, and the extension direction of each segment of the routing line 30 located in the second pixel area 020 and extending along at least part of the outline of the second pixel area 020 can be parallel to the extension direction of the signal line (gate line or data line) adjacent to the segment of the routing line 30 near the edge of the second pixel area 020.

[0099] For example, Figure 1 and Figure 4 As shown, the width of the gate line 200 corresponding to the second pixel area 020 can be the same as the width of the gate line 200 at the positions on both sides of the gate line pad 210 corresponding to the first pixel area 010. However, it is not limited to this. For example, the width of the gate line 200 corresponding to the second pixel area 020 can be different from the width of the gate line 200 at the positions on both sides of the gate line pad 210 corresponding to the first pixel area 010. For example, the widths of the gate lines 200 corresponding to the second pixel area 020 at various positions are the same, but it is not limited to this. The width of a portion of the gate line 200 corresponding to the second pixel area 020 can be different from the width of another portion. For example, the width of the gate electrode of the thin film transistor in the gate line 200 corresponding to the second pixel area 020 at the position where it is located can be greater than the width at other positions. For example, the gate electrode of the thin film transistor can be part of the gate line.

[0100] For example, Figures 1 to 4As shown, the common electrode 320 includes at least a portion of multiple segments of wiring, and the ratio of the area of the orthographic projection of the common electrode 320 in the first pixel region 010 on the substrate 100 to the area of the orthographic projection of the common electrode 320 in the second pixel region 020 on the substrate 100 is 0.8 to 1.2. For example, the ratio of the area of the orthographic projection of the common electrode 320 in the first pixel region 010 on the substrate 100 to the area of the orthographic projection of the common electrode 320 in the second pixel region 020 on the substrate 100 is 0.9 to 1.1. For example, the area of the orthographic projection of the common electrode 320 in the first pixel region 010 on the substrate 100 is substantially equal to the area of the orthographic projection of the common electrode 320 in the second pixel region 020 on the substrate 100.

[0101] The pixel electrodes in each pixel area overlap with the common electrode. By designing the ratio of the orthographic projection area of the common electrode arranged in the first pixel area corresponding to the gate line pad (i.e., the position where the support portion is provided) to the orthographic projection area of the common electrode arranged in the second pixel area corresponding to the non-gate line pad (i.e., the position where no support portion is provided) to be 0.8 to 1.2, the difference in capacitance generated between the pixel electrodes and the common electrode in different pixel areas can be reduced, the capacitance consistency of different pixel areas can be improved, and the display effect of the display device using the array substrate can be improved.

[0102] For example, the overlapping area between the common electrode 320 and the pixel electrode in the first pixel region 010 is a first overlapping area, and the overlapping area between the common electrode 320 and the pixel electrode in the second pixel region 020 is a second overlapping area. The ratio of the first overlapping area to the second overlapping area is 0.8 to 1.2. For example, the ratio of the first overlapping area to the second overlapping area is 0.9 to 1.1. For example, the first overlapping area and the second overlapping area are substantially equal.

[0103] By designing the ratio of the first overlapping area between the common electrode and the pixel electrode set in the first pixel area corresponding to the gate line pad (i.e., the position where the support portion is set) to the second overlapping area between the common electrode and the pixel electrode set in the second pixel area corresponding to the non-gate line pad (i.e., the position where the support portion is not set) to be 0.8 to 1.2, the difference between the capacitances generated between the pixel electrodes and the common electrodes in different pixel areas can be reduced, the capacitance consistency of different pixel areas can be improved, and the display effect of the display device using the array substrate can be improved.

[0104] For example, Figures 1 to 4As shown, the ratio of the length of the common electrode 320 in the first pixel region 010 to the length of the common electrode 320 in the second pixel region 020 is 0.8 to 1.2. For example, the ratio of the length of the common electrode 320 in the first pixel region 010 to the length of the common electrode 320 in the second pixel region 020 is 0.9 to 1.1. For example, the common electrode 320 in each pixel region 10 can be a metal trace with uniform width.

[0105] The common electrode includes a first routing line. An example of an embodiment of the present disclosure sets the common electrode in the first pixel area to a zigzag line shape corresponding to the position of the gate line pad, and each segment of the common electrode in the zigzag line metal layer is set to extend along the first direction or the second direction, which is beneficial to make the length of the common electrode in the first pixel area as equal as possible to the length of the common electrode in the second pixel area, which can reduce the difference in capacitance generated between the pixel electrodes and the common electrodes in different pixel areas, improve the capacitance consistency of different pixel areas, and thereby improve the display effect of the display device using the array substrate.

[0106] For example, Figure 1 As shown, the first wiring 31 may be a common electrode 320. For example, the length of each segment of the first wiring 31 may be smaller than the length of some segments of the wirings other than the first wiring 31 in the plurality of wiring segments 30.

[0107] For example, Figure 4 As shown, the common electrode 320 in the second pixel region 020 includes a first sub-common electrode 321 extending along the second direction and a second sub-common electrode 322 extending along the first direction. The first sub-common electrode 321 is located at a position away from the first electrode 510 of the thin-film transistor 500 corresponding to the pixel region in which it is located. The two ends of the first sub-common electrode 321 are respectively electrically connected to two second sub-common electrodes 322, and the two second sub-common electrodes 322 are respectively adjacent to two data lines 310. The above-mentioned "two second sub-common electrodes 322 are respectively adjacent to two data lines 310" may mean that no other common electrodes or other data lines are arranged between the orthographic projection of each second sub-common electrode 322 on the base substrate 100 and the orthographic projection of the corresponding data line 310 on the base substrate 100.

[0108] For example, Figures 1 to 4 As shown, the distance between the first wiring 31 in the first pixel area 010 and the first electrode 510 of the thin film transistor 500 corresponding to the first pixel area 010 is smaller than the distance between the first sub-common electrode 321 in the second pixel area 020 and the first electrode 510 of the thin film transistor 500 corresponding to the second pixel area 020.

[0109] For example, Figures 1 to 4 As shown, the common electrode 320 includes traces 30 connected end to end.

[0110] For example, Figures 1 to 4 As shown, multiple segments of wiring 30 are all common electrodes 320. Multiple segments of wiring 30 are connected end to end to form a ring with an opening. The first connecting portion 330 is inserted into the opening of the ring. The ring is insulated from the first connecting portion 330. For example, a gap is set between the first connecting portion 330 and the edge of the ring opening.

[0111] For example, Figures 1 to 4 As shown, each of the multiple routing segments 30 extends along the first direction or the second direction. Regardless of whether the gate line near the edge of the pixel area or the data line near the edge of the pixel area extends along the first direction or the second direction, by setting each of the multiple routing segments to extend along the first direction or the second direction, the impact of the multiple routing segments set by the metal layer on the aperture ratio of the pixel area can be minimized.

[0112] For example, Figures 1 to 4 As shown, the gate pad 210 includes a gate electrode 530 of a thin film transistor 500. For example, along a direction perpendicular to the base substrate 100, the gate electrode 530 of the thin film transistor 500 overlaps with the support portion 01. For example, the first electrode 510 and the second electrode 520 of the thin film transistor 500 can both overlap with the support portion 01.

[0113] For example, Figures 1 to 4 As shown, a straight line extending along the X direction passes through the orthographic projection of the gate 530 of the thin film transistor 500 on the substrate 100 and the orthographic projection of the via 12 on the substrate 100. For example, a straight line parallel to the first direction passes through the orthographic projection of the via 12 and the gate line pad 210 on the substrate 100.

[0114] For example, Figures 1 to 4 As shown, the first connection portion 330 extends along the first direction to be electrically connected to the pixel electrode 400. For example, the width of the first connection portion 330 at the position opposite to the via hole 12 is greater than the width of other positions of the first connection portion 330, so as to facilitate the electrical connection between the first connection portion 330 and the pixel electrode 400 through the via hole 12.

[0115] For example, Figures 1 to 4 As shown, the array substrate further includes a common electrode line 600, which is disposed on the same layer as the plurality of gate lines 200. For example, the common electrode 320 is electrically connected to the common electrode line 600.

[0116] For example, Figures 1 to 4 As shown, an insulating layer (not shown) is provided between the common electrode 320 and the common electrode line 600 , and the common electrode 320 is electrically connected to the common electrode line 600 through a via hole 11 in the insulating layer.

[0117] For example, Figures 1 to 4As shown, the common electrode 320 in at least one pixel region 10 may be an integrated structure, and the common electrode 320 in the pixel region 10 may be electrically connected to the common electrode line 600 through at least one via hole 11. However, the present invention is not limited thereto, and the common electrode in at least one pixel region may also be configured as at least two structures separated from each other, each structure being electrically connected to the common electrode line.

[0118] For example, Figures 1 to 4 As shown, the common electrode lines 600 extend along the second direction. For example, the gate lines 200 and the common electrode lines 600 may be alternately arranged along the first direction. For example, in a direction perpendicular to the base substrate 100, the common electrode lines 600 overlap with the pixel electrodes 400.

[0119] For example, Figures 1 to 4 As shown, along a direction perpendicular to the base substrate 100 , the first connection portion 330 overlaps the common electrode line 600 .

[0120] For example, Figure 1 and Figure 2 As shown, along a direction perpendicular to the base substrate 100 , the via hole 12 overlaps the common electrode line 600 .

[0121] For example, Figures 1 to 4 As shown, the common electrode 320 further includes a third sub-common electrode 323 extending along the first direction. The third sub-common electrode 323 and at least a portion of the first connecting portion 330 extending along the first direction are located on the same straight line, thereby dividing the pixel region 10 into two sub-pixel regions. For example, the third sub-common electrode 323 and the first connecting portion 330 are configured to work together to divide the pixel region 10 into two sub-pixel regions. Of course, the embodiments of the present disclosure are not limited to this. The third sub-common electrode and the first connecting portion may also be located in a direction that is not aligned with the first connecting portion.

[0122] For example, Figures 1 to 4 As shown, a pixel region 10 includes two sub-pixel regions arranged along the Y direction. For example, the shapes of the pixel electrodes in different sub-pixel regions can be the same or different. For example, the shapes of different sub-pixel regions in the same pixel region 10 can be the same or different. For example, the areas of different sub-pixel regions in the same pixel region 10 can be the same or different.

[0123] For example, Figures 1 to 4As shown, at least a portion of the first connection portion 330 and the third sub-common electrode 323 are respectively located on either side of the common electrode line 600. For example, the first connection portion 330 includes a portion overlapping with the common electrode line 600 and another portion not overlapping with the common electrode line 600. The portion of the first connection portion 330 not overlapping with the common electrode line 600 and the third sub-common electrode 323 are respectively located on either side of the common electrode line 600. Of course, the embodiments of the present disclosure are not limited to this. The first connection portion may also include two portions located on either side of the common electrode line, in which case the third sub-common electrode may not be provided. Alternatively, the portion of the first connection portion located on the same side of the common electrode line as the third sub-common electrode may be shorter to ensure spacing from the third sub-common electrode. For example, when the first connection portion includes two portions located on either side of the common electrode line, the widths of the two portions may be equal or unequal. For example, when the first connection portion includes two portions located on either side of the common electrode line, the width of the portion of the first connection portion located on the same side of the common electrode line as the third sub-common electrode may be the same as the width of the third sub-common electrode, but this is not limiting and the widths of the two portions may also be different.

[0124] Figure 5 for Figure 1 Schematic diagram of the portion of the protrusion and the first trace located at the edge of the portion of the protrusion. Figure 1 and Figure 5 As shown, the edge of the protrusion 211 of the gate line pad 210 includes a protrusion edge 2110 whose extension direction is not parallel to either the first direction or the second direction. For example, the protrusion 211 may include multiple edges, and in addition to the protrusion edge 2110, the multiple edges may also include an edge parallel to the first direction or the second direction. The above-mentioned "protrusion edge 2110 whose extension direction is not parallel to either the first direction or the second direction" means that the orthographic projection of the protrusion edge 2110 on the base substrate 100 is not parallel to either the first direction or the second direction.

[0125] For example, Figure 1 As shown, the edge of the protrusion 211 may include a protrusion edge 2110 that is not parallel to the first direction and the second direction, and an edge parallel to the second direction. However, not limited to this, the edge of the protrusion 211 may also include an edge parallel to the first direction. For example, the number of protrusion edges 2110 included in the protrusion 211 may be one, two or more. The embodiment of the present disclosure does not limit the number of protrusion edges that are not parallel to the first direction and the second direction included in each protrusion, and can be set according to product requirements. The above-mentioned "edge parallel to the second direction" means that the orthographic projection of the edge of the protrusion 211 on the base substrate 100 is parallel to the second direction; the above-mentioned "edge parallel to the first direction" means that the orthographic projection of the edge of the protrusion 211 on the base substrate 100 is parallel to the first direction.

[0126] For example, when the protrusion 211 includes multiple protrusion edges 2110, the lengths of the multiple protrusion edges 2110 can be the same or different. For example, the angles between the multiple protrusion edges 2110 and the second direction can be the same or different. The number of the multiple protrusion edges and their inclination angles relative to the second direction can be set according to product requirements. The length of the protrusion edge mentioned above can refer to the length of the orthographic projection of the protrusion edge on the base substrate.

[0127] For example, Figure 1 and Figure 5 As shown, the number of multiple segments of first routing lines 31 is greater than or equal to 2. For example, the number of first routing lines 31 corresponding to a protrusion edge 2110 of the protrusion 211 is not less than 2. For example, multiple segments of first routing lines 31 corresponding to a protrusion edge 2110 can be connected to each other to form a step structure. For example, the number of first routing lines 31 corresponding to different protrusion edges 211 in the same protrusion 211 can be the same or different, and the embodiments of the present disclosure are not limited to this. For example, the lengths of different segments of first routing lines 31 corresponding to the same protrusion edge 2110 can be different. For example, the widths of the orthographic projections of different segments of first routing lines 31 corresponding to the same protrusion edge 2110 on the base substrate 100 can be the same. For example, along a direction perpendicular to the base substrate 100, the thicknesses of different segments of first routing lines 31 corresponding to the same protrusion edge 2110 can be the same.

[0128] For example, Figure 1 and Figure 5 As shown, the edge of the protrusion 211 may include an edge parallel to the second direction, and the first trace 31 in the multiple sections of the first trace 31 opposite to the edge of the protrusion 211 parallel to the second direction is parallel to the edge of the protrusion 211, that is, the orthographic projection of the first trace 31 on the base substrate 100 is parallel to the orthographic projection of the edge of the protrusion 211 on the base substrate 100.

[0129] For example, Figure 1 and Figure 5 As shown, when the edge of the protrusion 211 includes an edge parallel to the first direction or the second direction, and an edge not parallel to the first direction and the second direction, the multiple sections of first traces 31 surrounding the edge of the protrusion 211 may include a first trace 31 parallel to a portion of the edge of the protrusion 211 and a first trace 31 not parallel to another portion of the edge of the protrusion 211.

[0130] For example, Figure 1 and Figure 5As shown, the orthographic projection of each first trace 31 on the substrate 100 is a first orthographic projection, and the orthographic projection of the protrusion edge 2110 on the substrate 100 is a second orthographic projection. The first orthographic projection includes a long side LL extending along its extension direction and close to the second orthographic projection, and a distance d is between the long side LL and the second orthographic projection. For example, the protrusion edge 2110 and the first trace 31 opposite it are non-parallel. The distance between the second orthographic projection of the protrusion edge 2110 on the substrate 100 and the long side LL of the first orthographic projection of the first trace 31 on the substrate 100 can include a maximum distance dmax and a minimum distance dmin. Multiple lines perpendicular to the second orthographic projection exist between the second orthographic projection and the long side LL of the first orthographic projection. The longest of these lines can have a length of dmax, and the shortest of these lines can have a length of dmin.

[0131] For example, Figure 1 and Figure 5 As shown, a protrusion edge 2110 in the protrusion 211 that is not parallel to the first direction and the second direction and a first line 31 extending along the second direction opposite to the protrusion edge 2110 are described as an example. The angle between the protrusion edge 2110 and the second direction is θ. For example, the angle between the second orthographic projection of the protrusion edge 2110 on the substrate 100 and the long side LL of the first orthographic projection of the first line 31 on the substrate 100 is θ; the length of the first line 31 is l, and the line width of the first line 31 is W; the distance between the second orthographic projection of the protrusion edge 2110 on the substrate 100 and the long side LL of the first orthographic projection of the first line 31 on the substrate 100 includes a minimum distance dmin; then the fringe field capacitance between the first line 31 and the protrusion edge 2110 satisfies the following relationship (1):

[0132]

[0133] Among them, ε d is the relative dielectric constant.

[0134] For example, the length of the first trace 31 is the length along the Y direction, and the width of the first trace 31 may refer to the size along the X direction.

[0135] Integrating the above fringe field capacitance yields the following equation (2):

[0136] C=ε d ×W×ln[(l / dmin)×sinθ+1].

[0137] For example, with Figure 5The length of the first trace 31 parallel to the second direction in the first trace 31 opposite to the protrusion edge 2110 shown in the figure can be a first length Lh, the minimum distance between the first trace 31 and the protrusion edge 2110 can be a first minimum distance dminh, and the capacitance between the first trace 31 and the protrusion edge 2110 can be Ch; Figure 5 The length of the first routing line 31 parallel to the first direction in the first routing line 31 relative to the protrusion edge 2110 shown can be the second length Lv, the minimum distance between the first routing line 31 and the protrusion edge 2110 can be the second minimum distance dminv, and the capacitance between the first routing line 31 and the protrusion edge 2110 can be Cv.

[0138] For example, the first length Lh can be 12.21 microns, the second length Lv can be 6.29 microns, the first minimum distance dminh can be 8.34 microns, the second minimum distance dminv can be 9.16 microns, the angle θ between the edge 2110 of the protrusion and the long side LL of the orthographic projection of the two sections of the first trace 31 can be 45 degrees, and the line width W of each section of the first trace 31 can be 3.5 microns.

[0139] For example, assuming ε d is 1, substituting the values of the first length Lh, the first minimum distance dminh, the line width W and the angle θ into the relationship formula ln[(l / dmin)×sinθ+1], the value thereof is 0.710606, substituting the values of the first length Lh, the first minimum distance dminh, the line width W and the angle θ into the relationship formula (2), the capacitance Ch is 2.487122F; substituting the values of the second length Lv, the second minimum distance dminv, the line width W and the angle θ into the relationship formula ln[(l / dmin)×sinθ+1], the value thereof is 0.39579, substituting the values of the second length Lv, the second minimum distance dminv, the line width W and the angle θ into the relationship formula (2), the capacitance Cv is 1.385264F, then Ch+Cv=3.872386.

[0140] The above ε d The value of 1 is only for illustration. In actual products, ε d The value of is related to the material of the insulating layer between the gate line layer and the metal layer. For example, the material of the insulating layer between the gate line layer and the metal layer may include an organic material or an inorganic material, such as silicon oxide or silicon nitride.

[0141] For example, the values of the first length Lh, the second length Lv, the first minimum distance dminh, and the second minimum distance dminv can be set according to the size of the display device to which the array substrate is applied. For example, the size of a sub-pixel on the array substrate can be 25 to 95 microns, then the minimum value of the first length Lh can be 2 microns, the minimum value of the second length Lv can be 2 microns, the minimum value of the first minimum distance dminh can be 2 microns, and the minimum value of the second minimum distance dminv can be 2 microns. Then, substituting the minimum values of the first length Lh, the second length Lv, the first minimum distance dminh, and the second minimum distance dminv into the relationship ln[(l / dmin)×sinθ+1], the first parameter C can be obtained. pad The minimum value is 0.483114. Similarly, the maximum value of the first length Lh can be 30 microns, the maximum value of the second length Lv can be 30 microns, the maximum value of the first minimum distance dminh can be 20 microns, and the maximum value of the second minimum distance dminv can be 20 microns. Substituting the maximum values of the first length Lh, the second length Lv, the first minimum distance dminh, and the second minimum distance dminv into the relationship ln[(l / dmin)×sinθ+1], the first parameter C can be obtained. pad The maximum value is 4.903148.

[0142] For example, according to the above calculation process, the length of each first trace 31 is L i The orthographic projection of each first trace 31 on the substrate 100 is the first orthographic projection, and the orthographic projection of the protruding edge 2110 on the substrate 100 is the second orthographic projection. The first orthographic projection includes a long side LL extending along its extension direction and close to the second orthographic projection. The minimum distance between the long side LL and the second orthographic projection is d i , the angle between the long side LL and the second orthographic projection is θ i , a first parameter C in the capacitance between the first trace 31 and the protrusion edge 2110 pad satisfy N is the number of the first multiple traces 31, i is a positive integer not less than 1, and N is a positive integer not less than 2. pad and is the relative dielectric constant ε d The product of the line width W is the above capacitance.

[0143] For example, the first parameter C pad Satisfy 0.035≤C pad ≤5. For example, the first parameter C pad Satisfying 0.1≤C pad≤4.5. For example, the first parameter C pad Satisfy 0.5≤C pad ≤4. For example, the first parameter C pad Satisfy 1≤C pad ≤3.5. For example, the first parameter C pad Satisfy 1.5≤C pad ≤3. For example, the first parameter C pad Satisfy 2≤C pad ≤2.5.

[0144] For example, a plurality of pixel regions 10 are provided on the array substrate, and the plurality of pixel regions 10 can be arranged in an array along a first direction and a second direction. For example, in the pixel regions 10 arranged along the first direction, three second pixel regions 020 are provided between two adjacent first pixel regions 010; and / or, in the pixel regions 10 arranged along the second direction, three second pixel regions 020 are provided between two adjacent first pixel regions 010. Of course, the present disclosure is not limited to this, and four or more second pixel regions can also be provided between two adjacent first pixel regions.

[0145] For example, the gate line pad can serve as a gate electrode in a thin film transistor.

[0146] The embodiments of the present disclosure provide an electrode line design suitable for use on an array substrate of a liquid crystal display device. This design can maintain the consistency of the storage capacitance of adjacent pixels or the capacitance (Cpd) generated between a common electrode and a pixel electrode, while minimizing the impact of the electrode line on the aperture ratio, and ultimately reducing the parasitic capacitance of the gate line or gate.

[0147] For example, the first routing line is not parallel to the edge contour of the protrusion at the edge of the protrusion, and the first routing line is in a step-shaped shape. Each section of the first routing line is parallel to the gate line and the data line, further reducing the capacitance Cgd between the gate line and the drain of the thin film transistor, and the capacitance Cgc between the gate line and the common electrode.

[0148] Figure 6 FIG. 1 is a schematic diagram of a partial planar structure of an array substrate provided according to another example of implementation of the present disclosure. Figure 6 As shown, the array substrate includes a base substrate 100, and a plurality of gate lines 200 and a metal layer 300 located on the base substrate 100. The metal layer 300 is located on a side of the plurality of gate lines 200 away from the base substrate 100. The metal layer 300 includes a plurality of data lines 310. The plurality of data lines 310 extend along a first direction and are arranged along a second direction. The plurality of gate lines 200 extend along the second direction and are arranged along the first direction. The first direction and the second direction intersect. The plurality of data lines 310 intersect with the plurality of gate lines 200 to define a plurality of pixel areas 10. Figure 6 A pixel area 10 is schematically shown.

[0149] For example, Figure 6 As shown, multiple data lines 310 extend along the X direction and are arranged along the Y direction; multiple gate lines 200 extend along the Y direction and are arranged along the X direction. For example, the first direction is the X direction, the second direction is the Y direction, and the first direction is perpendicular to the second direction. However, this is not limiting, and the first direction and the second direction may not be perpendicular. For example, the first direction and the second direction may be interchangeable.

[0150] For example, Figure 6 As shown, two adjacent data lines 310 and two adjacent gate lines 200 are arranged to cross to define a pixel area 10. For example, a pixel area 10 is a sub-pixel. For example, the array substrate includes a plurality of sub-pixels (a plurality of pixel areas 10), and the plurality of sub-pixels include sub-pixels configured to display different colors of light. For example, the plurality of sub-pixels may include a red sub-pixel configured to display red light, a green sub-pixel configured to display green light, and a blue sub-pixel configured to display blue light. For example, two adjacent sub-pixels arranged in at least one of the first direction and the second direction are respectively sub-pixels configured to display different colors of light.

[0151] For example, the shape of the pixel area 10 can be a polygon. For example, the shape of the pixel area 10 can be a quadrilateral. For example, the shape of the pixel area 10 can be a rectangle. The present disclosure does not limit this. The shape of the pixel area 10 is related to the shape of the edge of the data line 310 and the edge of the gate line 200.

[0152] For example, each pixel region 10 includes a display area for display, and the area of the display area may be smaller than that of the pixel region 10. For example, the shape of the display area may be the same as that of the pixel region 10, or the shape of the display area may be different from that of the pixel region 10.

[0153] like Figure 6 As shown, the metal layer 300 further includes a common electrode 320 located in the pixel area 10. For example, the common electrode 320 can be a film layer provided in the same layer as the data line 310 and made of the same material.

[0154] like Figure 6 As shown, at least one gate line 200 includes a gate line pad 210 , and the gate line pad 210 includes a protrusion 211 protruding into the pixel area 10 relative to a position on the gate line 200 except the gate line pad 210 .

[0155] For example, Figure 6As shown, the gate line pad 210 is a portion of the gate line 200. For example, along the X direction, the width of the gate line pad 210 is greater than the width of the gate line 200 other than the gate line pad 210. For example, in the width direction, the portion of the gate line pad 210 that protrudes relative to the portion of the gate line 200 other than the gate line pad 210 is a protrusion 211.

[0156] For example, Figure 6 The example shown is the same as Figure 1 The difference of the illustrated example is that the gate line pad 210 includes protrusions 211 protruding from both sides of the gate line 200. For example, a plurality of gate line pads 210 may be provided on one gate line 200, each of which includes protrusions 211 protruding from both sides of the gate line 200.

[0157] For example, Figure 6 As shown, the gate line pad 210 is configured to be arranged opposite to the support portion 01. For example, in a direction perpendicular to the base substrate 100, the gate line pad 210 overlaps with the support portion 01. For example, the orthographic projection of the gate line pad 210 on the base substrate 100 can overlap with the orthographic projection of the support portion 01 on the base substrate 100. For example, the orthographic projection of the support portion 01 on the base substrate 100 can completely fall within the orthographic projection of the gate line pad 210 on the base substrate 100. For example, the support portion 01 in this example can overlap with the orthographic projection of the gate line pad 210 on the base substrate 100. Figure 1 The supporting portion 01 in the example shown has the same features, which will not be described in detail here. Figure 6 The supporting portion 01 is schematically shown as being disposed on the array substrate, but is not limited thereto. The supporting portion may be disposed on the opposing substrate, and the position of the supporting portion may be set according to product requirements.

[0158] like Figure 6 As shown, the metal layer 300 located in the pixel area 10 includes a plurality of routing segments 30 extending along at least a portion of the outline of the pixel area 10. For example, at least some of the routing segments 30 are electrically connected routing segments. For example, the electrically connected routing segments 30 are integrated routing segments. The "integrated routing segments" may refer to routing segments formed by performing the same patterning process on the same metal material layer. The "multiple routing segments 30 extending along at least a portion of the outline of the pixel area 10" may refer to the plurality of routing segments extending along the edge of the data line 310 and the edge of the gate line 200. The plurality of routing segments extending along at least a portion of the outline of the pixel area may be parallel to the edge extension direction of the data line or the gate line, but is not limited thereto. Part of the routing segments may also be non-parallel to a portion of the edge of the gate line or the data line. Whether the routing segments are parallel to the edge of the signal line (including the gate line and the data line) adjacent thereto (in a plan view) may be set according to product requirements.

[0159] For example, Figure 6As shown, the edge of the protrusion 211 of the gate line pad 210 includes a fold line or a curve.

[0160] like Figure 6 As shown, the multiple traces 30 include multiple first traces 31 surrounding at least a portion of the edge of the protrusion 211. Each first trace 31 extends in the first direction or the second direction, and the multiple first traces 31 are connected end to end to form a stepped structure. The "multiple first traces 31 surrounding at least a portion of the edge of the protrusion 211" mentioned above may refer to the orthographic projections of the multiple first traces 31 on the substrate 100 surrounding at least a portion of the edge of the protrusion 211.

[0161] The embodiment of the present disclosure provides a step structure for the first routing line surrounding the protruding portion of the gate line pad, which helps to improve the consistency of the capacitance generated by the metal layer and the pixel electrode in different pixel areas while reducing the impact of the metal layer on the aperture ratio in the pixel area.

[0162] For example, two first traces 31 connected end to end among the multiple first traces 31 are electrically connected. For example, the multiple first traces 31 can be an integrated structure. For example, the distance between the orthographic projection of the multiple first traces 31 on the base substrate 100 and the orthographic projection of the edge of the protrusion 211 it surrounds on the base substrate is smaller than the distance between the orthographic projection of other traces on the base substrate 100 and the edge of the protrusion 211. For example, the distances between different first traces 31 and the edges of the protrusion 211 they surround can be the same or different. For example, the extension direction of the first trace 31 can be parallel to the edge of the protrusion 211 it surrounds; the extension direction of the first trace 31 can also intersect with the edge of the protrusion 211 it surrounds.

[0163] For example, Figure 6 As shown, the extension direction of the routing lines 30 other than the first routing line 31 in the multi-segment routing line 30 can be parallel to the extension direction of the adjacent data line 310 or gate line 200. For example, the extension direction of the routing lines 30 other than the first routing line 31 in the multi-segment routing line 30 can be parallel to the extension direction of the adjacent data line 310 or gate line 200 near the edge of the routing line 30.

[0164] For example, Figure 6 As shown, the two segments of the first trace 31 located at the outermost ends of the plurality of segments of the first trace 31 can extend along the second direction. For example, the two segments of the first trace 31 located at the outermost ends of the plurality of segments of the first trace 31 can both be electrically connected to the first trace 31. For example, the two segments of the first trace 31 located at the outermost ends of the plurality of segments of the first trace 31 can both be integrated with the first trace 31. However, this is not limiting. One of the two segments of the first trace 31 located at the outermost ends of the plurality of segments of the first trace can also be spaced apart from the first trace.

[0165] For example, Figure 6 As shown, any one of the multiple routing segments 30 31 may extend along the first direction or along the second direction.

[0166] For example, Figure 6 As shown, the shapes of the protrusions 211 located on both sides of the center line of a gate line 200 extending along the Y direction can be the same or different. For example, the shapes of the two protrusions 211 protruding relative to other positions of the gate line 200 included in the same gate line pad 210 can be the same or different. For example, the shape of the two protrusions 211 included in the same gate line pad 210 can both be trapezoidal, with the upper base of the trapezoid protruding into the pixel area 10 relative to the other parts of the gate line 200, and the lower base of the trapezoid can be flush with at least a portion of the edge of the other parts of the gate line 200.

[0167] For example, Figure 6 As shown, the gate line 200 is provided with protrusions 211 on both sides in the X direction. At this time, in one pixel area 10 , the multiple first routing segments 31 in the multiple routing segments 30 are concentrated at two locations in the multiple routing segments 30 .

[0168] For example, the array substrate further includes a plurality of pixel electrodes 400 and a plurality of thin film transistors 500. In this example, the pixel electrodes included in the array substrate may be Figure 2 The pixel electrodes shown have the same features, which will not be described again here.

[0169] For example, Figure 6 As shown, each pixel region 10 may include a thin film transistor 500, but is not limited thereto. The number of thin film transistors included in each pixel region may be set according to the performance of the required pixel circuit. For example, the number of thin film transistors in each pixel region may be two or more.

[0170] For example, Figure 6 As shown, each thin film transistor 500 includes a first electrode 510, a gate electrode 530, and a second electrode 520. The first electrode 510 and the second electrode 520 overlap with the film layer where the gate line 200 is located. For example, the thin film transistor 500 also includes an active layer, the first electrode 510 and the second electrode 520 overlap with the active layer, and the gate electrode 530 overlaps with the active layer. For example, the gate electrode 530 can be a partial structure of the gate line 200.

[0171] For example, Figure 6 As shown, the first electrode 510 of the thin film transistor 500 is electrically connected to the pixel electrode 400 through the first connecting portion 330 , and the second electrode 520 of the thin film transistor 500 is electrically connected to the data line 310 .

[0172] For example, Figure 6As shown, the first electrode 510 of the thin film transistor 500, the second electrode 520 of the thin film transistor 500, and the first connecting portion 330 are all structures in the metal layer 300, and the first electrode 510 of the thin film transistor 500 and the second electrode 520 of the thin film transistor 500 are both insulated from the common electrode 320. For example, the first electrode 510 of the thin film transistor 500 and the second electrode 520 of the thin film transistor 500 are both spaced apart from the common electrode 320. For example, the first connecting portion 330 is spaced apart from the common electrode 320.

[0173] For example, Figure 6 As shown, the first electrode 510 and the first connecting portion 330 of the thin film transistor 500 can be an integrated structure, but are not limited thereto and can also be a structure in which two parts are electrically connected. For example, the first electrode 510 of the thin film transistor 500 can be the portion where the metal layer 300 overlaps with the active layer, and the first connecting portion 330 can be the portion where the metal layer 300 does not overlap with the active layer.

[0174] For example, along a direction perpendicular to the base substrate 100, both the first connection portion 330 and the common electrode 320 overlap with the pixel electrode 400. For example, along a direction perpendicular to the base substrate 100, a portion of the first connection portion 330 overlaps with the pixel electrode 400. For example, along a direction perpendicular to the base substrate 100, a portion of the common electrode 320 overlaps with the pixel electrode 400.

[0175] For example, Figure 6 As shown, the second connecting portion 340 overlaps the gate line 200 in a direction perpendicular to the base substrate 100. For example, the second connecting portion 340 can be an integrated structure with the second electrode 520 of the thin film transistor 500. For example, the second connecting portion 340 can be an integrated structure with the data line 310. For example, the second electrode 520 of the thin film transistor 500, the second connecting portion 340, and the data line 310 can be an integrated structure. For example, the second connecting portion 340 can extend along the second direction. For example, the second connecting portion 340 is spaced apart from the common electrode 320.

[0176] For example, Figure 6 The array substrate shown is Figure 1 The differences between the array substrates shown include: Figure 6The gate electrode 530 of the thin film transistor 500 on the array substrate is shown as being located on the gate line 200, excluding the gate line pad 210. For example, the gate electrode 530 of the thin film transistor 500 can be located on one side of the gate line pad 210 in the Y direction. For example, in a direction perpendicular to the base substrate 100, the gate electrode 530 of the thin film transistor 500 does not overlap with the support portion 01, which helps to improve the flatness of the support portion. For example, in a direction perpendicular to the base substrate 100, both the first electrode 510 and the second electrode 520 of the thin film transistor 500 can not overlap with the support portion 01.

[0177] Figure 7 for Figure 6 Schematic diagram of another pixel area on the array substrate shown in FIG. Figure 6 and Figure 7 As shown, the multiple pixel areas 10 include at least one first pixel area 010 and at least one second pixel area 020. The first pixel area 010 is the pixel area 10 corresponding to the gate line pad 210, and the second pixel area 020 is the pixel area 10 corresponding to the position on the gate line 200 except the gate line pad 210.

[0178] For example, Figure 6 and Figure 7 As shown, the first pixel region 010 and the second pixel region 020 are different pixel regions, that is, the first pixel region 010 and the second pixel region 020 are regions defined by the intersection of different data lines 310 and different gate lines 200. For example, the number of the second pixel regions 020 can be greater than the number of the first pixel regions 010, but is not limited thereto. The number of the second pixel regions 020 can also be less than the number of the first pixel regions 010, or the number of the second pixel regions 020 can also be equal to the number of the first pixel regions 010.

[0179] For example, Figure 7 As shown, the second pixel area 020 is opposite to the position of the non-gate line pad, and the extension direction of the partial routing line 30 located in the second pixel area 020 and extending along at least part of the outline of the second pixel area 020 can be parallel to the extension direction of the signal line (gate line or data line) adjacent to the partial routing line 30 close to the edge of the second pixel area 020.

[0180] For example, Figure 7 It is schematically shown that the width of the position where the gate 530 of the thin film transistor 500 is set in the gate line 200 corresponding to the second pixel area 020 can be greater than the width at the position where the gate 530 is not set, but is not limited to this. The widths of the gate lines corresponding to the second pixel area at all positions can be the same.

[0181] For example, Figure 6 and Figure 7As shown, the common electrode 320 includes partial routing of multiple segments, and the ratio of the area of the orthographic projection of the common electrode 320 in the first pixel region 010 on the substrate 100 to the area of the orthographic projection of the common electrode 320 in the second pixel region 020 on the substrate 100 is 0.8 to 1.2. For example, the ratio of the area of the orthographic projection of the common electrode 320 in the first pixel region 010 on the substrate 100 to the area of the orthographic projection of the common electrode 320 in the second pixel region 020 on the substrate 100 is 0.9 to 1.1. For example, the area of the orthographic projection of the common electrode 320 in the first pixel region 010 on the substrate 100 is substantially equal to the area of the orthographic projection of the common electrode 320 in the second pixel region 020 on the substrate 100.

[0182] The pixel electrodes in each pixel area overlap with the common electrode. By designing the ratio of the orthographic projection area of the common electrode arranged in the first pixel area corresponding to the gate line pad (i.e., the position where the support portion is provided) to the orthographic projection area of the common electrode arranged in the second pixel area corresponding to the non-gate line pad (i.e., the position where no support portion is provided) to be 0.8 to 1.2, the difference in capacitance generated between the pixel electrodes and the common electrode in different pixel areas can be reduced, the capacitance consistency of different pixel areas can be improved, and the display effect of the display device using the array substrate can be improved.

[0183] For example, the overlapping area between the common electrode 320 and the pixel electrode in the first pixel area 010 is a first overlapping area, and the overlapping area between the common electrode 320 and the pixel electrode in the second pixel area 020 is a second overlapping area, and the ratio of the first overlapping area to the second overlapping area is 0.8 to 1.2. For example, the ratio of the first overlapping area to the second overlapping area is 0.9 to 1.1. For example, the first overlapping area is approximately equal to the second overlapping area. By designing the first overlapping area between the common electrode and the pixel electrode provided in the first pixel area corresponding to the gate line pad (i.e., the position where the support portion is provided) to be 0.8 to 1.2 compared to the second overlapping area between the common electrode and the pixel electrode provided in the second pixel area corresponding to the non-gate line pad (i.e., the position where the support portion is not provided), the difference between the capacitances generated between the pixel electrodes and the common electrodes in different pixel areas can be reduced, the capacitance consistency of different pixel areas can be improved, and the display effect of the display device using the array substrate can be improved.

[0184] For example, Figure 6 and Figure 7As shown, the ratio of the length of the common electrode 320 in the first pixel region 010 to the length of the common electrode 320 in the second pixel region 020 is 0.8 to 1.2. For example, the ratio of the length of the common electrode 320 in the first pixel region 010 to the length of the common electrode 320 in the second pixel region 020 is 0.9 to 1.1. For example, the common electrode 320 in each pixel region 10 can be a metal trace with uniform width.

[0185] The common electrode in the first pixel area is set to a zigzag shape corresponding to the position of the gate line pad, and each segment of the common electrode in the zigzag line is set to extend along the first direction or the second direction. This is beneficial to making the length of the common electrode in the first pixel area as equal as possible to the length of the common electrode in the second pixel area. It can reduce the difference in capacitance generated between the pixel electrodes and the common electrodes in different pixel areas, improve the consistency of capacitance in different pixel areas, and thus improve the display effect of the display device using the array substrate.

[0186] For example, Figure 6 As shown, the first connection portion 330 includes a portion of the multiple routing segments 30, and the ratio of the area of the orthographic projection of the first connection portion 330 in the first pixel region 010 on the substrate 100 to the area of the orthographic projection of the first connection portion 330 in the second pixel region 020 on the substrate 100 is 0.8 to 1.2. For example, the ratio of the area of the orthographic projection of the first connection portion 330 in the first pixel region 010 on the substrate 100 to the area of the orthographic projection of the first connection portion 330 in the second pixel region 020 on the substrate 100 is 0.9 to 1.1. For example, the area of the orthographic projection of the first connection portion 330 in the first pixel region 010 on the substrate 100 is substantially equal to the area of the orthographic projection of the first connection portion 330 in the second pixel region 020 on the substrate 100.

[0187] The pixel electrode in each pixel area overlaps with the first connecting portion. By designing the ratio of the orthographic projection area of the first connecting portion set in the first pixel area corresponding to the gate line pad (i.e., the position where the support portion is set) to the orthographic projection area of the first connecting portion set in the second pixel area corresponding to the non-gate line pad (i.e., the position where no support portion is set) to be 0.8 to 1.2, the difference between the capacitances generated between the pixel electrodes and the first connecting portions in different pixel areas can be reduced, the capacitance consistency of different pixel areas can be improved, and the display effect of the display device using the array substrate can be improved.

[0188] For example, the first connection portion 330 includes a portion of the multiple-segment routing 30, and the ratio of the overlapping area between the first connection portion 330 and the pixel electrode in the first pixel region 010 to the overlapping area between the first connection portion 330 and the pixel electrode in the second pixel region 020 is 0.8 to 1.2. For example, the ratio of the overlapping area between the first connection portion 330 and the pixel electrode in the first pixel region 010 to the overlapping area between the first connection portion 330 and the pixel electrode in the second pixel region 020 is 0.9 to 1.1. For example, the overlapping area between the first connection portion 330 and the pixel electrode in the first pixel region 010 and the overlapping area between the first connection portion 330 and the pixel electrode in the second pixel region 020 are substantially equal. By designing the ratio of the overlapping area between the first connecting portion provided in the first pixel area corresponding to the gate line pad (i.e., the position where the support portion is provided) and the pixel electrode to the overlapping area between the first connecting portion provided in the second pixel area corresponding to the non-gate line pad (i.e., the position where the support portion is not provided) and the pixel electrode to be 0.8 to 1.2, the difference between the capacitances generated between the pixel electrode and the first connecting portion in different pixel areas can be reduced, the capacitance consistency of different pixel areas can be improved, and the display effect of the display device using the array substrate can be improved.

[0189] For example, the ratio of the length of the first connection portion 330 in the first pixel region 010 to the length of the first connection portion 330 in the second pixel region 020 is 0.8 to 1.2. For example, the ratio of the length of the first connection portion in the first pixel region 010 to the length of the first connection portion in the second pixel region 020 is 0.9 to 1.1. For example, the length of the first connection portion in the first pixel region 010 is substantially equal to the length of the first connection portion in the second pixel region 020.

[0190] For example, Figure 6 As shown, the first connecting portion 330 is electrically connected to the pixel electrode through the via hole 12 in the insulating layer between the first connecting portion 330 and the pixel electrode. The orthographic projection of the first electrode 510 of the thin film transistor 500 on the base substrate 100 and the orthographic projection of the via hole 12 on the base substrate 100 cannot be passed by a straight line along the X direction. Therefore, the first connecting portion cannot only extend to the position of the via hole along the first direction. The first connecting portion is configured as a line inclined relative to the X direction or as a broken line with each segment extending along the first direction or the second direction to extend to the via hole, thereby electrically connecting to the pixel electrode.

[0191] The first connection portion in the first pixel area is set to a zigzag shape corresponding to the position of the gate line pad, and each segment of the first connection portion in the zigzag line is set to extend along the first direction or the second direction. This is beneficial for making the length of the first connection portion in the first pixel area as equal as possible to the length of the first connection portion in the second pixel area. It can reduce the difference in capacitance generated between the pixel electrode and the first connection portion in different pixel areas, improve the consistency of capacitance in different pixel areas, and thus improve the display effect of the display device using the array substrate.

[0192] For example, Figure 6 As shown, at least one of the common electrode 320 and the first connecting portion includes multiple first traces. For example, Figure 6 The array substrate shown is Figure 1 The difference of the array substrate shown also includes that the multiple first traces 31 include two parts, one of the two parts is a common electrode 320 , and the other of the two parts is a first connecting portion 330 .

[0193] For example, Figure 6 As shown, the two gate lines 200 located on both sides of at least one first pixel area 010 both include a gate line pad 210 protruding into the first pixel area 010, the common electrode 320 includes a first routing line 31 surrounding the protruding portion 211 of the gate line pad 210 on one of the two gate lines 200, and the first connecting portion 330 includes a first routing line 31 surrounding the protruding portion 211 of the gate line pad 210 on the other of the two gate lines 200.

[0194] For example, Figure 6 As shown, the gate line pad 210 includes two protrusions 211 protruding toward both sides of the gate line 200 in the X direction, namely, a first protrusion and a second protrusion. The first traces 31 surrounding the first protrusion 211 can all be common electrodes 320. A portion of the first traces 31 surrounding the second protrusion is the common electrode 320, and another portion is a first connecting portion 330. For example, all the first traces 31 surrounding the first protrusion 211 are continuously arranged and connected end to end. The first traces 31 surrounding the second protrusion 212 include two separated portions of first traces 31, each portion of which is continuously arranged and connected end to end.

[0195] For example, Figure 6 As shown, the first connection portion 330 includes a sub-portion extending along the first direction and a sub-portion extending along the second direction. For example, the first connection portion 330 may include at least one sub-portion extending along the first direction and at least one sub-portion extending along the second direction. Figure 6The first connection part 330 is schematically shown to include three sub-parts extending along the first direction and two sub-parts extending along the second direction, but is not limited to this. The number of sub-parts extending along the first direction and the number of sub-parts extending along the second direction in the first connection part can be set according to product requirements.

[0196] For example, Figure 6 As shown, a sub-portion of the first connection portion 330 is the first trace 31 surrounding the gate line pad 210 .

[0197] For example, Figure 7 As shown, the common electrode 320 in the second pixel region 020 includes a first sub-common electrode 321 extending along the second direction and a second sub-common electrode 322 extending along the first direction. The first sub-common electrode 321 is located at a position away from the first electrode 510 of the thin-film transistor 500 corresponding to the pixel region in which it is located. The two ends of the first sub-common electrode 321 are respectively electrically connected to two second sub-common electrodes 322, and the two second sub-common electrodes 322 are respectively adjacent to two data lines 310. The above-mentioned "two second sub-common electrodes 322 are respectively adjacent to two data lines 310" may mean that no other common electrodes or other data lines are arranged between the orthographic projection of each second sub-common electrode 322 on the base substrate 100 and the orthographic projection of the corresponding data line 310 on the base substrate 100.

[0198] For example, Figure 6 and Figure 7 As shown, the distance between the first wiring 31 in the first pixel area 010 and the first electrode 510 of the thin film transistor 500 corresponding to the first pixel area 010 is smaller than the distance between the first sub-common electrode 321 in the second pixel area 020 and the first electrode 510 of the thin film transistor 500 corresponding to the second pixel area 020.

[0199] For example, Figure 6 and Figure 7 As shown, the wiring 31 included in the common electrode 320 is connected end to end, and the wiring 30 included in the first connection portion 330 is connected end to end.

[0200] For example, Figure 6 and Figure 7 As shown, the common electrode 320 includes traces 30 connected end to end to form a ring with an opening, the opening of the ring is inserted into the first connecting portion 330, and the ring is insulated from the first connecting portion 330. For example, a gap is set between the first connecting portion 330 and the edge of the ring opening.

[0201] For example, Figure 6 and Figure 7As shown, each of the multiple routing segments 30 extends along the first direction or the second direction. Regardless of whether the gate line near the edge of the pixel area or the data line near the edge of the pixel area extends along the first direction or the second direction, by setting each of the multiple routing segments to extend along the first direction or the second direction, the impact of the multiple routing segments set by the metal layer on the aperture ratio of the pixel area can be minimized.

[0202] For example, Figure 6 and Figure 7 As shown, the width of the first connection portion 330 at the position facing the via hole 12 is greater than the width of other positions of the first connection portion 330 , so as to facilitate the electrical connection between the first connection portion 330 and the pixel electrode 400 through the via hole 12 .

[0203] For example, Figure 6 and Figure 7 As shown, the array substrate further includes a common electrode line 600 . The common electrode line 600 is provided in the same layer as the plurality of gate lines 200 , and the common electrode 320 is electrically connected to the common electrode line 600 .

[0204] For example, Figure 6 and Figure 7 As shown, an insulating layer (not shown) is provided between the common electrode 320 and the common electrode line 600 , and the common electrode 320 is electrically connected to the common electrode line 600 through a via hole 11 in the insulating layer.

[0205] For example, Figure 6 and Figure 7 As shown, the common electrode 320 in at least one pixel region 10 may be an integrated structure, and the common electrode 320 in the pixel region 10 may be electrically connected to the common electrode line 600 through at least one via hole 11. However, the present invention is not limited thereto, and the common electrode in at least one pixel region may also be configured as at least two structures separated from each other, each structure being electrically connected to the common electrode line.

[0206] For example, Figure 6 and Figure 7 As shown, the common electrode lines 600 extend along the second direction. For example, the gate lines 200 and the common electrode lines 600 may be alternately arranged along the first direction. For example, in a direction perpendicular to the base substrate 100, the common electrode lines 600 overlap with the pixel electrodes 400.

[0207] For example, Figure 6 and Figure 7 As shown, along a direction perpendicular to the base substrate 100 , the first connection portion 330 overlaps the common electrode line 600 .

[0208] For example, Figure 6 and Figure 7As shown, along a direction perpendicular to the base substrate 100 , the via hole 12 overlaps the common electrode line 600 .

[0209] For example, Figure 6 and Figure 7 As shown, the common electrode 320 further includes a third sub-common electrode 323 extending along the first direction. The third sub-common electrode 323 and at least a portion of the first connecting portion 330 extending along the first direction are located on the same straight line, thereby dividing the pixel area 10 into two sub-pixel areas. For example, the third sub-common electrode 323 and the first connecting portion 330 are configured to work together to divide a pixel area into two sub-pixel areas. Of course, the embodiments of the present disclosure are not limited to this. The third sub-common electrode and the first connecting portion may also be located in a direction that is not aligned with the same straight line.

[0210] For example, Figure 6 and Figure 7 As shown, a pixel region 10 includes two sub-pixel regions arranged along the Y direction. For example, the shapes of the pixel electrodes in different sub-pixel regions can be the same or different. For example, the shapes of different sub-pixel regions in the same pixel region 10 can be the same or different. For example, the areas of different sub-pixel regions in the same pixel region 10 can be the same or different.

[0211] For example, Figure 6 and Figure 7 As shown, at least a portion of the first connection portion 330 and the third sub-common electrode 323 are respectively located on either side of the common electrode line 600. For example, the first connection portion 330 includes a portion overlapping with the common electrode line 600 and another portion not overlapping with the common electrode line 600. The portion of the first connection portion 330 not overlapping with the common electrode line 600 and the third sub-common electrode 323 are respectively located on either side of the common electrode line 600. Of course, the embodiments of the present disclosure are not limited to this. The first connection portion may also include two portions located on either side of the common electrode line, in which case the third sub-common electrode may not be provided. Alternatively, the portion of the first connection portion located on the same side of the common electrode line as the third sub-common electrode may be shorter to ensure spacing from the third sub-common electrode. For example, when the first connection portion includes two portions located on either side of the common electrode line, the widths of the two portions may be equal or unequal. For example, when the first connection portion includes two portions located on either side of the common electrode line, the width of the portion of the first connection portion located on the same side of the common electrode line as the third sub-common electrode may be the same as the width of the third sub-common electrode, but this is not limiting and the widths of the two portions may also be different.

[0212] For example, Figure 6As shown, the edge of the protrusion 211 of the gate line pad 210 includes a protrusion edge 2110 whose extension direction is not parallel to either the first direction or the second direction. For example, the protrusion 211 may include multiple edges, and in addition to the protrusion edge 2110, the multiple edges may also include an edge parallel to the first direction or the second direction. The above-mentioned "protrusion edge 2110 whose extension direction is not parallel to either the first direction or the second direction" means that the orthographic projection of the protrusion edge 2110 on the base substrate 100 is not parallel to either the first direction or the second direction.

[0213] For example, Figure 6 As shown, the multiple edges of the protrusion 211 may include protrusion edges 2110 that are not parallel to the first direction and the second direction, and edges that are parallel to the second direction. However, not limited to this, the edges of the protrusion 211 may also include edges parallel to the first direction. For example, the number of protrusion edges 2110 included in the protrusion 211 may be one, two or more. The embodiment of the present disclosure does not limit the number of protrusion edges that are not parallel to the first direction and the second direction included in each protrusion, and can be set according to product requirements. The above-mentioned "edges parallel to the second direction" refer to the orthographic projection of the edge of the protrusion 211 on the base substrate 100 being parallel to the second direction; the above-mentioned "edges parallel to the first direction" refer to the orthographic projection of the edge of the protrusion 211 on the base substrate 100 being parallel to the first direction.

[0214] For example, when the protrusion 211 includes multiple protrusion edges 2110, the lengths of the multiple protrusion edges 2110 can be the same or different. For example, the angles between the multiple protrusion edges 2110 and the second direction can be the same or different. The number of the multiple protrusion edges and their inclination angles relative to the second direction can be set according to product requirements. The length of the protrusion edge mentioned above can refer to the length of the orthographic projection of the protrusion edge on the base substrate.

[0215] For example, Figure 6 As shown, the number of the multiple first traces 31 is greater than or equal to 2. For example, the number of the first traces 31 corresponding to one protrusion edge 2110 of the protrusion 211 is not less than 2. For example, the multiple first traces 31 corresponding to one protrusion edge 2110 can be connected to each other to form a step structure.

[0216] For example, the number of first traces 31 corresponding to different protrusion edges 2110 within the same protrusion 211 can be the same or different, and this is not a limitation in the presently disclosed embodiments. For example, the lengths of different segments of first traces 31 corresponding to the same protrusion edge 2110 can be different. For example, the widths of the orthographic projections of different segments of first traces 31 corresponding to the same protrusion edge 2110 on the base substrate 100 can be the same. For example, the dimensions of different segments of first traces 31 corresponding to the same protrusion edge 2110 can be the same along a direction perpendicular to the base substrate 100.

[0217] For example, Figure 6 As shown, the edge of the protrusion 211 may include an edge parallel to the second direction, and the first trace 31 in the multiple sections of the first trace 31 opposite to the edge of the protrusion 211 parallel to the second direction is parallel to the edge of the protrusion 211, that is, the orthographic projection of the first trace 31 on the base substrate 100 is parallel to the orthographic projection of the edge of the protrusion 211 on the base substrate 100.

[0218] For example, Figure 6 As shown, when the edge of the protrusion 211 includes an edge parallel to the first direction or the second direction, and an edge not parallel to the first direction and the second direction, the multiple sections of first traces 31 surrounding the edge of the protrusion 211 may include first traces 31 parallel to part of the edge of the protrusion 211 and first traces 31 not parallel to part of the edge of the protrusion 211.

[0219] In this example, the capacitance formed between the first trace included in the common electrode and the edge of the protruding portion can be formed by Figure 1 and Figure 5 The capacitance formed between the first trace and the edge of the protrusion in the example shown is calculated in the same way, and the capacitance formed between the first trace included in the first connection portion and the edge of the protrusion in this example can also be calculated in the same way as Figure 1 and Figure 5 The capacitance formed between the first trace and the edge of the protrusion in the illustrated example is calculated in the same manner and will not be described again herein.

[0220] For example, Figure 6 In the example shown, the first parameter C in the capacitance between the first trace and the protrusion edge of the protrusion is pad Satisfy 0.035≤C pad ≤5.

[0221] For example, Figure 7As shown, the multiple segments of wiring 30 within the second pixel region 020 include a second wiring 32 parallel to the second direction, and the edge of the gate line 200 closest to the second wiring 32, which is close to the second wiring 32, is an inclined edge that is not parallel to the second direction. For example, the second wiring 32 can be a structure in the first connecting portion 330 or a structure in the common electrode 320.

[0222] For example, Figure 7 The capacitance calculation method between the second trace 32 and the inclined edge of the gate line 200 adjacent thereto can refer to the method described in Figure 1 and Figure 5 The calculation method of the capacitance formed between the first trace and the edge of the protrusion in the example shown is as follows: Figure 7 The second parameter C in the capacitance between the second trace 32 and the inclined edge of the gate line 200 adjacent thereto is shown. tft Can satisfy C tft =ln[(L h / d h )×sinθ h +1]. The minimum distance between the orthographic projection of the second trace 32 on the substrate 100 and the orthographic projection of the inclined edge of the gate line 200 on the substrate 100 is d h The angle between the orthographic projection of the second trace 32 on the substrate 100 and the orthographic projection of the inclined edge of the gate line 200 on the substrate 100 is θ h , the length of the second trace 32 is L h The second parameter C tft and relative dielectric constant ε d The product of the width W of the second wiring 32 is the capacitance generated between the second wiring and the inclined edge of the gate line.

[0223] For example, the minimum distance d between the second wiring 32 and the gate line 200 is h The length L of the second trace 32 can be 8.955259 microns. h It may be 13.48103 microns. For example, the line width W of the second trace 32 may be 11.17 microns.

[0224] For example, assuming ε d =1, the minimum distance d between the second wiring 32 and the gate line 200 is set to h and the length L of the second trace 32 h Substitute into the relation ln[(L h / d h )×sinθ h +1] to get the second parameter C tft The value is 0.72487; Substitute the above value and the line width W of the second line 32 into W×ln[(Lh / d h )×sinθ h +1], the capacitance between the second trace 32 and the gate line 200 is 2.537044F. Figure 1 and Figure 5 The capacitance formed by the first trace 31 and the edge of the protrusion is Ch+Cv=3.872386, and the ratio of the capacitances at the two locations can be 1.526338.

[0225] For example, the length L of the second trace 32 is h The minimum value of can be 2 microns, and the minimum distance d between the second wiring 32 and the gate line 200 is h The minimum value can be 2 microns, then substitute the above minimum value into the relationship ln[(L h / d h )×sinθ h +1] to get the second parameter C tft The minimum value of is 0.068323. For example, the length L of the second trace 32 is h The maximum value of can be 30 microns, and the minimum distance d between the second wiring 32 and the gate line 200 is h The maximum value of can be 20 microns, then substitute the above maximum value into the relationship ln[(L h / d h )×sinθ h +1] to get the second parameter C tft The maximum value is 2.451574. Figure 1 and Figure 5 In the example shown, the first parameter C pad The maximum value 4.903148 and the first parameter C pad The minimum value is 0.483114, and the first parameter C can be obtained pad The maximum value of the second parameter C tft The ratio of the maximum value of is 2, the first parameter C pad The minimum value of the second parameter C tft The ratio of the minimum values is 7.071068.

[0226] For example, the second parameter C tft Satisfy 0.01≤C tft ≤2.5. For example, the second parameter C tft Satisfy 0.05≤C tft ≤2. For example, the second parameter C tft Satisfying 0.1≤C tft ≤2.2. For example, the second parameter C tft Satisfy 0.5≤C tft ≤2. For example, the second parameter Ctft Satisfy 1≤C tft ≤1.5. For example, the second parameter C tft Satisfy 1.5≤C tft ≤2.

[0227] For example, the first parameter C pad With the second parameter C tft The ratio satisfies 1≤C pad / C tft ≤7. For example, the first parameter C pad With the second parameter C tft The ratio satisfies 2≤C pad / C tft ≤6. For example, the first parameter C pad With the second parameter C tft The ratio satisfies 3≤C pad / C tft ≤5.

[0228] The embodiment of the present disclosure sets each first routing segment in the first pixel area corresponding to the gate line pad to extend along the first direction or the second direction, thereby reducing the ratio between the first parameter of the first pixel area and the second parameter of the second pixel area, which is beneficial to improving the capacitance consistency of different pixel areas and reducing the parasitic capacitance of the gate line.

[0229] Figure 8A FIG. 1 is a schematic diagram of a partial planar structure of an array substrate provided according to another example of implementation of the present disclosure. Figure 8A As shown, the array substrate includes a base substrate 100, and a plurality of gate lines 200 and a metal layer 300 located on the base substrate 100. The metal layer 300 is located on a side of the plurality of gate lines 200 away from the base substrate 100. The metal layer 300 includes a plurality of data lines 310. The plurality of data lines 310 extend along a first direction and are arranged along a second direction. The plurality of gate lines 200 extend along the second direction and are arranged along the first direction. The first direction and the second direction intersect. The plurality of data lines 310 intersect with the plurality of gate lines 200 to define a plurality of pixel areas 10. Figure 8A A pixel area 10 is schematically shown. For example, Figure 8A As shown, multiple data lines 310 extend along the X direction and are arranged along the Y direction; multiple gate lines 200 extend along the Y direction and are arranged along the X direction. For example, the first direction is the X direction, the second direction is the Y direction, and the first direction is perpendicular to the second direction. However, the present invention is not limited thereto, and the first direction and the second direction may not be perpendicular. For example, the first direction and the second direction may be interchangeable. For example, Figure 8AAs shown, two adjacent data lines 310 and two adjacent gate lines 200 are arranged to cross to define a pixel area 10. For example, a pixel area 10 is a sub-pixel. For example, the array substrate includes a plurality of sub-pixels (a plurality of pixel areas 10), and the plurality of sub-pixels include sub-pixels configured to display different colors of light. For example, the plurality of sub-pixels may include a red sub-pixel configured to display red light, a green sub-pixel configured to display green light, and a blue sub-pixel configured to display blue light. For example, two adjacent sub-pixels arranged in at least one of the first direction and the second direction are respectively sub-pixels configured to display different colors of light.

[0230] like Figure 8A As shown, at least one gate line 200 includes a gate line pad 210 , and the gate line pad 210 includes a protrusion 211 protruding into the pixel area 10 relative to a position on the gate line 200 except the gate line pad 210 .

[0231] like Figure 8A As shown, the metal layer 300 located in the pixel area 10 includes a plurality of routing segments 30 extending along at least a portion of the outline of the pixel area 10. For example, at least some of the routing segments 30 are electrically connected routing segments. For example, the electrically connected routing segments 30 are integrated routing segments. The "integrated routing segments" may refer to routing segments formed by performing the same patterning process on the same metal material layer. The "multiple routing segments 30 extending along the outline of the pixel area 10" may refer to the plurality of routing segments extending along the edge of the data line 310 and the edge of the gate line 200. The plurality of routing segments extending along the outline of the pixel area may be parallel to the edge extension direction of the data line or the gate line, but is not limited thereto. Part of the routing segments may also be non-parallel to a portion of the edge of the gate line or the data line. Whether the routing segments are parallel to the edge of the signal line (including the gate line and the data line) adjacent thereto (in a plan view) may be set according to product requirements.

[0232] like Figure 8A As shown, the multiple traces 30 include multiple first traces 31 surrounding at least a portion of the edge of the protrusion 211. Each first trace 31 extends in the first direction or the second direction, and the multiple first traces 31 are connected end to end to form a stepped structure. The "multiple first traces 31 surrounding at least a portion of the edge of the protrusion 211" mentioned above may refer to the orthographic projections of the multiple first traces 31 on the substrate 100 surrounding at least a portion of the edge of the protrusion 211.

[0233] The embodiment of the present disclosure provides a step structure for the first routing line surrounding the protruding portion of the gate line pad, which helps to improve the consistency of the capacitance generated by the metal layer and the pixel electrode in different pixel areas while reducing the impact of the metal layer on the aperture ratio in the pixel area.

[0234] For example, Figure 8A As shown, the gate line pad 210 is a portion of the gate line 200. For example, along the X direction, the width of the gate line pad 210 is greater than the width of the gate line 200 other than the gate line pad 210. For example, in the width direction, the portion of the gate line pad 210 that protrudes relative to the portion of the gate line 200 other than the gate line pad 210 is a protrusion 211.

[0235] For example, Figure 8A The example shown is the same as Figure 1 The illustrated example differs in that the gate line pad 210 includes protrusions 211 protruding from both sides of the gate line 200. For example, multiple gate line pads 210 may be provided on a single gate line 200, each of which includes a protrusion 211 protruding from both sides of the gate line 200. Of course, this example is not limited thereto, and the gate line pad in this example may also include only a protrusion protruding from one side of the gate line.

[0236] For example, Figure 8A The positional relationship between the gate line pad and the support portion in the array substrate shown can be Figure 1 The positional relationship between the gate line pad and the supporting portion in the array substrate shown is the same and will not be described again here.

[0237] For example, Figure 8A As shown, the edge of the protrusion 211 of the gate line pad 210 includes a fold line or a curve.

[0238] For example, the array substrate further includes a plurality of pixel electrodes 400 and a plurality of thin film transistors 500. In this example, the pixel electrodes included in the array substrate may be Figure 2 The pixel electrodes shown have the same features, which will not be described again here.

[0239] For example, Figure 8A As shown, each pixel region 10 may include a thin film transistor 500, but is not limited thereto. The number of thin film transistors included in each pixel region may be set according to the performance of the required pixel circuit. For example, the number of thin film transistors in each pixel region may be two or more.

[0240] For example, Figure 8A As shown, each thin film transistor 500 includes a first electrode 510, a gate electrode 530, and a second electrode 520. The first electrode 510 and the second electrode 520 overlap with the film layer where the gate line 200 is located. For example, the thin film transistor 500 also includes an active layer, the first electrode 510 and the second electrode 520 overlap with the active layer, and the gate electrode 530 overlaps with the active layer. For example, the gate electrode 530 can be a partial structure of the gate line 200.

[0241] For example, Figure 8AAs shown, the first electrode 510 of the thin film transistor 500 is electrically connected to the pixel electrode 400 through the first connecting portion 330 , and the second electrode 520 of the thin film transistor 500 is electrically connected to the data line 310 .

[0242] For example, Figure 8A As shown, the first electrode 510 of the thin film transistor 500 , the second electrode 520 of the thin film transistor 500 , and the first connecting portion 330 are all structures in the metal layer 300 .

[0243] For example, Figure 8A As shown, the first electrode 510 and the first connecting portion 330 of the thin film transistor 500 can be an integrated structure, but are not limited thereto and can also be a structure in which two parts are electrically connected. For example, the first electrode 510 of the thin film transistor 500 can be the portion where the metal layer 300 overlaps with the active layer, and the first connecting portion 330 can be the portion where the metal layer 300 does not overlap with the active layer.

[0244] For example, the first connection portion 330 overlaps the pixel electrode 400 along a direction perpendicular to the base substrate 100 . For example, a portion of the first connection portion 330 overlaps the pixel electrode 400 along a direction perpendicular to the base substrate 100 .

[0245] For example, Figure 8A As shown, the second connecting portion 340 overlaps the gate line 200 in a direction perpendicular to the base substrate 100. For example, the second connecting portion 340 can be an integrated structure with the second electrode 520 of the thin film transistor 500. For example, the second connecting portion 340 can be an integrated structure with the data line 310. For example, the second electrode 520 of the thin film transistor 500, the second connecting portion 340, and the data line 310 can be an integrated structure. For example, the second connecting portion 340 can extend along the second direction. For example, the second connecting portion 340 is spaced apart from the common electrode 320.

[0246] For example, Figure 8A The array substrate shown is Figure 1 The differences between the array substrates shown include: Figure 8A The gate electrode 530 of the thin film transistor 500 on the array substrate is shown as being located on the gate line 200, excluding the gate line pad 210. For example, the gate electrode 530 of the thin film transistor 500 can be located on one side of the gate line pad 210 in the Y direction. For example, in a direction perpendicular to the base substrate 100, the gate electrode 530 of the thin film transistor 500 does not overlap with the support portion 01, which helps to improve the flatness of the support portion. For example, in a direction perpendicular to the base substrate 100, both the first electrode 510 and the second electrode 520 of the thin film transistor 500 can not overlap with the support portion 01.

[0247] Figure 8A The array substrate shown is Figure 6 The difference between the array substrate shown is that the metal layer does not include a common electrode, and the wiring is all structured in the first connecting portion.

[0248] For example, Figure 8A As shown, all the routing lines 30 may be first routing lines 31 .

[0249] For example, Figure 8A As shown, the first connection portion 330 includes a first trace 31. For example, the first trace 31 may be a structure of the first connection portion 330.

[0250] For example, two first traces 31 connected end to end among the multiple first traces 31 are electrically connected. For example, the multiple first traces 31 can be an integrated structure. For example, the distance between the orthographic projection of the multiple first traces 31 on the base substrate 100 and the orthographic projection of the edge of the protrusion 211 it surrounds on the base substrate is smaller than the distance between the orthographic projection of other traces on the base substrate 100 and the edge of the protrusion 211. For example, the distances between different first traces 31 and the edges of the protrusion 211 they surround can be the same or different. For example, the extension direction of the first trace 31 can be parallel to the edge of the protrusion 211 it surrounds; the extension direction of the first trace 31 can also intersect with the edge of the protrusion 211 it surrounds.

[0251] For example, Figure 8A As shown, any one of the multiple routing segments 30 31 may extend along the first direction or along the second direction.

[0252] The relationship between the first trace included in the first connection portion and the edge of the protruding portion of the gate line pad in this example is the same as Figure 6 The relationship between the first trace included in the first connection portion and the edge of the protruding portion of the gate line pad in the array substrate shown in FIG has the same characteristics, which will not be repeated here. In this example, the capacitance formed between the first trace included in the first connection portion and the edge of the protruding portion can be formed by the same method as Figure 1 and Figure 5 The capacitance formed between the first trace and the edge of the protrusion in the illustrated example is calculated in the same manner.

[0253] For example, Figure 8A The second pixel region included in the array substrate can be Figure 7 The second pixel region shown has the same characteristics, Figure 8A The length ratio of the first connection portion and the area ratio of the first connection portion in the first pixel region and the second pixel region in the array substrate can be respectively Figure 6 and Figure 7 The length ratio of the first connection portions and the area ratio of the first connection portions in the first pixel region and the second pixel region in the array substrate have the same characteristics, which will not be described in detail here.

[0254] For example, Figure 8A The array substrate shown further includes a common electrode line 600, which can be connected to the common electrode line 600. Figure 6 The common electrode lines shown have the same features, which will not be described again here.

[0255] Figure 8B FIG. 1 is a schematic diagram of a partial planar structure of an array substrate provided according to another example of implementation of the present disclosure. Figure 8B As shown, the array substrate includes a base substrate 100, and a plurality of gate lines 200 and a metal layer 300 located on the base substrate 100. The metal layer 300 is located on a side of the plurality of gate lines 200 away from the base substrate 100. The metal layer 300 includes a plurality of data lines 310. The plurality of data lines 310 extend along a first direction and are arranged along a second direction. The plurality of gate lines 200 extend along the second direction and are arranged along the first direction. The first direction and the second direction intersect. The plurality of data lines 310 intersect with the plurality of gate lines 200 to define a plurality of pixel areas 10. Figure 8B A pixel area 10 is schematically shown.

[0256] For example, Figure 8B As shown, multiple data lines 310 extend along the X direction and are arranged along the Y direction; multiple gate lines 200 extend along the Y direction and are arranged along the X direction. For example, the first direction is the X direction, the second direction is the Y direction, and the first direction is perpendicular to the second direction. However, this is not limiting, and the first direction and the second direction may not be perpendicular. For example, the first direction and the second direction may be interchangeable.

[0257] For example, Figure 8B As shown, two adjacent data lines 310 and two adjacent gate lines 200 are arranged to cross to define a pixel area 10. For example, a pixel area 10 is a sub-pixel. For example, the array substrate includes a plurality of sub-pixels (a plurality of pixel areas 10), and the plurality of sub-pixels include sub-pixels configured to display different colors of light. For example, the plurality of sub-pixels may include a red sub-pixel configured to display red light, a green sub-pixel configured to display green light, and a blue sub-pixel configured to display blue light. For example, two adjacent sub-pixels arranged in at least one of the first direction and the second direction are respectively sub-pixels configured to display different colors of light.

[0258] For example, the shape of the pixel area 10 can be a polygon. For example, the shape of the pixel area 10 can be a quadrilateral. For example, the shape of the pixel area 10 can be a rectangle. The present disclosure does not limit this. The shape of the pixel area 10 is related to the shape of the edge of the data line 310 and the edge of the gate line 200.

[0259] For example, each pixel region 10 includes a display area for display, and the area of the display area may be smaller than that of the pixel region 10. For example, the shape of the display area may be the same as that of the pixel region 10, or the shape of the display area may be different from that of the pixel region 10.

[0260] like Figure 8B As shown, the metal layer 300 further includes a common electrode 320 located in the pixel area 10. For example, the common electrode 320 can be a film layer provided in the same layer as the data line 310 and made of the same material.

[0261] like Figure 8B As shown, at least one gate line 200 includes a gate line pad 210 , and the gate line pad 210 includes a protrusion 211 protruding into the pixel area 10 relative to a position on the gate line 200 except the gate line pad 210 .

[0262] For example, Figure 8B As shown, the gate line pad 210 is a portion of the gate line 200. For example, along the X direction, the width of the gate line pad 210 is greater than the width of the gate line 200 other than the gate line pad 210. For example, in the width direction, the portion of the gate line pad 210 that protrudes relative to the portion of the gate line 200 other than the gate line pad 210 is a protrusion 211.

[0263] For example, Figure 8B The example shown is the same as Figure 1 The difference of the illustrated example is that the gate line pad 210 includes protrusions 211 protruding from both sides of the gate line 200. For example, a plurality of gate line pads 210 may be provided on one gate line 200, each of which includes protrusions 211 protruding from both sides of the gate line 200.

[0264] For example, Figure 8B As shown, the gate line pad 210 is configured to be arranged opposite to the support portion 01. For example, in a direction perpendicular to the base substrate 100, the gate line pad 210 overlaps with the support portion 01. For example, the orthographic projection of the gate line pad 210 on the base substrate 100 can overlap with the orthographic projection of the support portion 01 on the base substrate 100. For example, the orthographic projection of the support portion 01 on the base substrate 100 can completely fall within the orthographic projection of the gate line pad 210 on the base substrate 100. For example, the support portion 01 in this example can overlap with the orthographic projection of the gate line pad 210 on the base substrate 100. Figure 1 The supporting portion 01 in the example shown has the same features, which will not be described in detail here. Figure 8B The supporting portion 01 is schematically shown as being disposed on the array substrate, but is not limited thereto. The supporting portion may be disposed on the opposing substrate, and the position of the supporting portion may be set according to product requirements.

[0265] like Figure 8BAs shown, the metal layer 300 located in the pixel area 10 includes a plurality of routing segments 30 extending along at least a portion of the outline of the pixel area 10. For example, at least some of the routing segments 30 are electrically connected routing segments. For example, the electrically connected routing segments 30 are integrated routing segments. The "integrated routing segments" may refer to routing segments formed by performing the same patterning process on the same metal material layer. The "multiple routing segments 30 extending along the outline of the pixel area 10" may refer to the plurality of routing segments extending along the edge of the data line 310 and the edge of the gate line 200. The plurality of routing segments extending along the outline of the pixel area may be parallel to the edge extension direction of the data line or the gate line, but is not limited thereto. Part of the routing segments may also be non-parallel to a portion of the edge of the gate line or the data line. Whether the routing segments are parallel to the edge of the signal line (including the gate line and the data line) adjacent thereto (in a plan view) may be set according to product requirements.

[0266] For example, Figure 8B As shown, the edge of the protrusion 211 of the gate line pad 210 includes a fold line or a curve.

[0267] like Figure 8B As shown, the multiple traces 30 include multiple first traces 31 surrounding at least a portion of the edge of the protrusion 211. Each first trace 31 extends in the first direction or the second direction, and the multiple first traces 31 are connected end to end to form a stepped structure. The "multiple first traces 31 surrounding at least a portion of the edge of the protrusion 211" mentioned above may refer to the orthographic projections of the multiple first traces 31 on the substrate 100 surrounding at least a portion of the edge of the protrusion 211.

[0268] The embodiment of the present disclosure provides a step structure for the first routing line surrounding the protruding portion of the gate line pad, which helps to improve the consistency of the capacitance generated by the metal layer and the pixel electrode in different pixel areas while reducing the impact of the metal layer on the aperture ratio in the pixel area.

[0269] For example, two first traces 31 connected end to end among the multiple first traces 31 are electrically connected. For example, the multiple first traces 31 can be an integrated structure. For example, the distance between the orthographic projection of the multiple first traces 31 on the base substrate 100 and the orthographic projection of the edge of the protrusion 211 it surrounds on the base substrate is smaller than the distance between the orthographic projection of other traces on the base substrate 100 and the edge of the protrusion 211. For example, the distances between different first traces 31 and the edges of the protrusion 211 they surround can be the same or different. For example, the extension direction of the first trace 31 can be parallel to the edge of the protrusion 211 it surrounds; the extension direction of the first trace 31 can also intersect with the edge of the protrusion 211 it surrounds.

[0270] For example, Figure 8BAs shown, the extension direction of the routing lines 30 other than the first routing line 31 in the multi-segment routing line 30 can be parallel to the extension direction of the adjacent data line 310 or gate line 200. For example, the extension direction of the routing lines 30 other than the first routing line 31 in the multi-segment routing line 30 can be parallel to the extension direction of the adjacent data line 310 or gate line 200 near the edge of the routing line 30.

[0271] For example, Figure 8B As shown, the two segments of the first trace 31 located at the outermost ends of the plurality of segments of the first trace 31 can extend along the second direction. For example, the two segments of the first trace 31 located at the outermost ends of the plurality of segments of the first trace 31 can both be electrically connected to the first trace 31. For example, the two segments of the first trace 31 located at the outermost ends of the plurality of segments of the first trace 31 can both be integrated with the first trace 31. However, this is not limiting. One of the two segments of the first trace 31 located at the outermost ends of the plurality of segments of the first trace can also be spaced apart from the first trace.

[0272] For example, Figure 8B As shown, any one of the multiple routing segments 30 31 may extend along the first direction or along the second direction.

[0273] For example, Figure 8B As shown, the shapes of the protrusions 211 located on both sides of the center line of a gate line 200 extending along the Y direction can be the same or different. For example, the shapes of the two protrusions 211 protruding relative to other positions of the gate line 200 included in the same gate line pad 210 can be the same or different. For example, the shape of the two protrusions 211 included in the same gate line pad 210 can both be trapezoidal, with the upper base of the trapezoid protruding into the pixel area 10 relative to the other parts of the gate line 200, and the lower base of the trapezoid can be flush with at least a portion of the edge of the other parts of the gate line 200.

[0274] For example, the array substrate further includes a plurality of pixel electrodes 400 and a plurality of thin film transistors 500. In this example, the pixel electrodes included in the array substrate may be Figure 2 The pixel electrodes shown have the same features, which will not be described again here.

[0275] For example, Figure 8B As shown, each pixel region 10 may include a thin film transistor 500, but is not limited thereto. The number of thin film transistors included in each pixel region may be set according to the performance of the required pixel circuit. For example, the number of thin film transistors in each pixel region may be two or more.

[0276] For example, Figure 8BAs shown, each thin film transistor 500 includes a first electrode 510, a gate electrode 530, and a second electrode 520. The first electrode 510 and the second electrode 520 overlap with the film layer where the gate line 200 is located. For example, the thin film transistor 500 also includes an active layer, the first electrode 510 and the second electrode 520 overlap with the active layer, and the gate electrode 530 overlaps with the active layer. For example, the gate electrode 530 can be a partial structure of the gate line 200.

[0277] For example, Figure 8B As shown, the first electrode 510 of the thin film transistor 500 is electrically connected to the pixel electrode 400 through the first connecting portion 330 , and the second electrode 520 of the thin film transistor 500 is electrically connected to the data line 310 .

[0278] For example, Figure 8B As shown, the first electrode 510 of the thin film transistor 500, the second electrode 520 of the thin film transistor 500, and the first connecting portion 330 are all structures in the metal layer 300, and the first electrode 510 of the thin film transistor 500 and the second electrode 520 of the thin film transistor 500 are both insulated from the common electrode 320. For example, the first electrode 510 of the thin film transistor 500 and the second electrode 520 of the thin film transistor 500 are both spaced apart from the common electrode 320. For example, the first connecting portion 330 is spaced apart from the common electrode 320.

[0279] For example, Figure 8B As shown, the first electrode 510 and the first connecting portion 330 of the thin film transistor 500 can be an integrated structure, but are not limited thereto and can also be a structure in which two parts are electrically connected. For example, the first electrode 510 of the thin film transistor 500 can be the portion where the metal layer 300 overlaps with the active layer, and the first connecting portion 330 can be the portion where the metal layer 300 does not overlap with the active layer.

[0280] For example, along a direction perpendicular to the base substrate 100, both the first connection portion 330 and the common electrode 320 overlap with the pixel electrode 400. For example, along a direction perpendicular to the base substrate 100, a portion of the first connection portion 330 overlaps with the pixel electrode 400. For example, along a direction perpendicular to the base substrate 100, a portion of the common electrode 320 overlaps with the pixel electrode 400.

[0281] For example, Figure 8BAs shown, the second connecting portion 340 overlaps the gate line 200 in a direction perpendicular to the base substrate 100. For example, the second connecting portion 340 can be an integrated structure with the second electrode 520 of the thin film transistor 500. For example, the second connecting portion 340 can be an integrated structure with the data line 310. For example, the second electrode 520 of the thin film transistor 500, the second connecting portion 340, and the data line 310 can be an integrated structure. For example, the second connecting portion 340 can extend along the second direction. For example, the second connecting portion 340 is spaced apart from the common electrode 320.

[0282] For example, Figure 8B The array substrate shown is Figure 1 The differences between the array substrates shown include: Figure 8B The gate electrode 530 of the thin film transistor 500 on the array substrate is shown as being located on the gate line 200, excluding the gate line pad 210. For example, the gate electrode 530 of the thin film transistor 500 can be located on one side of the gate line pad 210 in the Y direction. For example, in a direction perpendicular to the base substrate 100, the gate electrode 530 of the thin film transistor 500 does not overlap with the support portion 01, which helps to improve the flatness of the support portion. For example, in a direction perpendicular to the base substrate 100, both the first electrode 510 and the second electrode 520 of the thin film transistor 500 can not overlap with the support portion 01.

[0283] For example, Figure 8B The second pixel region included in the array substrate can be Figure 7 The second pixel region shown has the same characteristics, Figure 8B The length ratio of the common electrodes in the first pixel region and the second pixel region in the array substrate shown in FIG. Figure 6 and Figure 7 The length ratio of the common electrodes and the area ratio of the common electrodes in the first pixel region and the second pixel region in the array substrate shown have the same characteristics, which will not be described in detail here.

[0284] For example, Figure 8B The array substrate shown is Figure 6 The difference between the array substrate shown is that only the common electrode 320 includes multiple sections of the first wiring 31, and the first connecting portion 330 does not include the first wiring 31. Figure 8B As shown, at least one edge of the protrusion 211 included in the gate line pad 210 is not parallel to the first direction and the second direction.

[0285] For example, Figure 8BAs shown, the two gate lines 200 located on both sides of at least one first pixel region 010 each include a gate line pad 210 protruding into the first pixel region 010, the common electrode 320 includes a first routing line 31 surrounding the protrusion 211 of the gate line pad 210 on one of the two gate lines 200, the first connecting portion 330 surrounding at least a portion of the edge of the protrusion 211 of the gate line pad 210 on the other of the two gate lines 200, and the first connecting portion 330 surrounding at least a portion of the edge of the protrusion 211 includes multiple third routing segments, each third routing segment being parallel to the edge of the protrusion 211 adjacent thereto. For example, the orthographic projection of each third routing segment on the base substrate 100 is parallel to the orthographic projection of the edge of the protrusion 211 adjacent thereto on the base substrate 100. For example, at least one third routing segment is not parallel to either the first direction or the second direction.

[0286] For example, Figure 8B As shown, the gate line pad 210 includes two protrusions 211 protruding toward both sides of the gate line 200 in the X direction, namely, a first protrusion and a second protrusion. The first traces 31 surrounding the first protrusion can all be common electrodes 320, and the traces 30 surrounding the second protrusion are third traces, a portion of which is the common electrode 320, and another portion of which is the first connecting portion 330. For example, all first traces 31 surrounding the first protrusion are traces 30 that are continuously arranged and connected end to end, and the third traces surrounding the second protrusion include two third traces that are separated, at least a portion of which is continuously arranged and connected end to end. For example, the third traces included in the first connecting portion 330 surrounding the second protrusion are continuously arranged and connected end to end.

[0287] The relationship between the first trace included in the common electrode and the edge of the protruding portion of the gate line pad in this example is the same as Figure 6 The relationship between the first trace included in the common electrode and the edge of the protruding portion of the gate line pad in the array substrate shown has the same characteristics, which will not be repeated here. In this example, the capacitance formed between the first trace included in the common electrode and the edge of the protruding portion can be formed by the same method as Figure 1 and Figure 5 The capacitance formed between the first trace and the edge of the protrusion in the illustrated example is calculated in the same manner.

[0288] For example, Figure 8B As shown, the capacitance between the third trace parallel to the edge of the protrusion 211 and the edge of the protrusion 211 satisfies C=ε d ×W×L / d. Among them, ε d is the relative dielectric constant, W is the width of the third trace, L is the length of each third trace, and d is the distance between the third trace and the edge of the protrusion 211. For example, when the third trace is parallel to the edge of the protrusion 211, the capacitance C between the two can be 6.68.

[0289] For example, Figure 8B As shown, the first connection portion 330 includes multiple third routing lines, which may include third routing lines parallel to the first direction, third routing lines parallel to the second direction, and third routing lines not parallel to either the first direction or the second direction.

[0290] For example, Figure 8B As shown, the array substrate further includes a common electrode line 600 . The common electrode line 600 is provided in the same layer as the plurality of gate lines 200 , and the common electrode 320 is electrically connected to the common electrode line 600 .

[0291] For example, Figure 8B As shown, an insulating layer (not shown) is provided between the common electrode 320 and the common electrode line 600 , and the common electrode 320 is electrically connected to the common electrode line 600 through a via hole 11 in the insulating layer.

[0292] For example, Figure 8B As shown, the common electrode 320 in at least one pixel region 10 may be an integrated structure, and the common electrode 320 in the pixel region 10 may be electrically connected to the common electrode line 600 through at least one via hole 11. However, the present invention is not limited thereto, and the common electrode in at least one pixel region may also be configured as at least two structures separated from each other, each structure being electrically connected to the common electrode line.

[0293] For example, Figure 8B As shown, the common electrode lines 600 extend along the second direction. For example, the gate lines 200 and the common electrode lines 600 may be alternately arranged along the first direction. For example, in a direction perpendicular to the base substrate 100, the common electrode lines 600 overlap with the pixel electrodes 400.

[0294] For example, Figure 8B As shown, along a direction perpendicular to the base substrate 100 , the first connection portion 330 overlaps the common electrode line 600 .

[0295] For example, Figure 8B As shown, the common electrode 320 further includes a third sub-common electrode 323 extending along the first direction. The third sub-common electrode 323 and at least a portion of the first connecting portion 330 extending along the first direction are located on the same straight line, thereby dividing the pixel area 10 into two sub-pixel areas. For example, the third sub-common electrode 323 and the first connecting portion 330 are configured to work together to divide a pixel area into two sub-pixel areas. Of course, the embodiments of the present disclosure are not limited to this. The third sub-common electrode and the first connecting portion may also be located in a direction that is not aligned with the same straight line.

[0296] For example, Figure 8BAs shown, a pixel region 10 includes two sub-pixel regions arranged along the Y direction. For example, the shapes of the pixel electrodes in different sub-pixel regions can be the same or different. For example, the shapes of different sub-pixel regions in the same pixel region 10 can be the same or different. For example, the areas of different sub-pixel regions in the same pixel region 10 can be the same or different.

[0297] For example, Figure 8B As shown, at least a portion of the first connection portion 330 and the third sub-common electrode 323 are respectively located on either side of the common electrode line 600. For example, the first connection portion 330 includes a portion overlapping with the common electrode line 600 and another portion not overlapping with the common electrode line 600. The portion of the first connection portion 330 not overlapping with the common electrode line 600 and the third sub-common electrode 323 are respectively located on either side of the common electrode line 600. Of course, the embodiments of the present disclosure are not limited to this. The first connection portion may also include two portions located on either side of the common electrode line, in which case the third sub-common electrode may not be provided. Alternatively, the portion of the first connection portion located on the same side of the common electrode line as the third sub-common electrode may be shorter to ensure spacing from the third sub-common electrode. For example, when the first connection portion includes two portions located on either side of the common electrode line, the widths of the two portions may be equal or unequal. For example, when the first connection portion includes two portions located on either side of the common electrode line, the width of the portion of the first connection portion located on the same side of the common electrode line as the third sub-common electrode may be the same as the width of the third sub-common electrode, but this is not limiting and the widths of the two portions may also be different.

[0298] Figure 9 FIG. 1 is a schematic diagram of a partial planar structure of an array substrate provided according to another example of implementation of the present disclosure. Figure 9 As shown, the array substrate includes a base substrate 100, and a plurality of gate lines 200 and a metal layer 300 located on the base substrate 100. The metal layer 300 is located on a side of the plurality of gate lines 200 away from the base substrate 100. The metal layer 300 includes a plurality of data lines 310. The plurality of data lines 310 extend along a first direction and are arranged along a second direction. The plurality of gate lines 200 extend along the second direction and are arranged along the first direction. The first direction and the second direction intersect. The plurality of data lines 310 intersect with the plurality of gate lines 200 to define a plurality of pixel areas 10. Figure 9 A pixel area 10 is schematically shown.

[0299] For example, Figure 9 As shown, multiple data lines 310 extend along the X direction and are arranged along the Y direction; multiple gate lines 200 extend along the Y direction and are arranged along the X direction. For example, the first direction is the X direction, the second direction is the Y direction, and the first direction is perpendicular to the second direction. However, this is not limiting, and the first direction and the second direction may not be perpendicular. For example, the first direction and the second direction may be interchangeable.

[0300] For example, Figure 9 As shown, two adjacent data lines 310 and two adjacent gate lines 200 are arranged to cross to define a pixel area 10. For example, a pixel area 10 is a sub-pixel. For example, the array substrate includes a plurality of sub-pixels (a plurality of pixel areas 10), and the plurality of sub-pixels include sub-pixels configured to display different colors of light. For example, the plurality of sub-pixels may include a red sub-pixel configured to display red light, a green sub-pixel configured to display green light, and a blue sub-pixel configured to display blue light. For example, two adjacent sub-pixels arranged in at least one of the first direction and the second direction are respectively sub-pixels configured to display different colors of light.

[0301] For example, the shape of the pixel area 10 can be a polygon. For example, the shape of the pixel area 10 can be a quadrilateral. For example, the shape of the pixel area 10 can be a rectangle. The present disclosure does not limit this. The shape of the pixel area 10 is related to the shape of the edge of the data line 310 and the edge of the gate line 200.

[0302] For example, each pixel region 10 includes a display area for display, and the area of the display area may be smaller than that of the pixel region 10. For example, the shape of the display area may be the same as that of the pixel region 10, or the shape of the display area may be different from that of the pixel region 10.

[0303] like Figure 9 As shown, the metal layer 300 further includes a common electrode 320 located in the pixel area 10. For example, the common electrode 320 can be a film layer provided in the same layer as the data line 310 and made of the same material.

[0304] like Figure 9 As shown, at least one gate line 200 includes a gate line pad 210 , and the gate line pad 210 includes a protrusion 211 protruding into the pixel area 10 relative to a position on the gate line 200 except the gate line pad 210 .

[0305] For example, Figure 9 As shown, the gate line pad 210 is a portion of the gate line 200. For example, along the X direction, the width of the gate line pad 210 is greater than the width of the gate line 200 other than the gate line pad 210. For example, in the width direction, the portion of the gate line pad 210 that protrudes relative to the portion of the gate line 200 other than the gate line pad 210 is a protrusion 211.

[0306] For example, Figure 9 The example shown is the same as Figure 1The difference of the illustrated example is that the gate line pad 210 includes protrusions 211 protruding from both sides of the gate line 200. For example, a plurality of gate line pads 210 may be provided on one gate line 200, each of which includes protrusions 211 protruding from both sides of the gate line 200.

[0307] For example, Figure 9 As shown, the gate line pad 210 is configured to be arranged opposite to the support portion 01. For example, in a direction perpendicular to the base substrate 100, the gate line pad 210 overlaps with the support portion 01. For example, the orthographic projection of the gate line pad 210 on the base substrate 100 can overlap with the orthographic projection of the support portion 01 on the base substrate 100. For example, the orthographic projection of the support portion 01 on the base substrate 100 can completely fall within the orthographic projection of the gate line pad 210 on the base substrate 100. For example, the support portion 01 in this example can overlap with the orthographic projection of the gate line pad 210 on the base substrate 100. Figure 1 The supporting portion 01 in the example shown has the same features, which will not be described in detail here. Figure 9 The supporting portion 01 is schematically shown as being disposed on the array substrate, but is not limited thereto. The supporting portion may be disposed on the opposing substrate, and the position of the supporting portion may be set according to product requirements.

[0308] like Figure 9 As shown, the metal layer 300 located in the pixel area 10 includes a plurality of routing segments 30 extending along at least a portion of the outline of the pixel area 10. For example, at least some of the routing segments 30 are electrically connected routing segments. For example, the electrically connected routing segments 30 are integrated routing segments. The "integrated routing segments" may refer to routing segments formed by performing the same patterning process on the same metal material layer. The "multiple routing segments 30 extending along the outline of the pixel area 10" may refer to the plurality of routing segments extending along the edge of the data line 310 and the edge of the gate line 200. The plurality of routing segments extending along the outline of the pixel area may be parallel to the edge extension direction of the data line or the gate line, but is not limited thereto. Part of the routing segments may also be non-parallel to a portion of the edge of the gate line or the data line. Whether the routing segments are parallel to the edge of the signal line (including the gate line and the data line) adjacent thereto (in a plan view) may be set according to product requirements.

[0309] For example, Figure 9 As shown, the edge of the protrusion 211 of the gate line pad 210 includes a fold line or a curve.

[0310] like Figure 9As shown, the multiple traces 30 include multiple first traces 31 surrounding at least a portion of the edge of the protrusion 211. Each first trace 31 extends in the first direction or the second direction, and the multiple first traces 31 are connected end to end to form a stepped structure. The "multiple first traces 31 surrounding at least a portion of the edge of the protrusion 211" mentioned above may refer to the orthographic projections of the multiple first traces 31 on the substrate 100 surrounding at least a portion of the edge of the protrusion 211.

[0311] The embodiment of the present disclosure provides a step structure for the first routing line surrounding the protruding portion of the gate line pad, which helps to improve the consistency of the capacitance generated by the metal layer and the pixel electrode in different pixel areas while reducing the impact of the metal layer on the aperture ratio in the pixel area.

[0312] For example, two first traces 31 connected end to end among the multiple first traces 31 are electrically connected. For example, the multiple first traces 31 can be an integrated structure. For example, the distance between the orthographic projection of the multiple first traces 31 on the base substrate 100 and the orthographic projection of the edge of the protrusion 211 it surrounds on the base substrate is smaller than the distance between the orthographic projection of other traces on the base substrate 100 and the edge of the protrusion 211. For example, the distances between different first traces 31 and the edges of the protrusion 211 they surround can be the same or different. For example, the extension direction of the first trace 31 can be parallel to the edge of the protrusion 211 it surrounds; the extension direction of the first trace 31 can also intersect with the edge of the protrusion 211 it surrounds.

[0313] For example, Figure 9 As shown, the extension direction of the routing lines 30 other than the first routing line 31 in the multi-segment routing line 30 can be parallel to the extension direction of the adjacent data line 310 or gate line 200. For example, the extension direction of the routing lines 30 other than the first routing line 31 in the multi-segment routing line 30 can be parallel to the extension direction of the adjacent data line 310 or gate line 200 near the edge of the routing line 30.

[0314] For example, Figure 9 As shown, the two segments of the first trace 31 located at the outermost ends of the plurality of segments of the first trace 31 can extend along the second direction. For example, the two segments of the first trace 31 located at the outermost ends of the plurality of segments of the first trace 31 can both be electrically connected to the first trace 31. For example, the two segments of the first trace 31 located at the outermost ends of the plurality of segments of the first trace 31 can both be integrated with the first trace 31. However, this is not limiting. One of the two segments of the first trace 31 located at the outermost ends of the plurality of segments of the first trace can also be spaced apart from the first trace.

[0315] For example, Figure 9 As shown, any one of the multiple traces 30 may extend along the first direction or along the second direction.

[0316] For example, Figure 9 As shown, the shapes of the protrusions 211 located on both sides of the center line of a gate line 200 extending along the Y direction can be the same or different. For example, the shapes of the two protrusions 211 protruding relative to other positions of the gate line 200 included in the same gate line pad 210 can be the same or different. For example, the shape of the two protrusions 211 included in the same gate line pad 210 can both be trapezoidal, with the upper base of the trapezoid protruding into the pixel area 10 relative to the other parts of the gate line 200, and the lower base of the trapezoid can be flush with at least a portion of the edge of the other parts of the gate line 200.

[0317] For example, Figure 9 As shown, the gate line 200 is provided with protrusions 211 on both sides in the X direction. At this time, in one pixel area 10 , the multiple first routing segments 31 in the multiple routing segments 30 are concentrated at two locations in the multiple routing segments 30 .

[0318] For example, the array substrate further includes a plurality of pixel electrodes 400 and a plurality of thin film transistors 500. In this example, the pixel electrodes included in the array substrate may be Figure 2 The pixel electrodes shown have the same features, which will not be described again here.

[0319] For example, Figure 9 As shown, each pixel region 10 may include a thin film transistor 500, but is not limited thereto. The number of thin film transistors included in each pixel region may be set according to the performance of the required pixel circuit. For example, the number of thin film transistors in each pixel region may be two or more.

[0320] For example, Figure 9 As shown, each thin film transistor 500 includes a first electrode 510, a gate electrode 530, and a second electrode 520. The first electrode 510 and the second electrode 520 overlap with the film layer where the gate line 200 is located. For example, the thin film transistor 500 also includes an active layer, the first electrode 510 and the second electrode 520 overlap with the active layer, and the gate electrode 530 overlaps with the active layer. For example, the gate electrode 530 can be a partial structure of the gate line 200.

[0321] For example, Figure 9 As shown, the first electrode 510 of the thin film transistor 500 is electrically connected to the pixel electrode 400 through the first connecting portion 330 , and the second electrode 520 of the thin film transistor 500 is electrically connected to the data line 310 .

[0322] For example, Figure 9As shown, the first electrode 510 of the thin film transistor 500, the second electrode 520 of the thin film transistor 500, and the first connecting portion 330 are all structures in the metal layer 300, and the first electrode 510 of the thin film transistor 500 and the second electrode 520 of the thin film transistor 500 are both insulated from the common electrode 320. For example, the first electrode 510 of the thin film transistor 500 and the second electrode 520 of the thin film transistor 500 are both spaced apart from the common electrode 320. For example, the first connecting portion 330 is spaced apart from the common electrode 320.

[0323] For example, Figure 9 As shown, the first electrode 510 and the first connecting portion 330 of the thin film transistor 500 can be an integrated structure, but are not limited thereto and can also be a structure in which two parts are electrically connected. For example, the first electrode 510 of the thin film transistor 500 can be the portion where the metal layer 300 overlaps with the active layer, and the first connecting portion 330 can be the portion where the metal layer 300 does not overlap with the active layer.

[0324] For example, along a direction perpendicular to the base substrate 100, both the first connection portion 330 and the common electrode 320 overlap with the pixel electrode 400. For example, along a direction perpendicular to the base substrate 100, a portion of the first connection portion 330 overlaps with the pixel electrode 400. For example, along a direction perpendicular to the base substrate 100, a portion of the common electrode 320 overlaps with the pixel electrode 400.

[0325] For example, Figure 9 As shown, the second connecting portion 340 overlaps the gate line 200 in a direction perpendicular to the base substrate 100. For example, the second connecting portion 340 can be an integrated structure with the second electrode 520 of the thin film transistor 500. For example, the second connecting portion 340 can be an integrated structure with the data line 310. For example, the second electrode 520 of the thin film transistor 500, the second connecting portion 340, and the data line 310 can be an integrated structure. For example, the second connecting portion 340 can extend along the second direction. For example, the second connecting portion 340 is spaced apart from the common electrode 320.

[0326] For example, Figure 9 The array substrate shown is Figure 1 The differences between the array substrates shown include: Figure 9The gate electrode 530 of the thin film transistor 500 on the array substrate is shown as being located on the gate line 200, excluding the gate line pad 210. For example, the gate electrode 530 of the thin film transistor 500 can be located on one side of the gate line pad 210 in the Y direction. For example, in a direction perpendicular to the base substrate 100, the gate electrode 530 of the thin film transistor 500 does not overlap with the support portion 01, which helps to improve the flatness of the support portion. For example, in a direction perpendicular to the base substrate 100, both the first electrode 510 and the second electrode 520 of the thin film transistor 500 can not overlap with the support portion 01.

[0327] For example, Figure 9 The second pixel region included in the array substrate can be Figure 7 The second pixel region shown has the same characteristics, Figure 9 The length ratio of the common electrodes in the first pixel region and the second pixel region in the array substrate shown in FIG. Figure 6 and Figure 7 The length ratio of the common electrodes and the area ratio of the common electrodes in the first pixel region and the second pixel region in the array substrate shown have the same characteristics, which will not be described in detail here.

[0328] For example, Figure 9 The array substrate shown is Figure 8B The difference between the array substrate shown is that the first connection portion 330 and the common electrode 320 both include a first trace 31. Figure 9 As shown, at least one edge of the protrusion 211 included in the gate line pad 210 is not parallel to the first direction and the second direction.

[0329] For example, Figure 9 As shown, two gate lines 200 located on both sides of at least one first pixel region 010 each include a gate line pad 210 protruding into the first pixel region 010. The first connecting portion 330 includes a first routing line 31 surrounding a portion of the edge of the protrusion 211 of the gate line pad 210 on one of the two gate lines 200. The common electrode 320 includes a first routing line 31 surrounding another portion of the edge of the protrusion 211 of the gate line pad 210. The common electrode 320 also includes a routing line 30 surrounding the edge of the protrusion 211 of the gate line pad 210 on the other of the two gate lines 200. The common electrode 320 surrounding the edge of the protrusion 211 includes multiple third routing lines, each third routing line being parallel to the edge of the protrusion 211 adjacent thereto. For example, the orthographic projection of each third routing line on the base substrate 100 is parallel to the orthographic projection of the edge of the protrusion 211 adjacent thereto on the base substrate 100. For example, at least one third routing line is not parallel to either the first direction or the second direction.

[0330] For example, Figure 9As shown, the gate line pad 210 includes two protrusions 211 protruding toward both sides of the gate line 200 in the X direction, namely, a first protrusion and a second protrusion. A portion of the first trace 31 surrounding the first protrusion is a first connecting portion 330, another portion of the first trace 31 surrounding the first protrusion is a common electrode 320, and the trace 30 surrounding the second protrusion is a third trace, all of which are common electrodes 320. For example, all third traces surrounding the second protrusion are traces 30 that are continuously arranged and connected end to end. The first trace 31 surrounding the first protrusion includes two separated portions of first traces 31, at least a portion of which are continuously arranged and connected end to end. For example, the first trace 31 included in the first connecting portion 330 surrounding the first protrusion is continuously arranged and connected end to end. For example, the first trace 31 included in the common electrode 320 surrounding the first protrusion is continuously arranged and connected end to end.

[0331] The relationship between the first trace included in the common electrode and the edge of the protruding portion of the gate line pad in this example is the same as Figure 6 The relationship between the first trace included in the common electrode in the array substrate and the edge of the protruding portion of the gate line pad has the same characteristics, which will not be described in detail here.

[0332] In this example, the capacitance formed between the first trace included in the common electrode and the edge of the protruding portion can be formed by Figure 1 and Figure 5 The capacitance formed between the first trace and the edge of the protrusion in the example shown is calculated in the same way. The capacitance between the third trace and the edge of the protrusion in this example can be calculated in the same way. Figure 8B The capacitance between the third trace and the edge of the protrusion is calculated in the same manner and will not be repeated here.

[0333] For example, Figure 9 As shown, the array substrate further includes a common electrode line 600 . The common electrode line 600 is provided in the same layer as the plurality of gate lines 200 , and the common electrode 320 is electrically connected to the common electrode line 600 .

[0334] For example, Figure 9 As shown, an insulating layer (not shown) is provided between the common electrode 320 and the common electrode line 600 , and the common electrode 320 is electrically connected to the common electrode line 600 through a via hole 11 in the insulating layer.

[0335] For example, Figure 9 As shown, the common electrode 320 in at least one pixel region 10 may be an integrated structure, and the common electrode 320 in the pixel region 10 may be electrically connected to the common electrode line 600 through at least one via hole 11. However, the present invention is not limited thereto, and the common electrode in at least one pixel region may also be configured as at least two structures separated from each other, each structure being electrically connected to the common electrode line.

[0336] For example, Figure 9 As shown, the common electrode lines 600 extend along the second direction. For example, the gate lines 200 and the common electrode lines 600 may be alternately arranged along the first direction. For example, in a direction perpendicular to the base substrate 100, the common electrode lines 600 overlap with the pixel electrodes 400.

[0337] For example, Figure 9 As shown, along a direction perpendicular to the base substrate 100 , the first connection portion 330 overlaps the common electrode line 600 .

[0338] For example, Figure 9 As shown, the common electrode 320 further includes a third sub-common electrode 323 extending along the first direction. The third sub-common electrode 323 and at least a portion of the first connecting portion 330 extending along the first direction are located on the same straight line, thereby dividing the pixel area 10 into two sub-pixel areas. For example, the third sub-common electrode 323 and the first connecting portion 330 are configured to work together to divide a pixel area into two sub-pixel areas. Of course, the embodiments of the present disclosure are not limited to this. The third sub-common electrode and the first connecting portion may also be located in a direction that is not aligned with the same straight line.

[0339] For example, Figure 9 As shown, a pixel region 10 includes two sub-pixel regions arranged along the Y direction. For example, the shapes of the pixel electrodes in different sub-pixel regions can be the same or different. For example, the shapes of different sub-pixel regions in the same pixel region 10 can be the same or different. For example, the areas of different sub-pixel regions in the same pixel region 10 can be the same or different.

[0340] For example, Figure 9As shown, at least a portion of the first connection portion 330 and the third sub-common electrode 323 are respectively located on either side of the common electrode line 600. For example, the first connection portion 330 includes a portion overlapping with the common electrode line 600 and another portion not overlapping with the common electrode line 600. The portion of the first connection portion 330 not overlapping with the common electrode line 600 and the third sub-common electrode 323 are respectively located on either side of the common electrode line 600. Of course, the embodiments of the present disclosure are not limited to this. The first connection portion may also include two portions located on either side of the common electrode line, in which case the third sub-common electrode may not be provided. Alternatively, the portion of the first connection portion located on the same side of the common electrode line as the third sub-common electrode may be shorter to ensure spacing from the third sub-common electrode. For example, when the first connection portion includes two portions located on either side of the common electrode line, the widths of the two portions may be equal or unequal. For example, when the first connection portion includes two portions located on either side of the common electrode line, the width of the portion of the first connection portion located on the same side of the common electrode line as the third sub-common electrode may be the same as the width of the third sub-common electrode, but this is not limiting and the widths of the two portions may also be different.

[0341] Figure 10 FIG. 1 is a schematic diagram of a partial planar structure of an array substrate provided according to another example of implementation of the present disclosure. Figure 10 As shown, the array substrate includes a base substrate 100, and a plurality of gate lines 200 and a metal layer 300 located on the base substrate 100. The metal layer 300 is located on a side of the plurality of gate lines 200 away from the base substrate 100. The metal layer 300 includes a plurality of data lines 310. The plurality of data lines 310 extend along a first direction and are arranged along a second direction. The plurality of gate lines 200 extend along the second direction and are arranged along the first direction. The first direction and the second direction intersect. The plurality of data lines 310 intersect with the plurality of gate lines 200 to define a plurality of pixel areas 10.

[0342] like Figure 10 As shown, the metal layer 300 further includes a common electrode 320 located in the pixel area 10. For example, the common electrode 320 can be a film layer provided in the same layer as the data line 310 and made of the same material.

[0343] like Figure 10 As shown, at least one gate line 200 includes a gate line pad 210 , and the gate line pad 210 includes a protrusion 211 protruding into the pixel area 10 relative to a position on the gate line 200 except the gate line pad 210 .

[0344] like Figure 10As shown, the metal layer 300 located in the pixel region 10 includes multiple routing segments 30 extending along at least a portion of the outline of the pixel region 10. The multiple routing segments 30 include multiple first routing segments 31 surrounding at least a portion of the edge of the protrusion 211. Each first routing segment 31 extends along the first direction or the second direction, and the multiple first routing segments 31 are connected end to end to form a stepped structure. By configuring the first routing segments surrounding the protrusion of the gate line pad into a stepped structure, the disclosed embodiment improves the consistency of the capacitance generated by the metal layer and the pixel electrode in different pixel regions while reducing the impact of the metal layer on the aperture ratio in the pixel region.

[0345] The array substrate provided in this example is Figure 6 The difference between the array substrates shown is that the shape of the gate line pad 210 is different. Figure 10 As shown, the gate line pad 210 may be in a polygonal shape. For example, the protrusion 211 may be in a polygonal shape. For example, the protrusion 211 may be in an irregular shape.

[0346] For example, the distribution of the first traces 31 around at least a portion of the edge of the protrusion 211 of the gate line pad 210 in the array substrate provided in this example can be the same as Figure 6 The distribution pattern of the first trace shown is the same, and can also be compared with Figure 8B The distribution pattern of the first routing line shown in or 9 is the same, and the embodiment of the present disclosure is not limited to this.

[0347] The array substrate provided in this example includes the base substrate, data lines, common electrode lines, thin film transistors, first connecting parts, second connecting parts, and pixel electrodes. Figures 1 to 9 The structures of the base substrate, data lines, common electrode lines, thin film transistors, first connecting parts, second connecting parts and pixel electrodes in the array substrate shown have the same features and are not described in detail here.

[0348] Figure 11 FIG. 1 is a schematic diagram of a partial planar structure of an array substrate provided according to another example of implementation of the present disclosure. Figure 11 As shown, the array substrate includes a base substrate 100, and a plurality of gate lines 200 and a metal layer 300 located on the base substrate 100. The metal layer 300 is located on a side of the plurality of gate lines 200 away from the base substrate 100. The metal layer 300 includes a plurality of data lines 310. The plurality of data lines 310 extend along a first direction and are arranged along a second direction. The plurality of gate lines 200 extend along the second direction and are arranged along the first direction. The first direction and the second direction intersect. The plurality of data lines 310 intersect with the plurality of gate lines 200 to define a plurality of pixel areas 10.

[0349] like Figure 11As shown, the metal layer 300 further includes a common electrode 320 located in the pixel area 10. For example, the common electrode 320 can be a film layer provided in the same layer as the data line 310 and made of the same material.

[0350] like Figure 11 As shown, at least one gate line 200 includes a gate line pad 210 , and the gate line pad 210 includes a protrusion 211 protruding into the pixel area 10 relative to a position on the gate line 200 except the gate line pad 210 .

[0351] like Figure 11 As shown, the metal layer 300 located in the pixel region 10 includes multiple routing segments 30 extending along at least a portion of the outline of the pixel region 10. The multiple routing segments 30 include multiple first routing segments 31 surrounding at least a portion of the edge of the protrusion 211. Each first routing segment 31 extends along the first direction or the second direction, and the multiple first routing segments 31 are connected end to end to form a stepped structure. By configuring the first routing segments surrounding the protrusion of the gate line pad into a stepped structure, the disclosed embodiment improves the consistency of the capacitance generated by the metal layer and the pixel electrode in different pixel regions while reducing the impact of the metal layer on the aperture ratio in the pixel region.

[0352] The array substrate provided in this example is Figure 6 The difference between the array substrates shown is that the shape of the gate line pad 210 is different. Figure 11 As shown, the gate line pad 210 may be in a polygonal shape. For example, the protrusion 211 may be in a polygonal shape. For example, the protrusion 211 may be in an irregular shape.

[0353] For example, the distribution of the first traces 31 around at least a portion of the edge of the protrusion 211 of the gate line pad 210 in the array substrate provided in this example can be the same as Figure 6 The distribution pattern of the first trace shown is the same, and can also be compared with Figure 8B The distribution pattern of the first routing line shown in or 9 is the same, and the embodiment of the present disclosure is not limited to this.

[0354] The array substrate provided in this example includes the base substrate, data lines, common electrode lines, thin film transistors, first connecting parts, second connecting parts, and pixel electrodes. Figures 1 to 9 The structures of the base substrate, data lines, common electrode lines, thin film transistors, first connecting parts, second connecting parts and pixel electrodes in the array substrate shown have the same features and are not described in detail here.

[0355] Figure 12 FIG. 1 is a schematic diagram of a partial planar structure of an array substrate provided according to another example of implementation of the present disclosure. Figure 12As shown, the array substrate includes a base substrate 100, and a plurality of gate lines 200 and a metal layer 300 located on the base substrate 100. The metal layer 300 is located on a side of the plurality of gate lines 200 away from the base substrate 100. The metal layer 300 includes a plurality of data lines 310. The plurality of data lines 310 extend along a first direction and are arranged along a second direction. The plurality of gate lines 200 extend along the second direction and are arranged along the first direction. The first direction and the second direction intersect. The plurality of data lines 310 intersect with the plurality of gate lines 200 to define a plurality of pixel areas 10.

[0356] like Figure 12 As shown, the metal layer 300 further includes a common electrode 320 located in the pixel area 10. For example, the common electrode 320 can be a film layer provided in the same layer as the data line 310 and made of the same material.

[0357] like Figure 12 As shown, at least one gate line 200 includes a gate line pad 210 , and the gate line pad 210 includes a protrusion 211 protruding into the pixel area 10 relative to a position on the gate line 200 except the gate line pad 210 .

[0358] like Figure 12 As shown, the metal layer 300 located in the pixel region 10 includes multiple routing segments 30 extending along at least a portion of the outline of the pixel region 10. The multiple routing segments 30 include multiple first routing segments 31 surrounding at least a portion of the edge of the protrusion 211. Each first routing segment 31 extends along the first direction or the second direction, and the multiple first routing segments 31 are connected end to end to form a stepped structure. By configuring the first routing segments surrounding the protrusion of the gate line pad into a stepped structure, the disclosed embodiment improves the consistency of the capacitance generated by the metal layer and the pixel electrode in different pixel regions while reducing the impact of the metal layer on the aperture ratio in the pixel region.

[0359] The array substrate provided in this example includes the base substrate, data lines, gate lines, thin film transistors, first connecting parts, second connecting parts, and pixel electrodes. Figures 1 to 11 The structures of the base substrate, data lines, gate lines, thin film transistors, first connecting parts, second connecting parts and pixel electrodes in the array substrate shown have the same features and are not described in detail here.

[0360] The array substrate provided in this example is Figure 1The difference between the illustrated array substrate and the illustrated array substrate is that the common electrode 320 further includes a third sub-common electrode 323 extending along the first direction and two fourth sub-common electrodes 324 extending along the second direction. The two fourth sub-common electrodes 324 are located on either side of the first connecting portion 330 in the second direction, and the third sub-common electrode 323 and at least a portion of the first connecting portion 330 are located on the same straight line. For example, the common electrode 320 including the third sub-common electrode 323 and the fourth sub-common electrode 324 can divide a pixel region 10 into four sub-pixel regions. For example, the four sub-pixel regions can be arranged in a 2*2 array.

[0361] In this example, the third sub-common electrode 323 can be connected to Figure 1 The third sub-common electrode 323 shown has the same features, which will not be described again.

[0362] For example, Figure 12 As shown, the orthographic projection of the fourth sub-common electrode 324 on the base substrate 100 overlaps with the orthographic projection of the common electrode line 600 on the base substrate 100 .

[0363] For example, the distribution of the first traces 31 around at least a portion of the edge of the protrusion 211 of the gate line pad 210 in the array substrate provided in this example may not be limited to Figure 1 For example, the distribution of the first trace 31 in the array substrate provided in this example can be the same as Figure 6 The distribution pattern of the first trace is the same as shown, and can also be compared with Figure 8B The distribution pattern of the first routing line shown in or 9 is the same, and the embodiment of the present disclosure is not limited to this.

[0364] Figure 13 FIG. 1 is a schematic diagram of a partial planar structure of an array substrate provided according to another example of implementation of the present disclosure. Figure 13 As shown, the array substrate includes a base substrate 100, and a plurality of gate lines 200 and a metal layer 300 located on the base substrate 100. The metal layer 300 is located on a side of the plurality of gate lines 200 away from the base substrate 100. The metal layer 300 includes a plurality of data lines 310. The plurality of data lines 310 extend along a first direction and are arranged along a second direction. The plurality of gate lines 200 extend along the second direction and are arranged along the first direction. The first direction and the second direction intersect. The plurality of data lines 310 intersect with the plurality of gate lines 200 to define a plurality of pixel areas 10.

[0365] like Figure 13 As shown, the metal layer 300 further includes a common electrode 320 located in the pixel area 10. For example, the common electrode 320 can be a film layer provided in the same layer as the data line 310 and made of the same material.

[0366] like Figure 13As shown, at least one gate line 200 includes a gate line pad 210 , and the gate line pad 210 includes a protrusion 211 protruding into the pixel area 10 relative to a position on the gate line 200 except the gate line pad 210 .

[0367] like Figure 13 As shown, the metal layer 300 located in the pixel region 10 includes multiple routing segments 30 extending along at least a portion of the outline of the pixel region 10. The multiple routing segments 30 include multiple first routing segments 31 surrounding at least a portion of the edge of the protrusion 211. Each first routing segment 31 extends along the first direction or the second direction, and the multiple first routing segments 31 are connected end to end to form a stepped structure. By configuring the first routing segments surrounding the protrusion of the gate line pad into a stepped structure, the disclosed embodiment improves the consistency of the capacitance generated by the metal layer and the pixel electrode in different pixel regions while reducing the impact of the metal layer on the aperture ratio in the pixel region.

[0368] The array substrate provided in this example includes a base substrate, a data line, a common electrode, a thin film transistor, a first connecting portion, a second connecting portion, and a pixel electrode. Figures 1 to 11 The structures of the base substrate, data lines, common electrodes, thin film transistors, first connecting portions, second connecting portions and pixel electrodes in the array substrate shown have the same features and are not described in detail here.

[0369] The array substrate provided in this example is Figure 1 The difference between the array substrate shown is that the gate line 200 includes a hollow pattern 201, and the data line 310 overlaps the hollow pattern 201. For example, the hollow pattern 201 includes a single opening. For example, the hollow pattern 201 may include multiple openings. In the array substrate provided in this example, by providing a hollow pattern in the gate line and overlapping the hollow pattern of the gate line with the data line, the overlapping area of the data line and the gate line can be reduced, thereby reducing the capacitance generated when the two overlap.

[0370] For example, the distribution of the first traces 31 around at least a portion of the edge of the protrusion 211 of the gate line pad 210 in the array substrate provided in this example may not be limited to Figure 1 For example, the distribution of the first trace 31 in the array substrate provided in this example can be the same as Figure 6 The distribution pattern of the first trace is the same as shown, and can also be compared with Figure 8B The distribution pattern of the first routing line shown in or 9 is the same, and the embodiment of the present disclosure is not limited to this.

[0371] Figure 14 FIG. 1 is a schematic diagram of a partial planar structure of an array substrate provided according to another example of implementation of the present disclosure. Figure 14As shown, the array substrate includes a base substrate 100, and a plurality of gate lines 200 and a metal layer 300 located on the base substrate 100. The metal layer 300 is located on a side of the plurality of gate lines 200 away from the base substrate 100. The metal layer 300 includes a plurality of data lines 310. The plurality of data lines 310 extend along a first direction and are arranged along a second direction. The plurality of gate lines 200 extend along the second direction and are arranged along the first direction. The first direction and the second direction intersect. The plurality of data lines 310 intersect with the plurality of gate lines 200 to define a plurality of pixel areas 10.

[0372] like Figure 14 As shown, the metal layer 300 further includes a common electrode 320 located in the pixel area 10. For example, the common electrode 320 can be a film layer provided in the same layer as the data line 310 and made of the same material.

[0373] like Figure 14 As shown, at least one gate line 200 includes a gate line pad 210 , and the gate line pad 210 includes a protrusion 211 protruding into the pixel area 10 relative to a position on the gate line 200 except the gate line pad 210 .

[0374] like Figure 14 As shown, the metal layer 300 located in the pixel region 10 includes multiple routing segments 30 extending along at least a portion of the outline of the pixel region 10. The multiple routing segments 30 include multiple first routing segments 31 surrounding at least a portion of the edge of the protrusion 211. Each first routing segment 31 extends along the first direction or the second direction, and the multiple first routing segments 31 are connected end to end to form a stepped structure. By configuring the first routing segments surrounding the protrusion of the gate line pad into a stepped structure, the disclosed embodiment improves the consistency of the capacitance generated by the metal layer and the pixel electrode in different pixel regions while reducing the impact of the metal layer on the aperture ratio in the pixel region.

[0375] The array substrate provided in this example includes a base substrate, a data line, a common electrode, a thin film transistor, a first connecting portion, a second connecting portion, and a pixel electrode. Figures 1 to 11 The structures of the base substrate, data lines, common electrodes, thin film transistors, first connecting portions, second connecting portions and pixel electrodes in the array substrate shown have the same features and are not described in detail here.

[0376] The array substrate provided in this example is Figure 13 The difference in the array substrate shown is that both the second connection portion 340 and the data line 310 overlap with the hollow pattern 201. For example, the hollow pattern 201 includes a single opening. For example, the hollow pattern 201 may include multiple openings. In the array substrate provided in this example, by providing a hollow pattern in the gate line and overlapping the hollow pattern of the gate line with the data line and the second connection portion, the overlapping area of the data line and the second connection portion with the gate line can be reduced, thereby reducing the capacitance generated when the metal layer overlaps the gate line.

[0377] For example, Figure 14 As shown, the first end of the second connection portion 340 is electrically connected to the second electrode 520 of the thin film transistor 500, and the second end of the second connection portion 340 is electrically connected to the data line 310. The width of the hollow pattern 201 gradually increases along the direction from the first end to the second end. In this example, by setting the shape of the hollow pattern to gradually increase in width along the direction from the first end to the second end, it is beneficial to reduce the overlap area of the data line and the second connection portion with the gate line while preventing the hollow pattern from affecting the performance of the thin film transistor, such as reducing the sudden change of the source parasitic capacitance of the thin film transistor (TFT) and maintaining stable TFT performance.

[0378] For example, Figure 14 As shown, the shape of the hollow pattern 201 may include a trapezoid. For example, the upper base of the trapezoid is close to the thin film transistor 500 , and the lower base of the trapezoid is close to the data line 310 .

[0379] For example, the distribution of the first traces 31 around at least a portion of the edge of the protrusion 211 of the gate line pad 210 in the array substrate provided in this example may not be limited to Figure 1 For example, the distribution of the first trace 31 in the array substrate provided in this example can be the same as Figure 6 The distribution pattern of the first trace is the same as shown, and can also be compared with Figure 8B The distribution pattern of the first routing line shown in or 9 is the same, and the embodiment of the present disclosure is not limited to this.

[0380] Figure 15 A schematic diagram of a partial planar structure of an array substrate provided according to another example of implementation of the present disclosure. Figure 15 The array substrate shown is Figure 14 The difference between the array substrates shown is only in the shape of the hollow pattern 201 provided in the gate line 200. For example, Figure 15 As shown, the shape of the hollow pattern 201 is a triangle.

[0381] Figure 16 A schematic diagram of a partial planar structure of an array substrate provided according to another example of implementation of the present disclosure. Figure 16 The array substrate shown is Figure 14 The difference between the array substrates shown is only in the shape of the hollow pattern 201 provided in the gate line 200. For example, Figure 16 As shown, the shape of the hollow pattern 201 is a water drop shape.

[0382] Figure 17 FIG. 1 is a schematic diagram of a partial planar structure of an array substrate provided in another embodiment of the present disclosure. Figure 17As shown, the array substrate includes a base substrate 100, and a plurality of gate lines 200 and a metal layer 300 located on the base substrate 100. The metal layer 300 is located on a side of the plurality of gate lines 200 away from the base substrate 100. The metal layer 300 includes a plurality of data lines 310. The plurality of data lines 310 extend along a first direction and are arranged along a second direction. The plurality of gate lines 200 extend along the second direction and are arranged along the first direction. The first direction and the second direction intersect. The plurality of data lines 310 intersect with the plurality of gate lines 200 to define a plurality of pixel areas 10. Figure 17 A pixel area 10 is schematically shown.

[0383] For example, Figure 17 As shown, a plurality of data lines 310 extend along the X direction and are arranged along the Y direction; a plurality of gate lines 200 extend along the Y direction and are arranged along the X direction. Figure 17 In the schematic diagram, the first direction is the X direction, the second direction is the Y direction, and the first direction is perpendicular to the second direction. However, the present invention is not limited thereto. The first direction and the second direction may not be perpendicular to each other. For example, the angle between the first direction and the second direction may be 30 to 60 degrees. For example, the first direction and the second direction may be interchangeable.

[0384] For example, Figure 17 As shown, two adjacent data lines 310 and two adjacent gate lines 200 are arranged to cross to define a pixel area 10. For example, a pixel area 10 is a sub-pixel. For example, the array substrate includes a plurality of sub-pixels (a plurality of pixel areas 10), and the plurality of sub-pixels include sub-pixels configured to display different colors of light. For example, the plurality of sub-pixels may include a red sub-pixel configured to display red light, a green sub-pixel configured to display green light, and a blue sub-pixel configured to display blue light. For example, two adjacent sub-pixels arranged in at least one of the first direction and the second direction are respectively sub-pixels configured to display different colors of light.

[0385] For example, the shape of the pixel area 10 can be a polygon. For example, the shape of the pixel area 10 can be a quadrilateral. For example, the shape of the pixel area 10 can be a rectangle. The present disclosure does not limit this. The shape of the pixel area 10 is related to the shape of the edge of the data line 310 and the edge of the gate line 200.

[0386] For example, each pixel region 10 includes a display area for display, and the area of the display area may be smaller than that of the pixel region 10. For example, the shape of the display area may be the same as that of the pixel region 10, or the shape of the display area may be different from that of the pixel region 10.

[0387] like Figure 17 As shown, the metal layer 300 further includes a common electrode 320 located in the pixel area 10. For example, the common electrode 320 can be a film layer provided in the same layer as the data line 310 and made of the same material.

[0388] like Figure 17 As shown, at least one gate line 200 includes a gate line pad 210 , and the gate line pad 210 includes a protrusion 211 protruding into the pixel area 10 relative to a position on the gate line 200 except the gate line pad 210 .

[0389] For example, Figure 17 As shown, the gate line pad 210 is a portion of the gate line 200. For example, along the X direction, the width of the gate line pad 210 is greater than the width of the gate line 200 other than the gate line pad 210. For example, in the width direction, the portion of the gate line pad 210 that protrudes relative to the portion of the gate line 200 other than the gate line pad 210 is a protrusion 211.

[0390] For example, Figure 17 As shown, the gate line pad 210 may include a protrusion 211 protruding relative to one side of the gate line 200. For example, a plurality of gate line pads 210 may be provided on one gate line 200, each of the plurality of gate line pads 210 including a protrusion 211 protruding toward the same side of the gate line 200.

[0391] For example, the pixel region 10 does not include the protrusion 211 .

[0392] For example, Figure 17 As shown, the gate line pad 210 is configured to be arranged opposite to the support portion 01. For example, in a direction perpendicular to the base substrate 100, the gate line pad 210 overlaps with the support portion 01. For example, the orthographic projection of the gate line pad 210 on the base substrate 100 can overlap with the orthographic projection of the support portion 01 on the base substrate 100. For example, the orthographic projection of the support portion 01 on the base substrate 100 can completely fall within the orthographic projection of the gate line pad 210 on the base substrate 100. For example, Figure 17 The support portion 01 is schematically shown as having a circular shape in a plane parallel to the XY plane, but is not limited thereto and may also be a regular shape such as a polygon, or an irregular shape.

[0393] The above-mentioned “direction perpendicular to the base substrate 100 ” refers to a direction perpendicular to a main surface of the base substrate 100 for arranging structures such as gate lines, such as a direction perpendicular to an XY plane.

[0394] For example, the array substrate may be an array substrate in a liquid crystal display panel, and the liquid crystal display panel further includes an opposing substrate, a liquid crystal layer located between the array substrate and the opposing substrate, and a frame sealant that encapsulates the liquid crystal layer. For example, the opposing substrate may be a color filter substrate. For example, the support portion 01 (also referred to as a spacer) is located in the liquid crystal layer between the array substrate and the opposing substrate to maintain the uniformity of the thickness of the display panel. For example, the support portion 01 may be a photosensitive spacer, that is, a spacer with high positional accuracy is formed by photolithography using a photosensitive composition, and the support portion 01 includes a resin, a polymerizable compound, a photopolymerization initiator, etc., but the embodiments of the present disclosure are not limited thereto.

[0395] For example, the liquid crystal display panel further includes a first polarizing layer disposed on a side of the array substrate away from the opposing substrate and a second polarizing layer disposed on a side of the opposing substrate away from the array substrate. For example, a backlight source may be disposed on the non-display side of the display panel, the backlight source being configured to provide backlight to the display panel.

[0396] For example, the array substrate includes a support portion 01, which overlaps the gate line pad 210 in a direction perpendicular to the base substrate 100. However, the support portion may be provided on the opposing substrate, and its position may be set according to product requirements.

[0397] For example, the position of the gate line pad 210 can be set according to the position of the support part 01. For example, the number of the support parts 01 is K, the number of the gate line pad 210 is also K, and the support parts 01 and the gate line pads 210 are arranged in a one-to-one correspondence.

[0398] like Figure 17 As shown, the metal layer 300 located in the pixel area 10 includes a plurality of routing segments 30 extending along at least a portion of the outline of the pixel area 10. For example, at least some of the routing segments 30 are electrically connected routing segments. For example, the electrically connected routing segments 30 are integrated routing segments. The "integrated routing segments" may refer to routing segments formed by performing the same patterning process on the same metal material layer. The "multiple routing segments 30 extending along the outline of the pixel area 10" may refer to the plurality of routing segments extending along the edge of the data line 310 and the edge of the gate line 200. The plurality of routing segments extending along the outline of the pixel area may be parallel to the edge extension direction of the data line or the gate line, but is not limited thereto. Part of the routing segments may also be non-parallel to a portion of the edge of the gate line or the data line. Whether the routing segments are parallel to the edge of the signal line (including the gate line and the data line) adjacent thereto (in a plan view) may be set according to product requirements.

[0399] For example, Figure 17 As shown, the edge of the protrusion 211 of the gate line pad 210 includes a fold line.

[0400] like Figure 17As shown, the multi-segment trace 30 includes multiple trace sub-segments 33 surrounding at least a portion of the edge of the protrusion 211. Each trace sub-segment 33 is parallel to the edge of the protrusion 211 adjacent to it. For example, the orthographic projection of each trace sub-segment 33 on the substrate 100 is parallel to the orthographic projection of the edge of the protrusion 211 adjacent to it on the substrate 100. For example, at least one trace sub-segment 33 is not parallel to either the first direction or the second direction.

[0401] In the embodiment of the present disclosure, the routing sub-portion surrounding the protrusion of the gate line pad is arranged to be parallel to the extension direction of the edge of the protrusion, which is conducive to maximizing the aperture ratio of the pixel area.

[0402] For example, two end-to-end connected routing sub-segments 33 in a multi-segment routing sub-segment 33 are electrically connected. For example, the multi-segment routing sub-segment 33 may be an integrated structure. For example, the distance between the orthographic projection of the multi-segment routing sub-segment 33 on the base substrate 100 and the orthographic projection of the edge of the protrusion 211 it surrounds on the base substrate is smaller than the distance between the orthographic projection of other routing sub-segments on the base substrate 100 and the edge of the protrusion 211. For example, the distances between different routing sub-segments 33 and the edge of the protrusion 211 they surround are all the same.

[0403] For example, Figure 17 As shown, the extension direction of each segment of the multiple segments of the routing line 30 is parallel to the extension direction of the adjacent data line 310 or gate line 200 .

[0404] For example, Figure 17 As shown, the two routing segments 30 located at the two ends of the outermost edge of the multi-segment routing sub-section 33 can both be electrically connected to the routing sub-section 33. For example, the two routing segments 30 located at the two ends of the outermost edge of the multi-segment routing sub-section 33 can both be integrated with the routing sub-section 33. However, this is not limiting. One of the two routing segments located at the two ends of the outermost edge of the multi-segment first routing segment can also be spaced apart from the routing sub-section.

[0405] For example, Figure 17 As shown, the traces 30 except the trace sub-section 33 in the multiple trace sections 30 may extend along the first direction or along the second direction.

[0406] Figure 17 The shape and distribution of the protrusions in the example shown can be Figures 1 to 16 The shapes and distributions in any of the examples shown are the same and will not be described again here.

[0407] Figure 17 The base substrate 100, data line 310, thin film transistor 500, second connection portion 340 and pixel electrode in the array substrate of the example shown can be Figures 1 to 16The structures of the base substrate 100 , the data line 310 , the thin film transistor 500 , the second connection portion 340 and the pixel electrode 400 in the array substrate in any of the examples shown have the same features and are not described in detail here.

[0408] For example, Figure 17 The distribution of the multiple traces 30 shown may be similar to Figure 1 The distribution of the multiple traces 30 shown are all common electrodes, but are not limited thereto; for example, Figure 17 The multi-segment trace 30 shown may also be Figure 9 The distribution of the multiple segments of wiring 30 shown in FIG. 3 is shown in FIG. 3 , where a portion of the multiple segments of wiring 30 is a common electrode 320 and another portion is a first connecting portion 330 . For example, Figure 17 The multi-segment trace 30 shown may also be Figure 8A The distribution of multiple wiring segments 30 is shown, and the multiple wiring segments 30 are all first connecting portions 330 .

[0409] For example, Figure 17 As shown, when the routing sub-section 33 in the multi-segment routing 30 is a part of the first connecting portion 330, the distribution of the first connecting portion 330 can be the same as Figure 8B The distribution of the first connection parts 330 is the same as shown, and will not be repeated here.

[0410] For example, Figure 17 The capacitance between the trace portion 33 and the edge of the protrusion 211 can be calculated in the same manner as Figure 8B The capacitance C between the edge of the protrusion 211 and the third trace parallel to the edge of the protrusion 211 is shown as ε= d The calculation method of ×W×L / d is the same and will not be repeated here.

[0411] Figure 18 FIG. 1 is a schematic diagram of a partial planar structure of an array substrate provided in another embodiment of the present disclosure. Figure 18 As shown, the array substrate includes a base substrate 100, and a plurality of gate lines 200 and a metal layer 300 located on the base substrate 100. The metal layer 300 is located on a side of the plurality of gate lines 200 away from the base substrate 100. The metal layer 300 includes a plurality of data lines 310. The plurality of data lines 310 extend along a first direction and are arranged along a second direction. The plurality of gate lines 200 extend along the second direction and are arranged along the first direction. The first direction and the second direction intersect. The plurality of data lines 310 intersect with the plurality of gate lines 200 to define a plurality of pixel areas 10. Figure 18 A pixel area 10 is schematically shown.

[0412] For example, Figure 18 As shown, a plurality of data lines 310 extend along the X direction and are arranged along the Y direction; a plurality of gate lines 200 extend along the Y direction and are arranged along the X direction. Figure 18In the schematic diagram, the first direction is the X direction, the second direction is the Y direction, and the first direction is perpendicular to the second direction. However, the present invention is not limited thereto. The first direction and the second direction may not be perpendicular to each other. For example, the angle between the first direction and the second direction may be 30 to 60 degrees. For example, the first direction and the second direction may be interchangeable.

[0413] For example, Figure 18 As shown, two adjacent data lines 310 and two adjacent gate lines 200 are arranged to cross to define a pixel area 10. For example, a pixel area 10 is a sub-pixel. For example, the array substrate includes a plurality of sub-pixels (a plurality of pixel areas 10), and the plurality of sub-pixels include sub-pixels configured to display different colors of light. For example, the plurality of sub-pixels may include a red sub-pixel configured to display red light, a green sub-pixel configured to display green light, and a blue sub-pixel configured to display blue light. For example, two adjacent sub-pixels arranged in at least one of the first direction and the second direction are respectively sub-pixels configured to display different colors of light.

[0414] For example, the shape of the pixel area 10 can be a polygon. For example, the shape of the pixel area 10 can be a quadrilateral. For example, the shape of the pixel area 10 can be a rectangle. The present disclosure does not limit this. The shape of the pixel area 10 is related to the shape of the edge of the data line 310 and the edge of the gate line 200.

[0415] For example, each pixel region 10 includes a display area for display, and the area of the display area may be smaller than that of the pixel region 10. For example, the shape of the display area may be the same as that of the pixel region 10, or the shape of the display area may be different from that of the pixel region 10.

[0416] like Figure 18 As shown, the metal layer 300 further includes a common electrode 320 located in the pixel area 10. For example, the common electrode 320 can be a film layer provided in the same layer as the data line 310 and made of the same material.

[0417] like Figure 18 As shown, at least one gate line 200 includes a gate line pad 210 , and the gate line pad 210 includes a protrusion 211 protruding into the pixel area 10 relative to a position on the gate line 200 except the gate line pad 210 .

[0418] For example, Figure 18 As shown, the gate line pad 210 is a portion of the gate line 200. For example, along the X direction, the width of the gate line pad 210 is greater than the width of the gate line 200 other than the gate line pad 210. For example, in the width direction, the portion of the gate line pad 210 that protrudes relative to the portion of the gate line 200 other than the gate line pad 210 is a protrusion 211.

[0419] For example, Figure 18As shown, the gate line pad 210 may include a protrusion 211 protruding relative to one side of the gate line 200. For example, a plurality of gate line pads 210 may be provided on one gate line 200, each of the plurality of gate line pads 210 including a protrusion 211 protruding toward the same side of the gate line 200.

[0420] For example, the pixel region 10 does not include the protrusion 211 .

[0421] For example, Figure 18 As shown, the gate line pad 210 is configured to be arranged opposite to the support portion 01. For example, in a direction perpendicular to the base substrate 100, the gate line pad 210 overlaps with the support portion 01. For example, the orthographic projection of the gate line pad 210 on the base substrate 100 can overlap with the orthographic projection of the support portion 01 on the base substrate 100. For example, the orthographic projection of the support portion 01 on the base substrate 100 can completely fall within the orthographic projection of the gate line pad 210 on the base substrate 100. For example, Figure 17 The support portion 01 is schematically shown as having a circular shape in a plane parallel to the XY plane, but is not limited thereto and may also be a regular shape such as a polygon, or an irregular shape.

[0422] For example, the array substrate may be an array substrate in a liquid crystal display panel, and the liquid crystal display panel further includes an opposing substrate, a liquid crystal layer located between the array substrate and the opposing substrate, and a frame sealant that encapsulates the liquid crystal layer. For example, the opposing substrate may be a color filter substrate. For example, the support portion 01 (also referred to as a spacer) is located in the liquid crystal layer between the array substrate and the opposing substrate to maintain the uniformity of the thickness of the display panel. For example, the support portion 01 may be a photosensitive spacer, that is, a spacer with high positional accuracy is formed by photolithography using a photosensitive composition, and the support portion 01 includes a resin, a polymerizable compound, a photopolymerization initiator, etc., but the embodiments of the present disclosure are not limited thereto.

[0423] For example, the liquid crystal display panel further includes a first polarizing layer disposed on a side of the array substrate away from the opposing substrate and a second polarizing layer disposed on a side of the opposing substrate away from the array substrate. For example, a backlight source may be disposed on the non-display side of the display panel, the backlight source being configured to provide backlight to the display panel.

[0424] For example, the array substrate includes a support portion 01, which overlaps the gate line pad 210 in a direction perpendicular to the base substrate 100. However, the support portion may be provided on the opposing substrate, and its position may be set according to product requirements.

[0425] For example, the position of the gate line pad 210 can be set according to the position of the support part 01. For example, the number of the support parts 01 is K, the number of the gate line pad 210 is also K, and the support parts 01 and the gate line pads 210 are arranged in a one-to-one correspondence.

[0426] like Figure 18 As shown, the metal layer 300 located in the pixel area 10 includes a plurality of routing segments 30 extending along at least a portion of the outline of the pixel area 10. For example, at least some of the routing segments 30 are electrically connected routing segments. For example, the electrically connected routing segments 30 are integrated routing segments. The "integrated routing segments" may refer to routing segments formed by performing the same patterning process on the same metal material layer. The "multiple routing segments 30 extending along the outline of the pixel area 10" may refer to the plurality of routing segments extending along the edge of the data line 310 and the edge of the gate line 200. The plurality of routing segments extending along the outline of the pixel area may be parallel to the edge extension direction of the data line or the gate line, but is not limited thereto. Part of the routing segments may also be non-parallel to a portion of the edge of the gate line or the data line. Whether the routing segments are parallel to the edge of the signal line (including the gate line and the data line) adjacent thereto (in a plan view) may be set according to product requirements.

[0427] For example, Figure 18 As shown, the edge of the protrusion 211 of the gate line pad 210 includes a curve. For example, the edge of the protrusion 211 of the gate line pad 210 can be an arc shape. For example, the shape of the protrusion 211 can be a semicircle.

[0428] like Figure 18 As shown, the multi-segment routing 30 includes a plurality of routing sub-segments 33 surrounding at least part of the edge of the protrusion 211, and each routing sub-segment 33 is parallel to the edge of the protrusion 211 adjacent to it. For example, the orthographic projection of each routing sub-segment 33 on the base substrate 100 is parallel to the orthographic projection of the edge of the protrusion 211 adjacent to it on the base substrate 100. For example, at least one routing sub-segment 33 is not parallel to both the first direction and the second direction. For example, the routing sub-segment 33 surrounding the edge of a protrusion 211 can be in the shape of an arc, and the routing sub-segment 33 surrounding the edge of a protrusion 211 can be a whole routing segment 30. For example, when the edge profile of the routing sub-segment 33 is an infinite polygon, it is approximately in the shape of an arc, and the radius r of the arc is designed to be r=2l0 / π, where l0 is the equivalent length of the routing L' when the gate line corresponding to the position of the routing sub-segment 33 is not provided with a gate line pad.

[0429] In the embodiment of the present disclosure, the routing sub-portion surrounding the protrusion of the gate line pad is arranged to be parallel to the extension direction of the edge of the protrusion, which is conducive to maximizing the aperture ratio of the pixel area.

[0430] For example, Figure 18 The capacitance between the trace portion 33 and the edge of the protrusion 211 can be calculated in the same manner as Figure 8B The capacitance C between the edge of the protrusion 211 and the third trace parallel to the edge of the protrusion 211 is shown as ε= dThe calculation method of ×W×L / d is the same and will not be repeated here.

[0431] Figure 18 The array substrate shown is Figure 17 The difference between the array substrates shown is the shape of the gate line pad and the shape of the protrusion of the routing sub-part surrounding the gate line pad.

[0432] For example, Figure 18 The base substrate 100, data line 310, thin film transistor 500, second connection portion 340 and pixel electrode in the array substrate of the example shown can be Figures 1 to 17 The structures of the base substrate 100 , the data line 310 , the thin film transistor 500 , the second connection portion 340 and the pixel electrode 400 in the array substrate in any of the examples shown have the same features and are not described in detail here.

[0433] For example, Figure 18 As shown, when the gate line pad 210 has protrusions 211 on both sides of the gate line 200 in the Y direction, the routing sub-portion 33 surrounding the protrusion 211 can be at least one of the common electrode 320 and the first connecting portion 330 .

[0434] For example, Figure 18 As shown, two gate lines 200 located on both sides of at least one first pixel region 010 each include a gate line pad 210 protruding into the first pixel region 010, a common electrode 320 includes a routing sub-portion 33 surrounding the protrusion 211 of the gate line pad 210 on one of the two gate lines 200, a first connecting portion 330 surrounding at least a portion of the edge of the protrusion 211 of the gate line pad 210 on the other of the two gate lines 200, and the first connecting portion 330 surrounding at least a portion of the edge of the protrusion 211 includes a routing sub-portion 33, and each routing sub-portion 33 is parallel to the edge of the protrusion 211 adjacent thereto. For example, the orthographic projection of each routing sub-portion 33 on the base substrate 100 is parallel to the orthographic projection of the edge of the protrusion 211 adjacent thereto on the base substrate 100. For example, at least one routing sub-portion 33 is not parallel to either the first direction or the second direction.

[0435] For example, Figure 18 As shown, the gate line pad 210 includes two protrusions 211 protruding toward both sides of the gate line 200 in the X direction, that is, a first protrusion and a second protrusion. The first routing 31 surrounding the first protrusion can all be a common electrode 320, a portion of the routing sub-portion 33 surrounding the second protrusion is the common electrode 320, and the other portion of the routing sub-portion 33 is a first connecting portion 330.

[0436] Figure 18The illustrated example schematically shows that the gate electrode of the thin film transistor does not overlap with the support portion, but is not limited thereto. The gate electrode of the thin film transistor may also be arranged to overlap with the support portion.

[0437] Figure 18 The array substrate provided by the example shown is different from the above embodiment except that the shape of the gate line pad and the shape of the traces around the edge of the gate line pad are different. Figure 18 Other structures in the array substrate shown may have the same features as any of the above embodiments, and will not be described in detail here.

[0438] For example, another embodiment of the present disclosure provides a display device, comprising the array substrate provided by any of the aforementioned embodiments. In the display device provided by the embodiment of the present disclosure, by providing a stepped structure for the first trace surrounding the protruding portion of the gate line pad on the array substrate, this improves the consistency of the capacitance generated between the metal layer and the pixel electrode in different pixel regions while reducing the effect of the metal layer on the aperture ratio in the pixel region.

[0439] For example, the display device may further include a color filter substrate disposed opposite to the array substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate.

[0440] For example, the display device may be a liquid crystal display device, or any product or component with a display function, such as a television, digital camera, mobile phone, watch, tablet computer, laptop computer, or navigator including the liquid crystal display device, but this embodiment is not limited thereto.

[0441] There are a few points to note:

[0442] (1) The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure, and other structures can refer to general designs.

[0443] (2) In the absence of conflict, features in the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0444] The foregoing description is merely an exemplary embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. The scope of protection of the present disclosure is determined by the appended claims.

Claims

1. An array substrate, comprising: substrate; A plurality of gate lines are located on the substrate; a metal layer located on a side of the plurality of gate lines away from the base substrate, the metal layer comprising a plurality of data lines, the plurality of data lines extending along a first direction and arranged along a second direction, the plurality of gate lines extending along the second direction and arranged along the first direction, the first direction and the second direction intersecting, the plurality of data lines intersecting the plurality of gate lines to define a plurality of pixel areas; Wherein, at least one gate line includes a gate line pad, the gate line pad includes a protrusion protruding into the pixel area relative to a position on the gate line other than the gate line pad, and the metal layer located in the pixel area includes a plurality of routing segments extending along at least a portion of the outline of the pixel area; The multiple routing segments include multiple first routing segments surrounding at least a portion of an edge of the protrusion, each first routing segment extending along the first direction or the second direction, and the multiple first routing segments are connected end to end to form a step structure; The array substrate further includes a pixel electrode and a thin film transistor, wherein the thin film transistor includes a first electrode, a gate electrode, and a second electrode, the first electrode and the second electrode both overlap with the film layer where the gate line is located, the first electrode is electrically connected to the pixel electrode via a first connecting portion, and the second electrode is electrically connected to the data line; the first electrode, the second electrode, and the first connecting portion are all structures in the metal layer; The multiple pixel areas include at least one first pixel area and at least one second pixel area, the first pixel area is a pixel area corresponding to the gate line pad, and the second pixel area is a pixel area corresponding to a position on the gate line other than the gate line pad; the first connecting portion includes at least part of the routing of the multiple sections of the first routing, and the ratio of the area of the orthographic projection of the first connecting portion in the first pixel area on the substrate to the area of the orthographic projection of the first connecting portion in the second pixel area on the substrate is 0.8 to 1.

2.

2. The array substrate according to claim 1, wherein: Along a direction perpendicular to the base substrate, the first connection portion overlaps with the pixel electrode.

3. The array substrate according to claim 1, wherein: The metal layer further includes a common electrode located in the pixel area; Along a direction perpendicular to the base substrate, the common electrode overlaps with the pixel electrode, and the first electrode and the second electrode of the thin film transistor are both insulated from the common electrode.

4. The array substrate according to claim 3, wherein: The common electrode includes at least a portion of the plurality of first wiring segments.

5. The array substrate according to claim 4, wherein: A ratio of a length of the common electrode in the first pixel region to a length of the common electrode in the second pixel region is 0.8 to 1.

2.

6. The array substrate according to claim 1, wherein: A ratio of a length of the first connection portion in the first pixel region to a length of the first connection portion in the second pixel region is 0.8 to 1.

2.

7. The array substrate according to claim 1, wherein: The edge of the protrusion includes an edge of the protrusion whose extension direction is not parallel to the first direction and the second direction. The number of the multiple first routing segments is greater than or equal to 2, and the length of each first routing segment is L. i The orthographic projection of each first trace on the substrate is a first orthographic projection, and the orthographic projection of the edge of the protrusion on the substrate is a second orthographic projection. The first orthographic projection includes a long side extending along its extension direction and close to the second orthographic projection. The minimum distance between the long side and the second orthographic projection is d i , the angle between the long side and the second orthographic projection is θ i , a first parameter C in the capacitance between the first trace and the edge of the protrusion pad satisfy N is the number of the multiple first routing segments, i is a positive integer not less than 1, and N is a positive integer not less than 2.

8. The array substrate according to claim 7, wherein: The first parameter C pad Satisfy 0.035≤C pad ≤5.

9. The array substrate according to claim 7, wherein: The multiple routing segments in the second pixel area include a second routing segment parallel to the second direction, and an edge of the gate line closest to the second routing segment, which is close to the second routing segment, is an inclined edge that is not parallel to the second direction; The minimum distance between the orthographic projection of the second trace on the substrate and the orthographic projection of the inclined edge on the substrate is d h , the length of the second trace is L h The angle between the orthographic projection of the second line on the substrate and the orthographic projection of the inclined edge on the substrate is θ h , a second parameter C of the capacitance between the second trace and the inclined edge tft Satisfy C tft =ln[(L h / d h )×sinθ h +1].

10. The array substrate according to claim 9, wherein: The second parameter C tft Satisfy 0.01≤C tft ≤2.

5.

11. The array substrate according to claim 9, wherein: The ratio of the first parameter to the second parameter satisfies 1≤C pad / C tft ≤7.

12. The array substrate according to any one of claims 1 to 11, wherein: Each of the multiple routing segments extends along the first direction or the second direction.

13. The array substrate according to any one of claims 1 to 11, wherein: In a direction perpendicular to the base substrate, the gate line pad is configured to be arranged opposite to the supporting portion.

14. The array substrate according to any one of claims 1 to 11, wherein: The first connection portion extends along the first direction to be electrically connected to the pixel electrode.

15. The array substrate according to claim 14, wherein: The gate line pad includes the gate.

16. The array substrate according to any one of claims 3 to 5, wherein: The multiple first wiring segments include two parts, one of the two parts is the common electrode, and the other of the two parts is the first connecting portion.

17. The array substrate according to claim 16, wherein: The two gate lines located on both sides of at least one first pixel area each include the gate line pad protruding into the first pixel area, the common electrode includes the first routing surrounding the protruding portion of the gate line pad on one of the two gate lines, and the first connecting portion includes the first routing surrounding the protruding portion of the gate line pad on the other of the two gate lines.

18. The array substrate according to claim 16, wherein: The gate is located on the gate line except the gate line pad.

19. The array substrate according to claim 18, wherein: The first connection portion includes a sub-portion extending along the first direction and a sub-portion extending along the second direction.

20. The array substrate according to claim 3 or 4, further comprising: The common electrode line is provided in the same layer as the plurality of gate lines, and the common electrode is electrically connected to the common electrode line.

21. The array substrate according to claim 20, wherein: The common electrode line extends along the second direction, and along a direction perpendicular to the base substrate, the first connection portion overlaps the common electrode line.

22. The array substrate according to claim 20, wherein: An insulating layer is provided between the pixel electrode and the metal layer. The first connecting portion is electrically connected to the pixel electrode through a via hole in the insulating layer. A straight line parallel to the first direction passes through the via hole and the orthographic projection of the gate line pad on the base substrate.

23. The array substrate according to any one of claims 1 to 11, wherein: The edge of the protrusion includes a broken line or a curved line.

24. The array substrate according to any one of claims 1 to 11, wherein: The first connecting portion and the first electrode of the thin film transistor are integrated into one structure.

25. A display device comprising the array substrate according to any one of claims 1 to 24.

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