Cmos reference voltage source and design method thereof

Abstract

The present disclosure provides a CMOS reference voltage source and a design method thereof, which can provide a reference voltage under the temperature condition of-40 DEG C to 170 DEG C. The CMOS reference voltage source comprises: a CTAT voltage generating unit comprising a first circuit branch and a second circuit branch, for generating a CTAT voltage and a bias voltage respectively; and a PTAT voltage generating unit for generating a PTAT compensation voltage under the action of the bias voltage, so as to compensate the received CTAT voltage, and obtain and output a reference voltage. The power consumption of the CMOS reference voltage source is in the order of nW, and the required power voltage is less than 1V.

Description

Technical Field

[0001] This disclosure relates to the fields of integrated circuits and microelectronics, and in particular to a wide-temperature-range, low-supply-voltage, low-power CMOS reference voltage source. Background Technology

[0002] Reference circuits are generally divided into two main categories based on their circuit structure and application: one is the bandgap reference source based on bipolar junction transistors (BJTs), and the other is the CMOS reference source based on metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0003] The output reference voltage of a traditional bandgap or hybrid architecture reference voltage source is based on the base-emitter voltage (V) of a BJT. BE However, the use of BJTs limits the reduction of the reference voltage source's operating voltage (the minimum supply voltage is typically greater than 1V). Traditional CMOS reference voltage sources can achieve ultra-low power consumption and ultra-low supply voltage by using MOSFETs operating in the subthreshold region. However, for pW ultra-low power circuits, as the temperature decreases, the current becomes smaller and smaller, especially below 0°C. The MOSFET current approaches the leakage current of each PN junction, making it unable to operate normally. Generally, the lower limit of the temperature range is set near 0°C, making it unsuitable for low-temperature applications in some fields. Summary of the Invention

[0004] To address the aforementioned issues, this disclosure provides a CMOS reference voltage source and its design method to alleviate the technical problems described above in the prior art.

[0005] (I) Technical Solution

[0006] One aspect of this disclosure provides a CMOS reference voltage source capable of providing a reference voltage at temperatures ranging from -40°C to 170°C. The CMOS reference voltage source includes a CTAT voltage generation unit and a PTAT voltage generation unit. The CTAT voltage generation unit includes a first circuit branch and a second circuit branch for generating a CTAT voltage and a bias voltage, respectively. The PTAT voltage generation unit generates a PTAT compensation voltage under the influence of the bias voltage to perform temperature compensation with the received CTAT voltage, thereby obtaining and outputting the reference voltage.

[0007] According to an embodiment of this disclosure, the first circuit branch includes a first PMOS transistor group, a first NMOS transistor group, a bias resistor Rb, and a first DTMOS transistor M9; the second circuit branch includes a second PMOS transistor group, a second NMOS transistor group, and a second DTMOS transistor M9.10 The PMOS transistors in the first PMOS transistor group and the second PMOS transistor group are symmetrically matched; the NMOS transistors in the first NMOS transistor group and the second NMOS transistor group are symmetrically matched; the first DTMOS transistor M9 and the second DTMOS transistor M... 10 The size ratio is N:1, where N is between 2 and 10.

[0008] According to embodiments of this disclosure, the sources of the PMOS transistors in both the first and second PMOS transistor groups are connected to the power supply voltage; the sources of the NMOS transistors in the first NMOS transistor group are connected to a bias resistor R. b One end of the bias resistor Rb is connected to the source of the first DTMOS transistor M9. The substrate of the first DTMOS transistor M9 is connected to the drain and then grounded. The gate of the first DTMOS transistor M9 is also grounded. The sources of the NMOS transistors in the second NMOS transistor group are connected to the second DTMOS transistor M9. 10 The source of the second DTMOS transistor M 10 The substrate is connected to the drain and then grounded, and the second DTMOS transistor M 10 The gate is grounded.

[0009] According to an embodiment of this disclosure, the first PMOS transistor group includes a first PMOS transistor M1 and a second PMOS transistor M2 with a size ratio of K:1, where K is 1-4; the second PMOS transistor group includes a third PMOS transistor M3 and a fourth PMOS transistor M4 with a size ratio of 1:K; the gates of the first PMOS transistor M1 and the fourth PMOS transistor M4 are connected and connected to the drain of the second PMOS transistor M2; the gates of the second PMOS transistor M2 and the third PMOS transistor M3 are connected and connected to the drain of the third PMOS transistor M3.

[0010] According to an embodiment of this disclosure, the first NMOS transistor group includes a fifth NMOS transistor M5 and a sixth NMOS transistor M6 with a size ratio of K:1; the second NMOS transistor group includes a seventh NMOS transistor M7 and an eighth NMOS transistor M8 with a size ratio of 1:K; the gate of the fifth NMOS transistor M5 is connected to the gate of the seventh NMOS transistor M7 and is also connected to the drain of the fifth NMOS transistor M5, and the drain of the fifth NMOS transistor M5 is connected to the drain of the first PMOS transistor M1; the gate of the sixth NMOS transistor M6 is connected to the gate of the eighth NMOS transistor M8 and is also connected to the drain of the eighth NMOS transistor M8, and the drain of the eighth NMOS transistor M8 is connected to the drain of the fourth PMOS transistor M4.

[0011] According to an embodiment of this disclosure, the PTAT voltage generation unit includes an eleventh PMOS transistor M. 11 A PMOS differential pair circuit with an NMOS current mirror load.

[0012] Eleventh PMOS transistor M 11 The source of the transistor is connected to the power supply voltage, and its gate is connected to the drain of the second PMOS transistor M2, so as to generate a PTAT bias current at the drain under the action of the bias voltage.

[0013] PMOS differential pair circuit with NMOS current mirror load and eleventh PMOS transistor M 11 The drain is connected to the voltage, which is used to generate the PTAT compensation voltage under the action of the bias voltage.

[0014] According to an embodiment of this disclosure, the PMOS differential pair circuit with an NMOS current mirror load includes: a first input PMOS transistor M D1 The second input PMOS transistor M D2 First load current mirror tube M M1 Second load current mirror tube M M2 .

[0015] First input PMOS transistor M D1 The gate is connected to the second DTMOS transistor M. 10 The source of the first input transistor is used to receive the CTAT voltage; the second input PMOS transistor M... D2 The gate of the transistor is connected to the output port of the CMOS reference voltage source for outputting the reference voltage; the first load current mirror M... M1 After the gate is connected to the drain, it is connected to the first input PMOS transistor M. D1 The drain is connected, and the source is grounded; the second load current is reflected in the mirror tube M. M2 The gate of the mirror tube M is connected to the first load current. M1 The gate and drain of the transistor are connected to the second input PMOS transistor M. D2 The drain and gate of the transistor are connected, and the source is grounded; wherein, the first PMOS differential pair transistor M D1 Second PMOS differential pair transistor M D2 The sources of all are connected to the eleventh PMOS transistor M. 11 The drain is used to generate the PTAT compensation voltage after receiving the PTAT bias current.

[0016] According to embodiments of this disclosure, the magnitude of the PTAT bias current is determined by adjusting the size of the bias resistor Rb and the dimensions of the PMOS transistors, NMOS transistors, and DTMOS transistors in the first and second circuit branches; the magnitude of the PTAT compensation voltage is adjusted by adjusting the dimensions of the PMOS transistors and NMOS transistors in the PMOS differential pair circuit with an NMOS current mirror load, thereby performing temperature compensation with the received CTAT voltage.

[0017] According to embodiments of this disclosure, the power supply voltage is less than 1V, and the power consumption of the CMOS reference voltage source is in the nW range.

[0018] In another aspect, this disclosure provides a design method for a CMOS reference voltage source to obtain the CMOS reference voltage source described above, the design method comprising operations S1-S4. S1: Determine the bias resistor R in the CTAT voltage generation unit. b S1: Determine the size of the PTAT bias current in the nA level, and the dimensions of the PMOS, NMOS, and DTMOS transistors in the first and second circuit branches; S2: Determine the dimensions of the PMOS and NMOS transistors in the PTAT voltage generation unit to determine the magnitude of the PTAT compensation voltage; S3: At each process corner, adjust the dimensions of the PMOS and NMOS transistors in the PTAT voltage generation unit to achieve temperature coefficient calibration of the reference voltage at each process corner; S4: At each process corner, debug and verify the power supply rejection ratio and linear regulation of the reference voltage.

[0019] (II) Beneficial Effects

[0020] As can be seen from the above technical solutions, the CMOS reference voltage source and its design method disclosed herein have at least one or a part of the following beneficial effects:

[0021] (1) A wide temperature compensation range of -40 to 170°C is achieved by combining CTAT voltage and PTAT voltage with a wide temperature range.

[0022] (2) Utilizing DTMOS's V GS Its low voltage characteristics (typically less than 500mV) enable a low supply voltage of less than 1V;

[0023] (3) All MOSFETs operate in the subthreshold region, achieving low power consumption at the nW level. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the structure of an existing hybrid (BJT+MOSET) wide-temperature-range reference voltage source.

[0025] Figure 2 This is a schematic diagram illustrating the implementation principle of an existing hybrid (BJT+MOSFET) wide-temperature-range reference voltage source.

[0026] Figure 3 This is a schematic diagram of the CTAT voltage generation unit circuit structure based on 8 symmetrical matching transistors and DTMOS according to an embodiment of the present disclosure.

[0027] Figure 4This is a schematic diagram of the circuit structure of the PTAT voltage generation unit based on gate voltage difference according to an embodiment of the present disclosure.

[0028] Figure 5 This is a schematic diagram of the circuit structure of a CMOS reference voltage source according to an embodiment of the present disclosure.

[0029] Figure 6 This is a flowchart illustrating the design method of a CMOS reference voltage source according to an embodiment of this disclosure.

[0030] Figure 7 This is a schematic diagram showing the variation of the reference voltage of the CMOS reference voltage source in different process corners with the supply voltage according to an embodiment of this disclosure.

[0031] Figure 8 This is a schematic diagram comparing the temperature characteristics of the reference voltage of the CMOS reference voltage source under different process angles according to an embodiment of this disclosure. Detailed Implementation

[0032] This disclosure provides a CMOS reference voltage source and its design method. The CMOS reference voltage source has a current in the nA range and generates a negative temperature coefficient voltage V on a DTMOS (Dynamic Threshold Metal-Oxide-Semiconductor Field-Effect Transistor). GS Even at temperatures ranging from -40°C to 0°C, it still exhibits good CTAT (Complementary-To-Absolute Temperature) characteristics, which can effectively complement PTAT (Proportional-To-Absolute Temperature) voltages, ultimately achieving a reference voltage V with a small temperature coefficient over a wide temperature range of -40°C to 170°C. REF Furthermore, the application of DTMOS enables supply voltage designs below 1V, and all MOSFETs operate in the subthreshold region, achieving low-power designs at the nW level. The PTAT voltage of the CMOS reference voltage source disclosed herein can be adjusted by trimming the number of parallel MOSFETs to correct the temperature coefficient after process variations, thereby compensating for V-level fluctuations caused by process variations. DTMOS .

[0033] Traditional bandgap or hybrid architecture reference voltage sources are well-suited to CMOS manufacturing processes and offer good process stability, thus enjoying wide applications. However, to enable the transistors to function properly, they require significant power consumption and a larger area, which does not meet the requirements of low-voltage, low-power SoC chips. The advantage of traditional CMOS references is that they can generate a reference voltage with relatively low power consumption and area, but their parameters experience significant process fluctuations, leading to unstable temperature compensation. Furthermore, for ultra-low pW power circuits, as temperature decreases, the current diminishes, and the MOSFET current approaches the leakage current of each PN junction, rendering them unable to function properly. The lower limit of their temperature range is typically set near 0°C, making them unsuitable for low-temperature applications in some fields. Existing technologies struggle to provide a reference voltage source with low supply voltage, low power consumption, and a wide temperature range. Therefore, research on low-supply-voltage, low-power reference voltage sources with a wide temperature range is of great significance. For example, industrial-grade chips require an operating temperature range of -40°C to 85°C (referencing standards such as JESD47), while automotive-grade chips require an operating temperature range of -40°C to 150°C (referencing standards such as AEC-Q100).

[0034] The rise of electric vehicles and autonomous driving has driven a strong demand for automotive electronic chips, representing a major growth driver for the future chip industry. According to the AEC-Q100 standard for automotive electronic equipment, the ambient temperature range is -40℃ to 150℃. Automotive ICs are required to operate stably in extreme environments ranging from -40℃ to 150℃, while systems such as batteries and motors require even higher temperature resistance (stable operation at 170℃). Solving this problem is currently a key and challenging research area.

[0035] like Figure 1 As shown, the prior art provides a hybrid (BJT+MOSFET) reference voltage source [Reference paper: I. Lee and D. Blaauw, "A 31pW-to-113nW Hybrid BJT and CMOS Voltage Reference with 3.6% ± 3σ-inaccuracy from 0℃ to 170℃ for Low-Power High-Temperature IoT Systems," 2019 Symposium on VLSI Circuits, Kyoto, Japan, 2019, pp. C142-C143.]. M1 to M3 constitute the current generation and voltage linear regulation section, M4 to M5 are used to generate the PTAT voltage, and the BJT in D1 is used to generate the CTAT voltage. Its output reference voltage is determined by the CTAT voltage of the BJT (V... BE ) and PTAT voltage (V T It is composed of ( ) elements. The formula for the output reference voltage of this structure is:

[0036]

[0037] Where V BE It is the base-emitter voltage of the BJT, a CTAT voltage, which includes Eg / q as the bandgap voltage, V th V is the threshold voltage, m is the subthreshold slope factor, and V th / m originates from V BE , is the dominant part of the CTAT voltage in equation (1). μ is the mobility, C ox It is the gate oxide capacitance, W M3 and L M3 These are the width and length of M3, respectively. V PTAT V in voltage T The thermal voltage is positively correlated with temperature. N is the number of NMOS transistors connected in series in the PTAT voltage generation unit, and W... PTAT These are the widths of the NMOS transistors. V can be adjusted by changing the dimensions of M3, M4, and M5. PTAf The slope of the reference voltage is used to achieve temperature compensation for the zero temperature coefficient reference voltage.

[0038] like Figure 2 As shown, it introduces Figure 1 The implementation principle of this hybrid (BJT+MOSET) wide temperature range reference voltage source. For a typical BJT, a CTAT voltage V can be generated from the PN junction using a current source. BE To compensate for its negative temperature coefficient, a PTAT voltage V is generated in the subthreshold region using a CMOS transistor. T However, its positive temperature coefficient is not large enough to offset V. BE The negative temperature coefficient. To improve the positive temperature coefficient of the PTAT voltage, N transistors connected in series as diodes are used to form an N-fold positive temperature coefficient. This scheme uses two different types of devices (BJT+CMOS) to mutually compensate for their positive and negative temperature coefficients, thereby obtaining a reference voltage V with a temperature coefficient. REF Furthermore, this scheme saves power by using subthreshold current and sharing the same current in the same branch. Under a supply voltage of 0.9V to 3.3V and a temperature range of 0 to 170℃, it achieves power consumption at the pW level and a temperature coefficient in the range of 10 to 64ppm / ℃, with a linear regulation rate of 0.27%.

[0039] Figure 1The hybrid (BJT+MOSFET) wide-temperature-range reference voltage source shown uses a BJT combined with a MOSFET to provide two voltages with complementary temperature coefficients, which are then added together to obtain the output reference voltage, and can maintain a small temperature coefficient within the range of 0–170°C. However, as the temperature decreases, the operating current of the circuit becomes smaller and smaller. Below 0°C, for a circuit with ultra-low power consumption of pW, the MOSFET current approaches the leakage current of each PN junction, and it cannot function properly. Figure 1 If the circuit shown is to operate in the range of -40 to 0°C, the size of M4 to M5 needs to be increased by thousands of times to achieve a current of nA to enable it to operate normally at low temperatures, but this will result in a huge area cost.

[0040] Therefore, the purpose of this disclosure is to address the technical deficiency of existing hybrid low-power reference voltage sources that cannot operate in the low-temperature range of -40 to 0°C, and to provide a wide-temperature-range, low-supply-voltage, low-power CMOS reference voltage source, which adopts a structure based on 8 symmetrically matched transistors and DTMOS to generate a wide-temperature-range CTAT voltage V. DTMOS And utilize DTMOS's V GS The low voltage characteristic (typically less than 500mV) enables a low supply voltage of less than 1V. A PTAT voltage generation circuit based on gate voltage difference is used to obtain a wide-temperature-range PTAT voltage, which is temperature-compensated with the aforementioned CTAT voltage to generate a reference voltage that can operate over a wide temperature range of -40 to 170°C. The core circuit of the proposed reference voltage source consists entirely of MOSFETs operating in the subthreshold region, thus simultaneously achieving low power consumption in the nW range.

[0041] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0042] In this embodiment of the disclosure, a CMOS reference voltage source is provided, combined with Figures 3 to 5 As shown, the CMOS reference voltage source includes:

[0043] The CTAT voltage generation unit includes a first circuit branch and a second circuit branch, used to generate the CTAT voltage and the bias voltage, respectively; and

[0044] The PTAT voltage generating unit, connected to the CTAT voltage generating unit, is used to generate a PTAT compensation voltage under the action of the bias voltage, so as to perform temperature compensation with the received CTAT voltage, and obtain and output a reference voltage.

[0045] According to an embodiment of this disclosure, the first circuit branch includes a first PMOS transistor group, a first NMOS transistor group, and a bias resistor R. bThe second circuit branch includes a second PMOS transistor group, a second NMOS transistor group, and a second DTMOS transistor M9; 10 The PMOS transistors in the first PMOS transistor group and the second PMOS transistor group are symmetrically matched; the NMOS transistors in the first NMOS transistor group and the second NMOS transistor group are symmetrically matched; the first DTMOS transistor M9 and the second DTMOS transistor M... 10 The size ratio is N:1, where N is 2-10, preferably 4.

[0046] According to embodiments of this disclosure, in conjunction with Figures 3 to 5 As shown, the sources of the PMOS transistors in both the first and second PMOS transistor groups are connected to the power supply voltage; the sources of the NMOS transistors in the first NMOS transistor group are connected to a bias resistor R. b One end, bias resistor R b The other end is connected to the source of the first DTMOS transistor M9. The substrate of the first DTMOS transistor M9 is connected to the drain and then grounded, and the gate of the first DTMOS transistor M9 is grounded. The sources of the NMOS transistors in the second NMOS transistor group are connected to the second DTMOS transistor M9. 10 The source of the second DTMOS transistor M 10 The substrate is connected to the drain and then grounded, and the second DTMOS transistor M 10 The gate is grounded.

[0047] According to embodiments of this disclosure, in conjunction with Figures 3 to 5 As shown, the first PMOS transistor group includes a first PMOS transistor M1 and a second PMOS transistor M2 with a size ratio of K:1; the second PMOS transistor group includes a third PMOS transistor M3 and a fourth PMOS transistor M4 with a size ratio of 1:K; the gates of the first PMOS transistor M1 and the fourth PMOS transistor M4 are connected and connected to the drain of the second PMOS transistor M2 to receive a bias voltage V2; the gates of the second PMOS transistor M2 and the third PMOS transistor M3 are connected and connected to the drain of the third PMOS transistor M3 to receive a bias voltage V1.

[0048] According to embodiments of this disclosure, in conjunction with Figures 3 to 5As shown, the first NMOS transistor group includes a fifth NMOS transistor M5 and a sixth NMOS transistor M6 with a size ratio of K:1; the second NMOS transistor group includes a seventh NMOS transistor M7 and an eighth NMOS transistor M8 with a size ratio of 1:K; the gate of the fifth NMOS transistor M5 is connected to the gate of the seventh NMOS transistor M7, and is also connected to the drain of the fifth NMOS transistor M5 to receive a bias voltage V3, and the drain of the fifth NMOS transistor M5 is connected to the drain of the first PMOS transistor M1; the gate of the sixth NMOS transistor M6 is connected to the gate of the eighth NMOS transistor M8, and is also connected to the drain of the eighth NMOS transistor M8 to receive a bias voltage V4, and the drain of the eighth NMOS transistor M8 is connected to the drain of the fourth PMOS transistor M4. K is between 1 and 4, preferably 2.

[0049] In this embodiment of the disclosure, combined with Figures 3 to 5 As shown, the schematic diagram of the CTAT voltage generation circuit based on 8 symmetrically matched (symmetrical matching means consistent size and connection method) transistors and DTMOS (Dynamic Threshold Metal-Oxide-Semiconductor Field-Effect Transistor) is as follows: The principle is as follows: Flow into M 10 The current is I X =I XA +I XB The ratio of (W / L) of M3 and M4 is 1:K, where K takes values ​​from 1 to 4, with K=2 being the preferred value. Therefore, I XB =K·I XA For the entire loop, M1 and M4, M2 and M3, M5 and M8, and M6 and M7 are all symmetrically matched. Figure 3 Assume the transconductance of the PMOS transistors M1 to M4 is g. mp Its impedance is r dsp For NMOS transistors M5 to M8, their transconductance is g. mn Its impedance is r asn Let V OS =V Y -V X Then V OS To V DD The gain can be written as 2g mp g mn (r dsp ||r dsn ) 2 When V approaches the low frequency of DC infinitely, OS Approaching 0, therefore V X =V TThis method, which uses eight symmetrically matched transistors instead of operational amplifiers in a traditional bandgap reference, provides V... X =V T The clamping effect reuses the current of the bias circuit itself, reducing the power consumption of the operational amplifier.

[0050] For M9 and M 10 Two DTMOS transistors, Figure 3 In this context, N represents the (W / L) ratio of the two DTMOS transistors. For DTMOS transistors M9 and M... 10 Under a certain bias current, its gate-source voltage V GS It can be written as:

[0051]

[0052] Where V T =kT / q is the thermal voltage, m is the subthreshold slope factor, and V th For the threshold voltage, I BIAS I is the bias current of the DTMOS transistor. D0 It is a process-related characteristic current, W 10 and L 1o These represent the width and length of M10, respectively. In equation (1) The dominant component, through simulation, shows that the subthreshold slope factor m changes with temperature by approximately 0.01% / ℃, confirming that m hardly changes with temperature. Therefore, V GS This refers to the CTAT voltage.

[0053] For DTMOS transistors M9 and M 10 There exists a ratio N of (W / L) and V X =V GS10 =V Y Therefore, in resistor R b The pressure drop generated above is ΔV GS =V GS10 -V GS9 =V T ln(N), therefore:

[0054]

[0055] In this structure, the gate-source voltage V of the DTMOS transistor GS It can be written as:

[0056]

[0057] According to embodiments of this disclosure, in conjunction with Figures 3 to 5 As shown, the PTAT voltage generation unit is a PTAT voltage generation circuit based on gate voltage difference, including: an eleventh PMOS transistor M 11A PMOS differential pair circuit with an NMOS current mirror load. Wherein:

[0058] Eleventh PMOS transistor M 11 The source of the transistor is connected to the power supply voltage, and its gate is connected to the drain of the second PMOS transistor M2, so as to generate a PTAT bias current at the drain under the action of the bias voltage; the PMOS differential pair circuit with NMOS current mirror load and the eleventh PMOS transistor M 11 The drain is connected to the voltage, which is used to generate the PTAT compensation voltage under the action of the bias voltage.

[0059] According to embodiments of this disclosure, in conjunction with Figures 3 to 5 As shown, the PMOS differential pair circuit with NMOS current mirror load includes: a first input PMOS transistor M D1 The second input PMOS transistor M D2 First load current mirror tube M M1 Second load current mirror tube M M2 .in:

[0060] First input PMOS transistor M D1 The gate is connected to the second DTMOS transistor M 10 The source of the second input PMOS transistor is used to receive the CTAT voltage; the second input PMOS transistor is M. D2 The gate is connected to the output port of the CMOS reference voltage source, used to output the reference voltage; the first load current mirror M... M1 After the gate is connected to the drain, it is connected to the first input PMOS transistor M. D1 The drain is connected, and the source is grounded; the second load current is reflected in the mirror tube M. M2 The gate is connected to the first load current mirror M. M1 The gate and drain of the transistor are connected to the second input PMOS transistor M. D2 The drain and gate of the first PMOS differential pair transistor M is grounded. D1 Second PMOS differential pair transistor M D2 The sources of all are connected to the eleventh PMOS transistor M. 11 The drain is used to generate the PTAT compensation voltage after receiving the PTAT bias current.

[0061] In traditional hybrid (BJT+MOSET) reference voltage circuits, the PTAT voltage is generated using a BJT and a resistor. However, using a resistor at nA current levels incurs a significant area cost. Figure 4 The PTAT voltage generation circuit used in this disclosure consists of a PMOS differential pair with an NMOS current mirror load. When the MOSFET operates in the subthreshold region, the M in this circuit... D1 and M D2The difference in gate voltage V PTAT The PTAT compensation voltage can be expressed as:

[0062]

[0063] Where K D1 and K D2 These are the (W / L) values ​​of the input PMOS differential pair transistors, and K. M1 and K M2 These are the (W / L) values ​​of the NMOS load current mirror, where m is the subthreshold slope factor, and V... T It is the thermal voltage, specifically a PTAT voltage. Therefore, its positive temperature coefficient can be obtained from the formula... We can adjust the temperature coefficient to achieve the positive temperature coefficient value we want.

[0064] According to embodiments of this disclosure, in conjunction with Figures 3 to 5 As shown, the CMOS reference voltage source includes the CTAT voltage generation unit and the PTAT voltage generation unit mentioned above. All MOSFETs used in this disclosure are of the type with a standard threshold voltage and a withstand voltage of 2V.

[0065] The CTAT voltage generation units: M1 and M4, M2 and M3, M5 and M8, and M6 and M7 all use symmetrically matched transistors. 11 As the current source for the PTAT generation section. M9 and M 10 As two DTMOS transistors with a size ratio of N, two different CTAT voltages are generated. PMOS transistors M1-M4 and M... 11 The substrates of all transistors are connected to the source (connected to the power supply voltage), and the substrates of NMOS transistors M5 to M8 are all grounded. M9 and M... (The sentence is incomplete and requires more context to translate accurately.) 10 The substrate is connected to the drain, i.e., grounded. The resistor R used... b It is a POLY resistor implanted with N ions.

[0066] PTAT voltage generation unit: M D1 and M D2 As an input PMOS differential pair, its substrate is connected to the power supply voltage, M M1 and M M2 As a load current mirror, its substrate is grounded. In M D2 The gate generates a reference voltage output.

[0067] The above technical solution proposes a wide-temperature-range CTAT and PTAT voltage generation scheme, combined with compensation to obtain a reference voltage. This disclosure enables the reference voltage to operate in a low-supply-voltage, low-power mode over a wide temperature range. The expression for the output reference voltage can be written as:

[0068]

[0069] Among them, V DTMOS The CTAT voltage generated by the CTAT voltage generation unit, V PTAT The PTAT compensation voltage is obtained by applying the bias voltage generated by the CTAT voltage generation unit to the PTAT voltage generation unit.

[0070] Differentiating the negative temperature coefficient of the CTAT voltage section:

[0071]

[0072]

[0073] Differentiate the positive temperature coefficient of the voltage part of PTAT:

[0074]

[0075]

[0076] By selecting M9, M 10 M D1 M D2 M M1 and M M2 A suitable size can simultaneously achieve V REF Temperature compensation, i.e.

[0077] According to embodiments of this disclosure, the magnitude of the PTAT bias current is determined by adjusting the size of the bias resistor Rb and the dimensions of the PMOS transistors, NMOS transistors, and DTMOS transistors in the first and second circuit branches; the magnitude of the PTAT compensation voltage is adjusted by adjusting the dimensions of the PMOS transistors and NMOS transistors in the PMOS differential pair circuit with an NMOS current mirror load, thereby performing temperature compensation with the received CTAT voltage.

[0078] This disclosure also provides a design method for a CMOS reference voltage source, used to obtain the CMOS reference voltage source described above, such as... Figure 6 As shown, the design method includes:

[0079] Operation S1: Determine the value of the bias resistor Rb in the CTAT voltage generation unit, as well as the dimensions of the PMOS transistor, NMOS transistor, and DTMOS transistor in the first and second circuit branches, and determine the PTAT bias current in the nA range.

[0080] Operation S2: Determine the dimensions of the PMOS and NMOS transistors in the PTAT voltage generation unit, thereby determining the magnitude of the PTAT compensation voltage;

[0081] Operation S3: At each process corner, by adjusting the dimensions of the PMOS and NMOS transistors in the PTAT voltage generation unit, temperature coefficient calibration of the reference voltage is achieved at each process corner; and

[0082] Operation S4: At each process corner, debug and verify the power supply rejection ratio and linear regulation of the reference voltage.

[0083] According to embodiments of this disclosure, there are five main design parameters affecting the temperature coefficient in the entire CMOS reference voltage source circuit: determining the size ratio N of the DTMOS in the CTAT voltage generation unit, the appropriate bias resistor value, and the appropriate dimensions of each transistor; determining the nA-level bias current; and determining the appropriate K in the PTAT voltage generation unit. D1 K M2 / K D2 K M1 The value of K is adjusted to generate a suitable PTAT voltage compensation output reference voltage; at each process angle, K is adjusted... D1 K M2 / K D2 K M1 The temperature coefficient of the reference voltage is calibrated at each process corner; finally, the power supply rejection ratio and linear regulation of the reference voltage are debugged and verified at each process corner.

[0084] In practical implementation, the power consumption of the reference voltage source proposed in this disclosure is 187.9nW at room temperature (25℃), and the minimum supply voltage required at the three process corners (TT, SS, FF) is as low as 0.9V. Figure 7 As shown, their linear adjustment rates are all below 0.1% / V.

[0085] To verify the temperature compensation effect over a wide temperature range in this disclosure, the temperature characteristics of the proposed low-supply-voltage, low-power reference voltage source with a wide temperature range were simulated, such as... Figure 8 As shown. Under the three process corners (TT, SS, FF), by... Figure 5 M in D1 and M D2 By adjusting the number of parallel connections, a good temperature compensation effect can be achieved simultaneously at three process corners, including K at the TT process corner. D1 K M2 / K D2 K M1 Take 27 / 4, K under FF process angle D1 K M2 / K D2 K M1 Take 20 / 4, K under SS process angle D1 K M2 / K D2 KM1 Take 37 / 4, keeping other parameters unchanged. Figure 1 Compared to the existing reference voltage source with a temperature coefficient of 10 to 64 ppm / ℃ in the temperature range of 0 to 170℃, the present disclosure has a temperature coefficient of 15 to 33 ppm / ℃ in the temperature range of -40 to 170℃, which still has better temperature characteristics.

[0086] The embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. It should be noted that implementations not illustrated or described in the drawings or the main text of the specification are forms known to those skilled in the art and are not described in detail. Furthermore, the definitions of the various elements and methods described above are not limited to the specific structures, shapes, or methods mentioned in the embodiments, and those skilled in the art can easily modify or substitute them.

[0087] Based on the above description, those skilled in the art should have a clear understanding of the CMOS reference voltage source and its design method disclosed herein.

[0088] In summary, this disclosure provides a CMOS reference voltage source and its design method. The proposed method employs a structure based on symmetrically matched transistors and DTMOS to generate a CTAT voltage over a wide temperature range, and utilizes the Vt of DTMOS. GS The low voltage characteristic (typically less than 500mV) enables a low supply voltage of less than 1V. A PTAT voltage generation unit based on gate voltage difference is used to obtain a wide-temperature-range PTAT compensation voltage, which is then temperature-compensated with the aforementioned CTAT voltage to generate a reference voltage that can operate over a wide temperature range of -40 to 170°C. The core circuit of the proposed reference voltage source consists entirely of MOSFETs operating in the subthreshold region, thus simultaneously achieving low power consumption at the nW level.

[0089] It should also be noted that the above are different embodiments provided by this disclosure. These embodiments are used to illustrate the technical content of this disclosure and are not intended to limit the scope of protection of this disclosure. A feature of one embodiment can be applied to other embodiments through suitable modifications, substitutions, combinations, or separations.

[0090] It should be noted that, unless otherwise specified herein, having "a" element is not limited to having a single element, but may include one or more of the element.

[0091] Furthermore, unless otherwise specified, the ordinal numbers such as "first," "second," etc., used herein are merely for distinguishing multiple elements with the same name and do not indicate any hierarchy, order of execution, or process sequence among them. A "first" element and a "second" element may appear together in the same component or separately in different components. The presence of an element with a higher ordinal number does not necessarily indicate the presence of another element with a lower ordinal number.

[0092] In this document, unless otherwise specified, the term "characteristic A" or "and / or" and "characteristic B" means that A exists alone, B exists alone, or A and B exist simultaneously; the term "characteristic A" and "and" or "and" and "and" and "characteristic B" means that A and B exist simultaneously; the terms "including", "containing", "having", and "containing" refer to, but are not limited to, these.

[0093] Furthermore, in this document, terms such as "up," "down," "left," "right," "front," "back," or "between" are used only to describe the relative positions of multiple elements and can be extended to include translation, rotation, or mirroring. Additionally, unless otherwise specified, the statement "one element is on another element" or similar statements do not necessarily indicate that the element is in contact with the other element.

[0094] Furthermore, unless specifically described or required to occur in a specific order, the order of the above steps is not limited to those listed above and can be varied or rearranged according to the desired design. Moreover, the above embodiments can be used in combination with each other or with other embodiments based on design and reliability considerations; that is, technical features from different embodiments can be freely combined to form more embodiments.

[0095] The specific embodiments described above further illustrate the purpose, technical solutions, and beneficial effects of this disclosure. It should be understood that the above descriptions are merely specific embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A CMOS reference voltage source capable of providing a reference voltage at temperatures ranging from -40°C to 170°C, the CMOS reference voltage source comprising: The CTAT voltage generation unit includes a first circuit branch and a second circuit branch, which are used to generate the CTAT voltage and the bias voltage, respectively. as well as The PTAT voltage generation unit is used to generate a PTAT compensation voltage under the action of the bias voltage, so as to perform temperature compensation with the received CTAT voltage, obtain and output a reference voltage; The first circuit branch includes a first PMOS transistor group, a first NMOS transistor group, and a bias resistor R. b The second circuit branch includes a second PMOS transistor group, a second NMOS transistor group, and a second DTMOS transistor M9; 10 The PMOS transistors in the first PMOS transistor group and the second PMOS transistor group are symmetrically matched; the NMOS transistors in the first NMOS transistor group and the second NMOS transistor group are symmetrically matched; the first DTMOS transistor M9 and the second DTMOS transistor M... 10 The size ratio is N:1, where N ranges from 2 to 10; The sources of the PMOS transistors in both the first and second PMOS transistor groups are connected to the power supply voltage; the sources of the NMOS transistors in the first NMOS transistor group are connected to a bias resistor R. b One end, bias resistor R b The other end is connected to the source of the first DTMOS transistor M9. The substrate of the first DTMOS transistor M9 is connected to the drain and then grounded, and the gate of the first DTMOS transistor M9 is grounded. The sources of the NMOS transistors in the second NMOS transistor group are connected to the second DTMOS transistor M9. 10 The source of the second DTMOS transistor M 10 The substrate is connected to the drain and then grounded, and the second DTMOS transistor M 10 The gate is grounded; The first PMOS transistor group includes a first PMOS transistor M1 and a second PMOS transistor M2 with a size ratio of K:1, where K is 1-4; the second PMOS transistor group includes a third PMOS transistor M3 and a fourth PMOS transistor M4 with a size ratio of 1:K; the gates of the first PMOS transistor M1 and the fourth PMOS transistor M4 are connected and connected to the drain of the second PMOS transistor M2; the gates of the second PMOS transistor M2 and the third PMOS transistor M3 are connected and connected to the drain of the third PMOS transistor M3. The first NMOS transistor group includes a fifth NMOS transistor M5 and a sixth NMOS transistor M6 with a size ratio of K:1; the second NMOS transistor group includes a seventh NMOS transistor M7 and an eighth NMOS transistor M8 with a size ratio of 1:K; the gate of the fifth NMOS transistor M5 is connected to the gate of the seventh NMOS transistor M7 and is also connected to the drain of the fifth NMOS transistor M5, and the drain of the fifth NMOS transistor M5 is connected to the drain of the first PMOS transistor M1; the gate of the sixth NMOS transistor M6 is connected to the gate of the eighth NMOS transistor M8 and is also connected to the drain of the eighth NMOS transistor M8, and the drain of the eighth NMOS transistor M8 is connected to the drain of the fourth PMOS transistor M4; the drain of the sixth NMOS transistor M6 is connected to the drain of the second PMOS transistor M2, and the drain of the seventh NMOS transistor M7 is connected to the drain of the third PMOS transistor M3. The PTAT voltage generation unit includes an eleventh PMOS transistor M. 11 and a PMOS differential pair circuit with an NMOS current mirror load; the eleventh PMOS transistor M 11 The source of the transistor is connected to the power supply voltage, and its gate is connected to the drain of the second PMOS transistor M2, so as to generate a PTAT bias current at the drain under the action of the bias voltage. PMOS differential pair circuit with NMOS current mirror load and eleventh PMOS transistor M 11 The drain is connected to the voltage, which is used to generate the PTAT compensation voltage under the action of the bias voltage.

2. The CMOS reference voltage source according to claim 1, wherein, The PMOS differential pair circuit with NMOS current mirror load includes: First input PMOS transistor M D1 Its gate is connected to the second DTMOS transistor M. 10 The source is used to receive the CTAT voltage; Second input PMOS transistor M D2 Its gate is connected to the output port of the CMOS reference voltage source for outputting a reference voltage; First load current mirror M M1 Its gate is connected to the drain and then connected to the first input PMOS transistor M. D1 The drain is connected, and the source is grounded; and Second load current mirror M M2 Its gate is connected to the first load current mirror M. M1 The gate and drain of the transistor are connected to the second input PMOS transistor M. D2 The drain and gate are connected, and the source is grounded. Among them, the first input PMOS transistor M D1 Second input PMOS transistor M D2 The sources of all are connected to the eleventh PMOS transistor M. 11 The drain is used to generate the PTAT compensation voltage after receiving the PTAT bias current.

3. The CMOS reference voltage source according to claim 2, wherein, By adjusting the bias resistor R b The size of the PTAT bias current is determined by the size of the PMOS transistor, NMOS transistor, and DTMOS transistor in the first and second circuit branches. By adjusting the dimensions of the PMOS and NMOS transistors in the PMOS differential pair circuit with an NMOS current mirror load, the magnitude of the PTAT compensation voltage is adjusted, thereby achieving temperature compensation with the received CTAT voltage.

4. The CMOS reference voltage source according to claim 1 has a power supply voltage of less than 1V and a power consumption in the nW range.

5. A design method for a CMOS reference voltage source according to any one of claims 1-4, comprising: S1: Determine the bias resistor R in the CTAT voltage generation unit. b The size of the PMOS transistor, NMOS transistor, and DTMOS transistor in the first and second circuit branches are used to determine the nA level PTAT bias current. S2: Determine the dimensions of the PMOS and NMOS transistors in the PTAT voltage generation unit, thereby determining the magnitude of the PTAT compensation voltage; S3: At each process corner, by adjusting the dimensions of the PMOS and NMOS transistors in the PTAT voltage generation unit, temperature coefficient calibration of the reference voltage is achieved at each process corner; and S4: At each process angle, debug and verify the power supply rejection ratio and linear regulation of the reference voltage.

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