DAC offset voltage calibration circuit and calibration method

Abstract

This invention discloses a DAC offset voltage calibration circuit and calibration method. The DAC offset voltage calibration circuit includes N control nodes, a resistor array, and a current source. The resistor array includes: a first resistor, with its first and second ends connected to two adjacent control nodes respectively; and a second resistor, with its first end connected to a control node and its second end connected to a reference voltage V. REF Alternatively, it can be connected to ground potential; a third resistor, with its first end connected to the Nth control node and its second end connected to ground potential, and the resistance values ​​of both the second and third resistors are twice the resistance value of the first resistor; a current source is connected to at least one control node, and the current source is used to inject current into or draw current from the resistor array to calibrate the output node V. OUT The resulting offset voltage; where N is an integer and N≥2. This invention utilizes a current source to inject current into or extract current from a resistor array, thereby achieving calibration of the output node V. OUT The purpose of generating offset voltage.

Images