Display panel and display device

Abstract

The application provides a display panel and a display device. The display panel comprises a boosting circuit, the boosting circuit comprising a first switch, a second switch, a third switch, a first capacitor, a first gate signal line, a second gate signal line and a data signal line, and a constant voltage signal line. The control ends of the first switch and the second switch are electrically connected with the first gate signal line. The input end of the first switch is electrically connected with the data signal line, and the output end is electrically connected with a first node. The input end of the second switch is electrically connected with the constant voltage signal line, and the output end is electrically connected with a second node. The control end of the third switch is electrically connected with the second gate signal line, the input end is electrically connected with the data signal line, and the output end is electrically connected with the second node. The first plate and the second plate of the first capacitor are electrically connected with the first node and the second node, respectively. The boosting circuit in the display panel provided by the application can realize the voltage increase of the pixel electrode without changing the data signal voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device comprising the same. BACKGROUND

[0002] With the rapid development of display technology, display panels are widely used in people's daily life, such as televisions, computers, mobile phones and various electronic devices, and play an increasingly important role.

[0003] However, for some display panels, the voltage requirement of the data signal is high, and a higher voltage data signal is required, which results in high cost and high power consumption of the boost circuit of such display panels, thereby limiting the market competitiveness of such display panels, and further limiting the diversity development of display panels, which is not conducive to the wide application of display panels. SUMMARY

[0004] Therefore, the present application provides a display panel, and the scheme is as follows:

[0005] A display panel, comprising a first substrate and a second substrate, and a boost circuit layer and a pixel electrode layer arranged between the first substrate and the second substrate along a first direction, the first direction being directed from the first substrate to the second substrate; the boost circuit layer has a boost circuit, the boost circuit is electrically connected with a pixel electrode in the pixel electrode layer, and the boost circuit comprises a first switch, a second switch, a third switch, a first capacitor, a first gate signal line, a second gate signal line and a data signal line, and a constant voltage signal line;

[0006] The control end of the first switch is electrically connected with the first gate signal line, receives a first switch signal provided by the first gate signal line, and opens the first switch; the input end of the first switch is electrically connected with the data signal line, receives a data voltage signal provided by the data signal line, the output end of the first switch is electrically connected with a first node, and the first plate of the first capacitor is also electrically connected with the first node; the first node is an output port of the boost circuit, and the first node is also electrically connected with the pixel electrode in the pixel electrode layer;

[0007] The control end of the second switch is electrically connected with the first gate signal line, receives the first switch signal to open the second switch, the input end of the second switch is electrically connected with the constant voltage signal line, receives a constant voltage signal provided by the constant voltage signal line, and the output end of the second switch is electrically connected with a second node, and the second plate of the first capacitor is also electrically connected with the second node;

[0008] The control end of the third switch is electrically connected with the second gate signal line, receives a second switch signal provided by the second gate signal line, and opens the third switch.

[0009] Compared with the prior art, the technical scheme of the present application has the following beneficial effects:

[0010] The display panel provided in the present application comprises a boost circuit, which comprises a first switch, a second switch, a third switch, a first capacitor, a first gate signal line, a second gate signal line, a data signal line and a constant voltage signal line. The control ends of the first switch and the second switch are electrically connected with the first gate signal line, the input end of the first switch is electrically connected with the data signal line, and the output end is electrically connected with a first node. The input end of the second switch is electrically connected with the constant voltage signal line, and the output end is electrically connected with a second node. The control end of the third switch is electrically connected with the second gate signal line, the input end is electrically connected with the data signal line, and the output end is electrically connected with the second node. The first plate and the second plate of the first capacitor are respectively electrically connected with the first node and the second node. The first node is an output port of the boost circuit and is electrically connected with a pixel electrode. As known from the above, the opening of the first switch and the second switch is controlled through the first gate signal line, the opening of the third switch is controlled through the second gate signal line, the first plate of the first capacitor is electrically connected with the first switch, the second plate of the first capacitor is electrically connected with the second switch and the third switch, and thus the opening sequence of the first switch, the second switch and the third switch can be controlled through the first gate signal line and the second gate signal line, the first capacitor is self-boosted, and a self-boosting voltage is generated. Moreover, the output ends of the first switch and the third switch are electrically connected with the data signal line, and the input end of the second switch is electrically connected with the constant voltage signal line, and thus the voltage value of the self-boosting voltage is related to the voltage values of the data voltage signal and the constant voltage signal.

[0011] When the voltage of the constant voltage signal is 0, the voltage value of the self-boosting voltage is twice the voltage value of the data voltage signal, and thus the voltage value at the first node P1 is twice the voltage value of the data voltage signal, so that the voltage of the pixel electrode is twice the voltage value of the data voltage signal. Therefore, the boost circuit in the display panel provided in the present application can realize the increase of the voltage of the pixel electrode without changing the data signal voltage, that is, the display panel provided in the present application can realize high voltage of the pixel electrode with low data signal voltage, reduces the requirement for the voltage of the data signal, so that the voltage of the data voltage signal of the display panel can be low, and thus the cost and power consumption of the boost circuit of the display panel are low. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor based on the provided drawings.

[0013] The structures, proportions, sizes, etc. shown in the drawings of the present specification are only used to cooperate with the content disclosed in the present specification, to be understood and read by those skilled in the art, and are not used to limit the conditions that can be implemented by the present application, so they do not have technical significance. Any modification of structure, change of proportion relationship or adjustment of size, without affecting the effects and purposes that can be achieved by the present application, should still fall within the scope of the technical content disclosed by the present application.

[0014] Figure 1 A structural schematic diagram of a display panel provided by the present application is shown in the following figure:

[0015] Figure 2 A circuit diagram of a boost circuit in a display panel provided by the present application is shown in the following figure:

[0016] Figure 3 A timing diagram of a first switching signal, a second switching signal and a data voltage signal is shown in the following figure:

[0017] Figure 4 A structural schematic diagram of another display panel of the present application is shown in the following figure:

[0018] Figure 5 A circuit diagram of a boost circuit in another display panel provided by the present application is shown in the following figure:

[0019] Figure 6 A circuit diagram of a boost circuit in another display panel provided by the present application is shown in the following figure:

[0020] Figure 7 A structural schematic diagram of another display panel of the present application is shown in the following figure:

[0021] Figure 8 A structural schematic diagram of a boost circuit layer in a display panel provided by the present application is shown in the following figure:

[0022] Figure 9 A structural schematic diagram of a boost circuit layer in another display panel provided by the present application is shown in the following figure:

[0023] Figure 10 A structural schematic diagram of a boost circuit layer in another display panel provided by the present application is shown in the following figure:

[0024] Figure 11Fig. 2 shows a schematic diagram of a structure of a boost circuit layer in a display panel according to an embodiment of the present application;

[0025] Figure 12 Fig. 2 shows a schematic diagram of a structure of a boost circuit layer in a display panel according to an embodiment of the present application;

[0026] Figure 13 Fig. 2 shows a schematic diagram of a structure of a boost circuit layer in a display panel according to an embodiment of the present application;

[0027] Figure 14 Fig. 2 shows a schematic diagram of a structure of a boost circuit layer in a display panel according to an embodiment of the present application;

[0028] Figure 15 Fig. 2 shows a schematic diagram of a structure of a boost circuit layer in a display panel according to an embodiment of the present application. DETAILED DESCRIPTION

[0029] The embodiments of the present application will be described below in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments of the present application, all the other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of the present application.

[0030] In order to make the above objectives, features and advantages of the present application more apparent, the present application will be described in further detail below with reference to the accompanying drawings and specific embodiments.

[0031] As described in the background section, for a display panel requiring a higher voltage of a data signal, the higher voltage of the data signal results in a higher cost and power consumption of a boost circuit of the display panel, which limits the market competitiveness of the display panel, thereby limiting the development of the display panel and being not conducive to the wide application of the display panel.

[0032] Especially for a type of display panel commonly used in display panels, i.e., an electronic paper display panel, it is desired to apply a higher voltage on an electrophoretic film, which results in a higher voltage required for a corresponding pixel electrode and data signal, and further results in a higher voltage of the boost circuit, which further aggravates the cost and power consumption of the boost circuit, and is not conducive to the development and application of the electronic paper display panel.

[0033] Based on this, the present application provides a display panel, as shown in Figure 1 Figure 1 ​A structural schematic diagram of a display panel is provided in the present application, which comprises a first substrate 10 and a second substrate 20 (the second substrate 20 is not shown in the figure), and further comprises a boost circuit layer 30 and a pixel electrode layer 40 arranged along a first direction x between the first substrate 10 and the second substrate 20, wherein the first direction x is from the first substrate 10 to the second substrate 20. The boost circuit layer 30 comprises a boost circuit 100, as shown in Figure 2 Figure 2 A circuit diagram of a boost circuit 100 is provided in the present application, which comprises a first switch 101, a second switch 102, a third switch 103, a first capacitor 104, a first gate signal line 105, a second gate signal line 106, a data signal line 107 and a constant voltage signal line 108. It should be noted that the voltage of the signal on the constant voltage signal line 108 is a constant value. It should be noted that the adjacent film layers in the display panel are all insulated and separated by an insulating layer.

[0034] The control end of the first switch 101 is electrically connected with the first gate signal line 105, receives a first switch signal provided by the first gate signal line 105, and opens the first switch 101. The input end of the first switch 101 is electrically connected with the data signal line 107, and receives a data voltage signal provided by the data signal line 107. The output end of the first switch 101 is electrically connected with a first node P1. The first plate of the first capacitor 104 is also electrically connected with the first node P1, and the first node P1 is also electrically connected with a pixel electrode in the pixel electrode layer 40, that is, the first plate of the first capacitor 104 is electrically connected with the pixel electrode in the pixel electrode layer 40 through the first node P1, that is, the first plate of the first capacitor 104 is electrically connected with the pixel electrode in the pixel electrode layer 40.

[0035] The control end of the second switch 102 is electrically connected with the first gate signal line 105, receives the first switch to open the second switch 102. The input end of the second switch 102 is electrically connected with the constant voltage signal line 108, and receives a constant voltage signal provided by the constant voltage signal line. The output end of the second switch 102 is electrically connected with a second node P2, and the second plate of the first capacitor 104 is also electrically connected with the second node P2, that is, the output end of the second switch 102 is electrically connected with the second plate of the first capacitor 104 through the second node P2, that is, the output end of the second switch 102 is electrically connected with the second plate of the first capacitor 104.

[0036] ​The control end of the third switch 103 is electrically connected with the second gate signal line 106, receives the second switch signal provided by the second gate signal line 106, and opens the third switch 103. The input end of the third switch 103 is electrically connected with the data signal line 107, receives the data voltage signal, and the output end of the third switch 103 is electrically connected with the second node P2. It is known that the second plate of the first capacitor 104 is electrically connected with the second node P2, so the output end of the third switch 103 is electrically connected with the second plate of the first capacitor 104.

[0037] Specifically, in the embodiment of the present application, it is known from the above that the boost circuit includes the first capacitor 104, the first plate of the first capacitor 104 is electrically connected with the data signal line 107 through the first switch 101, the second plate of the first capacitor 104 is electrically connected with the constant voltage signal line 108 through the second switch 102, and the second plate of the first capacitor 102 is also electrically connected with the data signal line 107 through the third switch 103. And the first switch 101 and the second switch 102 are controlled to be opened through the first gate signal line 105, and the third switch 103 is controlled to be opened through the second gate signal line 106, so that the opening time and sequence of the first switch, the second switch and the third switch can be controlled through the first gate signal line 105 and the second gate signal line 106, the bootstrap of the output voltage of the first plate of the first capacitor 104 is realized, the bootstrap voltage is generated, and the voltage value of the finally generated bootstrap voltage is related to the voltage of the data voltage signal and the voltage of the constant voltage signal. For example, when the voltage of the constant voltage signal is 0, the voltage value of the bootstrap voltage is twice the voltage value of the data voltage signal, and the voltage value at the first node P1 is twice the voltage value of the data voltage signal, so that the voltage of the pixel electrode is twice the voltage value of the data voltage signal. Therefore, the boost circuit in the display panel provided by the present application can realize the increase of the voltage of the pixel electrode without changing the data signal voltage, that is, the display panel provided by the present application can realize high voltage of the pixel electrode with low data signal voltage, reduce the requirement for the voltage of the data signal, that is, the data voltage signal of the display panel can be lower, and the cost and power consumption of the boost circuit of the display panel are lower.

[0038] In an embodiment of the present application, the second gate signal line 106 is used to provide the second switch signal to open the third switch 103 after the first switch 101 and the second switch 102 are closed. Specifically, as shown in Figure 3 Figure 3 The timing diagram of the first switch signal Gate1, the second switch signal Gate2 and the data voltage signal Source is shown in Figure 3 ​It can be known that, when the voltage boosting circuit works, firstly, the first gate signal line 105 provides a first switch signal to open the first switch 101 and the second switch 102, so that the first plate of the first capacitor 104 is in communication with the data signal line 107, and the second plate of the first capacitor 104 is in communication with the constant voltage signal line 108, and then the voltage of the data voltage signal is charged to the first plate of the first capacitor 104, and the voltage of the constant voltage signal is charged to the second plate of the first capacitor 104, and the voltage of the first plate of the first capacitor 104 is the difference between the voltage of the data voltage signal and the voltage of the constant voltage signal, that is, the voltage at the first node P1 is the difference between the voltage of the data voltage signal and the voltage of the constant voltage signal. Then, the first switch 101 and the second switch 102 are closed, and after the first switch 101 and the second switch 102 are closed, the first plate of the first capacitor 104 is in a floating potential, and the charge quantity thereof no longer changes and is always the difference between the voltage of the data voltage signal and the voltage of the constant voltage signal.

[0039] Then, after the first switch 101 and the second switch 102 are closed, the second gate signal line 106 provides a second switch signal to open the third switch 103, so that the second plate of the first capacitor 104 is electrically connected with the data signal line 107, and the voltage of the data voltage signal is charged to the second plate of the first capacitor 104. Since the first switch 101 and the second switch 102 are closed, the voltage of the first plate of the first capacitor 104 is in a floating potential and no longer changes, and therefore when the voltage of the data voltage signal is charged to the second plate of the first capacitor 104, the voltage of the first plate of the first capacitor 104 will change due to the change of the voltage of the second plate thereof, and become the difference between 2 times the voltage value of the data voltage signal and the voltage value of the constant voltage signal. That is, if the voltage value of the data voltage signal is defined as V1 and the voltage value of the constant voltage signal is defined as V2, after the first switch 101 and the second switch 102 are closed and the third switch 103 is opened, the output voltage of the first plate of the first capacitor 104 is 2V1-V2, that is, the voltage at the first node P1 is 2V1-V2, so that when the voltage of the constant voltage signal is 0, the output voltage of the first plate of the first capacitor 104 is 2V1 which is 2 times the voltage of the data voltage signal. Therefore, the display panel provided by the present application can realize high voltage of the pixel electrode with low data signal voltage, thereby reducing the requirement for the voltage of the data signal, and the cost and power consumption of the voltage boosting circuit of the display panel are low.

[0040] It should be noted that after the first plate of the first capacitor 104 is at the floating potential, the third switch is opened, and the output voltage of the first plate of the first capacitor 104 changes according to the voltage difference between the voltage of the data voltage signal and the voltage of the constant voltage signal. When the constant voltage signal is not 0, if the voltage of the data voltage signal is less than the voltage of the constant voltage signal, the output voltage of the first plate of the first capacitor 104 is coupled downward, and if the voltage of the data voltage signal is greater than the voltage of the constant voltage signal, the output voltage of the first plate of the first capacitor 104 is coupled upward. However, generally, the voltage of the constant voltage signal is the average of the negative data voltage signal and the positive data voltage signal, so the voltage of the data voltage signal is generally greater than the voltage of the constant voltage signal.

[0041] In an embodiment of the present application, as shown in Figure 4 and Figure 5 , Figure 4 is another structural schematic diagram of a display panel provided by the present application, Figure 5 is a circuit schematic diagram of another boost circuit provided by the present application, and the display panel further comprises an electrophoretic display layer 50 and a common electrode layer 60 arranged along the first direction x between the first substrate 10 and the second substrate 20. The electrophoretic display layer 50 is located on the side of the pixel electrode layer away from the first substrate 10, the common electrode layer 60 is located between the electrophoretic display layer 50 and the second substrate 20, and on the side of the second substrate 20 facing the first substrate 10, and the common electrode layer 60 is used to provide a constant voltage signal, and the constant voltage signal line 108 is electrically connected with the common electrode layer 60. It should be noted that Figure 4 the connection between the common electrode layer 60 and the constant voltage signal line 108 is not shown in

[0042] Specifically, the display panel in the above embodiment is an electronic paper display panel, and the electric field formed between the pixel electrode layer 40 and the common electrode layer 60 controls the electrophoretic display layer to display a picture. Moreover, the common electrode layer 60 provides a constant voltage signal, so that the constant voltage signal line 108 is electrically connected with the common electrode layer 60, and the display panel does not need to be equipped with an additional constant voltage source, thereby simplifying the structure of the display panel and making the preparation process simpler.

[0043] It should be noted that the capacitance on the side of the second plate of the first capacitor 104 in the boost circuit of the display panel provided by the present application will affect the self-boosting effect of the output voltage of the first capacitor 104, i.e., the self-boosting voltage. The greater the capacitance on the side of the second plate of the first capacitor 104, the better the self-boosting effect. Therefore, in an embodiment of the present application, as shown in Figure 6 Figure 6 ​The circuit diagram for another boost circuit provided in this application shows that the boost circuit 100 further includes a second capacitor 109. The first plate of the second capacitor 109 is electrically connected to the second node P2, and the second plate of the second capacitor 109 is electrically connected to the constant voltage signal line 108 to receive a constant voltage signal. Specifically, it is known that the second plate of the first capacitor 104 is electrically connected to the second node P2, and the first plate of the second capacitor 109 is also electrically connected to the second node P2. Therefore, the second plate of the first capacitor 104 and the second capacitor 109 are electrically connected through the second node P2. That is to say, the second plate of the first capacitor 104 is also electrically connected to a capacitor, such that the capacitance on one side of the second plate of the first capacitor 104 is the sum of the capacitance of the first plate of the first capacitor 104 and the second capacitor. Thus, the second capacitor 109 can increase the capacitance of the second plate of the first capacitor 104, which helps to ensure the bootstrapping of the output capacitance of the first plate of the first capacitor 104.

[0044] Furthermore, it is known that the second switch 102 and the third switch 103 are electrically connected to the first plate of the first capacitor 104. The aforementioned boost circuit is also electrically connected to a second capacitor 109 on one side of the second plate of the first capacitor 104, which increases the capacitance on one side of the second plate of the first capacitor 104. Therefore, it is not necessary to use the second switch 102 and the third switch 103 with larger capacitance to ensure the bootstrap effect. This reduces the capacitance requirements of the boost circuit on the second switch 102 and the third switch 103, allowing ordinary switches to meet the requirements of the boost circuit 100. This helps to reduce the cost of the boost circuit 100 and, consequently, the cost of the display panel.

[0045] To gain a clearer understanding of the display panel provided in this application, the layout of the boost circuit layer in the display panel provided in this application is described below.

[0046] In one embodiment of this application, such as Figure 7 and Figure 8 As shown, Figure 7 This is a schematic diagram of the structure of a display panel provided in this application. Figure 8A structure diagram of a boost circuit layer in a display panel is provided, the boost circuit layer 30 includes: a first metal layer 31 and a second metal layer 32 arranged in sequence along a first direction. The first metal layer 31 includes a first gate signal line 105, a first sub-metal layer 311 and a second gate signal line 106 arranged in sequence along a second direction y, and the second metal layer 32 includes a constant voltage signal line 108, a second sub-metal layer 321 and a data signal line 107 arranged in sequence along a third direction z, the second direction y and the third direction z are both parallel to the plane where the first substrate 10 is located, and the second direction y and the third direction z are perpendicular to each other. Among them, the second sub-metal layer 321 and the part of the pixel electrode layer 40 corresponding to the second sub-metal layer 321 constitute a first capacitor 104, the second sub-metal layer 321 is opposite to the first sub-metal layer 311, and the second sub-metal layer 321 and the first sub-metal layer 311 constitute a second capacitor 109. It should be noted that it is known that adjacent film layers in the display panel are insulated and isolated by an insulating layer, so the first metal layer 31 and the second metal layer 32 are electrically connected through the first via hole 101, the second metal layer 32 and the pixel electrode layer 40 are electrically connected through the second via hole 102, and the same is true in the following embodiments, which will not be described here.

[0047] As can be seen from the above, the second plate of the second capacitor 105 in the boost circuit layer 30 is located in the same metal layer as the first gate signal line 105 and the second gate signal line 106, and is located between the first gate signal line 105 and the second gate signal line 106, which can be formed in the same process step as the first gate signal line 105 and the second gate signal line 106. The first metal layer 30 can be etched to simultaneously prepare the first gate signal line 105, the second gate signal line 106 and the first sub-metal layer 311, thereby simplifying the preparation process of the display panel. Moreover, the first sub-metal layer 311 is located in the same metal layer as the first gate signal line 105 and the second gate signal line 106, so a separate metal layer does not need to be formed for the second plate of the second capacitor 109, which can simplify the structure of the display panel and also reduce the thickness of the display panel. Similarly, the second sub-metal layer 321 belongs to the same metal layer as the constant voltage signal line 108 and the data voltage signal line 107, which can simplify the structure and preparation process of the display panel and reduce the thickness of the display panel.

[0048] Moreover, as can be seen from the above, the first sub-metal layer 311 and the second sub-metal layer 321 constitute the second capacitor 105, and the second sub-metal layer 321 and the part of the pixel electrode layer 40 corresponding to the second sub-metal layer 321 constitute the first capacitor 104. As can be seen, the second sub-metal layer 321 serves as both the first plate of the first capacitor 104 and the second plate of the second capacitor 105, thereby reducing the number of metal layers in the boost circuit layer 30 as much as possible, and further simplifying the structure and preparation process of the display panel.

[0049] On the basis of the above-mentioned embodiments, in one embodiment of the present application, as shown in Figure 7 and Figure 9 , Figure 8 Another structure schematic diagram of a boost circuit layer in a display panel provided by the present application is shown in the figure, the boost circuit layer 30 further includes an active layer 33 for forming the first switch 101, the second switch 102 and the third switch 103, and the active layer 33 is located between the first substrate 10 and the first metal layer 31, and the projection of the active layer 33 on the first substrate 10 is located between the projections of the first gate signal line 105 and the second gate signal line 106 on the first substrate 10, and also between the second sub-metal layer 321 and the projection of the data signal line 107 on the first substrate 10, the active layer 33 includes a first active layer 331, a second active layer 332 and a third active layer 333. Wherein one end of the first active layer 331 is electrically connected with the data signal line 107, and the other end is electrically connected with the pixel electrode layer 40. The first metal layer 31 further includes a third sub-metal layer 312 electrically connected with the first gate signal line 105, and the projection of the third sub-metal layer 312 on the first substrate 10 has a first overlapping area with the projection of the first active layer 331 on the first substrate 10, forming the first switch 101.

[0050] Specifically, the projection of the third sub-metal layer 312 on the first substrate 10 has a first overlapping area with the projection of the first active layer 331 on the first substrate 10, forming the first switch 101, that is, the part of the third sub-metal layer 312 and the first active layer 331 mutually overlapping constitutes the first switch 101, the first switch 101 includes the part belonging to the third sub-metal layer 312 and the part belonging to the first active layer 331, and the third sub-metal layer 312 is electrically connected with the first gate signal line 105, so that the control end of the first switch 101 is electrically connected with the first gate signal line 105. And one end of the first active layer 331 is electrically connected with the data signal line 107, so that the input end of the first switch 101 is electrically connected with the data signal line 107, and the other end of the first active layer 331 is electrically connected with the pixel electrode layer 40, so that the output end of the first switch 101 is electrically connected with the pixel electrode layer 40.

[0051] On the basis of the above-mentioned embodiments, in the embodiments of the present application, one end of the second active layer 332 is electrically connected with the constant voltage signal line 108 through the first sub-metal layer 311, and the other end is electrically connected with one end of the third active layer 333. The projection of the third sub-metal layer 312 on the first substrate 10 also has a second overlapping area with the projection of the second active layer 332 on the first substrate 10, forming the second switch 102. Meanwhile, the end of the third active layer 333 electrically connected with the second active layer 332 is also electrically connected with the second sub-metal layer 321, and the other end is electrically connected with the data signal line 107. The first metal layer 31 further comprises a fourth sub-metal layer 313 electrically connected with the second gate signal line 106. The projection of the fourth sub-metal layer 313 on the first substrate 10 has a third overlapping area with the projection of the third active layer 333 on the first substrate 10, forming the third switch 103.

[0052] Specifically, the projection of the third sub-metal layer 312 on the first substrate 10 also has a second overlapping area with the projection of the second active layer 332 on the first substrate 10, forming the second switch 102. That is, the part of the third sub-metal layer 312 and the part of the second active layer 332 that are mutually overlapped constitute the second switch 102. The third sub-metal layer 312 is electrically connected with the first gate signal line 105, so that the control end of the second switch 102 is electrically connected with the first gate signal line. And one end of the second active layer 332 is electrically connected with the constant voltage signal line 108 through the first sub-metal layer 311, so that the input end of the second switch 102 is electrically connected with the constant voltage signal line 108. The other end of the second active layer 332 is electrically connected with the third active layer 333, so that the output end of the second switch 102 is electrically connected with one end of the third active layer 333.

[0053] The projection of the fourth sub-metal layer 313 on the first substrate 10 has a third overlapping area with the projection of the third active layer 333 on the first substrate 10, forming the third switch 103. That is, the part of the fourth sub-metal layer 313 and the part of the third active layer 333 that are mutually overlapped constitute the third switch 103. The third switch 103 comprises the part of the fourth sub-metal layer 313 and the part of the third active layer 333. The fourth sub-metal layer 313 is electrically connected with the second gate signal line 106, so that the control end of the third switch 103 is electrically connected with the second gate signal line 106. And the end of the third active layer 333 electrically connected with the second active layer 332 is electrically connected with the second sub-metal layer 321, and the other end is electrically connected with the data signal line 107, so that the input end of the third switch 103 is electrically connected with the data signal line 107, and the output end is electrically connected with the second plate of the first capacitor 104. And the output end of the second switch 102 is electrically connected with the second plate of the first capacitor 104.

[0054] It should be noted that the second plate of the second capacitor 109 can be located on the side of the second gate signal line 106 away from the first gate signal line 105 in addition to being located between the first gate signal line 105 and the second gate signal line 106. Therefore, in another embodiment of the present application, as shown in Figure 7 and Figure 10 , Figure 8 FIG. 2 is a structural diagram of a boost circuit layer in a display panel provided by the present application. The boost circuit layer 30 includes a first metal layer 31 and a second metal layer 32 arranged in sequence along a first direction x. The first metal layer 31 includes a first gate signal line 105, a second gate signal line 106, and a fifth sub-metal layer 314 arranged in sequence along a second direction y, and the fifth sub-metal layer 314 includes a constant voltage signal line 108. The second metal layer 32 includes a sixth sub-metal layer 322 and a data signal line 107 arranged in sequence along a third direction z, and the second direction y and the third direction z are both parallel to the plane on which the first substrate 10 is located, and the second direction x and the third direction z are perpendicular to each other. The sixth sub-metal layer 322 and the portion of the pixel electrode layer 40 corresponding to the sixth sub-metal layer 322 constitute a first capacitor 104, the sixth sub-metal layer 322 is opposite to the fifth sub-metal layer 314, and the sixth sub-metal layer 322 and the fifth sub-metal layer 314 constitute a second capacitor 109, so that the sixth sub-metal layer 322 is the second plate of the first capacitor 104 and the first plate of the second capacitor 109.

[0055] Specifically, as known from the above, the first metal layer 31 includes the first gate signal line 105, the second gate signal line 106, and the fifth sub-metal layer 314, and the fifth sub-metal layer 314 includes the constant voltage signal line 108, so that the first gate signal line 105, the second gate signal line 106, the constant voltage signal line 108, the first plate of the first capacitor 104, and the second plate of the second capacitor 109 belong to the same metal layer and can be obtained in the same process step, thereby simplifying the process flow of the display panel. Moreover, the sixth sub-metal layer 322 is the second plate of the first capacitor 104 and the first plate of the second capacitor 109, so that the first capacitor 104 and the second capacitor 109 are constituted by three metal layers arranged in sequence, thereby simplifying the structure of the display panel and making the structure of the display panel relatively simple.

[0056] On the basis of the above embodiment, in an embodiment of the present application, as shown in Figure 7 and Figure 11 , Figure 11In another structure of the boost circuit layer in the display panel provided in the present application, the boost circuit layer 30 further comprises an active layer 33 between the first substrate 10 and the first metal layer 31, and the active layer 33 comprises a first active layer 331, a second active layer 332 and a third active layer 333. The first active layer 331 is electrically connected to the data signal line 107 at one end and to the pixel electrode layer 40 at the other end. The first metal layer 31 further comprises a seventh sub-metal layer 315 electrically connected to the first gate signal line 105, and the projection of the seventh sub-metal layer 315 on the first substrate 10 has a fourth overlapping area with the projection of the first active layer 331 on the first substrate 10, forming the first switch 101. Specifically, as known from the foregoing, the projection of the seventh sub-metal layer on the first substrate 10 has a fourth overlapping area with the projection of the first active layer 331 on the first substrate 10, forming the first switch 101, and the first switch 101 comprises a part belonging to the seventh sub-metal layer 315 and a part belonging to the first active layer 331, and the seventh sub-metal layer 315 is electrically connected to the first gate signal line 105, so that the control end of the first switch 101 is electrically connected to the first gate signal line 105. Meanwhile, the two ends of the first active layer 331 are respectively electrically connected to the data signal line 107 and the pixel electrode layer 40, so that the input end of the first switch 101 is electrically connected to the data signal line 107, and the output end of the first switch 101 is electrically connected to the pixel electrode layer 40.

[0057] In the embodiment of the present application, the second active layer 332 is electrically connected to the fifth sub-metal layer 314 at one end and to the third active layer 333 at the other end. The first metal layer 31 further comprises an eighth sub-metal layer 316 electrically connected to the first gate signal line 105, and the projection of the eighth sub-metal layer 316 on the first substrate 10 has a fifth overlapping area with the projection of the second active layer 332 on the first substrate 10, forming the second switch 102. Specifically, as known from the foregoing, the second switch 102 comprises a part belonging to the eighth sub-metal layer 316 and a part belonging to the second active layer 332, and the eighth sub-metal layer 316 is electrically connected to the first gate signal line 105, so that the control end of the second switch 102 is electrically connected to the first gate signal line 105. Meanwhile, the two ends of the second active layer are respectively electrically connected to the fifth sub-metal layer 314 and the third active layer 333, and it is known that the fifth sub-metal layer 314 comprises a constant voltage signal line, so that the input end of the second switch 102 is electrically connected to the constant voltage signal line, and the output end is electrically connected to the third active layer 333.

[0058] In the embodiment of the present application, one end of the third active layer 333, which is electrically connected with the second active layer 332, is electrically connected with the sixth sub-metal layer 322, and the other end is electrically connected with the data signal line 107 through the first active layer 331. The projection of the second gate signal line 106 on the first substrate 10 has a sixth overlapping area with the projection of the third active layer 333 on the first substrate 10, forming the third switch 103. As known from the above, the third switch 103 includes a part belonging to the second gate signal line 106 and a part belonging to the third active layer 333, so that the control end of the third switch 103 is electrically connected with the second gate signal line 106, and the two ends of the third active layer 333 are respectively electrically connected with the sixth sub-metal layer 322 and the data signal line 107, so that the input end of the third switch 103 is electrically connected with the data signal line 107, and the output end of the third switch 103 is electrically connected with the sixth sub-metal layer 322. It is known that the sixth sub-metal layer 322 is the first plate of the first capacitor 104, so that the output end of the third switch 103 is electrically connected with the first plate of the first capacitor 104. It is also known that the output end of the second switch 102 is electrically connected with one end of the third active layer 333, and the end of the third active layer 333, which is electrically connected with the second active layer 332, is electrically connected with the sixth sub-metal layer 322, so that the output end of the second switch 102 is electrically connected with the first plate of the first capacitor 104.

[0059] Optionally, in one embodiment of the present application, the first switch 101, the second switch 102 and the third switch 103 are all MOS tubes, and the channel types are the same. On this basis, in order to meet the anti-leakage requirements of the boost circuit, the first switch 101, the second switch 102 and the third switch 103 can be MOS tubes with double-gate structure. Therefore, in one embodiment of the present application, as shown in FIG. 1, Figure 12 Figure 12 ​In another structure of a boost circuit layer in a display panel provided in the present application, the first switch 101 includes a first sub-switch 1011 and a second sub-switch 1012, and the first active layer 331 includes a first portion 3311, a second portion 3312 and a third portion 3313. The projection of the first portion 3311 and the projection of the second portion 3312 on the first substrate 10 are located between the projection of the first gate signal line 105 and the projection of the second gate signal line 106 on the first substrate 10, the first portion 3311 is electrically connected with the data signal line 107, the second portion 3312 is electrically connected with the pixel electrode layer 40, and the third portion 3313 electrically connects the first portion 3311 and the second portion 3312, that is, the two ends of the third portion 3313 are electrically connected with the first portion 3311 and the second portion 3312 respectively, that is, the first portion 3311 and the second portion 3312 are electrically connected through the third portion 3313. The fourth overlap region includes a first sub-overlap region and a second sub-overlap region, and the projection of the first gate signal line on the first substrate 10 and the projection of the third portion 3313 on the first substrate 10 have the first sub-overlap region and the second sub-overlap region to form the first sub-switch 1011 and the second sub-switch 1012 respectively.

[0060] Specifically, the projection of the first gate signal line on the first substrate 10 and the projection of the third portion 3313 on the first substrate 10 have the first sub-overlap region and the second sub-overlap region to form the first sub-switch 1011 and the second sub-switch 1012 respectively, and the control end of the first sub-switch 1011 is electrically connected with the control end of the second sub-switch 1012, and in addition, the third portion 3313 also electrically connects the first portion 3311 and the second portion 3312, so that the output end of the first sub-switch 1011 is electrically connected with the input end of the second sub-switch 1012, thereby making the first switch 101 a double-gate structure, and the input end of the double-gate structure is electrically connected with the data signal line 107, and the output end is electrically connected with the pixel electrode layer 40.

[0061] On the basis of the above-mentioned embodiments, in one embodiment of the present application, as shown in Figure 13 Figure 13 ​This is a schematic diagram of the boost circuit layer in another display panel provided in this application. The second switch 102 includes a third sub-switch 1021 and a fourth sub-switch 1022. The second active layer 332 includes a fourth portion 3321, a fifth portion 3322, and a sixth portion 3323. The projections of the fourth portion 3321 and the fifth portion 3322 onto the first substrate 10 are located between the projections of the first gate signal line 105 and the second gate signal line 106 onto the first substrate 10. The fourth portion 3321 is electrically connected to the fifth sub-metal layer 314, the fifth portion 3322 is electrically connected to the third active layer 333, and the sixth portion 3323 is electrically connected to the fourth portion 3321 and the fifth portion 3322. The fifth overlapping region includes a third sub-overlapping region and a fourth sub-overlapping region. The projections of the first gate signal line 105 onto the first substrate 10 and the sixth portion 3323 onto the first substrate 10 have third and fourth sub-overlapping regions, respectively forming the third sub-switch 1021 and the fourth switch 1022.

[0062] As described above, the projection of the first gate signal line 105 on the first substrate 10 and the projection of the sixth portion 3323 on the first substrate 10 have a third sub-overlapping region and a fourth sub-overlapping region, respectively forming the third sub-switch 1021 and the fourth sub-switch 1022. Therefore, the control terminals of the third sub-switch 1021 and the fourth sub-switch 1022 are electrically connected. Furthermore, the two ends of the sixth portion 3323 are electrically connected to the fourth portion 3321 and the fifth sub-metal layer 3322, respectively. The fourth portion 3321 is electrically connected to the fifth sub-metal layer 314, and the fifth portion 3322 is electrically connected to the third active layer 333. The input terminal of the third sub-switch 1021 is electrically connected to the constant voltage signal line 108, and the output terminal is electrically connected to the input terminal of the fourth sub-switch 1022. The output terminal of the fourth sub-switch 1022 is electrically connected to the third active layer 333. Thus, the second switch 102 is a dual-gate structure switch including the third sub-switch 1021 and the fourth sub-switch 1022.

[0063] Based on the above embodiments, in one embodiment of this application, such as Figure 14 As shown, Figure 14In another structure of a boost circuit layer in a display panel provided in the present application, the third switch 103 includes a fifth sub-switch 1031 and a sixth sub-switch 1032, the third active layer 333 includes a seventh part 3331, an eighth part 3332 and a ninth part 3333, the projection of the seventh part 3331 and the eighth part 3332 on the first substrate 10 is located between the projection of the first gate signal line 105 and the second gate signal line 106 on the first substrate 10, the seventh part 3331 is electrically connected with the first part 3311, the eighth part 3332 is connected with the fifth part 3322, the eighth part 3332 is also electrically connected with the sixth sub-metal layer 322, and the ninth part 3333 electrically connects the seventh part 3331 and the eighth part 3332. The sixth overlap area includes a fifth sub-overlap area and a sixth sub-overlap area, and the projection of the second gate signal line 106 on the first substrate 10 has the fifth sub-overlap area and the sixth sub-overlap area with the surface of the ninth part 3333 on the first substrate 10, so as to form the fifth sub-switch 1031 and the sixth sub-switch 1032 respectively.

[0064] Specifically, the projection of the second gate signal line 106 on the first substrate 10 has the fifth sub-overlap area and the sixth sub-overlap area with the surface of the ninth part 3333 on the first substrate 10, so as to form the fifth sub-switch 1031 and the sixth sub-switch 1032 respectively, so as to form the fifth sub-switch 1031 and the sixth sub-switch 1032 which are electrically connected at the control end. Moreover, the ninth part 3333 electrically connects the seventh part 3331 and the eighth part 3332, while the seventh part 3331 is electrically connected with the first part 3311, the eighth part 3332 is connected with the fifth part 3322, and the eighth part 3332 is also electrically connected with the sixth sub-metal layer 322, so that the input end of the fifth sub-switch 1031 is electrically connected with the data signal line 107, the output end is electrically connected with the input end of the sixth sub-switch 1032, and the output end of the sixth sub-switch 1032 is electrically connected with the first plate of the first capacitor 104, so that the third switch 103 is a double-gate structure including the fifth sub-switch 1031 and the sixth sub-switch 1032.

[0065] It should be noted that the above embodiments describe the case that the first pair of the first sub-metal layer 311 is located between the first gate signal line 105 and the second gate signal line 106, and the first gate signal line 105 is located at the outermost side, and the second gate signal line 106 is located between the first gate signal line 105 and the first metal layer 31, but in actual cases, this is not limited, and the positional relationship between the three can also be that the second gate signal line 106 is located at the outermost side, and the first gate signal line 105 is located between the second gate signal line 106 and the first metal layer 31, etc. Moreover, the first switch 101, the second switch 102 and the third switch 103 can also be set to a double-gate structure according to actual conditions. Specifically, in a specific embodiment of the present application, as shown inFigure 15 As shown, Figure 15 Fig. 3 is a structural schematic diagram of a boost circuit layer of a display panel in one embodiment of the present application. In the embodiment, the first gate signal line 105 is located between the second gate signal line 106 and the first metal layer 31, and the second switch 102 and the third switch 103 are double-gate structures.

[0066] Optionally, in one embodiment of the present application, as shown in Fig. 3, the first switch signal is a pulse signal, the second switch signal is a pulse signal, and the data voltage signal is a pulse signal. The pulse width of the data voltage signal is greater than the sum of the pulse widths of the first switch signal and the second switch signal, i.e., the data voltage signal, so that the voltage value of the data voltage signal on the data signal line 107 remains unchanged and stable during the time when the first gate signal line 105 provides the first gate signal line and the second gate signal line 106 provides the second gate signal line. In this way, the data voltage signal remains unchanged during the entire working process of the boost circuit, so as to ensure the stability of the working of the boost circuit and avoid the change of the final output bootstrap voltage due to the change of the data voltage, thereby affecting the reliability of the boost circuit.

[0067] On the basis of the above embodiment, in one preferred embodiment of the present application, the pulse width of the first switch signal is equal to the pulse width of the second switch signal, and the pulse height of the first switch signal is equal to the pulse height of the second switch signal. However, the present application is not limited thereto, and in other embodiments of the present application, the pulse width of the first switch signal can be different from the pulse width of the second switch signal, and the pulse height of the first switch signal can be different from the pulse height of the second switch signal. The specific conditions are determined according to the situation, as long as the pulse width of the data voltage signal is greater than the sum of the pulse widths of the first switch signal and the second switch signal.

[0068] It should be noted that in the embodiments of the present application, the material of the active layer 33 can be any material capable of preparing an active layer. However, the layout structure in the above-described embodiment of the display panel layout is introduced on the basis that the material of the active layer is polysilicon. If the material of the active layer is other material, the layout can be modified accordingly, which will not be described here.

[0069] The present application also provides a display device, which comprises the display panel described in any of the above-described embodiments. It should be noted that the display panel has been described in detail in the above-described embodiments, which will not be described here.

[0070] In summary, the display panel and the display device are provided, the display panel comprises a boost circuit, the boost circuit comprises a first switch, a second switch, a third switch, a first capacitor, a first gate signal line, a second gate signal line and a data signal line, and a constant voltage signal line. The control end of the first switch and the second switch is electrically connected with the first gate signal line. The input end of the first switch is electrically connected with the data signal line, and the output end is electrically connected with a first node. The input end of the second switch is electrically connected with the constant voltage signal line, and the output end is electrically connected with a second node. The control end of the third switch is electrically connected with the second gate signal line, the input end is electrically connected with the data signal line, and the output end is electrically connected with the second node. The first plate and the second plate of the first capacitor are electrically connected with the first node and the second node respectively. The boost circuit in the display panel provided by the application can realize the voltage rise of the pixel electrode without changing the data signal voltage.

[0071] The various embodiments in the specification are described in a progressive, or parallel, or progressive and parallel combination manner, and each embodiment focuses on the difference from other embodiments. The same or similar regions between various embodiments can be referred to each other. For the device disclosed by the embodiments, since it corresponds to the method disclosed by the embodiments, the description is relatively simple, and the related parts can be referred to the method area description.

[0072] It should be noted that in the description of the present application, it should be understood that the terms "upper", "lower", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, therefore it cannot be understood as a limitation on the present application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there can be a component disposed therebetween.

[0073] It should also be noted that in this paper, relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such article or device. Without more limitation, the element defined by the sentence "including a…" does not exclude the presence of other identical elements in the article or device including the above-mentioned element.

[0074] The foregoing description of the disclosed embodiments enables a person skilled in the art to make or use the application. Modifications of these embodiments will occur to persons of skill in the art, and that the generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. Therefore, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized by, The display panel comprises a first substrate and a second substrate, and a boost circuit layer and a pixel electrode layer arranged along a first direction between the first substrate and the second substrate, the first direction being from the first substrate to the second substrate; The boost circuit layer has a boost circuit electrically connected with a pixel electrode in the pixel electrode layer, the boost circuit comprising a first switch, a second switch, a third switch, a first capacitor, a second capacitor, a first gate signal line, a second gate signal line and a data signal line, and a constant voltage signal line; The control end of the first switch is electrically connected with the first gate signal line to receive a first switch signal provided by the first gate signal line to open the first switch; the input end of the first switch is electrically connected with the data signal line to receive a data voltage signal provided by the data signal line; the output end of the first switch is electrically connected with a first node, and the first plate of the first capacitor is also electrically connected with the first node; the first node is an output port of the boost circuit, and is also electrically connected with the pixel electrode in the pixel electrode layer; The control end of the second switch is electrically connected with the first gate signal line to receive the first switch signal to open the second switch; the input end of the second switch is electrically connected with the constant voltage signal line to receive a constant voltage signal provided by the constant voltage signal line; the output end of the second switch is electrically connected with a second node, and the second plate of the first capacitor is also electrically connected with the second node; the first plate of the second capacitor is electrically connected with the second node, and the second plate of the second capacitor is electrically connected with the constant voltage signal line to receive the constant voltage signal; The control end of the third switch is electrically connected with the second gate signal line to receive a second switch signal provided by the second gate signal line to open the third switch; the input end of the third switch is electrically connected with the data signal line to receive the data voltage signal; and the output end of the third switch is electrically connected with the second node. The boost circuit layer comprises a first metal layer and a second metal layer arranged along the first direction; the first metal layer comprises the first gate signal line, a first sub-metal layer and the second gate signal line arranged along a second direction in sequence; the second metal layer comprises the constant voltage signal line, a second sub-metal layer and the data signal line arranged along a third direction in sequence; the second direction and the third direction are both parallel to the plane where the first substrate is located, and the second direction and the third direction are perpendicular; The second sub-metal layer and the part of the pixel electrode layer corresponding to the second sub-metal layer constitute the first capacitor, and the second sub-metal layer is opposite to the first sub-metal layer to constitute the second capacitor.

2. The display panel of claim 1, wherein, The second gate signal line is used to provide the second switch signal to open the third switch after the first switch and the second switch are closed.

3. The display panel of claim 1, wherein, The display panel further comprises an electrophoretic display layer and a common electrode layer arranged along the first direction between the first substrate and the second substrate, the electrophoretic display layer being located on a side of the pixel electrode layer away from the first substrate; The common electrode layer provides the constant voltage signal, and the constant voltage signal line is electrically connected with the common electrode layer.

4. The display panel of claim 1, wherein, The boost circuit layer further comprises an active layer, the active layer being located between the first substrate and the first metal layer, and a projection of the active layer on the first substrate being located between projections of the first gate signal line and the second gate signal line on the first substrate, and between projections of the second sub-metal layer and the data signal line on the first substrate, the active layer comprising a first active layer, a second active layer and a third active layer; One end of the first active layer is electrically connected with the data signal line, and the other end is electrically connected with the pixel electrode layer; the first metal layer further comprises a third sub-metal layer electrically connected with the first gate signal line, and a projection of the third sub-metal layer on the first substrate has a first overlapping area with a projection of the first active layer on the first substrate, forming the first switch; One end of the second active layer is electrically connected with the constant voltage signal line through the first sub-metal layer, and the other end is electrically connected with one end of the third active layer, and a projection of the third sub-metal layer on the first substrate further has a second overlapping area with a projection of the second active layer on the first substrate, forming the second switch; The other end of the third active layer electrically connected with the second active layer is electrically connected with the second sub-metal layer, and the other end is electrically connected with the data signal line; the first metal layer further comprises a fourth sub-metal layer electrically connected with the second gate signal line, and a projection of the fourth sub-metal layer on the first substrate has a third overlapping area with a projection of the third active layer on the first substrate, forming the third switch.

5. The display panel of claim 1, wherein, The boost circuit layer comprises a first metal layer and a second metal layer arranged along the first direction; The first metal layer comprises a first gate signal line, a second gate signal line and a fifth sub-metal layer arranged along a second direction in sequence, and the constant voltage signal line is included in the fifth sub-metal layer; the second metal layer comprises a sixth sub-metal layer and the data signal line arranged along a third direction in sequence; the second direction and the third direction are both parallel to a plane in which the first substrate is located, and the second direction and the third direction are perpendicular; The sixth sub-metal layer and a portion of the pixel electrode layer opposite to the sixth sub-metal layer constitute the first capacitor, and the sixth sub-metal layer is opposite to the fifth sub-metal layer, constituting the second capacitor.

6. The display panel of claim 5, wherein, The boost circuit layer further comprises an active layer, the active layer being located between the first substrate and the first metal layer, and the active layer comprising a first active layer, a second active layer and a third active layer; The first active layer is electrically connected to the data signal line at one end and to the pixel electrode layer at the other end; the first metal layer further comprises a seventh sub-metal layer electrically connected to the first gate signal line, and a fourth overlap area between a projection of the seventh sub-metal layer on the first substrate and a projection of the first active layer on the first substrate forms the first switch; The second active layer is electrically connected to the fifth sub-metal layer at one end and to the third active layer at the other end; the first metal layer further comprises an eighth sub-metal layer electrically connected to the first gate signal line, and a fifth overlap area between a projection of the eighth sub-metal layer on the first substrate and a projection of the second active layer on the first substrate forms the second switch; The third active layer is electrically connected to the sixth sub-metal layer at one end and to the data signal line through the first active layer at the other end; a sixth overlap area between a projection of the second gate signal line on the first substrate and a projection of the third active layer on the first substrate forms the third switch.

7. The display panel of claim 6, wherein, The first switch comprises a first sub-switch and a second sub-switch, the first active layer comprises a first part, a second part and a third part, the first part and the second part are located between projections of the first gate signal line and the second gate signal line on the first substrate, the first part is electrically connected to the data signal line, the second part is electrically connected to the pixel electrode layer, and the third part electrically connects the first part and the second part; The fourth overlap area comprises a first sub-overlap area and a second sub-overlap area, and the first gate signal line has the first sub-overlap area and the second sub-overlap area with the third part on the first substrate, respectively forming the first sub-switch and the second sub-switch.

8. The display panel of claim 7, wherein, The second switch comprises a third sub-switch and a fourth sub-switch, the second active layer comprises a fourth part, a fifth part and a sixth part, the fourth part and the fifth part are located between projections of the first gate signal line and the second gate signal line on the first substrate, the fourth part is electrically connected to the fifth sub-metal layer, the fifth part is electrically connected to the third active layer, and the sixth part electrically connects the fourth part and the fifth part; The fifth overlap area comprises a third sub-overlap area and a fourth sub-overlap area, and the first gate signal line has the third sub-overlap area and the fourth sub-overlap area with the sixth part on the first substrate, respectively forming the third sub-switch and the fourth sub-switch.

9. The display panel of claim 8, wherein, The third switch comprises a fifth sub-switch and a sixth sub-switch, the third active layer comprises a seventh part, an eighth part and a ninth part, projections of the seventh part and the eighth part on the first substrate are located between projections of the first gate signal line and the second gate signal line on the first substrate, the seventh part is electrically connected with the first part, the eighth part is connected with the fifth part, the eighth part is also electrically connected with the sixth sub-metal layer, and the ninth part electrically connects the seventh part and the eighth part; The sixth overlap area comprises a fifth sub-overlap area and a sixth sub-overlap area, the projection of the second gate signal line on the first substrate has the fifth sub-overlap area and the sixth sub-overlap area with the ninth part on the surface of the first substrate, and the fifth sub-switch and the sixth sub-switch are formed respectively.

10. The display panel of claim 1, wherein, The first switch signal is a pulse signal, the second switch signal is a pulse signal, and the data voltage signal is a pulse signal, and a pulse width of the data voltage signal is greater than a sum of pulse widths of the first switch signal and the second switch signal.

11. The display panel of claim 10, wherein, The pulse width of the first switch signal is equal to the pulse width of the second switch signal, and a pulse height of the first switch signal is equal to a pulse height of the second switch signal.

12. A display device comprising: The display panel comprises the display panel of any one of claims 1-11.

Images