Semiconductor device, memory system, and method of correcting signals transmitted from a memory controller to a memory device

Abstract

Embodiments provide a semiconductor device, a memory system, and a method of correcting a signal transmitted from a memory controller to a memory device capable of performing a drift compensation operation without reducing data transmission efficiency. A semiconductor device includes a drift detection circuit that retrieves a first delay amount of a reference signal passing through a circuit element at a first timing, determines a second delay amount of the reference signal passing through the circuit element at a second timing, and outputs a drift amount that is a difference between the first delay amount and the second delay amount, and a delay amount adjustment circuit that retrieves a third delay amount of a first signal transmitted to an external device at the first timing, determines a fourth delay amount as a delay amount to be applied to the first signal for a period after the second timing based on the third delay amount and the drift amount, and transmits the first signal to which the fourth delay amount has been applied to the external device.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Japanese Patent Application 2022-026051, filed on February 22, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments described herein generally relate to semiconductor devices, memory systems, and methods for calibrating signals sent from a memory controller to a memory device. Background Technology

[0004] The controller of the memory system has a timing adjustment function for correcting signal delay. When temperature or voltage changes, the signal delay changes. Therefore, drift compensation is required to readjust the timing according to the changed delay. However, when drift compensation takes a long time, data transmission efficiency decreases when performing drift compensation on a selected channel. Summary of the Invention

[0005] The embodiments provide a semiconductor device, a memory system, and a method for correcting signals sent from a memory controller to the memory device that can perform drift compensation operations without reducing data transmission efficiency.

[0006] Generally, according to one embodiment, a semiconductor device includes a drift detection circuit and a delay adjustment circuit. The drift detection circuit is configured to retrieve a previously determined first delay amount of a reference signal passing through a circuit element at a first timing, determine a second delay amount of the reference signal passing through the circuit element at a second timing after the first timing, and output a drift amount as the difference between the first delay amount and the second delay amount. The delay adjustment circuit retrieves a previously determined third delay amount of a first signal sent to an external device of the semiconductor device at the first timing, determines a fourth delay amount based on the third delay amount and the drift amount as a delay amount to be applied to the first signal during a period after the second timing, and sends the first signal with the fourth delay amount applied to it to the external device. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating the configuration of a memory system connected to a host according to a first embodiment.

[0008] Figure 2 This is a block diagram illustrating an example configuration of the timing adjustment circuit according to the first embodiment.

[0009] Figure 3 This is a block diagram illustrating an example of a detailed configuration of the timing adjustment circuit according to the first embodiment.

[0010] Figure 4A This is a block diagram illustrating an example of a master delay-locked loop (MDLL) circuit according to a first embodiment.

[0011] Figure 4B This is a timing diagram illustrating an example of the operation of the MDLL circuit according to the first embodiment.

[0012] Figure 5 This is a block diagram illustrating an example configuration of a variable delay circuit according to the first embodiment.

[0013] Figure 6 This is a flowchart illustrating an example of the processing flow during training according to the first embodiment.

[0014] Figure 7 This is a diagram illustrating the method for calculating the drift compensation amount according to the first embodiment.

[0015] Figure 8 This is a diagram illustrating a method for reducing computational load when calculating drift compensation amount according to the first embodiment.

[0016] Figure 9 This is a block diagram illustrating the configuration of the timing adjustment circuit according to the second embodiment.

[0017] Figure 10 This is a block diagram showing the detailed configuration of the duty cycle correction (DCC) circuit according to the second embodiment.

[0018] Figure 11 This is a block diagram illustrating the configuration of the timing adjustment circuit according to the third embodiment.

[0019] Figure 12 This is a block diagram illustrating the configuration of the timing adjustment circuit according to the first modified example of the third embodiment.

[0020] Figure 13 This is a block diagram showing the configuration of the timing adjustment circuit according to the second modified example of the third embodiment.

[0021] Figure 14 This is a block diagram illustrating the configuration of the timing adjustment circuit according to a third modification of the third embodiment.

[0022] Figure 15 This is a block diagram illustrating the configuration of the timing adjustment circuit according to the fourth embodiment.

[0023] Figure 16 This is a block diagram illustrating the configuration of the timing adjustment circuit according to the fifth embodiment. Detailed Implementation

[0024] In the following description, embodiments will be illustrated with reference to the accompanying drawings.

[0025] (First Embodiment)

[0026] Figure 1 This is a block diagram illustrating the configuration of a memory system connected to a host according to a first embodiment. Figure 1 As shown, the memory system 1 includes a semiconductor device 2 and a memory device 3. The memory system 1 can be connected to a host device 4. The host device 4 is, for example, an electronic device, such as a personal computer or a mobile terminal.

[0027] The memory device 3 is, for example, a non-volatile memory such as NAND flash memory. Hereinafter, the memory device 3 will be referred to as NAND flash memory 3. NAND flash memory 3 includes one or more memory chips 3A.

[0028] Semiconductor device 2 can be implemented as a circuit such as a system-on-a-chip (SoC). Each function of semiconductor device 2 can be implemented by dedicated hardware, a processor executing programs, or a combination thereof. Semiconductor device 2 serves as a memory controller configured to control NAND flash memory 3. Hereinafter, semiconductor device 2 is referred to as memory controller 2. Memory controller 2 includes control unit 5 and one or more NAND interface (I / F) circuits 6. Control unit 5 and NAND I / F circuits 6 are connected to each other via a bus. Control unit 5 and NAND I / F circuits 6 can be configured as independent semiconductor devices.

[0029] One or more NAND interface (I / F) circuits 6 and one or more memory chips 3A of the NAND flash memory 3 are electrically connected to each other via one or more channels 7. Each channel 7 has a configuration that bundles multiple signal lines together. The memory controller 2 can control each channel 7 individually. By controlling one or more channels 7 individually, the memory controller 2 can simultaneously operate one or more memory chips 3A connected to different channels 7. The channel 7 that sends / receives data between the memory controller 2 and the memory chip 3A is called the selected channel. The channel 7 that does not send / receive data between the memory controller 2 and the memory chip 3A is called the non-selected channel.

[0030] The host device 4 and the memory controller 2 (more specifically, the control unit 5) are connected to each other via a predetermined interface. Various interfaces can be used as the interface, such as the parallel interface of an embedded multimedia card (eMMC), the serial expansion interface of peripheral component rapid interconnect (PCIe), and the high-speed serial interface of an M-PHY. Each of the host device 4 and the memory controller 2 has built-in interface circuitry corresponding to the interface used in the various interfaces.

[0031] The host device 4 sends a write request or a read request to the control unit 5. Based on the request from the host device 4, the control unit 5 controls the writing of data to the NAND flash memory 3 and the reading of data from the NAND flash memory 3.

[0032] NAND I / F circuit 6 is electrically connected to memory controller 2 and NAND flash memory 3. NAND I / F circuit 6 conforms to various interface standards such as Toggle DDR and Open NAND Flash Memory Interface (ONFI).

[0033] The memory controller 2 (more specifically, the NAND I / F circuit 6) and the NAND flash memory 3 send / receive various signals via multiple signal lines arranged in channel 7. These signals include, for example, eight data signals DQ<7:0> and two strobe signals DQS and DQSn. The eight data signals DQ<7:0> include, for example, command, address, data, and status. Other signals sent / received between the memory controller 2 and the NAND flash memory 3 may include the chip enable signal CEn, the ready / busy signal RBn, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, the read enable signals RE and REn, and the write protect signal WPn. Here, adding "n" to the signal name indicates that the signal is an active-low signal.

[0034] The NAND I / F circuit 6 includes a timing adjustment circuit 6A. The timing adjustment circuit 6A performs timing adjustment on various signals such as the data signal DQ<7:0> or the data strobe signals DQS and DQSn.

[0035] The timing adjustment circuit 6A according to this embodiment is applicable not only to the NAND I / F circuit 6, but also to various interface circuits built into the NAND flash memory 3 and the host device 4.

[0036] The configuration of the timing adjustment circuit will be described next.

[0037] Figure 2This is a block diagram illustrating an example configuration of the timing adjustment circuit 6A according to the first embodiment.

[0038] Figure 3 This is a block diagram illustrating an example of a detailed configuration of the timing adjustment circuit 6A according to the first embodiment. Figure 4A This is a block diagram illustrating an example of a master delay-locked loop (MDLL) circuit according to a first embodiment. Figure 4B This is a timing diagram illustrating an example of the operation of the MDLL circuit according to the first embodiment. Figure 5 This is a block diagram illustrating an example configuration of a variable delay circuit according to the first embodiment.

[0039] like Figure 2 As shown, the timing adjustment circuit 6A includes a reference circuit 10, a drift detection circuit 20, an arithmetic circuit 30, and a delay adjustment circuit 40. The timing adjustment circuit 6A adds a delay to each of the internal data signals iDQ<7:0> and iDQS and iDQSn, which are input from the control unit 5 and output to the NAND flash memory 3 as data signals DQ<7:0> and data strobe signals DQS and DQSn.

[0040] Reference circuit 10 generates a reference clock. Drift detection circuit 20 detects the drift amount based on the reference clock output from reference circuit 10. Arithmetic circuit 30 calculates a delay setpoint based on the drift detection result from drift detection circuit 20 to set the delay amount for various signals. Delay adjustment circuit 40 adjusts the delay amount based on the delay setpoint calculated by arithmetic circuit 30.

[0041] The reference circuit 10 includes a bandgap reference (BGR) circuit 11 and an oscillator (OSC) circuit 12. Even if the voltage or temperature changes, as long as the change is within a predetermined range, the BGR circuit 11 outputs a constant voltage to the OSC circuit 12. The OSC circuit 12 generates a clock based on the input voltage. Therefore, the reference circuit 10 generates a reference clock independently of changes in voltage and temperature and outputs the reference clock to the drift detection circuit 20.

[0042] The drift detection circuit 20 includes a master delay-locked loop (DLL) circuit 21, a subtraction circuit 22, and a memory 23. In the following description, the master DLL circuit 21 is simply referred to as the MDLL circuit 21.

[0043] like Figure 4AAs shown, the MDLL circuit 21 is implemented as a time-to-digital converter (TDC) circuit. The MDLL circuit 21 includes a clock generation circuit 24, a delay line 25, multiple flip-flops FF, and a code generation circuit 26. The delay line 25 includes multiple buffers B connected in series with each other. Buffers B are examples of circuit elements. Furthermore, buffers B are examples of delay elements. The multiple buffers B in the delay line 25 are examples of multiple first delay elements. The multiple flip-flops FF are connected to the corresponding outputs of the multiple buffers B.

[0044] like Figure 4B As shown, during training, during the preparation period before data transmission, or every predetermined cycle during data transmission (e.g., every 64 cycles of the reference clock CLK), the timing t1 input to the clock generation circuit 24 at the first rising edge of the reference clock CLK is changed from low to high (or from high to low) by the signal CLKDLY input to the delay line 25. The signal CLKDLY input to the delay line 25 is delayed by buffer B and then input to buffer B and flip-flop FF in subsequent stages. That is, Figure 4B The deviation between the signals CLKDLY shown indicates the delay of stage B of buffer B. Figure 4B In the example shown, the clock generation circuit 24 inputs the signal CLKDLY, which transitions from a low level to a high level, to the delay line 25. The high-level period of the signal CLKDLY is equal to one cycle of the reference clock CLK, but can be longer than one cycle.

[0045] Furthermore, at the rising edge following the first rising edge of the reference clock CLK input during training, during the preparation period before data transmission, and at timing t2 of each predetermined cycle during data transmission, the clock generation circuit 24 starts providing a clock CLKDET to each flip-flop FF. On the rising edge of the provided clock CLKDET, each flip-flop FF latches the signal CLKDLY from the buffer B connected to each flip-flop FF and outputs the latched signal CLKDLY to the code generation circuit 26.

[0046] For example, when the signal CLKDLY input to delay line 25 changes from low to high, the high-level signal CLKDLY input to delay line 25 is delayed by buffer B in the first stage and then output to buffer B in the second stage. The high-level signal CLKDLY input to buffer B in the second stage is delayed by buffer B in the second stage and then output to buffer B in the third stage. Similarly, a high-level signal CLKDLY input to a buffer B is delayed by that buffer B and output to buffer B in the next stage. That is, buffer B through which the high-level signal CLKDLY input to delay line 25 outputs a high-level signal CLKDLY. Simultaneously, buffer B through which the high-level signal CLKDLY input to delay line 25 has not yet passed outputs a low-level signal CLKDLY.

[0047] As described above, the clock CLKDET supplied to each flip-flop FF rises at timing t2. As a result, the flip-flop FF connected to buffer B, which outputs a high-level signal CLKDLY one cycle before the reference clock CLK (i.e., before timing t2), latches the high-level signal CLKDLY according to the clock CLKDET. Simultaneously, the flip-flop FF connected to buffer B, which has not yet outputted a high-level signal CLKDLY one cycle before the reference clock CLK (i.e., before timing t2), latches the low-level signal CLKDLY according to the clock CLKDET. Each flip-flop FF outputs the latched signal CLKDLY to the code generation circuit 26.

[0048] Furthermore, the clock generation circuit 24 outputs a high-level signal CLKREG to the code generation circuit 26 at timing t2, so that the code generation circuit 26 outputs the first code value. The clock generation circuit 24 can also output a high-level signal CLKREG to the code generation circuit 26 on the rising edge of the reference clock CLK after timing t2.

[0049] When the high-level signal CLKREG, used to output the first code value, is input from the clock generation circuit 24, the code generation circuit 26 observes the level of the signal input from each flip-flop FF and counts the number of flip-flops FF that output a high-level (or low-level) signal. This determines which stage of buffer B the signal input to delay line 25 has passed through. Based on this determination, the code generation circuit 26 generates a first code value indicating how many stages of buffer B in delay line 25 correspond to one cycle of the reference clock. By performing the above operation via the MDLL circuit 21 at a second timing after the first timing (e.g., during training, a preparation period before data transmission, or a predetermined period during data transmission), the first code value can indicate how many stages of buffer B in delay line 25 correspond to one cycle of the reference clock at the second timing and the first timing. The first code value is an example of a second set value. The code generation circuit 26 outputs the generated first code value to the subtraction circuit 22.

[0050] like Figure 2 As shown, a first code value from MDLL circuit 21 and a second code value from memory 23 are input to subtraction circuit 22. The second code value is a code value indicating the number of cycle detection stages during training; specifically, how many stages of buffer B in delay line 25 correspond to one cycle of the reference clock during training. The second code value indicates how many stages of buffer B in delay line 25 correspond to one cycle of the reference clock at the first timing (e.g., during training). The second code value is an example of the first set value. The details of training will be described later.

[0051] Subtraction circuit 22 calculates the difference between the first code value from MDLL circuit 21 and the second code value from memory 23. That is, subtraction circuit 22 calculates the difference between the number of buffers B corresponding to one cycle of the current reference clock at a specific timing and the number of buffers B corresponding to one cycle of the reference clock during training. Therefore, drift detection circuit 20 can detect the amount of drift since training. That is, the amount of drift since training is indicated, for example, by the difference in the number of buffers B corresponding to one cycle of the reference clock. Drift detection circuit 20 outputs the detected drift amount to arithmetic circuit 30.

[0052] In this way, the drift detection circuit 20 determines a first delay amount, which is the delay amount of buffer B at a first timing. Furthermore, the drift detection circuit 20 determines a second delay amount, which is the delay amount of buffer B at a second timing after the first timing. Then, the drift detection circuit 20 detects the drift amount as the difference between the first and second delay amounts. In other words, the drift detection circuit 20 generates a reference signal (signal CLKDLY) with a first period and determines the first or second delay amount based on the time required for the reference signal to pass through multiple buffers B.

[0053] The operational circuit 30 includes a combinational circuit 31 and a memory 37. For example... Figure 3 As shown, the combinational circuit 31 includes a combinational circuit 32, an adder circuit 33, a selection signal generation unit 34, a selector 35, and an adder circuit 36.

[0054] Combinational circuit 32 performs a right shift operation, shifting the output value of subtraction circuit 22 to the right. Generally, for every 1 bit shifted right, the value of the binary bit string is multiplied by 1 / 2. Therefore, when the binary bit string is shifted right by 1 bit, its value is multiplied by 1 / 2; when it is shifted right by 2 bits, its value is multiplied by 1 / 4; and when it is shifted right by 3 bits, its value is multiplied by 1 / 8. When combinational circuit 32 shifts the output value of subtraction circuit 22 right by 1 bit, the output value of subtraction circuit 22 becomes 4 / 8 (1 / 2). When combinational circuit 32 shifts the output value of subtraction circuit 22 right by 2 bits, the output value of subtraction circuit 22 becomes 2 / 8 (1 / 4). When combinational circuit 32 shifts the output value of subtraction circuit 22 right by 3 bits, the output value of subtraction circuit 22 becomes 1 / 8. Therefore, the output value of subtraction circuit 22 is multiplied by 1 / 8, 2 / 8, and 4 / 8 through the operation of combinational circuit 32 and is input to selector 35. Furthermore, the values ​​of 1 / 8 and 2 / 8 are input to the adder circuit 33. The adder circuit 33 adds the values ​​of 1 / 8 and 2 / 8, calculates the value of 3 / 8 as the output value of the subtractor circuit 22, and outputs this value to the selector 35. Additionally, 0 (in the context of a low-level signal from ground) is also input. Figure 3 The difference (denoted as difference × 0) is input to selector 35. Thus, combination circuit 32 outputs the first difference to delay adjustment circuit 40, which is the result of a shift operation on the difference between the first code value and the second code value.

[0055] The selection signal generation unit 34 generates a selection signal for each signal (e.g., the data signal DQ<7:0> and the data strobe signals DQS and DQSn) based on the second code value from memory 23 (i.e., the number of periodic detection levels during training) and the correction levels for each signal during training from memory 37. The correction levels for each signal during training will be described later. The selection signal generation unit 34 outputs the generated selection signal to selectors 35 provided for each of the data signal DQ<7:0> and the data strobe signals DQS and DQSn.

[0056] Specifically, when the value of the correction level of each signal during training divided by the periodic detection level during training is 0 or greater but less than 1 / 16, the selection signal generation unit 34 outputs a selection signal to the selector 50 to enable the selector 35 to select a value of difference × 0. Furthermore, when the value of the correction level of each signal during training divided by the periodic detection level during training is 1 / 16 or greater but less than 3 / 16, the selection signal generation unit 34 outputs a selection signal to the selector 35 to select a value of difference × 1 / 8. Moreover, when the value of the correction level of each signal during training divided by the periodic detection level during training is 3 / 16 or greater but less than 5 / 16, the selection signal generation unit 34 outputs a selection signal to the selector 35 to select a value of difference × 2 / 8. Furthermore, when the value of the correction level of each signal during training divided by the periodic detection level during training is 5 / 16 or greater but less than 7 / 16, the selection signal generation unit 34 outputs a selection signal to the selector 35 to enable the selector 35 to select a value of difference × 3 / 8. Additionally, when the value of the correction level of each signal during training divided by the periodic detection level during training is 7 / 16 or greater, the selection signal generation unit 34 outputs a selection signal to the selector 50 to enable the selector 35 to select a value of difference × 4 / 8.

[0057] When a larger delay is required in the variable delay circuit 41, values ​​greater than difference × 4 / 8, such as difference × 5 / 8, difference × 6 / 8, difference × 7 / 8, and difference × 8 / 8, can be generated by the combination circuit 32 and the adder circuit 33 and can be input to the selector 35. Then, the selection signal generation unit 34 outputs a selection signal to the selector 35 based on the value of the correction level of each signal during training divided by the period detection level during training. For example, when the value of the correction level of each signal during training divided by the period detection level during training is 15 / 16 or greater, the selection signal generation unit 34 outputs a selection signal to the selector 35 to cause the selector 35 to select the value of difference × 8 / 8.

[0058] For example, when the number of cyclic detection levels during training is 444, and the data signal DQ during training... <0> When the correction level is 100, the value of 100 / 444 is greater than 3 / 16 and less than 5 / 16. As a result, the selection signal generation unit 34 generates signals corresponding to the data signal DQ. <0> Selector 35 selects a selection signal with a difference of 2 / 8 and outputs the selection signal to the corresponding data signal DQ. <0> Selector 35.

[0059] Furthermore, for example, when the number of cyclic detection levels during training is 444, and the data signal DQ during training... <1> When the correction level is 50, the value of 50 / 444 is greater than 1 / 16 and less than 3 / 16. As a result, the selection signal generation unit 34 generates signals corresponding to the data signal DQ. <1> Selector 35 selects a selection signal with a difference of 1 / 8 and outputs the selection signal to the corresponding data signal DQ. <1> Selector 35.

[0060] The selection signal generation unit 34 includes a memory 34a. The number of periodic detection levels and the correction levels for each signal (data signal DQ<7:0>, data strobe signals DQS and DQSn) during training are determined during training. The selection signal generation unit 34 determines, for each signal, which value (0, 1 / 8, 2 / 8, 3 / 8, or 4 / 8) is closest to the value of the correction level divided by the number of periodic detection levels during training, and stores this information in the memory 34a. That is, the selection signal generation unit 34 stores information in the memory 34a indicating which signal to select for each selector 35. During data transmission, the selection signal generation unit 34 outputs the selection signal to each selector 35 based on the information stored in the memory 34a. Thus, the selection signal generation unit 34 performs quantization, which approximates the value of the correction level divided by the number of periodic detection levels during training to any one of the values ​​0, 1 / 8, 2 / 8, 3 / 8, or 4 / 8. Then, the selection signal generation unit 34 outputs the selection signal to each selector 35, thereby selecting the difference obtained by multiplying by the approximation.

[0061] A selector 35 is provided for each of the data signal DQ<7:0> and the data strobe signals DQS and DQSn. A selection signal generated by the selection signal generation unit 34 for each of the data signal DQ<7:0> and the data strobe signals DQS and DQSn is input to each selector 35. Based on the selection signal generated for each of the data signal DQ<7:0> and the data strobe signals DQS and DQSn, each selector 35 selects any input value and outputs the selected value to the adder circuit 36.

[0062] An adder circuit 36 ​​is provided for each of the data signal DQ<7:0> and the data strobe signals DQS and DQSn. Each adder circuit 36 ​​adds the output of the selector 35 to the correction level during training (corresponding to the correction level for each of the data signal DQ<7:0> and the data strobe signals DQS and DQSn) from the memory 37, and outputs a control code as a delay setting value to the delay adjustment circuit 40.

[0063] The delay adjustment circuit 40 includes a variable delay circuit 41 for each of the data signal DQ<7:0> and the data strobe signals DQS and DQSn. Each variable delay circuit 41 delays each of the internal data signal iDQ<7:0> and the internal data strobe signals iDQS and iDQSn based on a delay setting value from each adder circuit 36, and sends the delayed signal as the data signal DQ<7:0> and the data strobe signals DQS and DQSn to the NAND flash memory 3.

[0064] like Figure 5 As shown, the variable delay circuit 41 includes a delay line 42 and a selector 43. The delay line 42 includes a plurality of buffers B connected in series with each other. The plurality of buffers B in the delay line 42 are examples of a plurality of second delay elements. The delay amount of each buffer B in the delay line 42 is equal to the delay amount of each buffer B in the delay line 25 of the MDLL circuit 21.

[0065] The input of buffer B in the first stage of delay line 42 is connected to one of the internal data signal iDQ<7:0> and the internal data strobe signals iDQS and iDQSn. The output of each buffer B in delay line 42 is connected to selector 43.

[0066] Selector 43 selectively outputs either the input signal or the output signal of each buffer B in delay line 42 based on a delay setting value. That is, selector 43 selectively outputs either the input signal or the output signal of each buffer B in delay line 42 based on a delay setting value. Therefore, the amount of delay from the input signal to the output signal can be changed.

[0067] In this way, the variable delay circuit 41 sends the first signal (e.g., data signal DQ<7:0> and data strobe signals DQS and DQSn) to an external device (e.g., memory device 3) based on a set delay amount.

[0068] Next, the training and drift compensation operations will be described.

[0069] When data transfer is performed between memory controller 2 and NAND flash memory 3, training is performed before the data transfer. For example, training is performed during pre-shipment testing. During training, memory controller 2 and NAND flash memory 3 send / receive determined test patterns and determine the delay amount for each signal so that the test patterns can be correctly sent / received. In training, for example, the delay amount for each signal is determined such that each of the data signals DQ<7:0> has sufficient timing margin for the data strobe signals DQS and DQSn.

[0070] Figure 6 This is a flowchart illustrating an example of the processing flow during training according to the first embodiment.

[0071] First, the control unit 5 sends / receives test modes between the memory controller 2 and the NAND flash memory 3 while sequentially changing the delay amount of the variable delay circuit 41, and determines the test results (step S1).

[0072] Specifically, first, the control unit 5 sets the delay amount of the variable delay circuit 41 for each signal (e.g., data signal DQ<7:0> and data strobe signals DQS and DQSn) to zero. Then, the control unit 5 sends / receives test patterns to / from the NAND flash memory 3 to determine whether an error has occurred or not. Next, the control unit 5 sets the delay amount of the variable delay circuit 41 for each signal to the first level of buffer B in the delay line 42. Then, the control unit 5 sends / receives test patterns to / from the NAND flash memory 3 to determine whether an error has occurred or not. In this way, the control unit 5 sends / receives test patterns between the memory controller 2 and the NAND flash memory 3 while sequentially changing the delay amount of each signal, and determines the test results.

[0073] Next, the control unit 5 detects the optimal delay setting value for each signal based on the test results (step S2). For example, for the data signal DQ <0> Suppose the following scenario: the test result using delay levels 0 to 75 of buffer B in delay line 42 is an error, the test result using levels 76 to 124 of buffer B is a pass, and the test result using level 125 or higher of buffer B is an error. In this case, control unit 5 will detect the intermediate value of levels 76 to 124 of buffer B, where the test result is a pass, as the optimal value. That is, control unit 5 will detect level 100 of buffer B in delay line 42 as the data signal DQ. <0> The optimal delay setting value is determined. Similarly, the control unit 5 detects the optimal delay setting value for each of the data strobe signals DQS and DQSn and the data signal DQ<7:1>.

[0074] Thus, the delay adjustment circuit 40 determines a third delay, which is the delay of the first signal when the first signal sent to the external device of the semiconductor device 2 is received error-free in the external device. The third delay corresponds to the total delay of one or more buffers B in the delay line 42 through which the first signal passes, wherein the number of these buffers B is equal to the delay setting value set in the variable delay circuit 41 during training. The delay adjustment circuit 40 sets the determined third delay as the delay of the first signal used during the time period from the first timing to the second timing.

[0075] Furthermore, the delay adjustment circuit 40 determines a fourth delay based on the third delay and the drift, and sets the determined fourth delay as the delay of the first signal used in the period following the second timing. The fourth delay corresponds to the total delay of one or more buffers B in the delay line 42 through which the first signal passes, wherein the number of the one or more buffers B is equal to the delay setting value set in the variable delay circuit 41 during data transmission. The delay adjustment circuit 40 determines the fourth setting value based on the result obtained by adding the first difference input from the arithmetic circuit 30 (more specifically, the combination circuit 32) to the third setting value.

[0076] Next, the control unit 5 stores the optimal delay setting value for each detected signal in the memory 37 as the correction level for each signal during training (step S3).

[0077] Next, the timing adjustment circuit 6A detects the number of stages of buffer B corresponding to one cycle of the reference clock in delay line 25 (step S4). The number of stages of buffer B corresponding to one cycle of the reference clock is detected by the MDLL circuit 21. Through this process, the timing adjustment circuit 6A can calculate the delay amount of one stage of buffer B. Finally, the timing adjustment circuit 6A stores the detected value of the number of stages of buffer B corresponding to one cycle of the reference clock in memory 23 as a second code value (i.e., the number of stages detected during training) (step S5).

[0078] As a result of training performed before data transmission, for example, when the delay of level 1 of buffer B is detected to be 1.88 ps, and the delay of level 100 of buffer B in delay line 42 is set for the data signal DQ <0> In terms of optimal timing, the data signal DQ <0> The optimal latency is 188 ps. When the temperature and voltage during data transmission are approximately equal to those during training, this optimal latency (188 ps) can be used by setting the same latency setting.

[0079] At the same time, when the temperature or voltage drifts relative to the training time, the optimal delay setting during training and data transmission is not always the same due to the temperature and voltage dependence of the delay line 42.

[0080] For example, when the delay of stage B of buffer B changes from 1.88 ps to 2.12 ps due to temperature or voltage drift, and the delay setting is set to 100, the delay of delay line 42 is 212 ps, which deviates from the optimal delay. As a result, the delay setting of the input channel variable delay circuit 41 needs to be changed to correct the delay to the optimal value. In this case, by reducing the delay setting from 100 to 88, the delay of delay line 42 becomes 186 ps, thus providing the optimal delay. This change in the delay setting corresponding to the optimal delay of delay line 42 (-12 in the example above) is called the drift compensation amount. Furthermore, the operation used to calculate the drift compensation amount is called the drift compensation operation.

[0081] Next, the method for calculating the drift compensation amount will be described. Figure 7 This is a diagram illustrating the method for calculating the drift compensation amount according to the first embodiment.

[0082] When the delay of the first stage of buffer B in delay line 25 is 1.88 ps, the number of stages of buffer B corresponding to one cycle of a reference clock with a period of 833 ps is 444. The number of stages of buffer B corresponding to one cycle of the reference clock during training is stored in memory 23 as the number of cycle detection stages during training.

[0083] Furthermore, assuming a certain signal during training (e.g., DQ) <0> The optimal delay of the variable delay circuit 41 is 100 levels (i.e., 188 ps) of the buffer B in the delay line 42. In this training, the number of buffers B (100) is stored in the memory 37 as the correction level of the signal during training.

[0084] As described above, when the delay of the first stage of buffer B becomes 2.12 ps due to temperature or voltage drift, and the delay setting of the variable delay circuit 41 remains the same, the delay becomes 212 ps. Here, when the MDLL circuit 21 detects the number of stages of buffer B corresponding to one cycle of the reference clock, independent of temperature and voltage, the detected value decreases to 393 due to the increase in the delay of the first stage of buffer B. That is, the change in the detected value of the MDLL circuit 21 is -51 (=393-444).

[0085] The MDLL circuit 21 and the variable delay circuit 41 have delay lines 25 and 42, which include buffers B with the same delay value. As a result, in order to generate a delay equal to that of the variable delay circuit 41 during training, the number of stages of buffer B needs to be reduced by the same proportion as that of delay line 25 in the MDLL circuit 21.

[0086] Specifically, the drift compensation amount can be calculated by multiplying the change in the detection value of the MDLL circuit 21 by (the delay setting value of the variable delay circuit 41 during training) / (the detection value of the MDLL circuit 21 during training)). Here, the detection value of the MDLL circuit 21 during training is the number of periodic detection stages stored in the memory 23. The delay setting value of the variable delay circuit 41 during training is the number of signal correction stages stored in the memory 37. In the example above, the drift compensation amount is -51 × (100 / 444) = -12. As a result, the delay setting value of the variable delay circuit 41 after the drift compensation operation becomes 88, and the delay amount becomes 186 ps.

[0087] Next, we will describe methods to reduce the computational load when calculating drift compensation. Figure 8 This is a diagram illustrating a method for reducing computational load when calculating drift compensation amount according to the first embodiment.

[0088] When high-speed computing is required Figure 7 When calculating the drift compensation amount shown, a division circuit needs to be implemented in memory controller 2. However, in general, the size of the division circuit is very large. Furthermore, the division performed by the processor executing the program takes a long time to calculate.

[0089] The storage controller 2 according to an embodiment includes a circuit configuration that shortens the processing (computation) time before the drift compensation operation is completed. The storage controller 2 according to this embodiment can complete the drift compensation operation of a selected channel at high speed, thus preventing a decrease in data transmission efficiency.

[0090] Specifically, the memory controller 2 approximates (quantizes) the division result when calculating the drift compensation amount ([the delay setting value of the variable delay circuit 41 during training] / [the detection value of the MDLL circuit 21 during training]) as an integer multiple of "1 / (power of 2)" (i.e., N×1 / 2). n Therefore, the calculation time can be shortened without using a division circuit.

[0091] More specifically, such as Figure 8As shown, the ratio of the delay setting value of the variable delay circuit 41 during training to the detection value of the MDLL circuit 21 during training is not 100 / 444, but 2 / 8, i.e., quantized to 1 / 4. By multiplying the obtained 1 / 4 by -51, which is the "change in the detection value of the MDLL circuit 21", -13 is obtained. As described above, this calculation result is obtained by right-shifting the binary bit string corresponding to the decimal number -51 by 2 bits. In the adder circuit 36, the training correction stage stored in the memory 37 is added to the obtained -13 to obtain 87, which is the optimal delay setting value for data transmission. Therefore, the variable delay circuit 41 selects buffer B in the 87th stage of the delay line 42 and outputs a signal in which the input signal is delayed to 184 ps.

[0092] Generally, the values ​​input to the arithmetic circuit are represented in binary, so calculations of "powers of 2" or "1 / (power of 2)" can be performed by simply shifting each bit of the value. Therefore, not only can the calculation time be shortened, but the size of the circuit can also be greatly reduced.

[0093] exist Figure 7 The calculation method shown can reduce the inaccuracy of drift compensation within the delay range of the first stage of buffer B. However, this calculation method necessitates the use of a large-size and / or long-time division circuit.

[0094] Regarding this point, Figure 8 In the calculation method shown, the correction coefficient ([delay setting value of variable delay circuit 41 during training] / [detection value of MDLL circuit 21 during training]) is approximated (quantized) as an integer multiple of "1 / (power of 2)". For quantization, for example, the above-mentioned division such as 100 / 444 is necessary. In this embodiment, this division can be performed by a processor that executes the program during training. Then, during training, the correction coefficient quantized based on the division result is stored in memory 34a. Therefore, during data transmission, the drift compensation amount can be calculated by right-shifting the output value of subtraction circuit 22 based on the correction coefficient, or by adding the results of multiple right-shifting operations on the output value of subtraction circuit 22. That is, the calculation time during data transmission can be shortened.

[0095] exist Figure 7 In the calculation method shown, the drift compensation amount applied after the delay setting is 186 ps, but... Figure 8 The calculation method shown uses 184 ps. This is due to the inaccuracy of the correction coefficient caused by quantization (quantization error). Figure 8 The inaccuracy of the optimal delay in the calculation method shown becomes greater than Figure 7The calculation method shown exhibits inaccuracies in the optimal delay amount. However, compared to 212 ps before applying drift compensation, the delay was significantly reduced by using [the method described]. Figure 8 The calculation method shown performs drift compensation, which can reduce the inaccuracy of the optimal delay amount.

[0096] Generally, retraining for drift compensation operations takes approximately several microseconds. Furthermore, during retraining, the channel between memory controller 2 and NAND flash memory 3 is occupied, resulting in reduced data transfer efficiency. Methods for performing drift compensation operations using non-selected channels are known, but these methods cannot perform drift compensation operations on the selected channel itself.

[0097] In this respect, in this embodiment, the drift compensation operation can be performed at high speed using the above-described calculation method. Specifically, the process from detecting the drift amount in the MDLL circuit 21 to changing the delay setting value of the variable delay circuit 41 can be completed within approximately 10 ns to 20 ns. Generally, after the memory controller 2 issues a command to the NAND flash memory 3, a preparation period of 200 ns to 300 ns is required for operations in the NAND flash memory 3 before data transfer between the memory controller 2 and the NAND flash memory becomes possible. According to the structure of the NAND I / F circuit 6 according to this embodiment, even in a selected channel, the drift compensation operation can be performed during the preparation period before data transfer. As a result, in the memory system 1 according to this embodiment, the drift compensation operation of a selected channel can be performed without reducing data transfer efficiency.

[0098] The quantization correction coefficient resolution of the timing adjustment circuit 6A according to this embodiment is 1 / 8, but this resolution can be other values, as long as it is "1 / (a power of 2)", such as 1 / 4, 1 / 16, or 1 / 32. Generally, when the quantization resolution changes from 1 / 8 to 1 / 16, the inaccuracy caused by the quantization of the correction coefficient decreases, but the size of the circuit configured to calculate the correction coefficient increases. Specifically, when the quantization resolution is 1 / 8, such as... Figure 3 As shown, adder circuit 33 needs to be configured to calculate correction coefficient 3 / 8. When the quantization resolution is 1 / 16, adder circuits need to be configured to calculate correction coefficients of 3 / 16, 5 / 16, 6 / 16, and 7 / 16. As a result, the optimal value for the quantization resolution is determined based on a trade-off between circuit size and permissible inaccuracies.

[0099] (Second Embodiment)

[0100] Next, the second embodiment will be described.

[0101] Figure 9This is a block diagram illustrating the configuration of the timing adjustment circuit according to the second embodiment. Figure 9 In, with Figure 2 The same configurations are represented by the same reference numerals, and their descriptions will be omitted.

[0102] like Figure 9 As shown, compared with the timing adjustment circuit 6A according to the first embodiment, the timing adjustment circuit 6B according to the second embodiment further includes a combination circuit 50 and a duty cycle correction (DCC) circuit 51.

[0103] A first code value is input from MDLL circuit 21 to combinational circuit 50. This first code value indicates how many stages of buffer B in delay line 25 correspond to one cycle of the reference clock. Combinational circuit 50 performs a predetermined operation on the first code value from MDLL circuit 21, such as the same operation as in combinational circuit 31, and outputs the result to DCC circuit 51.

[0104] The internal data signal iDQ<7:0> and the internal data strobe signals iDQS and iDQSn are input to the DCC circuit 51. The DCC circuit 51 includes an adjustment circuit 52 and a control circuit 57, and adjusts the duty cycle of the internal data signal iDQ<7:0> and the internal data strobe signals iDQS and iDQSn with high accuracy based on the calculation results from the combination circuit 50. The DCC circuit 51 outputs the internal data signal iDQ<7:0> and the internal data strobe signals iDQS and iDQSn with the high-accuracy adjusted duty cycle to the delay adjustment circuit 40.

[0105] An internal data signal iDQ<7:0> with a duty cycle adjusted with high accuracy by DCC circuit 51, along with internal data strobe signals iDQS and iDQSn, are input to each variable delay circuit 41 of delay adjustment circuit 40. Each variable delay circuit 41 is based on the input from each adder circuit 36 ​​(reference). Figure 3 The delay setting value is used to delay each of the internal data signal iDQ<7:0> and the internal data strobe signals iDQS and iDQSn, so as to output the data signal DQ<7:0> and the data strobe signals DQS and DQSn to the NAND flash memory 3.

[0106] Figure 10 This is a block diagram showing the detailed configuration of the duty cycle correction (DCC) circuit according to the second embodiment.

[0107] The adjustment circuit 52 includes a variable delay circuit 53, an AND circuit 54, an OR circuit 55, and a selector 56. Input signals are input to the variable delay circuit 53, the AND circuit 54, the OR circuit 55, and the control circuit 57. A first code value is input to the variable delay circuit 53.

[0108] The variable delay circuit 53 has the same configuration as the variable delay circuit 41, including a selector and delay lines connecting multiple buffers. The selector selects either the input signal or the output signal of each buffer in the delay line based on a first code value, and outputs the selected signal to the AND circuit 54 and the OR circuit 55.

[0109] The AND circuit 54 calculates the logical product of the input and output signals of the variable delay circuit 53 and outputs the result to the selector 56. The OR circuit 55 calculates the logical sum of the input and output signals of the variable delay circuit 53 and outputs the result to the selector 56.

[0110] The control circuit 57 detects the pulse width of the input signal and outputs a selection signal to the selector 56 to choose whether to delay the rising edge or the falling edge of the input signal.

[0111] Before the selection signal is provided, selector 56 is inactive and does not output an output signal. Selector 56 selects either the output of AND circuit 54 or the output of OR circuit 55 based on the selection signal, and outputs the selected one as the output signal. Specifically, when the rising edge of the input signal is delayed according to the selection signal to adjust the duty cycle, selector 56 selects the output of AND circuit 54. When the falling edge of the input signal is delayed according to the selection signal to adjust the duty cycle, selector 56 selects the output of OR circuit 55.

[0112] With this configuration, the timing adjustment circuit 6B can simultaneously perform drift compensation operations for timing adjustment of the data signal DQ<7:0> and the data strobe signals DQS and DQSn, as well as drift compensation operations for duty cycle adjustment.

[0113] (Third Embodiment)

[0114] Next, the third embodiment will be described.

[0115] Figure 11 This is a block diagram illustrating the configuration of the timing adjustment circuit according to the third embodiment. Figure 11 In, with Figure 2 The same configurations are represented by the same reference numerals, and their descriptions will be omitted.

[0116] like Figure 11 As shown, compared with the timing adjustment circuit 6A according to the first embodiment, the timing adjustment circuit 6C according to the third embodiment further includes an amplifier circuit 60. The amplifier circuit 60 is disposed between the drift detection circuit 20 and the arithmetic circuit 30, amplifies the drift amount detected by the drift detection circuit 20, and outputs the amplified drift amount to the arithmetic circuit 30.

[0117] By performing the process of step S1 described in the reference at multiple temperatures (e.g., 0 °C, 30 °C, and 85 °C), for example, during the test before the product leaves the factory, the amplification factor A of the amplifier circuit 60 is determined to match the temperature and voltage-related changes of the NAND flash memory 3. That is, when the NAND flash memory 3 has temperature and voltage correlation and the optimal delay setting value of the variable delay circuit 41 changes, the output (drift amount) of the drift detection circuit 20 can be amplified using the amplification factor A, so as to set the optimal delay setting value that matches the temperature and voltage correlation of the NAND flash memory 3. Figure 6 For example, when A > 1, each signal (data signals DQ<7:0>, data strobe signals DQS and DQSn) is corrected more strongly compared to the actual drift amount. In this case, the delay setting value input to the variable delay circuit 41 is corrected to have a negative temperature and voltage correlation with respect to the drift amount. When A = 1, each signal is corrected according to the actual drift amount. In this case, the delay setting value input to the variable delay circuit 41 is corrected to have no temperature and voltage correlation with respect to the change in the drift amount. When 0 < A < 1, each signal is corrected more weakly compared to the actual drift amount. In this case, the delay setting value input to the variable delay circuit 41 is corrected such that the temperature and voltage correlation is weaker than the change in the drift amount. When A = 0, each signal is not corrected. In this case, the delay setting value input to the variable delay circuit 41 is not corrected and is independent of the change in the drift amount. When A < 0, each signal is corrected reversely. In this case, the delay setting value input to the variable delay circuit 41 is corrected to have a stronger temperature and voltage correlation than the change in the drift amount.

[0118] In this way, the timing adjustment circuit 6C amplifies the detected drift amount so that the drift compensation amount has temperature and voltage correlation. As a result, the timing adjustment circuit 6C can correct the drift amount while not only considering the drift amount in the variable delay circuit 41 but also considering the fluctuations in the drift amount in the peripheral circuits or inside the NAND flash memory 3.

[0119] In this embodiment, the amplifier circuit 60 serves as a circuit for amplifying the drift amount, but the amplifier circuit is not limited to this. For example, an adder circuit can be used. In addition, the circuit configuration for making the drift compensation amount have temperature and voltage correlation is not limited to

[0120] the configuration in Figure 11 but can have Figures 12 to 14 the configuration shown in

[0121] Figures 12 to 14 is a block diagram showing another configuration of the timing adjustment circuit for making the drift compensation amount have temperature and voltage correlation.

[0122] [First Amendment Example]

[0123] like Figure 12 As shown, the timing adjustment circuit 6D according to the first modified example uses a temperature-to-absolute-temperature (PTAT) circuit 13 instead of the BGR circuit 11 of the timing adjustment circuit 6A according to the first embodiment.

[0124] The PTAT circuit 13 has the characteristic of changing its output voltage proportionally to temperature. That is, the PTAT circuit 13 outputs an output voltage that depends on the temperature of the timing adjustment circuit 6D and the NAND flash memory 3 to the OSC circuit 12. Therefore, the OSC circuit 12 generates a clock that is temperature-dependent, and the voltage changes with temperature.

[0125] The drift detection circuit 20 uses a temperature-dependent clock to detect the amount of drift. Thus, the timing adjustment circuit 6D according to the first modified example can detect the amount of drift by using a temperature-dependent PTAT circuit 13 instead of a temperature- and voltage-independent BGR circuit 11, taking into account the temperature dependence of the NAND flash memory 3. Therefore, an optimal delay setting value matching the temperature dependence of the NAND flash memory 3 can be set.

[0126] [Second Amendment]

[0127] like Figure 13 As shown, the timing adjustment circuit 6E according to the second modification example has a configuration in which the power supply of the MDLL circuit 21 and the variable delay circuit 41 of the timing adjustment circuit 6D of the first modification example is shared with the power supply of the NAND flash memory 3. That is, the MDLL circuit 21 can detect the amount of drift while taking into account the voltage dependence of the NAND flash memory 3. In addition, the variable delay circuit 41 can set the optimal delay setting value while taking into account the voltage dependence of the NAND flash memory 3.

[0128] According to this configuration, the timing adjustment circuit 6E can set an optimal delay setting that matches the voltage dependence of the NAND flash memory 3. Furthermore, the timing adjustment circuit 6E can detect the amount of drift by using the PTAT circuit 13, taking into account the temperature dependence of the NAND flash memory 3. As a result, the timing adjustment circuit 6E can set an optimal delay setting that matches both the temperature and voltage dependence of the NAND flash memory 3.

[0129] [Third Amendment Example]

[0130] like Figure 14As shown, the timing adjustment circuit 6F according to the third modification example has a configuration in which the functions of the timing adjustment circuit 6C according to the third embodiment and the timing adjustment circuit 6E according to the second modification example are combined. That is, compared with the timing adjustment circuit 6E according to the second modification example, the timing adjustment circuit 6F further includes an amplifier circuit 60. Compared with the timing adjustment circuit 6C according to the third embodiment or the timing adjustment circuit 6E according to the second modification example, with this configuration, the timing adjustment circuit 6F can set an optimal delay setting value that matches the temperature and voltage dependence of the NAND flash memory 3.

[0131] (Fourth Embodiment)

[0132] Next, the fourth embodiment will be described.

[0133] Figure 15 This is a block diagram illustrating the configuration of the timing adjustment circuit according to the fourth embodiment. Figure 15 In, with Figure 2 The same configurations are represented by the same reference numerals, and their descriptions will be omitted.

[0134] like Figure 15 As shown, the timing adjustment circuit 6G according to the fourth embodiment has a configuration in which the reference circuit 10 is removed from the timing adjustment circuit 6A according to the first embodiment. Instead, a reference clock is provided to the MDLL circuit 21 of the timing adjustment circuit 6G from an external clock source 70. The external clock source 70 includes a crystal oscillator 71 and a PLL circuit 72.

[0135] The timing adjustment circuit 6G uses a clock generated by an external clock source 70 as a reference clock. This external clock source 70 includes a crystal oscillator 71 that has very high frequency accuracy to temperature changes, etc. Therefore, the temperature and voltage dependence of the reference clock can be reduced.

[0136] (Fifth Embodiment)

[0137] Next, the fifth embodiment will be described.

[0138] Figure 16 This is a block diagram illustrating the configuration of the timing adjustment circuit according to the fifth embodiment. Figure 16 In, with Figure 2 The same configurations are represented by the same reference numerals, and their descriptions will be omitted.

[0139] like Figure 16As shown, the timing adjustment circuit 6H according to the fifth embodiment has a configuration in which a timer circuit 80 is added to the timing adjustment circuit 6A according to the first embodiment. The timer circuit 80 measures time and outputs a control signal to the MDLL circuit 21 at predetermined intervals. The MDLL circuit 21 performs drift detection at predetermined intervals based on the control signal from the timer circuit 80. When the MDLL circuit 21 does not perform drift detection, operation stops.

[0140] When the MDLL circuit 21 is not performing drift detection, power consumption can be reduced by stopping its operation. Furthermore, the operating environment is unlikely to change drastically, and therefore the drift amount is also unlikely to change drastically. As a result, optimal delay can be maintained simply by using the timer circuit 80 to perform drift compensation operations at predetermined intervals.

[0141] Although specific embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of this disclosure. In fact, the novel embodiments described herein may be embodied in many other forms; furthermore, various omissions, substitutions, and changes may be made to the form of the embodiments described herein without departing from the spirit of this disclosure. The appended claims and their equivalents are intended to cover such forms or modifications that fall within the scope and spirit of this disclosure.

[0142] 1. Memory System

[0143] 2. Semiconductor devices (memory controllers)

[0144] 3. Memory devices (NAND flash memory)

[0145] 3A memory chip

[0146] 4. Main unit

[0147] 5 Control Unit

[0148] 6 NAND I / F circuits

[0149] Timing adjustment circuits 6A, 6B, 6C, 6D, 6E, 6F, 6G, 6H

[0150] 10. Reference Circuit

[0151] 11 BGR circuit

[0152] 12 OSC circuit

[0153] 13 PTAT Circuit

[0154] 20 Drift Detection Circuit

[0155] 21 MDLL circuits

[0156] 22 Subtraction Circuit

[0157] 23, 34A, 37 memory

[0158] 24-Clock Generation Circuit

[0159] 25, 42 delay lines

[0160] 26 Code Generation Circuit

[0161] 30 Operational Circuit

[0162] 31, 32, 50 combined circuit

[0163] Adder circuits 33 and 36

[0164] 34 Select Signal Generation Unit

[0165] 35, 43, 56 selectors

[0166] 40 Delay Adjustment Circuit

[0167] 41 Variable Delay Circuit

[0168] 51 DCC circuit

[0169] 52 Adjustment Circuit

[0170] 53 Variable Delay Circuit

[0171] 54 AND circuit

[0172] 55 OR circuit

[0173] 57 Control Circuit

[0174] 60 Amplifier Circuit

[0175] 70 External clock source

[0176] 71 Crystal Oscillator

[0177] 72 PLL circuit

[0178] 80 Timer Circuit

Claims

1. A semiconductor device, comprising: A drift detection circuit is configured to retrieve a first delay amount of a reference signal that has been previously determined to pass through a circuit element at a first timing, determine a second delay amount of the reference signal that passes through the circuit element at a second timing after the first timing, and output a drift amount as the difference between the first delay amount and the second delay amount. as well as A delay adjustment circuit is configured to retrieve a previously determined third delay amount of a first signal sent to an external device of the semiconductor device at a first timing, determine a fourth delay amount based on the third delay amount and the drift amount as a delay amount to be applied to the first signal for a period of time after the second timing, and send the first signal with the fourth delay amount applied to it to the external device.

2. The semiconductor device according to claim 1, wherein, The delay adjustment circuit determines the drift compensation amount by multiplying the drift amount by the ratio of the third delay amount to the first delay amount, and determines the fourth delay amount based on the drift compensation amount and the third delay amount.

3. The semiconductor device according to claim 2, wherein, The delay adjustment circuit determines the fourth delay by adding the drift compensation amount to the third delay amount.

4. The semiconductor device according to claim 2, wherein The drift detection circuit includes a plurality of first delay elements. The number of first delay elements having a total delay corresponding to a first period of the reference signal at the first timing is determined as a first set value, and the number of first delay elements having a total delay corresponding to the first period of the reference signal at the second timing is determined as a second set value. The delay adjustment circuit determines the drift compensation amount based on a first difference, which is the result of performing a displacement operation on the difference between the first set value and the second set value.

5. The semiconductor device according to claim 4, wherein The delay adjustment circuit includes a plurality of second delay elements, each of the first and second delay elements having the same delay amount, and The delay adjustment circuit determines the number of second delay elements having a total delay corresponding to the third delay as a third set value, and determines the fourth delay based on the result of adding the first difference to the third set value.

6. The semiconductor device according to claim 4, wherein, The drift detection circuit determines the displacement amount of the displacement operation based on the ratio of the third delay amount to the first delay amount.

7. The semiconductor device according to claim 1, wherein The circuit element is a delay circuit, and The drift detection circuit generates a reference signal with a first period, and determines the first delay amount based on the time period required for the reference signal to pass through multiple delay elements in the delay circuit.

8. The semiconductor device according to claim 1, wherein, The first delay and the third delay are determined during training.

9. The semiconductor device according to claim 1, further comprising: A reference circuit is configured to generate a reference clock that does not change due to temperature variations within a first range and voltage variations within a second range. The reference clock is provided to the drift detection circuit as the reference signal.

10. The semiconductor device of claim 1, further comprising: A duty cycle adjustment circuit is configured to adjust the duty cycle of the first signal based on the drift amount.

11. The semiconductor device according to claim 1, further comprising: An amplifier circuit is configured to amplify the drift.

12. The semiconductor device according to claim 1, wherein, The power supply for the drift detection circuit and the delay adjustment circuit is shared with the power supply for the external device.

13. The semiconductor device according to claim 1, wherein, The drift detection circuit determines the amount of drift based on a reference clock generated by an external clock source.

14. The semiconductor device of claim 1, further comprising: Timer circuit, The drift detection circuit determines the drift amount at predetermined intervals based on a control signal generated by the timer circuit at predetermined intervals.

15. A memory system, comprising: Non-volatile memory; as well as A semiconductor device electrically connected to the non-volatile memory and configured to control the non-volatile memory, the semiconductor device comprising: A drift detection circuit is configured to retrieve a first delay amount of a reference signal that has been previously determined to pass through a circuit element at a first timing, determine a second delay amount of the reference signal that passes through the circuit element at a second timing after the first timing, and output a drift amount as the difference between the first delay amount and the second delay amount. as well as A delay adjustment circuit is configured to retrieve a previously determined third delay amount of a first signal sent to the non-volatile memory at the first timing, determine a fourth delay amount based on the third delay amount and the drift amount as a delay amount to be applied to the first signal for a period of time after the second timing, and send the first signal with the fourth delay amount applied to it to the non-volatile memory.

16. The memory system according to claim 15, wherein, The first signal is a data signal or data strobe signal sent from the semiconductor device to the non-volatile memory.

17. A method for correcting signals transmitted from a memory controller to a memory device, the method comprising: Determine the first delay amount of the reference signal passing through multiple delay circuits during the training phase; Determine a second delay amount of the reference signal passing through the plurality of delay circuits during a preparation phase following the training phase; Determine a third delay amount for the signal sent from the memory controller to the memory device during the training phase; A fourth delay amount is determined based on the difference between the first delay amount and the second delay amount during the preparation phase, and the third delay amount; as well as During the operation phase following the preparation phase, the signal is delayed by the fourth delay amount and the delayed signal is sent from the memory controller to the memory device.

18. The method according to claim 17, wherein, The fourth delay is determined based on the third delay and the drift compensation, wherein the drift compensation is obtained by multiplying the difference between the first delay and the second delay by the ratio of the third delay to the first delay.

19. The method according to claim 18, wherein, The fourth delay is determined by adding the third delay to the drift compensation.

20. The method of claim 17, further comprising: A reference clock is generated that will not change due to temperature variations within a first range or voltage variations within a second range. The reference clock serves as the reference signal and passes through the plurality of delay circuits.

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