Method of manufacturing an electrical contact junction that allows current flow

Abstract

The present disclosure provides a method of fabricating an electrical contact junction that allows current flow, the method comprising: providing a substrate comprising a first layer of superconductor material; removing native oxide of the superconductor material of the first layer from a first region of the first layer; forming a capping layer in contact with the first region of the first layer, wherein the capping layer prevents reformation of the native oxide of the superconductor material in the first region; after forming the capping layer, forming a second layer of superconductor material electrically connected to the first region of the first layer of superconductor material to provide an electrical contact junction that allows current flow.

Description

[0001] This application is a divisional application of the patent application filed on September 15, 2016, with application number 201680090090.5 and entitled "A coating for reducing ion polishing damage". Technical Field

[0002] This disclosure relates to a coating for reducing ion milling damage. Background Technology

[0003] Quantum computing is a relatively new method of computation that utilizes quantum effects, such as the superposition and entanglement of fundamental states, to perform certain computations more efficiently than traditional digital computers. Compared to digital computers, which store and manipulate information in bits (e.g., "1" or "0"), quantum computing systems can manipulate information using qubits. A qubit can be defined as a quantum device capable of superimposing multiple states (e.g., data in "0" and "1" states) and / or superimposing the data itself in multiple states. In conventional terms, the superposition of "0" and "1" states in a quantum system can be represented, for example, as α|0> + β|1>. The "0" and "1" states of a digital computer are analogous to the │0> and │1> fundamental states of a qubit, respectively. Value │α│ 2 This represents the probability that a qubit is in the |0> state, while the value |β| represents the probability of the qubit being in the |0> state. 2 This represents the probability that a qubit is in the |1> fundamental state. Summary of the Invention

[0004] Typically, in some aspects, the subject matter of this disclosure can be embodied as a method of manufacturing an electrical contact junction that allows current flow, the method comprising: providing a substrate comprising a first layer of superconducting material; removing the native oxide of the first layer of superconducting material from a first region of the first layer; forming a capping layer in contact with the first region of the first layer, wherein the capping layer prevents the reformation of the native oxide of the superconducting material in the first region; and, after forming the capping layer, forming a second layer of superconducting material electrically connected to the first region of the first layer of superconducting material to provide an electrical contact junction that allows current flow.

[0005] The implementation of the method may include one or more of the following features. For example, in some embodiments, removing native oxides includes ion milling a first region of the first layer of superconducting material.

[0006] In some embodiments, removing native oxide from a first region of the first superconductor material includes: applying a first photoresist layer to the first superconductor material; patterning the first photoresist layer to expose a first region of the first superconductor material; and ion-milling the exposed first region of the first superconductor material. Forming a capping layer may include: forming a capping layer on the patterned first photoresist layer such that a portion of the capping layer is in direct contact with the ion-milled exposed first region of the first superconductor material; and removing a portion of the capping layer that is not in direct contact with the ion-milled exposed first region of the first superconductor material. Forming a second superconductor material may include: applying a second photoresist layer; patterning the second photoresist layer to expose a capping layer and a portion of the substrate surface; and forming a second superconductor material on the exposed portions of the capping layer and the substrate surface. Forming a second superconductor material may include: applying a second photoresist layer; patterning the second photoresist layer to expose a capping layer and a portion of the substrate surface; removing the capping layer to expose a portion of the first layer without native oxides; and forming the second superconductor material on the first exposed region of the first layer without native oxides and on the exposed portion of the substrate surface.

[0007] In some embodiments, the capping layer comprises a material that, when subjected to ion polishing under a predetermined set of ion beam parameters, has an etch rate higher than that of a native oxide subjected to the same predetermined set of ion beam parameters. The predetermined set of ion beam parameters may include beam voltage, beam current, and beam width. The etch rate of the capping layer material may be at least five times higher than that of the native oxide. The etch rate of the capping layer material may be at least fifteen times higher than that of the native oxide. The capping layer material may include silver or gold. The capping layer material may include a metal, the thickness of which is such that when the electrical contact junction is cooled below the critical temperature of the first layer of superconducting material, the metal behaves as a superconductor due to the superconducting proximity effect. The thickness of the metal may be between about 5 nm and about 10 nm. The capping layer material may include a superconducting material. The superconducting material of the capping layer may include titanium nitride, rhenium, or ruthenium.

[0008] In some implementations, the superconducting material of the first layer includes aluminum.

[0009] In some implementations, the superconducting material of the second layer includes aluminum.

[0010] Typically, in another aspect, the subject matter of this disclosure can be embodied as a device comprising: a substrate; a first layer of superconducting material on the substrate, the first layer of superconducting material having first and second opposing surfaces, wherein the second surface faces away from the substrate; a capping layer in contact with the second surface of the first layer of superconducting material, wherein the capping layer suppresses the formation of native oxide on the first layer, and wherein the region in contact with the capping layer of the second surface of the first layer of superconducting material is free of native oxide of the superconducting material; and a second layer of superconducting material in direct contact with the capping layer.

[0011] The device may have one or more of the following features. For example, in some embodiments, a first layer of superconducting material, a capping layer, and a second layer of superconducting material form an electrical contact junction that allows unimpeded flow of DC current.

[0012] In some embodiments, the capping layer includes a material that can be associated with an ion-milling etch rate, the ion-milling etch rate being higher, under a predetermined set of ion beam parameters, than the ion-milling etch rate associated with the natural oxide of the first layer superconducting material under the same set of predetermined ion beam parameters. The predetermined set of ion beam parameters may include beam voltage, beam current, and beam width. The etch rate associated with the capping layer material may be at least five times higher than the etch rate of the natural oxide of the first layer superconducting material. The etch rate associated with the capping layer material may be at least fifteen times higher than the etch rate of the natural oxide of the first layer superconducting material. The capping layer material may include silver or gold. The capping layer material may include a metal, the thickness of which is such that when the electrical contact junction is cooled below the critical temperature of the first layer superconducting material, the metal behaves as a superconductor due to the superconducting proximity effect. The thickness of the metal may be between about 5 nm and about 10 nm. The capping layer material may include a superconducting material. The capping layer material may include titanium nitride, rhenium, or ruthenium.

[0013] In some implementations, the superconductor material of the first layer may be aluminum.

[0014] In some implementations, the superconductor material of the second layer can be aluminum.

[0015] In some implementations, the device may be a quantum bit.

[0016] In some implementations, the device may be a capacitor.

[0017] In some implementations, the device may be a bridge.

[0018] Implementations may include one or more of the following advantages. For example, in some implementations, the capping layer prevents the reformation of native oxides on the underlying superconductor. In some implementations, the opening region forming the capping layer may be positioned only above the area of ​​the substrate to be contacted (with removable resist in other areas with protective devices), such that any residue formed due to ion polishing is confined to the opening region. Additionally, since contaminants on the metal / superconductor surface of the substrate cannot store as much energy as on the dielectric surface of the substrate (due to the relative permittivity between the vacuum (1) and the substrate material), residues may deposit less on the substrate surface than on the substrate surface protected by the resist. Furthermore, in some implementations, residues formed in the opening region may be buried between the substrate and the subsequent junction metal / superconductor layer to be deposited.

[0019] For the purposes of this disclosure, superconducting (or alternatively superconducting) materials can be understood as materials that exhibit superconducting properties at or below the superconducting critical temperature. Examples of superconducting materials include aluminum (superconducting critical temperature, for example, 1.2 Kelvin), niobium (superconducting critical temperature, for example, 9.3 Kelvin), and titanium nitride (superconducting critical temperature, for example, 5.6 Kelvin).

[0020] Details of one or more embodiments are set forth in the accompanying drawings and the following description. Other features and advantages will become apparent from the specification, drawings, and claims. Attached Figure Description

[0021] Figure 1A-1D This is an example of the process and a schematic diagram of the resulting damage, in which ion milling is used to remove native oxides from the superconductor substrate.

[0022] Figure 2A This is a circuit diagram of an example of xmon qubits.

[0023] Figure 2B This is a scanning electron microscope image showing an example of a portion of the xmon qubit.

[0024] Figure 3 This is a scanning electron microscope image showing an example of xmon qubits.

[0025] Figures 4A-4F This is a schematic diagram illustrating an example of the process in which native oxides are removed from the superconductor substrate using ion milling and a capping layer. Detailed Implementation

[0026] Quantum computing requires coherent processing of quantum information stored in qubits (qubits) of a quantum computer. In some types of quantum computing processors, such as quantum annealers, the qubits are coupled together in a controllable manner, such that the quantum state of each qubit affects the corresponding quantum state of the other qubits it is coupled with. Superconducting quantum computing is a promising realization of quantum computing technology, in which quantum circuit elements are partially formed from superconducting materials. Superconducting quantum computers are typically multi-stage systems, with only the first two stages serving as the computational basis. In some implementations, quantum circuit elements, such as qubits, operate at very low temperatures to achieve superconductivity, and therefore thermal fluctuations do not cause transitions between energy levels. It may be preferable that the quantum circuit elements operate with low energy loss and dissipation (e.g., the quantum circuit elements exhibit a high quality factor Q) to avoid, for example, quantum decoherence. Factors that can lead to energy loss and / or decoherence include, for example, material defects, electronic system excitations, and undesirable radiative coupling.

[0027] Superconducting materials can be used to form a variety of quantum circuit elements and components, such as Josephson junctions, superconducting coplanar waveguides, quantum LC oscillators, qubits (e.g., flux qubits or charge qubits), superconducting quantum interference devices (SQUIDs) (e.g., RF-SQUIDs or DC-SQUIDs), inductors, capacitors, transmission lines, ground planes, etc. The fabrication of certain quantum circuit elements (including, for example, Josephson junctions, multilevel capacitors, and crossing bridges (sometimes also called air bridges)) may require multiple processing steps, where a first patterned superconducting layer is formed and then directly contacted with a second patterned superconducting layer. To reduce losses and achieve a high quality factor, the interface between the two superconducting layers should provide direct electrical contact for current, allowing DC current to flow substantially without loss. However, in some embodiments, the presence of native oxide at the interface between the superconducting layers can inhibit the formation of direct electrical and physical contacts between the superconducting layers. For example, native oxide can be used as an unintended capacitor and an additional Josephson junction, thus a lossy component. Typically, this native oxide is relatively thin, for example, about a few nanometers thick.

[0028] In the absence of native oxide between superconducting layers, DC current can flow unimpeded. Therefore, to maintain low-loss direct electrical contact between the first and second superconducting materials, techniques such as ion milling can be used to remove the native oxide. Ion milling is a physical etching technique in which ions of an inert gas (typically Ar) are accelerated from a broad-beam ion source to the material surface to remove material to a desired depth or subsurface. When using ion milling to remove the native oxide from superconducting materials, ion bombardment can also attack other materials in the device, such as the substrate or dielectric layer, causing damage to these materials. Alternatively or additionally, ion bombardment can cause partially redeposited photoresist that has already been ion-milled onto the areas where the native oxide has been removed, as well as other areas of the substrate. The redeposited resist can become a mixture of metals that are difficult, or in some cases practically impossible, to remove without damaging other areas of the substrate. In both cases (due to ion damage to other materials remaining on the device surface and residues), the final quality factor of the device manufactured using this technique can be significantly reduced. An example of a superconducting material that can be used to form quantum circuit elements and form the native oxide is aluminum. Aluminum has natural oxides (such as Al₂O₃), which can be particularly difficult to remove by ion polishing, thus requiring a relatively long etching time. The longer the substrate or other layers are exposed to ion bombardment, the more severe the damage. For example, in the case of aluminum, ion polishing can result in a quality factor reduction of ten times or more.

[0029] Figure 1A-1D An example of the process and the resulting damage is shown, in which ion milling is used to remove native oxides from the superconducting substrate, thereby allowing direct electrical contact with the substrate. Specifically, Figure 1A-1D The example process depicted in the image shows a cross-sectional view of the formation of a portion of the xmon qubit. Figure 2A The diagram shows a circuit schematic of an example of the xmon qubit 200.

[0030] Xmon qubits typically consist of a planar structure with four arms, each arm serving a different function. (See reference...) Figure 2A The xmon qubit can provide a first arm 202 for coupling to a measurement readout resonator; a second arm 204 for coupling to one or more other qubits via, for example, a quantum bus resonator; a third arm 206 for providing XY control to excite the qubit state; and a fourth arm 208 for providing Z control to tune the qubit frequency. At the end of the fourth arm 208, the xmon qubit can include a tunable Josephson junction formed by a ring SQUID. This ring intersects with two tunnel junctions 212 and is connected to the ground and the Z control line. The intersection of the four arms provides a qubit capacitance 210. Figure 2AThe other capacitors shown represent coupling capacitances to other components, such as readout resonators, XY drivers, and quantum buses. Figure 2B This is a scanning electron micrograph showing a top view of the region where the Josephson junction forms in the example xmon qubit. Figure 2B As illustrated in the example, a multilayer superconducting material (such as aluminum) can be used to form qubits: a base aluminum wiring layer 250, a first aluminum layer 252 formed on the surface of the base aluminum wiring layer 250, and a second aluminum layer 254 formed on the surface of the first aluminum layer 252. A Josephson junction 256 is formed between the first aluminum layer 252 and the second aluminum layer 254 by oxidizing the surface of the first aluminum layer 252 in contact with the second aluminum layer 254. To suppress the formation of other unintended Josephson junctions, the region 258 where the first aluminum layer 252 and the second aluminum layer 254 overlap with the base aluminum wiring layer 250 should provide a direct electrical contact that allows unimpeded flow of DC current. Figure 1A-1D The manufacturing process shown focuses on one of the 258 regions where xmon qubits are formed (in Figure 2B (Represented by black dashed lines in the middle), where the first aluminum wiring layer is in contact with the second aluminum wiring layer.

[0031] like Figure 1A As shown, a substrate 102 having a base layer 104 is provided. The base layer 104 can be formed of a superconducting material. For example, the base layer 104 can be formed of aluminum, niobium, or titanium nitride. The base layer 104 can be patterned (using, for example, photolithography and etching or lift-off techniques) to define a first portion of the junction. The substrate 102 on which the base layer 104 is formed can include a dielectric material, such as silicon or sapphire. For example, in some embodiments, the substrate 102 can be a silicon or sapphire wafer.

[0032] The processing of substrate 102 and base layer 104 occurs partly at or near standard ambient temperature and pressure (e.g., 25°C and 1 bar). As a result, the superconducting material of base layer 104 can form a relatively thin layer of native oxide 106 on its surface exposed to the atmosphere. As explained herein, ion milling can be used to remove the native oxide 106 from areas where electrical contact without impedance is desired. For example, as... Figure 1B As shown, ion polishing 101 can be applied to region 108 of substrate 102 and base layer 104, region 108 being defined by a patterned photoresist layer 110, to remove native oxide 106. In the case of an aluminum base layer, Ar ion polishing can be applied for approximately 3 minutes using the following beam parameters to remove native aluminum oxide: 400V, 21mA, and a beam width of approximately 3.2″. After the ion polishing step, a second superconducting material layer 112 can be formed on region 108, such that direct electrical contacts allowing unimpeded flow of DC current are formed by the base layer 104, as shown. Figure 1CAs shown. Then, the unwanted portions of the second superconductor layer 112 are removed. For example, as... Figure 1D As shown, a portion of the second superconductor layer 112 outside region 108 is removed using a stripping process. Figure 1D As shown, the second superconductor layer 112 may have its own native oxide layer 118. The aforementioned process can lead to substantial damage to the substrate (region 114) and leave redeposited resist as residue 116, both of which can increase losses and thus reduce the quality factor associated with the circuit elements being formed. Figure 3 These are scanning electron microscope images showing an example of substrate surface damage that may have resulted from ion polishing to remove native oxides during the formation of xmon qubits. Damage in area 300 is highlighted.

[0033] To reduce losses associated with ion polishing, a coating layer can be introduced, which prevents the reformation of native oxides and allows the process to be altered to avoid damage caused by ion polishing and hardening of the resist. Figures 4A-4F This is a schematic diagram illustrating an example of the process, in which ion milling and a capping layer are used to remove native oxides from the superconductor substrate, allowing for impedance-free electrical contact with the substrate. Specifically, Figures 4A-4F The example process depicted shows a cross-sectional view of the formation of a portion of an xmon qubit. However, the use of a capping layer, as detailed herein, can also be applied during the formation of other devices, such as in the formation of superconducting quantum circuit elements that include capacitors or bridging.

[0034] like Figure 4A As shown, a substrate 402 having a base layer 404 is provided. The base layer 404 can be formed of a superconducting material. For example, the base layer 404 can be formed of aluminum, niobium, or titanium nitride. The base layer 404 can be patterned (using, for example, photolithography and etching or lift-off techniques) to define a first portion of the junction. Figure 1A-1D As in the example, the superconducting material of the base layer 404 forms a natural oxide 406. The substrate 402 on which the base layer 404 is formed may include a dielectric material, such as silicon or sapphire. For example, in some embodiments, the substrate 402 may be a silicon or sapphire wafer.

[0035] In the next step, such as Figure 4B As shown, a photoresist layer 408 is deposited and patterned to define an opening region 401 that exposes a portion of the substrate 404. (Compared to...) Figure 1A-1D Conversely, the opening region 401 may be limited only to the area of ​​the base layer 404 that contacts the second superconductor layer. The remaining portions of the base layer 404 and substrate 402 are covered by a photoresist layer 408. Other areas of the device may also be protected with the photoresist layer 408.

[0036] The native oxide 406 of the substrate 404 in the opening region 401 can then be removed using ion milling 403. For example, the substrate 404 may comprise aluminum, and ion milling can remove the native aluminum oxide from the substrate 404. The presence of the photoresist layer 408 prevents ion bombardment and thus damage to the surfaces of permanent structures, such as the substrate 402 or other material layers that will be used to form circuit devices. Forming the opening region 401 only above the area of ​​the substrate 404 to be contacted has several advantages. For example, since ion milling now only occurs on the top surface of the substrate 404 defined by the photoresist 408 (ion milling of the resist itself can be ignored), any residues formed can be confined to the opening region 401. This can be advantageous because contaminants on the metal / superconductor surface of the substrate 404 cannot store as much energy as on the dielectric surface of the substrate (due to the relative permittivity between the vacuum (1) and the substrate material (about 10-11 for sapphire and silicon)). Therefore, it is considered that the deposition of residues on the substrate surface is less than that on the substrate surface. Additionally, any remaining residue can be embedded between the substrate 404 and the subsequently deposited junction metal / superconductor layer. In some embodiments, this eliminates energy stored in the opening region 401 because the two metal / superconductor layers will be at the same potential due to DC electrical contact. Furthermore, in some embodiments, the metal / superconductor material forming the substrate 404 can be etched at a lower rate than the substrate under ion milling, thus reducing the likelihood of forming difficult-to-remove photoresist residue complexes.

[0037] After removing the native oxides, a capping layer 410 can be formed in the opening region 401, such as... Figure 4CAs shown. The capping layer 410 can be formed to contact the surface of the substrate 404, from which native oxide is removed. With the capping layer 410 in place, additional device processing can be performed in region 401 without the reformation of native oxide when the device is exposed to atmospheric oxygen. Furthermore, the capping layer 410 can be formed of a material that is easier to remove than native oxide. For example, the capping layer 410 can be formed of a material whose etching rate, when ion-milled under a predetermined set of ion beam parameters, can be higher than the etching rate of the native oxide of the superconducting material of the substrate 404 when ion-milled under the same predetermined set of ion beam parameters. The predetermined set of ion beam parameters may include, for example, beam voltage, beam current, and / or beam width. In this way, when removing the capping layer 410, the technique used to remove the capping layer 410 (e.g., ion milling) can cause less overall damage to the device than in the case of removing native oxide, because it may require less total time to remove material of the same thickness. The thinnest possible thickness of the capping layer 410 corresponds to the thickness that prevents the reformation of native oxide. Depending on the material and deposition parameters, this can be as small as a few nanometers. In some implementations, the cover layer 410 may have a thickness extending to a few micrometers or greater.

[0038] Under the same processing parameters, the removal rate of the capping layer 410 can vary relative to the removal rate of the native oxide. For example, in some embodiments, the capping layer 410 may be associated with an etching rate by ion milling that is at least two, at least five, at least ten, at least fifteen, or at least twenty times higher than the etching rate by ion milling associated with the native oxide of the superconducting material of the substrate 404 under the same predetermined set of ion milling beam parameters.

[0039] Table 1 below illustrates various examples of etching rates for different materials subjected to ion milling under the same beam parameters of 80 mA, 100 V acceleration, and constant beam width. Values ​​are rounded to the nearest integer.

[0040] Table 1

[0041]

[0042] As can be seen from Table 1, alumina exhibits approximately [a certain property] when subjected to ion milling. The etching rate. Various different materials can be selected as the capping material, having a higher ion-milling etch rate than alumina. In some embodiments, it may be advantageous to select a material with a higher etch rate than materials that also undergo ion milling (other than capping 410). For example, in some embodiments, areas other than capping 410 may be subjected to ion bombardment during capping 410 removal. These other areas may include, for example, the substrate surface of the device or other layers. Examples of such materials include silicon and silicon oxide (e.g., SiO2), which, respectively, with… and The ion-milling etching rate is related to the etch rate, as shown in Table 1. These other areas may not be protected by temporary capping layers such as resists. By selecting capping materials with a higher etch rate than native oxides and a higher etch rate than other materials exposed to ion bombardment, the amount of undesirable damage to those other materials can be reduced. This is because capping materials can be etched much faster than other materials exposed to ion milling.

[0043] As an example, in some implementations, the cover layer 410 may be made of silver (ion polishing etch rate of 0.5%). ) or gold (ion polishing etching rate is Alternatively, the capping layer 410 may be formed of a superconducting material. In some embodiments, the capping layer 410 may be formed of a superconducting material that does not form or minimizes native oxides and still has a higher etch rate than the native oxides of the base material covered by the capping layer 410. For example, in some embodiments, the capping layer 410 may be formed of titanium nitride, rhenium, or ruthenium.

[0044] After the capping layer 410 is formed, the photoresist layer 408 defining the opening region 401 can be removed. For example, layer 408 can be removed by applying a photoresist stripping solution to the device or by performing O2 ashing (also known as plasma ashing) of the resist. Figure 4D As shown, a second photoresist layer 412 can then be deposited and patterned to define the region 405 where the second superconductor layer will be deposited. However, the capping layer 410 can be removed before depositing the second superconductor layer. As explained herein, the capping layer 410 can be removed using ion milling. Because the material of the capping layer 410 can be associated with a relatively high etch rate, the capping layer 410 can be removed quickly and with minimal damage to the photoresist hardening compared to removing the natural oxide of the superconductor material from the base layer 404.

[0045] like Figure 4EAs shown, a second superconducting layer 414 can then be deposited and patterned such that it is in direct electrical and physical contact with the base layer 404 and with the substrate 402. The second superconducting layer 414 can be formed of the same or different material as the base layer 404. For example, the second superconducting layer 414 can be formed of aluminum, titanium nitride, or niobium, among other materials. The second superconducting layer 414 can be patterned using, for example, a stripping process, in which undesirable portions of the superconducting material are removed when the photoresist 412 is stripped. Figure 4E As shown, the second superconductor layer 414 may have its own natural oxide layer 416.

[0046] Alternatively, in some embodiments, the cover layer 410 is not removed, such as Figure 4F As shown. Conversely, a second superconducting layer 414 can be formed on and in contact with the capping layer 410. If, for example, the capping layer 410 is formed of a superconducting material, direct electrical contact that allows unimpeded flow of DC current can still exist between the base layer 404 and the second superconducting layer 414. For example, if a superconducting material with little or no native oxides (e.g., TiN, Re, or Ru) is chosen as the capping layer 410, the native oxides on the capping layer 410 itself can be removed by relatively rapid ion milling with little damage or resist hardening.

[0047] In some embodiments, the capping layer 410 may be formed of a metal, the thickness of which causes the metal to behave as a superconductor due to the superconducting proximity effect. The superconducting proximity effect occurs when a superconducting material comes into contact with a non-superconducting material (e.g., gold or silver), causing the non-superconducting material to begin exhibiting zero or near-zero resistance at mesoscopic distances. Typically, the proximity effect can be observed when two superconducting materials are separated by a thin film of non-superconducting metal. In some embodiments, the proximity effect can cause the critical temperature T of the superconductor adjacent to the non-superconductor to increase. c The thickness can be reduced. Thicknesses that can utilize the proximity effect in this way include, for example, from about 5 nm to about several hundred nanometers (e.g., about 100 nm, about 200 nm, about 300 nm, about 400 nm, or about 500 nm). For example, in some embodiments, the thickness can be between about 5 nm and about 10 nm.

[0048] exist Figure 4F In the example shown, a metal such as gold or silver can be chosen as the capping layer 410. By leaving the capping layer 410 in place, direct electrical contact that allows DC current to flow unimpeded can be maintained without having to perform a second ion polishing step, thus further reducing potential damage and improving the quality factor of the manufactured device.

[0049] The processes described herein may require the deposition of one or more materials, such as superconductors, dielectrics, and / or metals. Depending on the materials chosen, these materials may be deposited using deposition processes such as chemical vapor deposition, physical vapor deposition (e.g., evaporation or sputtering), epitaxy, and other deposition processes. The processes described herein may also require the removal of one or more materials from the device during fabrication. Depending on the materials to be removed, the removal process may include, for example, wet etching, dry etching, or a stripping process.

[0050] The implementations of quantum themes and quantum operations described in this specification can be implemented in suitable quantum circuits, or more generally in quantum computing systems, including the structures disclosed in this specification and their structural equivalents, or combinations thereof. The term "quantum computing system" may include, but is not limited to, a quantum computer, a quantum information processing system, a quantum encryption system, or a quantum simulator.

[0051] The terms quantum information and quantum data refer to information or data carried, held, or stored in quantum systems, the smallest nontrivial system being a qubit, such as a system that defines a unit of quantum information. It should be understood that the term "qubit" includes all quantum systems that can be appropriately approximated as a two-level system in the appropriate context. Such quantum systems can include multi-level systems, such as those having two or more levels. For example, such systems can include atoms, electrons, photons, ions, or superconducting qubits. In many implementations, the computational fundamental state is identified using a ground state and a first excited state, but it should be understood that other settings where the computational state is identified using a higher-level excited state are possible. It can be understood that a quantum memory is a device capable of storing quantum data for a long time with high fidelity and efficiency, such as a light-matter interface, where light is used for transmission and matter is used for storing and preserving quantum features of quantum data such as superposition or quantum coherence.

[0052] Quantum circuit elements can be used to perform quantum processing operations. That is, quantum circuit elements can be configured to perform operations on data in a nondeterministic manner using quantum mechanical phenomena such as superposition and entanglement. Some quantum circuit elements, such as qubits, can be configured to simultaneously represent and manipulate information from more than one state. Examples of superconducting quantum circuit elements that can be formed using the processes disclosed herein include circuit elements such as coplanar waveguides, quantum LC oscillators, qubits (e.g., flux qubits or charge qubits), superconducting quantum interference devices (SQUIDs) (e.g., RF-SQUIDs or DC-SQUIDs), inductors, capacitors, transmission lines, ground planes, etc.

[0053] In contrast, classical circuit elements typically process data in a deterministic manner. Classical circuit elements can be configured to collectively execute instructions of a computer program by performing basic arithmetic, logic, and / or input / output operations on data, where the data is represented in analog or digital form. In some implementations, classical circuit elements can be used to transmit data to and / or receive data from quantum circuit elements via electrical or electromagnetic connections. Examples of classical circuit elements that can be formed using the processes disclosed herein include fast single-throughput quantum (RSFQ) devices, reciprocal quantum logic (RQL) devices, and ERSFQ devices, which are energy-efficient versions of RSFQs that do not use bias resistors. Other classical circuit elements can also be formed using the processes disclosed herein.

[0054] During the operation of a quantum computing system using superconducting quantum circuit elements and / or superconducting classical circuit elements (such as those described herein), the superconducting circuit elements are cooled in a cryostat to a temperature that allows the superconducting material to exhibit superconducting properties.

[0055] While this specification contains numerous specific details of implementation, these should not be construed as limiting the scope of possible claims, but rather as descriptions of features that may be specific to particular embodiments. Some features described herein in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of individual embodiments may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although the features above may be described as operating in certain combinations, and even initially stated so, in some cases one or more features from the claimed combination may be removed from the combination, and the claimed combination may be for sub-combinations or variations thereof.

[0056] Similarly, although the operations are depicted in a specific order in the accompanying drawings, this should not be construed as requiring that these operations be performed in the specific order shown or sequentially, or that all of the shown operations be performed to achieve the desired result. For example, the actions recited in the claims can be performed in a different order and still achieve the desired result. In some cases, multitasking in parallel may be advantageous. Furthermore, the separation of various components in the above embodiments should not be construed as requiring such separation in all embodiments.

[0057] Many embodiments have been described. However, it should be understood that various modifications can be made without departing from the spirit and scope of the invention. Other embodiments are within the scope of the following claims.

Claims

1. A method for manufacturing an electrical contact junction that allows current to flow, the method comprising: Provide a substrate including a first layer of superconducting material; Remove the natural oxide of the superconducting material of the first layer from the first region of the first layer; A capping layer is formed in contact with the first region of the first layer, wherein the capping layer prevents the reformation of the natural oxide of the superconducting material in the first region. The overlay comprises a material that, when subjected to ion milling under a predetermined set of ion beam parameters, has an etch rate higher than that of a native oxide subjected to the same predetermined set of ion beam parameters. as well as After the capping layer is formed, a second layer of superconducting material is formed, which is electrically connected to the first region of the first layer of superconducting material to provide an electrical contact junction that allows current to flow.

2. The method according to claim 1, wherein the thickness of the covering layer is between 5 nm and 10 nm.

3. The method of claim 1, wherein the capping layer comprises a metal having a thickness such that when the electrical contact junction is cooled below the critical temperature of the superconducting material, the metal behaves as a superconductor due to the superconducting proximity effect.

4. The method according to claim 1, wherein the superconducting material of the first layer comprises aluminum, niobium, or titanium nitride.

5. The method of claim 1, wherein the coating layer comprises titanium nitride, rhenium, or ruthenium.

6. The method of claim 1, wherein the covering layer comprises a superconductor.

7. The method of claim 1, wherein the covering layer comprises silver or gold.

8. The method according to claim 1, wherein the predetermined set of ion beam parameters includes beam voltage, beam current and beam width.

9. The method of claim 1, wherein the etching rate of the overlay is at least five times higher than the etching rate of the natural oxide.

10. The method of claim 1, wherein the etching rate of the overlay is at least fifteen times higher than the etching rate of the natural oxide.

11. The method of claim 1, wherein the superconducting material of the second layer comprises titanium nitride, rhenium, or ruthenium.

12. The method of claim 1, wherein the electrical contact junction forms a portion of the qubit.

13. The method of claim 1, wherein the electrical contact junction forms a portion of the capacitor.

14. The method of claim 1, wherein the electrical contact junction forms a portion of the bridge.

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