Method and system for testing and collecting the function and performance of an execution unit based on synchronization

Abstract

The application discloses a kind of based on synchronous method test collection execution unit function and performance method and system, belong to electric power system relay protection technical field.The method of the present application, including: based on external clock source, to be tested collection execution unit and the test system for testing to be tested collection execution unit are time-synchronized;After the time-synchronization is completed, based on the function and performance test of the synchronous method to the collection execution unit to be tested.The test method of the present application, collection execution unit is tested by test system and clock source, can satisfy the field test and laboratory test of collection execution unit, by testing the performance and function of collection execution unit, can find the defect and hidden danger of collection execution unit equipment in advance, can guide to improve product quality, guarantee the reliability of new generation substation collection execution unit function performance and information interaction.

Description

Technical Field

[0001] This invention relates to the field of power system relay protection technology, and more specifically, to a method and system for testing the function and performance of a data acquisition and execution unit based on a synchronization method. Background Technology

[0002] Process-level equipment, as one of the key technologies and main characteristics of smart substations, has experienced rapid development and widespread application over the past decade. In terms of relay protection acquisition and execution technology, the functions of relay protection acquisition and execution in conventional substations are distributed among various specific secondary devices. Primary instrument transformers directly input secondary signals to the protection device via cables. The protection device has a dedicated small instrument transformer acquisition circuit to convert analog quantities into digital quantities. Simultaneously, the protection device connects to the circuit breaker auxiliary position node and disconnector position node via cables, and drives the circuit breaker opening and closing through a cable control operating box. With the development of digital and smart substation technologies, dedicated acquisition units (merging units) and execution units (intelligent terminals) have emerged to replace the corresponding functional components originally integrated into the protection device. The main function of the merging unit is to collect and synchronize the output signals of multiple instrument transformers, acquire power system current and voltage sampling values, and transmit them with a certain data quality to power system electrical measuring instruments and relay protection equipment. It is a crucial link in the connection between instrument transformers and the substation secondary system, providing a unified data source for secondary equipment such as protection, measurement and control, PMU, and fault recording. As an intelligent component of the circuit breaker, the intelligent terminal replaces the conventional relay logic circuit through programming, converting GOOSE control commands into circuit breaker operation commands, measuring circuit breaker status variables and non-electrical quantities, and possessing self-testing functions. To ensure reliable operation of the secondary equipment in the intelligent station, merging units and intelligent terminals are generally arranged independently by bay and configured in a dual manner according to the secondary equipment design. The sampled values ​​of the dual protection systems are taken from independent merging units, and the dual-configuration merging units correspond one-to-one with the two independent secondary sampling systems of the electronic instrument transformers. The tripping circuits of the dual protection systems correspond to independent intelligent terminals, and the dual-configuration intelligent terminals correspond to the two tripping coils of the primary circuit breaker.

[0003] With the development of smart substation construction, in order to reduce the number of devices and substation land use, integrated units and intelligent terminals have emerged, such as the 110kV integrated smart terminal unit, which meets the requirements of 110kV bay three-phase signal acquisition and circuit breaker three-phase opening and closing. The integrated smart terminal unit laid the technical foundation for the development of acquisition and execution unit equipment; however, due to the larger number of phase-separated signals and nodes in 220kV substations, the integrated smart terminal unit has not been applied. In terms of smart substation testing technology, the development and application of smart substation relay protection testing technology based on DL / T 860 and related testing equipment are of significant practical importance for improving relay protection testing levels, preventing malfunctions of relay protection and safety automatic devices, and ensuring the safe operation of the power grid.

[0004] With technological advancements and practical application needs, and to reduce the number of secondary equipment and interfaces in substations while further improving the functional integration of process-level products, a merging unit intelligent terminal integration device has been developed for use in substations at voltage levels of 110kV and below. In intelligent substation engineering applications, process-level equipment merging units and intelligent terminals at voltage levels of 220kV and above are configured independently, resulting in a large number of devices and a significant number of switches used for network communication. This leads to substantial upfront investment and heavy maintenance workload. Therefore, an optimized design for process-level equipment has been developed, proposing an application acquisition and execution unit to meet the application needs of various secondary specialties.

[0005] However, no relevant research has been conducted to address the new testing requirements of the safe and reliable new generation of substation secondary systems. The safe and reliable new generation of substation acquisition and execution units are developed based on domestically produced chips, and their various functions, performance, anti-interference capabilities, and reliability all need to be fully evaluated and verified. Existing testing methods and means face significant applicability challenges in the face of the new characteristics, new technologies, and new architectures of the safe and reliable new generation of substation secondary systems. There is a lack of a unified and efficient testing scheme to guide laboratory testing and substation on-site acceptance and commissioning. Summary of the Invention

[0006] To address the above problems, this invention proposes a method for testing the functionality and performance of a data acquisition execution unit based on a synchronization method, comprising:

[0007] Based on an external clock source, the test acquisition and execution unit under test and the test system that performs the test on the test acquisition and execution unit under test are synchronized in time;

[0008] The analog signal source of the control test system starts synchronously every second, using the 0 value of voltage and current as the initial analog quantity, and sends out analog quantities for a preset time. It controls the acquisition and execution unit under test to sample the analog quantity at equal intervals according to the preset sampling rate to obtain digital quantity sample values, and sends the digital quantity sample values ​​to the test system. It also identifies the frame number of each sampling point and flips the frame number at the start of the second synchronization to 0.

[0009] The test system is controlled to internally sample the analog signal emitted by the analog signal source every second to obtain the output analog signal. At the same time, it receives the digital sample value sent by the acquisition and execution unit under test, and restores the digital sample value according to the frame number starting from the frame number 0 to obtain the output digital signal.

[0010] The output analog quantity and the output digital quantity are respectively calculated by Fast Fourier Transform (FFT) to obtain the amplitude, phase and frequency of the output analog quantity and the output digital quantity. Based on the amplitude, phase and frequency, the ratio difference and phase difference of the output analog quantity and the output digital quantity are determined.

[0011] Based on the ratio difference and phase angle difference, and the error requirement table for the function and performance of the acquisition execution unit under test, the function and performance of the acquisition execution unit under test are determined.

[0012] Optional, the preset time is not less than 1 minute.

[0013] Optionally, the preset sampling rate is not less than 4kHz.

[0014] Optionally, the sampled value can be in SV message format.

[0015] Optionally, after the test system obtains the output analog quantity and the output digital quantity, it controls the test system to cache the output analog quantity and the output digital quantity. After caching the output analog quantity and the output digital quantity with a preset number of sampling points, it performs Fast Fourier Transform (FFT) calculation on the output analog quantity and the output digital quantity respectively.

[0016] Optionally, the preset number of sampling points is 60-2048.

[0017] Optionally, the output analog quantity and the output digital quantity are respectively subjected to Fast Fourier Transform (FFT) calculation, including:

[0018] The output analog quantity and the output digital quantity are respectively decomposed into two sub-signals, and the two sub-signals are summed to obtain two summation terms;

[0019] Use the two summed terms as a DFT of a preset length;

[0020] Perform a butterfly operation on the DFT.

[0021] Optionally, the function and performance of the acquisition execution unit under test are determined, the difference in comparison values ​​and the phase angle difference are compared with the error requirement table of the function and performance of the acquisition execution unit under test, and the comparison results are obtained. Based on the comparison results, the function and performance of the acquisition execution unit under test are determined. The function and performance include at least one of the following: the sampling synchronization of the interval board and the bus board of the acquisition execution unit under test, the sampling accuracy of the board of the acquisition execution unit under test, and the independence of the interval board and the bus board of the acquisition execution unit under test.

[0022] Optionally, the ratio difference and phase angle difference include: the ratio difference of the protection voltage, the measurement voltage, the protection current and the measurement current, and the phase angle difference of the protection voltage, the measurement voltage, the protection current and the measurement current, respectively.

[0023] This invention also proposes a system for testing the function and performance of a data acquisition and execution unit based on a synchronization method, comprising:

[0024] The time synchronization module is used to synchronize the time of the test acquisition and execution unit and the test system that tests the test acquisition and execution unit based on an external clock source;

[0025] Test module,

[0026] The analog signal source used to control the test system starts every second, with the voltage and current values ​​of 0 as the initial analog quantity, and sends out analog quantities for a preset time to control the acquisition and execution unit under test to sample the analog quantity at equal intervals according to the preset sampling rate to obtain digital quantity sample values, and sends the digital quantity sample values ​​to the test system, and identifies the frame number of each sampling point, and flips the frame number at the start of every second synchronization to 0.

[0027] The test system is controlled to internally sample the analog signal emitted by the analog signal source every second to obtain the output analog signal. At the same time, it receives the digital sample value sent by the acquisition and execution unit under test, and restores the digital sample value according to the frame number starting from the frame number 0 to obtain the output digital signal.

[0028] The output analog quantity and the output digital quantity are respectively calculated by Fast Fourier Transform (FFT) to obtain the amplitude, phase and frequency of the output analog quantity and the output digital quantity. Based on the amplitude, phase and frequency, the ratio difference and phase difference of the output analog quantity and the output digital quantity are determined.

[0029] Based on the ratio difference and phase angle difference, and the error requirement table for the function and performance of the acquisition execution unit under test, the function and performance of the acquisition execution unit under test are determined.

[0030] Optional, the preset time is not less than 1 minute.

[0031] Optionally, the preset sampling rate is not less than 4kHz.

[0032] Optionally, the sampled value can be in SV message format.

[0033] Optionally, the test system is also used to control the test system to cache the output analog quantity and output digital quantity after obtaining the output analog quantity and output digital quantity. After caching the output analog quantity and output digital quantity with a preset number of sampling points, the test system performs Fast Fourier Transform (FFT) calculation on the output analog quantity and output digital quantity respectively.

[0034] Optionally, the preset number of sampling points is 60-2048.

[0035] Optionally, the test module performs Fast Fourier Transform (FFT) calculations on the output analog quantity and the output digital quantity respectively, including:

[0036] The output analog quantity and the output digital quantity are respectively decomposed into two sub-signals, and the two sub-signals are summed to obtain two summation terms;

[0037] Use the two summed terms as a DFT of a preset length;

[0038] Perform a butterfly operation on the DFT.

[0039] Optionally, the function and performance of the acquisition and execution unit under test are determined, and the ratio difference and phase angle difference are compared with the error requirement table of the function and performance of the acquisition and execution unit under test to obtain the comparison results. Based on the comparison results, the function and performance of the acquisition and execution unit under test are determined. The function and performance include at least one of the following: the sampling synchronization of the interval board and bus board of the acquisition and execution unit under test, the sampling accuracy of the board of the acquisition and execution unit under test, and the independence of the interval board and bus board of the acquisition and execution unit under test. Optionally, the ratio difference and phase angle difference respectively include: the ratio difference of the protection voltage, the measurement voltage, the protection current, and the measurement current, and the phase angle difference of the protection voltage, the measurement voltage, the protection current, and the measurement current.

[0040] In another aspect, the present invention also provides a computing device, comprising: one or more processors;

[0041] A processor is used to execute one or more programs;

[0042] When the one or more programs are executed by the one or more processors, the method described above is implemented.

[0043] In another aspect, the present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed, implements the method described above.

[0044] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0045] This invention provides a method for testing the function and performance of a data acquisition and execution unit (TAU) based on a synchronization method, comprising: synchronizing the TAU and the test system based on an external clock source; controlling the analog signal source of the test system to emit analog signals for a preset time at the start of each second of synchronization, using zero values ​​of voltage and current as initial analog quantities; controlling the TAU to sample the analog quantities at equal intervals according to a preset sampling rate to obtain digital sample values; sending the digital sample values ​​to the test system; identifying the frame number for each sampling point; and flipping the frame number at the start of each second of synchronization to 0; and controlling the test system to synchronize the analog signal source... The system internally samples the analog signals emitted every second to obtain the output analog signal. Simultaneously, it receives digital sample values ​​sent by the acquisition execution unit under test (ADT). Starting from frame number 0, the digital sample values ​​are restored according to frame number to obtain the output digital signal. Fast Fourier Transform (FFT) calculations are performed on both the output analog and output digital signals to obtain their amplitude, phase, and frequency. Based on these amplitude, phase, and frequency, the ratio difference and phase angle difference between the output analog and output digital signals are determined. According to the ratio difference and phase angle difference, and the error requirement table for the ADT's function and performance, the function and performance of the ADT are determined. The testing method of this invention tests the acquisition and execution unit using a testing system and a clock source. This method can meet the requirements for both on-site and laboratory testing of the acquisition and execution unit. By testing the performance and functions of the acquisition and execution unit, defects and potential problems in the unit can be identified in advance. This can guide improvements in product quality, ensure the reliability of the functionality, performance, and information interaction of the acquisition and execution unit in the new generation of substations, and simultaneously promote the optimization and upgrading of on-site maintenance and testing equipment. It also improves the efficiency of on-site commissioning and acceptance, enhances the safety level of secondary system construction and operation, provides solid technical support for the reliable operation of the acquisition and execution unit in the new generation of safe and reliable substations, and promotes the construction of demonstration projects for safe and reliable new generation substation secondary systems and the comprehensive application of the technological achievements. Attached Figure Description

[0046] Figure 1 This is a flowchart of the method of the present invention;

[0047] Figure 2 This is a schematic diagram of the signal transmission of the test system, acquisition and execution unit, and clock source in an embodiment of the method of the present invention;

[0048] Figure 3 This is a schematic diagram of the waveforms of analog and digital quantities sampled by the test system in an embodiment of the method of the present invention;

[0049] Figure 4This is a schematic diagram of the sampling synchronization test of the acquisition execution unit in an embodiment of the method of the present invention;

[0050] Figure 5 This is a schematic diagram illustrating the accuracy test of the data acquisition execution unit in an embodiment of the method of the present invention;

[0051] Figure 6 This is a schematic diagram illustrating the test system performing tests in an embodiment of the method of the present invention;

[0052] Figure 7 This is a schematic diagram of the software architecture of the test system in an embodiment of the method of the present invention;

[0053] Figure 8 This is a schematic diagram illustrating the testing process principle of the testing system in an embodiment of the method of the present invention;

[0054] Figure 9 This is a structural diagram of the system of the present invention. Detailed Implementation

[0055] Exemplary embodiments of the invention will now be described with reference to the accompanying drawings. However, the invention may be embodied in many different forms and is not limited to the embodiments described herein. These embodiments are provided to fully and completely disclose the invention and to fully convey its scope to those skilled in the art. The terminology used in the exemplary embodiments illustrated in the drawings is not intended to limit the invention. In the drawings, the same units / elements are referred to by the same reference numerals.

[0056] Unless otherwise stated, the terms used herein (including technical terms) have their common meaning as understood by one of ordinary skill in the art. Furthermore, it is understood that terms defined in commonly used dictionaries should be understood to have a meaning consistent with the context of their relevant field, and not to be interpreted as having an idealized or overly formal meaning.

[0057] Example 1:

[0058] This invention proposes a method for testing the functionality and performance of a data acquisition execution unit based on a synchronization method, such as... Figure 1 As shown, it includes:

[0059] Step 1: Based on an external clock source, synchronize the time of the acquisition and execution unit under test and the test system that tests the acquisition and execution unit under test;

[0060] Step 21: Control the analog signal source of the test system to start synchronizing every second, using the 0 value of voltage and current as the initial analog quantity, and send out the analog quantity for a preset time. Control the acquisition and execution unit under test to sample the analog quantity at equal intervals according to the preset sampling rate to obtain the digital quantity sample value, and send the digital quantity sample value to the test system. Identify the frame number for each sampling point, and flip the frame number at the start of synchronizing every second to 0.

[0061] Step 22: Control the test system to internally sample the analog quantity emitted by the analog signal source every second to obtain the output analog quantity, and at the same time receive the digital quantity sampled value sent by the acquisition execution unit under test, and restore the digital quantity sampled value according to the frame number starting from the frame number 0 to obtain the output digital quantity.

[0062] Step 23: Perform Fast Fourier Transform (FFT) calculations on the output analog quantity and the output digital quantity respectively to obtain the amplitude, phase and frequency of the output analog quantity and the output digital quantity, and determine the ratio difference and phase difference of the output analog quantity and the output digital quantity based on the amplitude, phase and frequency;

[0063] Step 24: Based on the ratio difference and phase angle difference, and the error requirement table for the function and performance of the acquisition execution unit under test, determine the function and performance of the acquisition execution unit under test.

[0064] The preset time is no less than 1 minute.

[0065] The preset sampling rate is no less than 4kHz.

[0066] The sampled values ​​are in SV message format.

[0067] In this process, after the test system obtains the output analog quantity and the output digital quantity, it controls the test system to cache the output analog quantity and the output digital quantity. After caching the output analog quantity and the output digital quantity with a preset number of sampling points, it performs Fast Fourier Transform (FFT) calculation on the output analog quantity and the output digital quantity respectively.

[0068] The preset number of sampling points is 60-2048.

[0069] Specifically, the Fast Fourier Transform (FFT) calculation is performed on both the output analog quantity and the output digital quantity, including:

[0070] The output analog quantity and the output digital quantity are respectively decomposed into two sub-signals, and the two sub-signals are summed to obtain two summation terms;

[0071] Use the two summed terms as a DFT of a preset length;

[0072] Perform a butterfly operation on the DFT.

[0073] The process involves determining the function and performance of the data acquisition and execution unit under test (DUT), comparing the ratio difference and phase angle difference with the error requirements table for the function and performance of the DUT, obtaining the comparison results, and determining the function and performance of the DUT based on the comparison results. The function and performance include at least one of the following: the sampling synchronization of the DUT's interval boards and busbar boards, the sampling accuracy of the DUT boards, and the independence of the DUT's interval boards and busbar boards. The ratio difference and phase angle difference respectively include: the ratio difference between the protection voltage, the measurement voltage, the protection current, and the measurement current, and the phase angle difference between the protection voltage, the measurement voltage, the protection current, and the measurement current.

[0074] The present invention will be further described below with reference to embodiments:

[0075] The testing method of the present invention includes:

[0076] Establish a synchronous testing system, such as Figure 2 As shown, an external clock source is used to synchronize the acquisition execution unit and the test system. The test system integrates an analog signal source, which sends 0 values ​​for analog voltage and current at the start of synchronization every second. The acquisition execution unit samples at equal intervals according to the sampling rate (e.g., 4000Hz) and identifies each sampling point with a frame number. At the start of synchronization every second, the frame number is flipped to 0. That is, at the beginning of each second, the acquisition execution unit samples and sends the sampled values ​​at intervals (1 / 4000s).

[0077] The test system begins internal sampling of the output analog signal every second, while simultaneously receiving sampled values ​​(digital signals) from the acquisition and execution unit. These are then reconstructed starting from sequence number 0 according to frame number, meaning every 80 points constitute one cycle. The message points for the analog and digital signals are in one-to-one correspondence. After continuously sampling 2048 points, FFT (Fast Fourier Transform) calculations are performed on each point to obtain the amplitude, phase, and frequency of the output analog and digital signals. Finally, the ratio difference and phase angle difference are calculated.

[0078] The process of converting time-domain signals (analog and digital quantities acquired by the test system) into frequency-domain signals (output analog and signal quantities) includes the following steps:

[0079] Step 1: Decompose the signal x[n] into two sub-signals;

[0080] Even-numbered sample point signal: x[2n];

[0081] For an odd-numbered sample signal: x[2n+1]; N=0,1,2,…,(N / 2-1), then:

[0082]

[0083] Step 2: Interpret the two summation terms as two DFTs of length N / 2;

[0084]

[0085] in:

[0086]

[0087] Therefore:

[0088]

[0089] The DFT of the even-numbered sample point signal is as follows:

[0090]

[0091] DFT of odd-sample signal:

[0092]

[0093] Step 3: The specific calculation process of FFT (visualized through a butterfly diagram);

[0094] because It is periodic for both k and n: Therefore:

[0095]

[0096]

[0097] After the butterfly operation described above, N complex numbers are obtained. Each complex number contains information about a specific frequency. Based on these N complex numbers, the frequencies obtained by splitting the original signal and their amplitude values ​​can be determined. By obtaining the real part sequence and the imaginary part sequence, the maximum value of the frequency domain array modulus is found. Since the main lobe must be adjacent to the spectral line with the largest modulus, the main lobe, i.e., the fundamental frequency, is thus found.

[0098] Step 4: Amplitude Calculation

[0099] First, calculate the modulus of all N complex numbers. Then, based on the modulus, extract the signal strength corresponding to 0Hz, i.e., the DC component. The amplitude of the DC component is MAG0 = current value / N. Similarly, the amplitude of other components is MAGK = current value / (N / 2).

[0100] Step 5: Angle Calculation:

[0101] The starting angle is calculated from the real and imaginary parts of N complex numbers.

[0102] The tested acquisition and execution unit (AMU) and the test system sample at equal intervals according to a 4kHz sampling rate. When the second pulse of the time synchronization signal arrives, the sampling sequence number SampCnt of the AMU's SV message flips to 0, and the SV message sampling data with sampling sequence number 0 corresponds to the analog value at the arrival of the second pulse; the test system also samples the analog value at the arrival of the second pulse. This sampled value is synchronized with the SV message sampling value with sampling sequence number 0 of the AMU, and the correspondence of other sampled values ​​follows the same pattern. Figure 3 As shown.

[0103] The amplitude and phase of the sampled data of the analog quantity output by the test system and the digital quantity output by the acquisition and execution unit are calculated by FFT. For example, the amplitude of the analog quantity is A1 and the phase is θ1, and the amplitude of the digital quantity is A2 and the phase is θ2. The phase and angle difference are in units of ', and the amplitude is in units of A or V. The calculation formulas for the ratio difference k and the angle difference Δθ are shown in formula (9) and formula (10).

[0104]

[0105] Δθ=θ2-θ1 (10)

[0106] The testing method for the sampling synchronization of the acquisition execution unit interval board and the bus board includes the following steps:

[0107] Step 1, according to Figure 4 The sampling synchronization accuracy test system is wired. The test system simultaneously outputs the rated voltage analog quantity to the bus board, outputs the rated current analog quantity to the bay board, and receives the SV message output by the acquisition and execution unit.

[0108] Step 2: During the synchronization test, the test system starts sampling from the SV message with a frame count of 0, and takes 2048 consecutive frames of message channel data. FFT operations are performed on the voltage channel and the current channel respectively to obtain the amplitude, phase and frequency of the channel sampled values.

[0109] Step 3: Calculate the phase angle difference between the voltage and current channels, and record it continuously for 1 minute. The maximum value of the phase angle difference is the sampling synchronization error accuracy. Specifically, the synchronization error between voltage and protection current should not exceed ±10′, and the synchronization error between voltage and measuring current should not exceed ±60′.

[0110] The testing method for the sampling accuracy of the acquisition execution unit board includes the following steps:

[0111] Step 1, press Figure 5The steady-state performance testing system is wired up. The testing system outputs a rated voltage analog quantity to the bus board and a rated current analog quantity to the bay board. It collects the output values ​​of the voltage and current channels and receives the SV message output by the acquisition execution unit.

[0112] Step 2: Analyze the ratio and angle difference between analog and digital voltage quantities, and analyze the ratio and angle difference between analog and digital current quantities. Apply the current for 1 minute each time, and record the ratio and angle difference at 60 points. The largest ratio and angle difference is the sampling accuracy error.

[0113] Step 3: Sampling error requirements are shown in Table 1 below.

[0114] Table 1

[0115]

[0116]

[0117] The test method for the independence of the acquisition execution unit bay board and bus board includes the following steps:

[0118] Step 1: When the interval execution unit and the bus execution unit are cascaded, the bus acquisition board malfunction will not affect the accuracy of the sampling circuit of the interval execution unit; the test system outputs the rated current analog quantity to the acquisition execution unit, analyzes the ratio difference and angle difference between the current analog quantity and the digital quantity, applies for 1 minute each time, and records the ratio difference and angle difference at 60 points, among which the largest ratio difference and angle difference value should meet the error requirements in Table 1.

[0119] Step 2: When the busbar board of the interval execution unit is abnormal, the abnormality of the interval board will not affect the accuracy of the busbar acquisition board; the test system outputs the rated voltage analog quantity to the acquisition execution unit, analyzes the ratio difference and angle difference between the voltage analog quantity and the digital quantity, applies for 1 minute each time, and records the ratio difference and angle difference at 60 points, among which the largest ratio difference and angle difference value should meet the error requirements in Table 1.

[0120] The processing and execution process of the test system is as follows: Figure 6 As shown.

[0121] Step 1: The test system and data acquisition execution unit are synchronized with time using an external time synchronization device;

[0122] Step 2: The test system outputs an analog signal to the acquisition and execution unit, and simultaneously samples the output analog signal and the SV message output by the acquisition and execution unit;

[0123] Step 3: In the synchronous test mode, the sampling point caching unit module starts caching sampling point data from the PPS signal time. When the cached back sampled data and SV data reach 2048 sampling points, it will switch to the next module for processing.

[0124] Step 4: Based on the current test module parameters, perform FFT calculation and result calculation, and determine whether the test results meet the corresponding test error requirements.

[0125] The software architecture of the testing system includes a three-layer structure: the interface layer, the middleware service layer, and the hardware layer, such as... Figure 7 As shown.

[0126] The data in the interface layer corresponds one-to-one with the user settings data, using a specific format, and the conversion from human-computer interface input parameters to interface parameters is achieved through data binding.

[0127] The intermediate service layer acts as a relay between the interface layer and the hardware layer. It connects upward to the interface layer, receives test parameters and control parameters from the interface layer, and uploads test data and test results to the interface layer for display. It connects downward to the hardware layer, converts interface data into hardware layer data, controls the input and output of the hardware layer, receives test data or sampling point data uploaded by the hardware layer, and performs caching, calculation, and processing.

[0128] The hardware layer controls the power amplifier output, analog signal retrieval, and digital signal sampling of the hardware based on the data sent down from the intermediate service layer. This mainly includes output control logic, packet packing and unpacking, analog signal sampling, control of analog channel output data, and functions such as hardware input / output flip-through capture and uploading.

[0129] The testing process principle of the testing system, such as... Figure 8 As shown, it includes:

[0130] Step 1: Configure the time synchronization mode of the test system

[0131] Both the acquisition and execution unit and the test system use an external clock for time synchronization.

[0132] Step 2: Configure the communication settings for the SV message data output by the acquisition and execution unit.

[0133] Since the SV message transmits a single value, while the power amplifier output and result calculation are both quadratic values, it is necessary to configure the channel type and channel ratio of the SV control block channel. Configuring the virtual channel of the SV control block channel is to facilitate switching tests between multiple acquisition and execution units.

[0134] Step 3: Configure test parameters

[0135] The test parameters include the control parameters of the power amplifier output of the test system, the mapping between channels and virtual channels (for result processing), etc.

[0136] Step 4: Start the experiment, issue parameters, and start the power amplifier output and sampling.

[0137] The experiment begins. The interface sends the test parameters to the intermediate service layer, which then sends the power amplifier output control parameters to the hardware layer. The hardware layer starts the power amplifier output and simultaneously enables the sampling of the output analog quantity and the sampling of the SV message output by the acquisition execution unit.

[0138] Step 5: Process and cache sample point data

[0139] The hardware layer caches 200ms of sampling point data and sends it to the intermediate service layer in the form of data blocks. The intermediate service layer checks whether there is a sampling point with samplecnt=0 in the current data block. If not, the data block is discarded. If it exists, the sampling points are cached starting from that sampling point until 2048 are cached. When both samples have cached 2048 data points, the calculation begins.

[0140] Step 6: Calculate FFT and obtain experimental results

[0141] According to the channel mapping logic issued by the interface, FFT calculation is performed on each group to obtain the amplitude, phase and frequency of the channel. Based on the FFT calculation results and the cached sampling points, the test results of each test are calculated and uploaded to the interface layer.

[0142] Each module can be repeated N times. If the current number of trials is less than the total number of trials, the process restarts from step 5. If the current number of trials equals the total number of trials, the interface is notified to process the trial results.

[0143] Step 7: Statistical Analysis and Verification of Test Results

[0144] Based on the N test results of the module, the initial value and error, maximum value and error, minimum value and error, variation, etc. of each channel test result of the current module are statistically analyzed. Based on the accuracy level of the current channel, it is determined whether the maximum error meets the error requirements in the standard. If it does, the test is qualified.

[0145] The testing method of this invention tests the acquisition and execution unit using a testing system and a clock source. This method can meet the requirements for both on-site and laboratory testing of the acquisition and execution unit. By testing the performance and functions of the acquisition and execution unit, defects and potential problems in the unit can be identified in advance. This can guide improvements in product quality, ensure the reliability of the functionality, performance, and information interaction of the acquisition and execution unit in the new generation of substations, and simultaneously promote the optimization and upgrading of on-site maintenance and testing equipment. It also improves the efficiency of on-site commissioning and acceptance, enhances the safety level of secondary system construction and operation, provides solid technical support for the reliable operation of the acquisition and execution unit in the new generation of safe and reliable substations, and promotes the construction of demonstration projects for safe and reliable new generation substation secondary systems and the comprehensive application of the technological achievements.

[0146] Example 2:

[0147] This invention also proposes a system 200 for testing the function and performance of a data acquisition and execution unit based on a synchronous method, such as... Figure 9 As shown, it includes:

[0148] The time synchronization module 201 is used to synchronize the time of the acquisition and execution unit under test and the test system that tests the acquisition and execution unit under test based on an external clock source.

[0149] Test module 201, used for

[0150] The analog signal source of the control test system starts synchronously every second, using the 0 value of voltage and current as the initial analog quantity, and sends out analog quantities for a preset time. It controls the acquisition and execution unit under test to sample the analog quantity at equal intervals according to the preset sampling rate to obtain digital quantity sample values, and sends the digital quantity sample values ​​to the test system. It also identifies the frame number of each sampling point and flips the frame number at the start of the second synchronization to 0.

[0151] The test system is controlled to internally sample the analog signal emitted by the analog signal source every second to obtain the output analog signal. At the same time, it receives the digital sample value sent by the acquisition and execution unit under test, and restores the digital sample value according to the frame number starting from the frame number 0 to obtain the output digital signal.

[0152] The output analog quantity and the output digital quantity are respectively calculated by Fast Fourier Transform (FFT) to obtain the amplitude, phase and frequency of the output analog quantity and the output digital quantity. Based on the amplitude, phase and frequency, the ratio difference and phase difference of the output analog quantity and the output digital quantity are determined.

[0153] Based on the ratio difference and phase angle difference, and the error requirement table for the function and performance of the acquisition execution unit under test, the function and performance of the acquisition execution unit under test are determined.

[0154] The preset time is no less than 1 minute.

[0155] The preset sampling rate is no less than 4kHz.

[0156] The sampled values ​​are in SV message format.

[0157] The test system is also used to control the test system to cache the output analog quantity and output digital quantity after the test system obtains the output analog quantity and output digital quantity. After caching the output analog quantity and output digital quantity with a preset number of sampling points, the test system performs Fast Fourier Transform (FFT) calculation on the output analog quantity and output digital quantity respectively.

[0158] The preset number of sampling points is 60-2048.

[0159] The testing module performs Fast Fourier Transform (FFT) calculations on both the output analog and output digital quantities, including:

[0160] The output analog quantity and the output digital quantity are respectively decomposed into two sub-signals, and the two sub-signals are summed to obtain two summation terms;

[0161] Use the two summed terms as a DFT of a preset length;

[0162] Perform a butterfly operation on the DFT.

[0163] The process involves determining the function and performance of the data acquisition and execution unit under test (DUT), comparing the ratio difference and phase angle difference with the error requirements table for the function and performance of the DUT, obtaining the comparison results, and determining the function and performance of the DUT based on the comparison results. The function and performance include at least one of the following: the sampling synchronization of the DUT's interval boards and busbar boards, the sampling accuracy of the DUT boards, and the independence of the DUT's interval boards and busbar boards. The ratio difference and phase angle difference respectively include: the ratio difference between the protection voltage, the measurement voltage, the protection current, and the measurement current, and the phase angle difference between the protection voltage, the measurement voltage, the protection current, and the measurement current.

[0164] Example 3:

[0165] Based on the same inventive concept, this invention also provides a computer device, which includes a processor and a memory. The memory stores a computer program, which includes program instructions. The processor executes the program instructions stored in the computer storage medium. The processor may be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. It is the computing and control core of the terminal, suitable for implementing one or more instructions, specifically suitable for loading and executing one or more instructions in the computer storage medium to implement corresponding method flows or corresponding functions, thereby implementing the steps of the methods in the above embodiments.

[0166] Example 4:

[0167] Based on the same inventive concept, this invention also provides a storage medium, specifically a computer-readable storage medium (Memory), which is a memory device in a computer device used to store programs and data. It is understood that the computer-readable storage medium here can include both the built-in storage medium in the computer device and extended storage media supported by the computer device. The computer-readable storage medium provides storage space that stores the terminal's operating system. Furthermore, this storage space also stores one or more instructions suitable for loading and execution by a processor. These instructions can be one or more computer programs (including program code). It should be noted that the computer-readable storage medium here can be high-speed RAM or non-volatile memory, such as at least one disk storage device. The processor can load and execute one or more instructions stored in the computer-readable storage medium to implement the steps of the method in the above embodiments.

[0168] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of the present invention can be implemented using various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0169] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0170] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0171] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0172] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the invention.

[0173] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A method for testing the function and performance of a data acquisition execution unit based on a synchronous method, characterized in that, The method includes: Based on an external clock source, the test acquisition and execution unit under test and the test system that performs the test on the test acquisition and execution unit under test are synchronized in time; The analog signal source of the control test system starts synchronously every second, using the 0 value of voltage and current as the initial analog quantity, and sends out analog quantities for a preset time. It controls the acquisition and execution unit under test to sample the analog quantity at equal intervals according to the preset sampling rate to obtain digital quantity sample values, and sends the digital quantity sample values ​​to the test system. It also identifies the frame number of each sampling point and flips the frame number at the start of the second synchronization to 0. The test system is controlled to internally sample the analog signal emitted by the analog signal source every second to obtain the output analog signal. At the same time, it receives the digital sample value sent by the acquisition and execution unit under test, and restores the digital sample value according to the frame number starting from the frame number 0 to obtain the output digital signal. The output analog quantity and the output digital quantity are respectively calculated by Fast Fourier Transform (FFT) to obtain the amplitude, phase and frequency of the output analog quantity and the output digital quantity. Based on the amplitude, phase and frequency, the ratio difference and phase difference of the output analog quantity and the output digital quantity are determined. Based on the ratio difference and phase angle difference, and the error requirement table for the function and performance of the acquisition execution unit under test, the function and performance of the acquisition execution unit under test are determined.

2. The method according to claim 1, characterized in that, The preset time is no less than 1 minute.

3. The method according to claim 1, characterized in that, The preset sampling rate is not less than 4kHz.

4. The method according to claim 1, characterized in that, The sampled value is in SV message format.

5. The method according to claim 1, characterized in that, After obtaining the output analog quantity and the output digital quantity, the test system controls the test system to cache the output analog quantity and the output digital quantity. After caching the output analog quantity and the output digital quantity with a preset number of sampling points, the Fast Fourier Transform (FFT) is performed on the output analog quantity and the output digital quantity respectively.

6. The method according to claim 5, characterized in that, The preset number of sampling points is 60-2048.

7. The method according to claim 1, characterized in that, The step of performing Fast Fourier Transform (FFT) calculations on the output analog quantity and the output digital quantity respectively includes: The output analog quantity and the output digital quantity are respectively decomposed into two sub-signals, and the two sub-signals are summed to obtain two summation terms; The two summation terms are used as the Discrete Fourier Transform (DFT) of a preset length; Perform a butterfly operation on the DFT.

8. The method according to claim 1, characterized in that, The process involves determining the function and performance of the acquisition execution unit under test, comparing the difference in values ​​and the phase angle difference with the error requirement table for the function and performance of the acquisition execution unit under test, obtaining the comparison results, and determining the function and performance of the acquisition execution unit under test based on the comparison results. The function and performance include at least one of the following: the sampling synchronization of the interval board and bus board of the acquisition execution unit under test, the sampling accuracy of the board of the acquisition execution unit under test, and the independence of the interval board and bus board of the acquisition execution unit under test.

9. The method according to claim 1, characterized in that, The ratio difference and phase angle difference respectively include: the ratio difference of the protection voltage, the measurement voltage, the protection current and the measurement current, and the phase angle difference of the protection voltage, the measurement voltage, the protection current and the measurement current.

10. A system for testing the function and performance of a data acquisition and execution unit based on a synchronous method, characterized in that, The system includes: The time synchronization module is used to synchronize the time of the test acquisition and execution unit and the test system that tests the test acquisition and execution unit based on an external clock source; Test module, The analog signal source used to control the test system starts every second, with the voltage and current values ​​of 0 as the initial analog quantity, and sends out analog quantities for a preset time to control the acquisition and execution unit under test to sample the analog quantity at equal intervals according to the preset sampling rate to obtain digital quantity sample values, and sends the digital quantity sample values ​​to the test system, and identifies the frame number of each sampling point, and flips the frame number at the start of every second synchronization to 0. The test system is controlled to internally sample the analog signal emitted by the analog signal source every second to obtain the output analog signal. At the same time, it receives the digital sample value sent by the acquisition and execution unit under test, and restores the digital sample value according to the frame number starting from the frame number 0 to obtain the output digital signal. The output analog quantity and the output digital quantity are respectively calculated by Fast Fourier Transform (FFT) to obtain the amplitude, phase and frequency of the output analog quantity and the output digital quantity. Based on the amplitude, phase and frequency, the ratio difference and phase difference of the output analog quantity and the output digital quantity are determined. Based on the ratio difference and phase angle difference, and the error requirement table for the function and performance of the acquisition execution unit under test, the function and performance of the acquisition execution unit under test are determined.

11. The system according to claim 10, characterized in that, The preset time is no less than 1 minute.

12. The system according to claim 10, characterized in that, The preset sampling rate is not less than 4kHz.

13. The system according to claim 10, characterized in that, The sampled value is in SV message format.

14. The system according to claim 10, characterized in that, The test system is also used to control the test system to cache the output analog quantity and output digital quantity after the test system obtains the output analog quantity and output digital quantity. After caching the output analog quantity and output digital quantity with a preset number of sampling points, the test system performs Fast Fourier Transform (FFT) calculation on the output analog quantity and output digital quantity respectively.

15. The system according to claim 14, characterized in that, The preset number of sampling points is 60-2048.

16. The system according to claim 10, characterized in that, The test module performs Fast Fourier Transform (FFT) calculations on the output analog quantity and the output digital quantity, respectively, including: The output analog quantity and the output digital quantity are respectively decomposed into two sub-signals, and the two sub-signals are summed to obtain two summation terms; Use the two summed terms as a DFT of a preset length; Perform a butterfly operation on the DFT.

17. The system according to claim 10, characterized in that, The process involves determining the function and performance of the acquisition execution unit under test, comparing the difference in values ​​and the phase angle difference with the error requirement table for the function and performance of the acquisition execution unit under test, obtaining the comparison results, and determining the function and performance of the acquisition execution unit under test based on the comparison results. The function and performance include at least one of the following: the sampling synchronization of the interval board and bus board of the acquisition execution unit under test, the sampling accuracy of the board of the acquisition execution unit under test, and the independence of the interval board and bus board of the acquisition execution unit under test.

18. The system according to claim 10, characterized in that, The ratio difference and phase angle difference respectively include: the ratio difference of the protection voltage, the measurement voltage, the protection current and the measurement current, and the phase angle difference of the protection voltage, the measurement voltage, the protection current and the measurement current.

19. A computer device, characterized in that, include: One or more processors; A processor is used to execute one or more programs; When the one or more programs are executed by the one or more processors, the method described in any one of claims 1-9 is implemented.

20. A computer-readable storage medium, characterized in that, It contains a computer program, which, when executed, implements the method as described in any one of claims 1-9.

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