Semiconductor devices, display devices, and electronic devices

Abstract

A semiconductor device which stably operates with low failure due to noise, low power consumption, and small change in characteristics; a display device including the semiconductor device; and an electronic device including the display device are provided. An output terminal is connected to a power supply line, thereby reducing a change in potential of the output terminal. In addition, a gate electrode potential of a transistor which is kept on is maintained due to a capacitance of the transistor. In addition, a change in transistor characteristics is reduced by a signal line for reverse biasing.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device, a display device, and an electronic device.

[0002] This application is a divisional application of the following invention patent application:

[0003] Inventive name: Semiconductor device, display device, and electronic device; Application No. 201610550684.1; Filing date: December 28, 2006. BACKGROUND

[0004] A shift register circuit is a circuit which operates in a manner that its contents are shifted by one pulse at a time in a single stage. By using this property, a shift register is used in a circuit which converts a serial signal and a parallel signal to each other. The above-mentioned circuit which converts a serial signal to a parallel signal, or a parallel signal to a serial signal is mainly used in a network which has circuits connected to each other. The number of propagation paths for connecting circuits to each other and transmitting signals in the network is usually smaller than the amount of data to be transmitted. In this case, a parallel signal is converted to a serial signal in a transmitter circuit, and sequentially transmitted to a transmission path, and a serial signal which has been sequentially transmitted is converted to a parallel signal in a receiver circuit. Thus, a small number of propagation paths can be used to exchange signals.

[0005] A display device displays an image by controlling the luminance of each pixel in accordance with an image signal inputted from the outside. Here, because it is difficult to use a large number of propagation paths of the image signal from the outside equal to the number of pixels, the image signal must be subjected to serial-parallel conversion. Therefore, a shift register is used in a circuit which transmits an image signal to a display device and a circuit which drives a display device which receives an image signal.

[0006] A CMOS circuit which combines an n-channel transistor and a P-channel transistor is generally used in the above-mentioned shift register circuit. However, in order to form a CMOS circuit which combines an n-channel transistor and a P-channel transistor over the same substrate, it is necessary to form transistors having opposite conduction types to each other over the same substrate, so the manufacturing process inevitably becomes complicated. Therefore, this results in an increase in cost or a decrease in yield of semiconductor devices.

[0007] Therefore, a circuit in which all transistors have the same polarity (also called a unipolar circuit) has been designed. A unipolar circuit can omit some steps in the manufacturing process, such as a step of adding an impurity element. Thus, an increase in cost and a decrease in yield are suppressed.

[0008] For example, consider the case of forming a logic circuit in which all of the transistors have n-channel polarity. Such a circuit has a problem in that the voltage of an output signal attenuates compared to the voltage of an input signal when outputting a potential of a high potential power source in accordance with the threshold of an n-channel transistor. Therefore, a circuit called a bootstrap circuit is widely used so that the voltage of the output signal does not attenuate. The bootstrap circuit is realized when the gate electrode of a transistor that is capacitively coupled to an output terminal is in a floating state after a transistor connected to a high potential power source is turned on so that current begins to flow through the channel. Thus, the potential of the output terminal rises and the potential of the gate electrode of the transistor also rises accordingly so that eventually exceeds the potential of the high potential power source plus the threshold voltage of the transistor. Thus, it is possible to make the potential of the output terminal almost equal to the potential of the high potential power source.

[0009] Using the bootstrap circuit described above, it is possible to realize a semiconductor device in which the output potential does not attenuate even in the case of using unipolar transistors. In addition, a shift register circuit is formed using a bootstrap circuit (for example, reference 1: Japanese Laid-Open Patent Application No. 2002-215118 and reference 2: SID 2005, p. 1050, "An Improved Dynamic Ratio Less Shift Register Circuit Suitable for LTPS-TFT LCD Panels"). SUMMARY

[0010] Figure 37A and 37B A conventional example in reference 2 is shown (note that the reference codes and the like have been changed). In Figure 37A and 37B In the shift register circuit shown, when an input signal is input to Vin, the potential of terminal Pl rises and a transistor connected to signal line Vl turns on. Then, the transistor boots up in response to the rise in the potential of signal line Vl, so the potential of signal line Vl is sent to the next stage without lowering the potential of signal line Vl. Figure 37A A circuit diagram of the first four stages of the shift register circuit is shown to help understand the circuit arrangement, Figure 37B A portion of Figure 37A surrounded by a broken line is shown. Figure 37B A minimum unit of the circuit for forming Figure 37A the circuit shown, Figure 37B corresponds to one output terminal (OUTl to OUT4) of the circuit of Figure 37A In the specification, the structural unit of the circuit, for example, with respect to Figure 37A the circuit of Figure 37BThe structure shown is called a single-stage circuit. Here, a transistor for controlling the on / off of the connection between terminal Pl and power line Vss is turned on in response to the output of the next stage. However, because the time during which the transistor is turned on is limited to a period in which the output of the next stage has a higher potential (H level), terminal Pl and terminal OUTl are in a floating state during most of the period when a lower potential (L level) is output to terminal OUTl (also called a non-selection period). These also apply to terminal Px and terminal OUTx in the next stage. Therefore, there is a problem of malfunction due to noise generated by clock signal 1 and clock signal 2 or noise caused by electromagnetic waves from outside the circuit.

[0011] To overcome these problems, in Reference 2, the structure shown in Figure 38A and 38B is used. Note that Figure 38A is a circuit diagram of a first six-stage shift register circuit. To help understand the circuit structure, Figure 38B shows the single-stage circuit of Figure 38A surrounded by a broken line in Figure 38A . In the structure shown in Figure 38A and 38B , the period during which the transistor that resets terminal Pl and terminal Px to the L level in the subsequent stage is turned on occupies most of the non-selection period. With this structure, in the non-selection period, it is possible to suppress the change in the potential of terminal Pl and terminal Px in the subsequent stage to some extent.

[0012] However, in the structure shown in Figure 38A and 38B , in the non-selection period, terminal OUTl and terminal OUTFx in the next stage are in a floating state. Therefore, there is a problem of malfunction of terminal OUT due to noise generated by clock signal 1 and clock signal 2 or noise caused by electromagnetic waves from outside the circuit. In addition, because a capacitive element is provided between the electrode that connects the gate electrode of the transistor for resetting terminal Px in each stage and the input terminal Vin in the structure shown in Figure 38A and 38B , the load for driving the input terminal Vin is heavy. Therefore, there are also problems of distortion of the waveform of the signal and large power consumption. Because the transistor for resetting terminal Px in each stage is turned on during most of the non-selection period, there is a problem of the voltage being heavily biased on the gate electrode and the characteristics easily changing.

[0013] In view of the above problems, it is an object of the present application to provide a semiconductor device that has low malfunction due to noise, low power consumption, and small change in characteristics and operates stably; a display device that includes the semiconductor device; and an electronic device that includes the display device.

[0014] In the present application, the term "display panel" includes a liquid crystal display panel configured using a liquid crystal element, and a display panel having a light emitting element typified by an electroluminescence (EL) element. In addition, the display device includes a display device having a display panel and a peripheral circuit for driving the display panel.

[0015] The semiconductor device according to the mode of the present application includes an input terminal, an output terminal, a first terminal, a second terminal, a third terminal, and a fourth terminal; a first transistor for transmitting a potential of the first terminal to the output terminal; a rectifier element for turning on the first transistor in accordance with a potential of the input terminal; a second transistor for fixing a potential of the output terminal by conducting between the output terminal and the second terminal in accordance with a potential of the fourth terminal; and a third transistor for fixing a potential of the third terminal by conducting between the third terminal and the second terminal in accordance with a potential of the fourth terminal.

[0016] The semiconductor device according to another mode of the present application includes an input terminal, an output terminal, a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal; a first transistor for transmitting a potential of the first terminal to the output terminal; a rectifier element for turning on the first transistor in accordance with a potential of the input terminal; a second transistor for fixing a potential of the output terminal by conducting between the output terminal and the second terminal in accordance with a potential of the fifth terminal; and a third transistor for fixing a potential of the third terminal by conducting between the third terminal and the second terminal in accordance with a potential of the fourth terminal; and a circuit for inverting the potential of the third terminal and outputting the potential to the fifth terminal.

[0017] The semiconductor device according to another mode of the present application includes an input terminal, an output terminal, a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, and a sixth terminal; a first transistor for transmitting a potential of the first terminal to the output terminal; a first rectifier element for turning on the first transistor in accordance with a potential of the input terminal; a second transistor for fixing a potential of the output terminal by conducting between the output terminal and the second terminal in accordance with a potential of the fourth terminal; and a third transistor for fixing a potential of the third terminal by conducting between the third terminal and the second terminal in accordance with a potential of the fourth terminal; a second rectifier element for raising a potential of the fifth terminal in accordance with a potential of the output terminal; and a fourth transistor for connecting a low potential of the sixth terminal by conducting between the second terminal and the third terminal.

[0018] A semiconductor device according to another mode of the present application includes an input terminal, an output terminal, a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, a sixth terminal, and a seventh terminal; a first transistor for sending a potential of the first terminal to the output terminal; a first rectifying element for turning on the first transistor according to a potential of the input terminal; a second transistor for fixing a potential of the output terminal by conducting between the output terminal and the second terminal according to a potential of the seventh terminal; and a third transistor for fixing a potential of the third terminal by conducting between the third terminal and the second terminal according to a potential of the fourth terminal; a second rectifying element for raising a potential of the fifth terminal according to a potential of the output terminal; a fourth transistor for connecting a low potential of the sixth terminal by conducting between the second terminal and the third terminal; and a circuit for inverting the potential of the third terminal and outputting the potential to the seventh terminal.

[0019] A semiconductor device according to another mode of the present application includes an input terminal, an output terminal, a first terminal, a second terminal, a third terminal, a fourth terminal, a rectifying element, a first transistor, a second transistor, and a third transistor. One electrode of the rectifying element is electrically connected to the input terminal, and the other electrode of the rectifying element is electrically connected to the third terminal; a gate electrode of the first transistor is electrically connected to the third terminal, one of a source electrode and a drain electrode of the first transistor is electrically connected to the first terminal, and the other of the source electrode and the drain electrode of the first transistor is electrically connected to the output terminal; a gate electrode of the second transistor is electrically connected to the fourth terminal, one of a source electrode and a drain electrode of the second transistor is electrically connected to the second terminal, and the other of the source electrode and the drain electrode of the second transistor is electrically connected to the output terminal; and a gate electrode of the third transistor is electrically connected to the fourth terminal, one of a source electrode and a drain electrode of the third transistor is electrically connected to the second terminal, and the other of the source electrode and the drain electrode of the third transistor is electrically connected to the third terminal.

[0020] A semiconductor device according to another mode of the present application includes an input terminal, an output terminal, a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, a rectifying element, a first transistor, a second transistor, a third transistor, and a potential inverting circuit. One electrode of the rectifying element is electrically connected to the input terminal, and the other electrode of the rectifying element is electrically connected to the third terminal; a gate electrode of the first transistor is electrically connected to the third terminal, one of a source electrode and a drain electrode of the first transistor is electrically connected to the first terminal, and the other of the source electrode and the drain electrode of the first transistor is electrically connected to the output terminal; a gate electrode of the second transistor is electrically connected to the fifth terminal, one of a source electrode and a drain electrode of the second transistor is electrically connected to the second terminal, and the other of the source electrode and the drain electrode of the second transistor is electrically connected to the output terminal; a gate electrode of the third transistor is electrically connected to the fourth terminal, one of a source electrode and a drain electrode of the third transistor is electrically connected to the second terminal, and the other of the source electrode and the drain electrode of the third transistor is electrically connected to the third terminal; and one electrode of the potential inverting circuit is electrically connected to the third terminal, and the other electrode of the potential inverting circuit is electrically connected to the fifth terminal.

[0021] A semiconductor device according to another mode of the present application includes an input terminal, an output terminal, a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, a sixth terminal, a first rectifying element, a second rectifying element, a first transistor, a second transistor, a third transistor, and a fourth transistor. One electrode of the first rectifying element is electrically connected to the input terminal, and the other electrode of the first rectifying element is electrically connected to the third terminal; a gate electrode of the first transistor is electrically connected to the third terminal, one of a source electrode and a drain electrode of the first transistor is electrically connected to the first terminal, and the other of the source electrode and the drain electrode of the first transistor is electrically connected to the output terminal; a gate electrode of the second transistor is electrically connected to the fourth terminal, one of a source electrode and a drain electrode of the second transistor is electrically connected to the second terminal, and the other of the source electrode and the drain electrode of the second transistor is electrically connected to the output terminal; a gate electrode of the third transistor is electrically connected to the fourth terminal, one of a source electrode and a drain electrode of the third transistor is electrically connected to the second terminal, and the other of the source electrode and the drain electrode of the third transistor is electrically connected to the third terminal; one electrode of the second rectifying element is electrically connected to the output terminal, and the other electrode of the second rectifying element is electrically connected to the fifth terminal; a gate electrode of the fourth transistor is electrically connected to the fourth terminal, one of a source electrode and a drain electrode of the fourth transistor is electrically connected to the second terminal, and the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the sixth terminal.

[0022] A semiconductor device according to another mode of the present application includes an input terminal, an output terminal, a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, a sixth terminal, a seventh terminal, a first rectifying element, a second rectifying element, a first transistor, a second transistor, a third transistor, a fourth transistor, and a potential reversing circuit. One electrode of the first rectifying element is electrically connected to the input terminal, and the other electrode of the first rectifying element is electrically connected to the third terminal; a gate electrode of the first transistor is electrically connected to the third terminal, one of a source electrode and a drain electrode of the first transistor is electrically connected to the first terminal, and the other of the source electrode and the drain electrode of the first transistor is electrically connected to the output terminal; a gate electrode of the second transistor is electrically connected to the seventh terminal, one of a source electrode and a drain electrode of the second transistor is electrically connected to the second terminal, and the other of the source electrode and the drain electrode of the second transistor is electrically connected to the output terminal; a gate electrode of the third transistor is electrically connected to the fourth terminal, one of a source electrode and a drain electrode of the third transistor is electrically connected to the second terminal, and the other of the source electrode and the drain electrode of the third transistor is electrically connected to the third terminal; one electrode of the second rectifying element is electrically connected to the output terminal, and the other electrode of the second rectifying element is electrically connected to the fifth terminal; a gate electrode of the fourth transistor is electrically connected to the fourth terminal, one of a source electrode and a drain electrode of the fourth transistor is electrically connected to the second terminal, and the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the sixth terminal; and one electrode of the potential reversing circuit is electrically connected to the third terminal, and the other electrode of the potential reversing circuit is electrically connected to the seventh terminal.

[0023] With the structure of the present application as described above, a shift register circuit that stably operates with little noise-induced malfunction can be provided.

[0024] Further, in the semiconductor device according to the present application, the rectifying element can be a diode-connected transistor. In this case, the number of types of elements fabricated on the substrate can be reduced; thus, the manufacturing process is simplified.

[0025] Further, the semiconductor device according to the present application has a signal line capable of turning on the third transistor and the second transistor. In this case, a shift register circuit whose operation can be stopped at an arbitrary timing and can be initialized can be provided.

[0026] Further, the semiconductor device according to the present application has a signal line capable of reverse-biasing the third transistor and the second transistor. In this case, a shift register circuit that stably operates with less variation in characteristics can be provided.

[0027] Further, in the semiconductor device according to the present application, the signals input to the first clock signal line and the second clock signal line each have a duty cycle of less than 50%, and more preferably the difference between the middle of the period in which the signal input to one of them is at the low level and the middle of the period in which the signal input to the other of them is at the high level can be within a range of 10% of the time period of the clock signal. Thus, the interval between the output signals output from the respective output terminals and a highly improved shift register circuit can be provided.

[0028] Further, in the semiconductor device according to the present application, it is preferable that the average of the area of the gate electrode in the third transistor and the area of the gate electrode in the second transistor be larger than the gate electrode in the first transistor. With this structure, the potential of the output terminal can be stably fixed, thereby providing a shift register circuit having less noise-induced malfunction.

[0029] Further, in the semiconductor device according to the present application, the power supply line, the first clock signal line, and the second clock signal line can be arranged on opposite sides of the output terminal with respect to the first transistor, the third transistor, and the second transistor. With this structure, the potential of the output terminal can be stably fixed, thereby providing a shift register circuit having less noise-induced malfunction.

[0030] Further, the semiconductor device of the present application includes a first wiring layer, a second wiring layer, a third wiring layer, an insulating film, and an interlayer insulating film. The insulating film is formed between the first wiring layer and the second wiring layer. The interlayer insulating film is formed between the second wiring layer and the third wiring layer. The interlayer insulating film is thicker than the insulating film. The electrode electrically connected to the first electrode is formed at least by the second wiring layer. The electrode electrically connected to the output terminal is formed at least by the first wiring layer and the third wiring layer. In a region where the electrode electrically connected to the output terminal and the electrode electrically connected to the first terminal cross, the electrode electrically connected to the output terminal can be formed by the third wiring layer. With this structure, the potential of the output terminal can be stably fixed, thereby providing a shift register circuit having less noise-induced malfunction.

[0031] Further, in the semiconductor device according to the present application, the shift register circuit is formed over a substrate provided with a pixel region. With this structure, the production cost of the display panel can be reduced.

[0032] Further, in another mode of the semiconductor device according to the present application, the shift register circuit is provided as an IC over a substrate provided with a pixel region, and is connected to a wiring on the substrate through COG (Chip On Glass). Thus, a low-power display panel having less variation in characteristics can be provided.

[0033] Further, in another mode of the semiconductor device according to the present application, a shift register circuit is provided as an IC over a connection wiring substrate connected to a substrate provided with a pixel region, and is connected to a wiring on the connection wiring substrate by TAB (tape automated bonding). Thus, a low power consumption display panel with high reliability and small variation in characteristics can be provided.

[0034] A semiconductor device according to another mode of the present application includes a first electrode, a second electrode, a third electrode, a transistor, and a rectifier element. A gate electrode of the transistor is electrically connected to the second electrode, one of a source electrode and a drain electrode of the transistor is electrically connected to the first electrode, and the other of the source electrode and the drain electrode of the transistor is electrically connected to the third electrode; one electrode of the rectifier element is electrically connected to the third electrode, and the other electrode of the rectifier element is electrically connected to the second electrode. Thus, a display panel which operates stably with small variation in characteristics can be provided.

[0035] A semiconductor device according to another mode of the present application includes a first electrode, a second electrode, a third electrode, a fourth electrode, a first transistor, and a second transistor. A gate electrode of the first transistor is electrically connected to the second electrode, one of a source electrode and a drain electrode of the first transistor is electrically connected to the first electrode, and the other of the source electrode and the drain electrode of the first transistor is electrically connected to the third electrode; a gate electrode of the second transistor is electrically connected to the fourth electrode, one of a source electrode and a drain electrode of the second transistor is electrically connected to the second electrode, and the other of the source electrode and the drain electrode of the second transistor is electrically connected to the third electrode. Thus, a display panel which operates stably with small variation in characteristics can be provided.

[0036] Further, a display device according to the mode of the present application includes the above semiconductor device, an external drive circuit, and a connection wiring substrate; the display panel and the external drive circuit are connected to each other with one connection wiring substrate. Thus, a display device with high reliability and fewer connection points can be provided.

[0037] Further, a display device according to another mode of the present application includes the above semiconductor device, an external drive circuit, and a plurality of connection wiring substrates; the display panel and the external drive circuit are connected to each other with two or more connection wiring substrates and a plurality of individual drivers (a data line driver and a scan line driver). Thus, a large display panel with high reliability can be provided even though the drivers do not need to have excellent performance.

[0038] Further, an electronic device according to the present application uses the display device as a display portion.

[0039] Note that the switch in the specification can be an electronic switch or a mechanical switch. Any type of switch can be used as long as the flow of current can be controlled. A transistor, a diode (PN diode, PIN diode, Schottky diode, diode-connected transistor, or the like), or a logic circuit in which the above diodes are combined can be used. Thus, when a transistor is used as a switch, the transistor functions only as a switch; therefore, there is no particular limitation on the polarity (conductivity type) of the transistor. However, when a low off-state current is desired, a transistor of a polarity with a small off-state current is preferably used. As a transistor with a small off-state current, a transistor with an LDD region, a transistor with a multi-gate structure, or the like can be used. Further, when the potential of the source terminal of the transistor used as a switch is close to a low-potential power supply (Vss, GND, or 0 V), an n-channel transistor is preferably used, whereas when the transistor operates in a state where the potential of the source terminal is close to a potential of a high-potential power supply (Vdd or the like), a P-channel transistor is preferably used. This facilitates easy operation of the transistor as a switch, because the absolute value of the gate-source voltage of the transistor can be increased. Note that a CMOS switch can also be applied by using an n-channel transistor and a P-channel transistor.

[0040] The display element is not particularly limited and can be, for example, a display medium whose contrast is changed by electromagnetic force, such as an EL element (organic EL element, inorganic EL element, or EL element using an organic material and an inorganic material), an electron emission element, a liquid crystal element, electronic ink, a grating light valve (GLV), a plasma display panel (PDP), a digital micromirror device (DMD), a piezoelectric ceramic display, a carbon nanotube, or the like. Note that as a display device using an EL element, an EL display can be used; as a display device using an electron emission element, a field emission display (FED), an SED flat panel display (surface-conduction electron-emitter display), or the like can be used; as a display device using a liquid crystal element, a liquid crystal display can be used; as a display device using electronic ink, electronic paper can be used.

[0041] There is no particular limitation on the kind of transistor used in the present application. The transistor suitable for the present application includes a thin film transistor (TFT) using a non-single-crystal semiconductor thin film represented by amorphous silicon and polycrystalline silicon, a MOS transistor formed using a semiconductor substrate or an SOI substrate, a junction transistor, a bipolar transistor, a transistor using an organic semiconductor or a carbon nanotube, and other kinds of transistors. There is no particular limitation on the kind of substrate over which a transistor is provided, and a transistor can be provided over a single-crystal substrate, an SOI substrate, a glass substrate, or the like.

[0042] In the present application, "connection" means "electrical connection". Therefore, in the structure disclosed in the present application, another element (e.g., another element (e.g., a transistor, a diode, a resistor, or a capacitor), a switch, or the like) that makes electrical connection possible can be provided between given connection portions in addition to the intended connection.

[0043] The structure of the transistor is not particularly limited. For example, a multi-gate structure in which the number of gate electrodes is two or more, a structure in which a gate electrode is disposed above and below a channel, a structure in which a gate electrode is disposed above a channel, a structure in which a gate electrode is disposed below a channel, a staggered structure, or an inverted staggered structure can be used. In addition, a channel region can be divided into a plurality of regions, which can be connected in parallel or in series; a source electrode or a drain electrode can overlap with a channel (or a part of a channel); or an LDD region can be provided.

[0044] Note that in the specification, a semiconductor device corresponds to a device including a circuit including a semiconductor element (e.g., a transistor or a diode). In addition, a semiconductor device can be a device that can typically operate using semiconductor characteristics. In addition, the term "display device" includes not only a main body in which a display panel including a plurality of pixels including a display element such as a liquid crystal element or an EL element and a peripheral driver for driving the pixels is formed over a substrate, but also a display panel provided with a flexible printed circuit (FPC) or a printed wiring board (PWB). An emission device particularly relates to a display device using a self-luminous display element such as an element for an EL element or an FED.

[0045] In addition, among the transistors of the present application, a transistor in which a gate electrode is connected to a source electrode or a drain electrode is sometimes referred to as a diode-connected transistor. All of the diode-connected transistors of the present application can be replaced with another rectifier element such as a PN junction diode, a PIN diode, or a light-emitting diode.

[0046] As described above, by utilizing the present application, a semiconductor device in which a terminal OUT is connected to a power supply line through a second transistor in at least one-half of a period, which has less noise-induced malfunction and operates stably; a display device including the semiconductor device; and an electronic device including the display device can be provided.

[0047] In addition, when the average of the gate area of the third transistor and the gate area of the second transistor is made larger than the gate area of the first transistor, since it is not necessary to connect a capacitor element to an input terminal, the load of the input terminal can be minimized. Thus, a semiconductor device with small waveform distortion and low power consumption; a display device including the semiconductor device; and an electronic device including the display device can be provided.

[0048] When the diode element or diode-connected transistor is connected to the gate electrode of the long-period ON transistor, sufficient reverse bias can be applied to the gate electrode of the long-period ON transistor. Thus, a semiconductor device that stably operates and has less variation in characteristics, a display device including the semiconductor device, and an electronic device including the display device can be provided. BRIEF DESCRIPTION OF DRAWINGS

[0049] Figures 1A to 1C A shift register circuit of the present application and a timing chart thereof are explained.

[0050] Figures 2A to 2C A shift register circuit of the present application is explained.

[0051] Figures 3A to 3C A shift register circuit of the present application is explained.

[0052] Figure 4 A timing chart of a shift register circuit of the present application is explained.

[0053] Figures 5A to 5C A shift register circuit of the present application is explained.

[0054] Figure 6 A timing chart of a shift register circuit of the present application is explained.

[0055] Figures 7A to 7C A shift register circuit of the present application and a timing chart thereof are explained.

[0056] Figures 8A to 8C A shift register circuit of the present application is explained.

[0057] Figures 9A to 9D A reverse bias circuit of the present application is explained.

[0058] Figures 10A to 10H A reverse bias circuit of the present application is explained.

[0059] Figures 11A to 11C A shift register circuit of the present application is explained.

[0060] Figure 12 A timing chart of a shift register circuit of the present application is explained.

[0061] Figures 13A to 13C A shift register circuit of the present application and a timing chart thereof are explained.

[0062] Figures 14A to 14C A shift register circuit of the present application is explained.

[0063] Figures 15A to 15D A reverse bias-reset circuit of the present application is explained.

[0064] Figures 16A to 16H A reverse bias-reset circuit of the present application is described.

[0065] Figure 17 is a top view of a shift register circuit of the present application.

[0066] Figure 18 is a sectional view of a shift register circuit of the present application.

[0067] Figure 19 is a top view of a shift register circuit of the present application.

[0068] Figure 20 is a top view of a shift register circuit of the present application.

[0069] Figure 21 is a top view of a shift register circuit of the present application.

[0070] Figure 22A and 22B is a cross-sectional view applied to a shift register circuit of the present application.

[0071] Figure 23 is a top view of a shift register circuit of the present application.

[0072] Figure 24A and 24B is a cross-sectional view applied to a shift register circuit of the present application.

[0073] Figure 25 is a top view of a shift register circuit of the present application.

[0074] Figure 26 is a top view of a shift register circuit of the present application.

[0075] Figure 27A and 27B is a cross-sectional view of a shift register circuit of the present application.

[0076] Figure 28 is a top view of a shift register circuit of the present application.

[0077] Figure 29A and 29B is a cross-sectional view of a shift register circuit of the present application.

[0078] Figure 30 is a top view of a shift register circuit of the present application.

[0079] Figures 31A to 31E A display panel using a shift register circuit of the present application is described.

[0080] Figure 32 A display device using a shift register circuit of the present application is described.

[0081] Figure 33 A display device using the shift register circuit of the present application is described.

[0082] Figures 34A to 34H An electronic device using the shift register circuit of the present application is described.

[0083] Figures 35A to 35F Operation of the shift register circuit of the present application is described.

[0084] Figures 36A to 36D The shift register circuit of the present application and its timing chart are described.

[0085] Figure 37A and 37B A conventional shift register is described.

[0086] Figure 38A and 38B A conventional shift register is described. DETAILED DESCRIPTION

[0087] Embodiment Modes

[0088] Embodiment modes of the present application are described with reference to the drawings. Note that the present application is shown in many different modes, and it is easily understood by those skilled in the art that the modes and details can be variously changed without departing from the spirit and scope of the present application. Therefore, the present application is not to be considered as limited to the description of the embodiment modes. In the following description of the structure of the present application, the same reference numerals are used throughout the drawings to designate the same portions having similar functions, and the description of the above portions is not repeated.

[0089] Embodiment Mode 1

[0090] In this embodiment mode, a circuit structure of a shift register is described, in which the potential of an output terminal is fixed to a non-selection period, thereby reducing the occurrence of a malfunction caused by a clock signal or noise. Figures 1A to 1C An example of a circuit structure of the shift register of the present application is shown. Figure 1A The entire circuit structure of the shift register circuit of the present application is shown. Figure 1B An example of a circuit structure of a single-stage circuit showing the shift register of the present application is shown. Note that in this specification, a single-stage circuit refers to the smallest unit used to form a circuit, which corresponds to an output terminal (L(l) to L(n)) of the circuit, as shown in FIGS. 1A and IB. Figure 1A related Figure 1B as shown in Embodiment Mode 1. Figure 1C The waveforms of an input signal, an internal electrode, and an output signal in the circuit shown in Embodiment Mode 1 are shown. Figure 1A and 1B The waveforms of an input signal, an internal electrode, and an output signal in the circuit shown in Embodiment Mode 1 are shown.

[0091] Figure 1A The circuit shown has a start pulse terminal SP, a first clock signal line CLK1 (also referred to as a first wiring), a second clock signal line CLK2 (also referred to as a second wiring), a power supply line Vss, a transistor 18, n circuits 14 (n is an integer greater than or equal to two), and output terminals L(k) (k is an integer greater than or equal to one and less than or equal to n) corresponding to the output terminals provided by the circuit 10. In Figures 1A to 1C In the drawing (and all corresponding drawings in the specification), the kth stage, where k is an integer greater than or equal to one and less than or equal to n, is not shown. However, the output terminal L(k) is provided between the output terminal L(l) and the output terminal L(n), and the terminal P(k) is provided between the terminal P(l) and the terminal P(n). Figure 1B The circuit 10 shown has a terminal IN, a terminal OUT, a terminal G, a terminal R, a terminal F, a terminal B, a terminal C, transistors 11, 12, 13, 15, 16, and 17, a capacitor element 14, and a terminal P. Note that in the specification, a terminal is an electrode electrically connected to the outside of the circuit. Here, the transistor 11 is another element having a rectifying characteristic, and functions as a rectifying element for input (also referred to as a first rectifying element). Also, the transistor 15 is another element having a rectifying characteristic, and functions as a rectifying element for reset (also referred to as a second rectifying element). The transistor 12 functions as a transfer transistor (also referred to as a first transistor). The transistor 13 functions as an internal voltage clamping transistor (also referred to as a third transistor). The transistor 17 functions as an internal output voltage clamping transistor (also referred to as a second transistor). The transistor 16 functions as a set transistor (also referred to as a fourth transistor).

[0092] Note that the terminal P of the circuit 10 in the kth stage is also referred to as the terminal P(k). Also, the embodiment mode specifies the capacitor element 14; however, the function of the capacitor element 14 can also be achieved by a parasitic capacitance formed between the gate electrode and the drain electrode (or the source electrode) of the transistor 12. Therefore, the present application includes not only the case where the capacitor element 14 is formed as an independent electrical element, but also the case where the capacitor element 14 is a parasitic capacitance element associated with the transistor 12.

[0093] Figure 1B The gate electrode of the transistor 11 of the circuit 10 shown is connected to the terminal IN, one of the source electrode and the drain electrode of the transistor 11 is connected to the terminal IN, and the other of the source electrode and the drain electrode of the transistor 11 is connected to the terminal P. The gate electrode of the transistor 12 is connected to the terminal P, one of the source electrode and the drain electrode of the transistor 12 is connected to the terminal C, and the other of the source electrode and the drain electrode of the transistor 12 is connected to the terminal OUT.

[0094] Additionally, the gate electrode of transistor 13 is connected to terminal R, one of the source and drain electrodes of transistor 13 is connected to terminal G, and the other of the source and drain electrodes of transistor 13 is connected to terminal P. Furthermore, one electrode of capacitor element 14 is connected to terminal P, and the other electrode of capacitor element 14 is connected to terminal OUT.

[0095] Transistor 15 has its gate electrode connected to terminal OUT, one of its source and drain electrodes connected to terminal OUT, and the other of its source and drain electrodes connected to terminal B. Similarly, transistor 16 has its gate electrode connected to terminal P, one of its source and drain electrodes connected to terminal G, and the other of its source and drain electrodes connected to terminal F. Likewise, transistor 17 has its gate electrode connected to terminal R, one of its source and drain electrodes connected to terminal G, and the other of its source and drain electrodes connected to terminal OUT.

[0096] like Figure 1A As shown, terminal IN of circuit 10 in the first stage is connected to the start pulse terminal SP and the gate electrode of transistor 18. Additionally, terminal SR(1) of the first stage is connected to terminal B of circuit 10 in the second stage, and to one of the source and drain electrodes of transistor 18. The other of the source and drain electrodes of transistor 18 is connected to the power supply line Vss. Furthermore, the power supply line Vss is connected to terminal G of each stage of circuit 10; even more specifically, the first clock signal line CLK1 is connected to terminal C of each odd-numbered stage of circuit 10, and the second clock signal line CLK2 is connected to terminal C of each even-numbered stage.

[0097] Then, describe the state Figure 1A The circuit connection of circuit 10 at stage k is shown. Electrode SR(k) connected to terminal R of circuit 10 at stage k is connected to terminal B of circuit 10 at stage (k+1) and terminal F of circuit 10 at stage (kl). Additionally, output terminal L(k) connected to terminal OUT of circuit 10 at stage k is connected to terminal IN of circuit 10 at stage (k+l). Here, as... Figure 1A As shown, the connections of circuit 10 at the first or nth stage can differ from those of circuit 10 at another stage. For example, electrode SR(n) at the nth stage is connected to electrode SR(n-1).

[0098] Here, in the embodiment mode, the number n of the circuits 10 is odd; however, in the present application, n can be even. Also, in the present embodiment mode, the first clock signal line CLK1 is connected to the terminal C of the circuit 10 at the odd-numbered stage, and the second clock signal line CLK2 is connected to the terminal C of the circuit 10 at the even-numbered stage. Alternatively, in the present application, the connection of CLK1 and CLK2 can be reversed, specifically, the first clock signal line CLK1 is connected to the terminal C of the circuit 10 at the even-numbered stage, and the second clock signal line CLK2 is connected to the terminal C of the circuit 10 at the odd-numbered stage. Also, in the present application, the number of the clock signal lines is not limited to two, and it can be two or more. In this case, it is preferable that the number of the kinds of the signals input to the clock signal lines (the number of phases) is the same as the number of the clock signal lines. For example, it is preferable that the number of the kinds of the clock signals input to the circuit 10 (three phases) is three in the case of using three clock signal lines.

[0099] Then, referring to Figure 1C described Figure 1A and 1B the operation of the circuit shown. Figure 1C is a description of the signals input to Figure 1A and 1B the circuit shown, the internal electrodes, and the waveforms of the output signals. The vertical axis indicates the potential of the signals, and the input signals and the output signals can be digital signals having a potential of a high level (also referred to as an H level or a Vdd level) or a low level (also referred to as an L level or a Vss level). The horizontal axis indicates time. In the present embodiment mode, a description is given of inputting the input signals repeatedly according to time TO. Note that the present application is not limited to this, and includes variously changing the input signals to obtain a desired output signal.

[0100] Also, in the present embodiment mode, the operation of sequentially selecting the selected (scan) output terminals L(l) to OUT(n) as will be described for the output signal (scan). This operation is widely applied to, for example, a peripheral driver that controls the on / off of a switch for selecting a pixel. Note that, in the present embodiment mode, the signal input to the start pulse terminal SP in Figure 1C the input signals. Also, the potential of the power supply line Vss is assumed to be almost equal to the potential of the L level of the input signals. However, the potential of the power supply line Vss in the present application is not limited to this.

[0101] Then, referring to Figures 35A to 35F described Figures 1A to 1C the operation of the circuit shown. Figures 35A to 35F is a description of the operation of the circuit in time series. Figure 1B Figures 35A to 35F ​The transistors indicated by dotted lines are in the off state, and the transistors indicated by solid lines are in the on state. In addition, the arrows in the figure indicate the current direction in the point of operation. In addition, the potentials of the electrodes and the terminals in the point of the figure are placed in <>. Note that the lower potential is assumed to be the potential of the power supply line Vss, and the potentials of the clock signals are indicated as <vss>, or expressed as a higher potential <vdd>.

[0102] First, referring to Figure 35A The operation of canceling the reset operation of the current stage by the preceding stage will be described. Herein, in the specification, the operation of raising the potential of the terminal R to turn on the internal voltage clamping transistor 13 and the output voltage clamping transistor 17 is called the reset operation. On the other hand, the operation of lowering the potential of the terminal R to turn off the internal voltage clamping transistor 13 and the output voltage clamping transistor 17 is called the set operation. During the reset operation, the potentials of the terminal P and the terminal OUT are forced to be at <vss>Therefore, in order to operate the circuit 10, the set operation is first required. The potential of the terminal R of the present stage is made to be in the state of the low level by using the set transistor 16 of the preceding stage when the potential of the terminal P of the preceding stage rises <vss>To perform the set operation. Figure 35A In the diagram, transistors 11, 12, 13, 15, 16, and 17 are all in the off state, which is considered to be the initialization state.

[0103] Then, refer to Figure 35B This describes the pulse input operation. A pulse is input to terminal IN, and then the potential of terminal IN rises. The potential of terminal IN rises above the potential of terminal P by the threshold voltage (also known as Vthll) of transistor 11 or more, thus turning on transistor 11. Therefore, the potential of terminal P also rises above that of terminal IN. <vdd>of the transistor 11 and 16, the potential of the terminal OUT becomes equal to the potential of the terminal C <vss>In addition, the potential of the terminal F becomes <vss>; thus, the potential of the terminal R of the next stage is <vss>That is, the transistor 16 of the current stage is set to the on state to perform a set operation on the next stage.

[0104] The bootstrap operation is then described with reference to Figure 35C The terminal IN, which raises the potential of the terminal P, returns to the potential <vss>. Even if the potential of the terminal IN returns to <vss>At this time, the transistor 11 is diode-connected and in an off state. Therefore, the transistor 11 does not affect the potential of the terminal P. That is, the transistor 11 raises the potential of the terminal P according to the rise of the potential of the terminal IN, but does not need to lower it, and functions as a rectifying element for input.

[0105] In the case where the potential of the terminal P rises, the clock signal is input and the potential of the terminal C becomes <vdd>current flows from the terminal C to the terminal OUT through the transfer transistor 12, and the potential of the terminal OUT also rises. At this time, since the terminal P and the terminal OUT are connected through the capacitor element 14, the potential of the terminal P also rises in accordance with the rise in the potential of the terminal OUT. The value of the rise in the potential of the terminal P depends on the capacitance value of the parasitic capacitor element, not the capacitor element 14 connected to the terminal P. As long as the potential is < Vdd + |Vthll|> or higher, there is a problem in operation, the potential of the terminal OUT rises to <vdd>, equal to the potential of the clock signal. Therefore, in the figure, the potential of terminal P at this time is represented as <Vdd + |Vthll| (upward arrow)>, referring to the potential of <Vdd + |Vthll|> or higher.

[0106] Then, refer to Figure 35D , and describe the operation of resetting the previous stage by the current stage. As Figure 35C shown, when the potential of terminal OUT increases to <vdd>When the potential of the terminal B rises, the transistor 15 is turned on, and thus the potential of the terminal B rises. Since the transistor 15 is turned off when the potential of the terminal B is lowered from the potential of the terminal OUT by a threshold voltage (also referred to as Vthl5) of the transistor 15, the potential of the terminal B stops rising, and the potential of the terminal B is settled at <Vdd - |Vthl5|>. Thus, since the potential of the terminal R of the preceding stage rises to <Vdd - |Vthl5|>, the preceding stage is reset, and the potentials of the terminal P and the terminal OUT of the preceding stage are fixed at <vss>; thus, no pulse is input to the terminal IN of the current stage.

[0107] Then, the operation of the clock signal returning to Vss is described with reference to Figure 35E , When the potential of the clock signal returns to <vss>and the potential of terminal C returns to <vss>When the potential of the terminal IN is higher than that of the terminal OUT, the transmission transistor 12 is in an on state. Therefore, current flows from the terminal OUT to the terminal C through the transmission transistor 12; thus, the potential of the terminal OUT also returns to the potential of the terminal C <vss>Therefore, the potential of the terminal P also returns to <Vdd - |Vthll|>. In addition, since the transistor 15 is in the off state, even when the potential of the terminal OUT returns to <vss>The potential of the terminal B is still kept at <Vdd - |Vthl5|>. In other words, the transistor 15 raises the potential of the terminal B according to the potential of the terminal OUT, but does not need to lower it, and functions as a rectifying element for the reset.

[0108] Then, the operation of resetting the current stage by the next stage will be described with reference to Figure 35F When the rise of the potential of the terminal OUT of the current stage is sent to the terminal of the next stage, the potential of the terminal OUT of the next stage rises, and the transistor 15 of the next stage turns on. Then, the potential of the terminal B of the next stage rises, and the potential of the terminal R of the current stage rises to <Vdd - |Vthl5|>. Thus, the current stage is reset. Therefore, the internal voltage clamp transistor 13 and the output voltage clamp transistor 17 of the current stage turn on, and each of the terminal P and the terminal OUT is fixed at <vss>the potential of the terminal OUT. Thus, the current stage is reset by the operation of the lower stage, and the transfer transistor 12 is thereby turned off. Therefore, the electrical connection between the terminal OUT and the terminal C is interrupted.

[0109] When the potential of the terminal R is lowered due to the drain current of the transistor element connected to the terminal R, and thus the internal voltage clamp transistor 13 and the output voltage clamp transistor 17 are naturally turned off, or the set transistor 16 of the current stage is turned on, and thus the potential of the terminal R becomes <vss>so that the internal voltage clamping transistor 13 and the output voltage clamping transistor 17 are forced to be turned off (see Figure 35A ), the interruption ends. In the present specification, the period from the state shown in Figure 35F to the state shown in Figure 35A is called a non-selection period. The potential of the terminal P and the terminal OUT is stabilized and fixed at <vss>It is important. In other words, it is important to maintain the on state of the transistor having the connection terminal R as the gate electrode.

[0110] Note that the single-stage circuit in the shift register circuit of the present application includes an output voltage clamping transistor so as to prevent the output terminal from being in a floating state when the transfer transistor is in an off state, thereby determining the electrical connection to the power supply line. Therefore, how to perform the reset operation or the set operation of the terminal R is not limited to the above-described example. Figure 36A and 36C The configuration shown can be used for the single-stage circuit.

[0111] Figure 36A The circuit 310 shown includes the terminals IN, OUT, R, G, and C, the terminal P, and the transistors 311, 312, 313, and 317. The gate electrode of the transistor 311 is connected to the terminal IN, one of the source electrode and the drain electrode of the transistor 311 is connected to the terminal IN, and the other of the source electrode and the drain electrode of the transistor 311 is connected to the terminal P. The gate electrode of the transistor 312 is connected to the terminal P, one of the source electrode and the drain electrode of the transistor 312 is connected to the terminal C, and the other of the source electrode and the drain electrode of the transistor 312 is connected to the terminal OUT.

[0112] The gate electrode of the transistor 313 is connected to the terminal R, one of the source electrode and the drain electrode of the transistor 313 is connected to the terminal G, and the other of the source electrode and the drain electrode of the transistor 313 is connected to the terminal P. The gate electrode of the transistor 317 is connected to the terminal R, one of the source electrode and the drain electrode of the transistor 317 is connected to the terminal G, and the other of the source electrode and the drain electrode of the transistor 317 is connected to the terminal OUT. Note that the transistor 311 can function as a rectifying element for input (first rectifying element).

[0113] In addition, the transistor 312 can function as a transfer transistor (first transistor). The transistor 317 can function as an output voltage clamping transistor (second transistor). The transistor 313 functions as an internal voltage clamping transistor (third transistor).

[0114] Here, the operation of the circuit shown is described with reference to Figure 36B Figure 36A the time chart of the change in the potential of each terminal. The case where a clock signal is input to the terminal C, a pulse for raising the potential of the terminal P is input to the terminal IN, the terminal G is fixed to the L level, and a pulse for lowering the potential of the terminal P is input to the terminal R is described. Figure 36B Figure 36A the time chart of the change in the potential of each terminal. The case where a clock signal is input to the terminal C, a pulse for raising the potential of the terminal P is input to the terminal IN, the terminal G is fixed to the L level, and a pulse for lowering the potential of the terminal P is input to the terminal R is described.

[0115] ​​When the potential of the terminal R is low, and a pulse is input to the terminal IN with the internal voltage clamp transistor and the output voltage clamp transistor in the on state, the potential of the terminal P rises through the rectifying element for input, so the transfer transistor turns on. Then, when the potential of the terminal C is raised, the transfer transistor is bootstrapped, and the potential of the terminal C is sent to the terminal OUT. Then, when the potential of the terminal R rises, the internal voltage clamp transistor and the output voltage clamp transistor turn on, so the terminal P and the terminal OUT are fixed to the L level. However, the signal waveform of the signal input to the circuit 310 of the present application is not limited to these.

[0116] Thus, in the circuit 310 of the present application, the signal input to the terminal C is sent to the terminal OUT only during the period in which the potential of the terminal R is low. In addition, in the period in which the potential of the terminal R is high, the terminal P and the terminal OUT can be fixed to the L level.

[0117] Figure 36C The circuit 320 of the display includes terminals IN, OUT, R, G, and C, terminals P and Q, and transistors 321, 322, 323, and 327a, an inverter 327b, and a capacitor element 324. Note that the capacitor element 324 need not be connected as shown in Figure 36A The gate electrode of the transistor 321 is connected to the terminal IN, one of the source electrode and the drain electrode of the transistor 321 is connected to the terminal IN, and the other of the source electrode and the drain electrode of the transistor 321 is connected to the terminal P.

[0118] The gate electrode of the transistor 322 is connected to the terminal P, one of the source electrode and the drain electrode of the transistor 322 is connected to the terminal C, and the other of the source electrode and the drain electrode of the transistor 322 is connected to the terminal OUT. The gate electrode of the transistor 323 is connected to the terminal R, one of the source electrode and the drain electrode of the transistor 323 is connected to the terminal G, and the other of the source electrode and the drain electrode of the transistor 323 is connected to the terminal P. One of the electrodes of the capacitor element 324 is connected to the terminal P, and the other of the electrodes of the capacitor element 324 is connected to the terminal OUT. The gate electrode of the transistor 327a is connected to the terminal Q, one of the source electrode and the drain electrode of the transistor 327a is connected to the terminal G, and the other of the source electrode and the drain electrode of the transistor 327a is connected to the terminal OUT.

[0119] The input electrode of the inverter 327b is connected to the terminal P, and the output electrode of the inverter 327b is connected to the terminal Q. Note that the transistor 321 can function as a rectifying element for input (first rectifying element). Also, the transistor 322 can function as a transfer transistor (first transistor). Further, the transistor 327a can function as an output voltage clamping transistor (second transistor). Also, the transistor 323 functions as an internal voltage clamping transistor (third transistor).

[0120] Here, with reference to Figure 36D description Figure 36C operation of the circuit shown. Figure 36D is Figure 36C a time chart showing a change in potential of each terminal. An explanation is given of the case where a clock signal is input to the terminal C, a pulse for raising the potential of the terminal P is input to the terminal IN, the terminal G is fixed to the L level, and a pulse for lowering the potential of the terminal P is input to the terminal R.

[0121] When the potential of the terminal R is low, and the internal voltage clamping transistor is in the off state, if a pulse is input to the terminal IN, the potential of the terminal P is raised by the rectifying element for input, and thereby the transfer transistor is turned on. At this time, the terminal Q is inverted to the L level due to the potential of the terminal P. Therefore, the output voltage clamping transistor is in the off state. Then, when the potential of the terminal C is raised, the transfer transistor is bootstrapped, and the potential of the terminal C is sent to the terminal OUT. Also, when the potential of the terminal R is raised, the internal voltage clamping transistor is turned on. Thus, the terminal P is fixed to the L level. Therefore, when the potential of the terminal Q becomes the H level, the output voltage clamping transistor is turned on, and the terminal OUT is fixed to the L level. As such, in the circuit 320 of the present application, the signal input to the terminal C is sent to the terminal OUT only during a period in which the potential of the terminal R is low. Also, in a period in which the potential of the terminal R is high, the terminal P and the terminal OUT can be fixed to the L level. However, the signal waveform input to the circuit 320 of the present application is not limited to these.

[0122] Then, with reference to Figures 1A to 1C , a start pulse input to the start pulse terminal SP at time TO is described. The pulse width of the start pulse is arbitrary. Assuming that the period of the signal input to the first clock signal line CLK1 and the second clock signal line CLK2 is Tc, the pulse width is preferably Tc / 2 or more and Tc or less. Thus, the potential of the terminal P(l) connected to the start pulse terminal SP through the diode-connected transistor 11 can be sufficiently raised. Also, when the potential of the terminal P is lowered due to the on state of the transistor 13 of the circuit 10, power consumption can be suppressed because there is no path of stable current through the terminal IN, the transistor 11, the terminal P, the transistor 13, and the terminal G.

[0123] The signals input to the first clock signal line CLKl and the second clock signal line CLK2 are then described. It is preferable that the percentage (duty ratio) of the first clock signal and the second clock signal which are at the H level in one time period be less than 50%. Further, it is more preferable that the difference between the middle of the period in which one signal is at the H level and the middle of the period in which the other signal is at the L level be within the range of 10% of the time period. Thus, the output signal is similar to a pulse signal having a single frequency. Further, temporary overlap of the H levels of adjacent output terminals is prevented. This is advantageous since simultaneous selection of multiple lines can be prevented when a shift register circuit is used as a peripheral driver circuit for controlling the on / off of switches for selecting pixels in an active matrix display device in the present embodiment mode.

[0124] A description is given of the case where the potential of terminal P(l) is at the L level and the potential of terminal IN changes from the L level to the H level when a start pulse is input at time TO with the initial potential of terminal P(l) in the first stage circuit. Here, terminal R is at the L level and transistor 13 is in the off state. Thus, transistor 11 is on and the potential of terminal P(l) rises. Then, when the potential of terminal P(l) rises to the H level potential of the start pulse minus the threshold voltage of transistor 11, transistor 11 is turned off. Thus, the increase in the potential of terminal P(l) is stopped. When the potential of terminal P(l) once rises, transistor 11 remains off even if the potential of terminal IN later falls and returns to the L level. Thus, the potential of terminal P(l) does not decrease but is floating.

[0125] Thus, in the state where the potential of terminal P(l) is rising, transistor 12 is on since the potential of terminal C is at the L level. Thus, an L level is output to terminal OUT. Then, the potential of terminal C rises and the potential of terminal OUT also rises. Further, since terminal P(l) is floating, the potential of terminal P(l) also rises as the potential of terminal OUT rises through capacitor element 14. Thus, the change in the potential of terminal C is sent to terminal OUT without attenuation due to the bootstrap operation of transistor 12.

[0126] Thus, in the period where transistor 13 is in the off state and terminal P(l) is also floating at a high potential, the change in the potential of terminal C is sent to terminal OUT as is. Thus, in the case where the clock signal is not output to the output terminal as is, transistor 13 is on at some time by raising the potential of terminal R; thus, the potential of terminal P(l) becomes the L level. Then, transistor 12 is turned off, so the potential of terminal C is not sent to terminal OUT as is.

[0127] The terminal OUT is connected to the terminal IN of the circuit 10 of the second stage through the output terminal L(l). Specifically, the output of the circuit 10 of the first stage is used as a start pulse; thus, the circuit 10 of the second stage operates in the same manner as the above-mentioned circuit 10 of the first stage.

[0128] The timing of the reset operation is then described. The timing of the reset operation is arbitrary; the reset operation can be implemented at a point at which a pulse of the clock signal is transmitted from the terminal C to the terminal OUT. Specifically, the reset operation of the kth stage is implemented at a time at which the potential of the terminal OUT of the (k+l)th stage rises. In addition, as the circuit configuration of this case, as shown in Figure 1A and 1B it is preferable to use a configuration in which the terminal OUT of the (k+l)th stage and the terminal B are connected through the diode-connected transistor 15, and the terminal B of the (k+l)th stage is connected to the terminal R of the kth stage using the electrode SR(k).

[0129] When this configuration is used, the clock signal is sent to the terminal OUT of the circuit 10 of the kth stage, and when the clock signal is input to the terminal IN of the circuit 10 of the (k+l)th stage, the clock signal having a phase different from the output signal of the circuit 10 of the kth stage is output to the terminal OUT of the circuit 10 of the (k+l)th stage. Thus, the potential of the terminal B of the circuit 10 of the (k+l)th stage rises at the same time as the potential of the terminal OUT of the circuit 10 of the (k+l)th stage rises. Specifically, the potential of the terminal R of the circuit 10 of the kth stage rises at the same time as the potential of the terminal OUT of the circuit 10 of the (k+l)th stage rises, thereby resetting the circuit 10 of the kth stage. When the potential of the terminal OUT of the circuit 10 of the (k+l)th stage rises, the pulse of the output terminal is one since the circuit 10 of the kth stage outputs an L level after the pulse at which the clock signal is transmitted. In this way, the output terminal of the shift register of the present embodiment mode is at an H level, and OUT(l) is sequentially formed; thus, the shift register can be used for a peripheral driver circuit for controlling the on / off of a switch for selecting a pixel in an active matrix display device.

[0130] Note that the timing of the reset operation of the present application is not limited to this, and the reset operation can be implemented at any time. For example, the reset operation can be implemented when the potential of the output terminal of the stage two stages after the current stage rises, or when the potential of the output terminal of more than three stages after the current stage rises. At this time, since the signal line that defines the timing for the reset operation is away from the current stage, the distance of the lead electrode SR becomes long, so that the value of the parasitic capacitance related to the electrode SR becomes large. This is advantageous for holding the potential of the electrode SR.

[0131] The shift register of the present embodiment mode can be used for a peripheral driver circuit for controlling the on / off of a switch for selecting a pixel in an active matrix display device. For example, as shown in Figure 1A The final output of the illustrated connection of the electrode SR(n) and the electrode SR(n-1) causes the reset operation of the final stage. Thus, the reset (operation of returning to the potential of the power supply line Vss) of the terminal P(n) and the output terminal L(n) can be performed. In addition, a common timing pulse can be additionally input to all stages for the reset operation. Alternatively, a start pulse can be used as the common timing pulse.

[0132] Then, except for the period in which the output terminal L(k) of the kth stage is conducted to the clock signal line through the transistor 12 in the on state (in which the potential of the terminal P(k) is at the L level in the period in the Figure 1C In the (k+l)th stage of the circuit 10, when the potential of the terminal OUT rises, the potential of the terminal B rises to the potential of the H level minus the threshold voltage of the transistor 15 due to the diode-connected transistor 15 in the on state. However, when the potential of the terminal OUT falls, the transistor 15 is cut off; thus, the potential of the terminal B does not fall. Thus, the potential of the electrode SR(k) rises due to the rise of the potential of the terminal OUT of the (k+l)th stage, but does not fall. Therefore, the potential of the terminal R remains at the H level after the reset operation of the kth stage, and thus the transistors 13 and 17 remain on. Thus, the potential of the terminal P(k) and the potential of the terminal OUT are fixed at the L level.

[0133] If the potential of the reset terminal R is not maintained at the H level after the reset operation, the transistors 13 and 17 are cut off; thus, the terminal P(k) and the terminal OUT are floating. Since the terminal P(k) is connected to one of the first clock signal line and the second clock signal line through the gate capacitor of the transistor 12, if the terminal P(k) is floating, the potential of the terminal P(k) easily changes. In addition, since the terminal OUT is capacitively coupled to the terminal P(k) through the capacitor element 14, if the potential of the terminal P(k) changes when the terminal OUT is floating, the potential of the terminal OUT also changes. In addition, the potential of the output terminal L(k) changes even by the parasitic capacitance of the clock signal line. The change of the potential of the output terminal L(k) causes the instability and malfunction of the shift register circuit; thus, it is important to maintain the potential of the terminal R at the H level in order to fix the potentials of the terminals P and OUT.

[0134] Note that the period in which the potential of the terminal R is maintained at the H level for fixing the potentials of the terminals P and OUT is preferably at least half of the period of the start pulse.

[0135] Note that since the potential of the electrode SR and the terminal R is maintained at the H level after the reset operation, it is not necessary to connect a capacitive element. The average area of the gate electrodes of the internal voltage clamping transistor 13 and the output voltage clamping transistor 17 is larger than the area of the transfer transistor 12; thus, after the reset operation, the potential of the electrode SR and the terminal R can be maintained at the H level. Further, the length of the electrode SR leading from the terminal R of the kth stage is longer than the pitch between the circuit 10 of the kth stage and the circuit 10 of the (k+1)th stage, so as to increase the value of the parasitic capacitance associated with the electrode SR, thereby maintaining the potential of the electrode SR and the terminal R. Naturally, the potential of the electrode SR and the terminal R can be maintained by connecting a capacitive element between the electrode SR and the power supply line Vss or the start pulse terminal SP.

[0136] As described above, it is important to maintain the potential of the terminal R and the electrode SR at the H level after the reset operation for stable operation of the shift register circuit. However, in the case where the operation of the kth stage circuit 10 is performed once, the start pulse is input again, and then the kth stage circuit 10 is not operated again unless the transistors 13 and 17 are in the off state. Thus, before the circuit 10 of the kth stage is operated, the potential of the terminal R and the electrode SR(k) returns to the L level. In the specification, this operation is referred to as a "set operation". The timing at which the set operation is performed is arbitrary. The set operation of the kth stage can be performed at the timing at which the potential of the terminal P(k-l) of the (k-l)th stage rises. As the circuit configuration in this case, as shown in Fig. 6, the terminal F and the electrode SR(k) are connected using a transistor 16 in which the gate electrode is connected to the terminal P(k-l), one of the source electrode and the drain electrode is connected to the terminal G, and the other of the source electrode and the drain electrode is connected to the terminal F. Figure 1A and 1B , it is preferable to use a transistor 16 in which the gate electrode is connected to the terminal P(k-l), one of the source electrode and the drain electrode is connected to the terminal G, and the other of the source electrode and the drain electrode is connected to the terminal F.

[0137] In the case where this configuration is used, since the potential of the terminal P(k-l) of the (k-l)th stage rises before the pulse is input to the terminal IN of the kth stage, the transistor 16 of the (k-l)th stage is turned on at this time. Thus, the potential of the terminal F becomes the L level. Therefore, the terminal R of the kth stage changes from the maintained H level to the L level, and thus the transistors 13 and 17 are turned off. Then, the output of the (k-l)th stage is input to the terminal IN of the kth stage. Thus, the operation of the circuit 10 of the kth stage is started.

[0138] Here, the gate electrode of the transistor 16 of the (k-l)th stage is connected to the terminal OUT of the (k-l)th stage instead of being connected to the terminal F of the (k-l)th stage. In this case, when the output of the (k-l)th stage is input to the terminal IN of the kth stage, the set operation of the kth stage is performed.

[0139] In addition, the setting operation of the kth stage can be performed at the time when the potential of the terminal P(k-2) and the terminal OUT of the (k-2)th stage rises. Alternatively, the setting operation can be performed at the time when the potential of the terminal P(k-2) and the terminal OUT of the (k-2)th stage rises. In the case where the electrode SR is connected to the other stages, the length of the electrode SR leading from the terminal R of the kth stage is made longer than the pitch between the circuit 10 of the kth stage and the circuit 10 of the (k+l)th stage; thus, the parasitic capacitance value associated with the electrode SR can be made large. It is thus advantageous to ensure that the potential of the electrode SR and the terminal R is held.

[0140] A common timing pulse can be additionally input to all stages to perform the setting operation. Alternatively, the start pulse can be used as the common timing pulse. The electrode SR(l) of the first stage can be connected to one of the source and drain electrodes of the transistor 18 instead of being connected to the terminal F of the preceding stage. Thus, the setting operation of the first stage is performed when the start pulse is input.

[0141] Another circuit configuration of the shift register in which the potential of the fixed output terminal is held during the non-selection period is described below, which reduces the malfunction due to the clock signal and noise. Figures 2A to 2C Examples of the shift register having different circuit configurations according to the present application are described. Figure 2A A circuit configuration of the overall shift register of the present application is described. Figure 2B A configuration example of the circuit 20 corresponding to the single-stage circuit of the present application is described. Figure 2C A configuration example of the circuit 20 corresponding to the single-stage circuit of the present application is described. Figure 2B Another circuit configuration of the overall shift register of the circuit 20 is described.

[0142] Figure 2A The circuit shown has a start pulse terminal SP, a first clock signal line CLK1, a second clock signal line CLK2, a power supply line Vss, a transistor 28, and n blocks of the circuit 20 (n is an integer greater than or equal to two), and output terminals L(k) (k is an integer from 1 to n (including n)) provided corresponding to the circuit 20.

[0143] Figure 2B The display circuit 20 has terminals IN, OUT, G, R, F, B, C, and V, transistors 21, 22, 23, 25, 26, 27a, 27b, and 27c, a capacitor element 24, and a terminal P. Here, the transistor 21 can be replaced with another element having a rectifying property, which functions as a rectifying element for input (first rectifying element). In addition, the transistor 25 is another element having a rectifying property, which functions as a rectifying element for reset (also referred to as a second rectifying element). In addition, the transistor 22 functions as a transfer transistor (also referred to as a first transistor). The transistor 23 functions as an internal voltage clamping transistor (also referred to as a third transistor). The transistor 27a functions as an output voltage clamping transistor (also referred to as a second transistor). Further, the transistor 26 functions as a set transistor (also referred to as a fourth transistor).

[0144] Note that the terminal P of the circuit 20 at the kth stage is also referred to as a terminal P(k). In addition, the embodiment mode specifies the capacitor element 24; however, the function of the capacitor element 24 can also be achieved by a parasitic capacitance formed between the gate electrode and the drain electrode (or the source electrode) of the transistor 22. Therefore, the present application includes not only the case where the capacitor element 24 is formed as an electric element, but also the case where the capacitor element 24 is a parasitic capacitance element associated with the transistor 22. Figure 2C The display circuit of the display has a configuration in which a power supply line Vdd is added to Figure 2A The configuration of the display circuit.

[0145] Figure 2B The gate electrode of the transistor 21 of the display circuit 20 is connected to the terminal IN, one of the source electrode and the drain electrode of the transistor 21 is connected to the terminal IN, and the other of the source electrode and the drain electrode of the transistor 21 is connected to the terminal P. The gate electrode of the transistor 22 is connected to the terminal P, one of the source electrode and the drain electrode of the transistor 22 is connected to the terminal C, and the other of the source electrode and the drain electrode of the transistor 22 is connected to the terminal OUT.

[0146] In addition, the gate electrode of the transistor 23 is connected to the terminal R, one of the source electrode and the drain electrode of the transistor 23 is connected to the terminal G, and the other of the source electrode and the drain electrode of the transistor 23 is connected to the terminal P. In addition, one of the electrodes of the capacitor element 24 is connected to the terminal P, and the other of the electrodes of the capacitor element 24 is connected to the terminal OUT.

[0147] The gate electrode of transistor 25 is connected to terminal OUT, one of the source and drain electrodes of transistor 25 is connected to terminal OUT, and the other of the source and drain electrodes of transistor 25 is connected to terminal B. Additionally, the gate electrode of transistor 26 is connected to terminal P, one of the source and drain electrodes of transistor 26 is connected to terminal G, and the other of the source and drain electrodes of transistor 26 is connected to terminal F.

[0148] Additionally, the gate electrode of transistor 27a is connected to terminal Q, one of the source and drain electrodes of transistor 27a is connected to terminal G, and the other of the source and drain electrodes of transistor 27a is connected to terminal OUT. The gate electrode of transistor 27b is connected to terminal P, one of the source and drain electrodes of transistor 27b is connected to terminal G, and the other of the source and drain electrodes of transistor 27b is connected to terminal Q. The gate electrode of transistor 27c is connected to terminal V, one of the source and drain electrodes of transistor 27c is connected to terminal V, and the other of the source and drain electrodes of transistor 27c is connected to terminal Q.

[0149] Then, the description is in Figure 2A The connection of circuit 20 at level k in the circuit shown. Figure 2A The displayed circuit has the same Figure 1A The circuit shown has the same configuration, except for terminal V. Therefore, the same description will not be repeated. Terminal V can be connected to... Figure 2A Terminal C shown is connected to a different clock signal line than the one connected to terminal C. Although not shown, terminal V can be connected to the same clock signal line as terminal C.

[0150] Figure 2C The display shows that the power line Vdd, used to connect terminal V, is added to... Figure 2A The circuit shown is the circuit of the circuit. For example... Figure 2C As shown, connect the terminals V of all stages to the power line Vdd. The potential applied to the power line Vdd can be any potential, as long as it is higher than the threshold voltage of transistors 27a and 27c by a factor of two or more than the L level.

[0151] Then, Figure 2A The input and output signals of the circuits displayed in 2B and 2C are... Figure 1C The same. Figures 2A to 2C The displayed circuit and Figures 1A to 1C The difference in the displayed circuit lies in the use of transistors 27a, 27b, and 27c to fix the potential of terminal OUT to the L level. Figure 1B The function of transistor 17. Specifically, the gate electrode of transmission transistor 22 and the gate electrode of output voltage clamping transistor 27a are connected to each other through a circuit for outputting an inverted signal.

[0152] In Figure 2B the circuit, when the circuit is not operated and the potential of the terminal P is fixed at the L level by the transistor 23, the transistor 27b is in the off state. Here, since the potential of the electrode Q is at the H level, the transistor 27a is in the on state. Specifically, when the terminal P is fixed at the L level, the terminal OUT is also fixed at the L level, thereby reducing the malfunction of the output terminal due to the capacitive coupling with the clock signal line.

[0153] In the case where the circuit 20 is operated, since the pulse is input to the terminal IN and the potential of the terminal P rises, the transistor 27b is turned on. Thus, the potential of the electrode Q approaches the L level, so that the transistor 27a is turned off. Specifically, when the potential of the terminal P rises and the terminal OUT is electrically conducted to the terminal C, the transistor 27a is turned off. Thus, the circuit 20 can realize the operation similar to that of the circuit 10 shown. Figures 1A to 1C

[0154] Note that according to the embodiment mode, the period in which the terminal OUT is fixed at the low level is long, which is an advantage of the shift register of the present application. In other words, since the terminal OUT is fixed at the low level for a long time, the malfunction of the terminal OUT due to the operation of another signal line or the noise from the outside is reduced; thus, the stability in operation is high. In addition, as for the shift register of the present application, the switching frequency of the signal input to the transistor connected to the terminal OUT is low; thus, since the feedthrough of the signal hardly changes the potential of the terminal OUT, the high stability in operation can be realized.

[0155] Embodiment Mode 2

[0156] In the embodiment mode, the reset operation of the last stage of the shift register circuit of the present application and the reset operation of all stages are described.

[0157] In the circuit configuration described in Embodiment Mode 1, the reset operation of the current stage is performed at the time when the next stage is operated. Here, since there is no stage after the shift register circuit of the last stage, the pulse that does not limit the timing of the reset operation is input to the last stage. Therefore, by the reset operation, the potential of the electrode SR(n) does not become the H level. Thus, the clock signal is continuously output to the terminal OUT of the last stage.

[0158] In view of this, in Embodiment Mode 1, the electrode SR(n) is connected as Figure 1A , Figure 2A , and Figure 2C ​The electrode SR(n-1) is shown. Thus, the reset operation is performed by outputting the electrode SR(n) at the H level with the output of the terminal OUT of the last stage itself. Therefore, it is possible to prevent the potential of the clock signal line from being continuously output to the output terminal L(n) of the last stage. In this case, the pulse width of the output of the last stage is smaller than the pulse width of the output of the clock signal. Here, in the case where the clock signal is continuously output to the last stage and the output of the last stage is not actively used except for the reset operation of the preceding stage, the remaining power is consumed for charging or discharging a parasitic capacitance element connected to the output terminal of the last stage.

[0159] The configuration described in this embodiment mode is different from the configuration shown in Embodiment Mode 1, in which the last stage can operate as a shift register. Figure 3A , 3B, and 3C each illustrate a configuration in which the transistor 29 for the reset operation of the last stage is added to Figure 1A , Figure 2A , and Figure 2C each of the configurations shown. The gate electrode of the transistor 29 is connected to the start pulse terminal SP, one of the source electrode and the drain electrode of the transistor 29 is connected to the start pulse terminal SP, and the other of the source electrode and the drain electrode of the transistor 29 is connected to the electrode SR(n).

[0160] Further, as Figures 3A to 3C indicated, in the case where the transistor 29 is used for the reset operation of the last stage, the reset operation of the last stage does not need to be performed by the last stage itself, and the reset operation can be performed at the timing of input of the start pulse; therefore, the electrode SR(n) and the electrode SR(n-1) do not need to be connected.

[0161] Figure 4 is a timing chart for explaining Figures 3A to 3C the operation of the circuit shown. The difference from Figure 1C is that the reset operation of the terminal P(n) of the last stage is performed at the timing of input of the start pulse (time TO), and thus the output terminal L(n) of the last stage also operates as a shift register circuit. Here, in the timing chart of Figure 4 , when the period of input of the start pulse is T, the total number of pulses of the clock signal input during the period T is preferably greater than the number n of stages of the shift register circuit. Thus, the reset operation of the last stage can be safely performed during the period T.

[0162] Then, with reference to 5A to 5C and Figure 6 , the shift register circuit of the present application in which a signal line for the reset operation is added is described.

[0163] Figure 5A each of FIGS. 5B, and 5C shows a configuration in which the signal line RES for the reset operation and the transistor RE(k) (k is an integer from 1 to n (including n)) connecting the signal line RES are added to Figure 1A , Figure 2A , and Figure 2C each of the configurations shown. The gate electrode of the transistor RE(k) is connected to the signal line RES, one of the source electrode and the drain electrode of the transistor RE(k) is connected to the signal line RES, and the other of the source electrode and the drain electrode of the transistor RE(k) is connected to the electrode SR(k).

[0164] FIG. 5 and Figure 6 shows a shift register circuit in which the transistor RE(k) is additionally connected to each stage, so that all the stages can be reset at any time, which can return to the initial state before the operation of the last stage. However, the present application is not limited to this, and the number of the transistors RE(k) is arbitrary. For example, the transistor RE is provided only in the last stage, only on odd-numbered stages or only on even-numbered stages, or only in the upper half stages or only in the lower half stages. There is an advantage in reducing the number of the transistors RE, so that the circuit scale becomes small; thus, the percentage of the circuit occupying the substrate is reduced. In addition, when the number of the transistors RE is reduced, the load of driving the signal line RES and the power consumption can be reduced, which is advantageous.

[0165] Here, the operation of the shift register circuit of the present application in which the signal line for the reset operation is added is described with reference to Figure 6 Figure 6 is a time chart of the potential changes of the input signal, the terminal P, and the output terminal L at the time Tr when a pulse is input to the signal line RES to reset all the stages. When the start pulse is input at the time TO, the same operation as Figure 1C is performed until the pulse is input to the signal line RES. However, when the pulse is input to the signal line RES at the time Tr, the potential of the electrode SR of all the stages is at the H level; thus, the output terminal L and the terminal P are fixed at the L level. Here, the transistor 16 or 26 for changing the potential of the electrode SR to the L level is cut off because the potential of the terminal P becomes the L level. Therefore, a path through which a current flows from the signal line RES to the power supply line Vss when the pulse is input to the signal line RES is not formed.

[0166] Thus, as for the operation of the shift register circuit of the present application in which the signal line for the reset operation is added, the operation of the shift register circuit of the present application is the same as that of the shift register circuit of the prior art until the pulse is input to the signal line RES. Figures 5A to 5C ​In the shift register circuit of the present application, a signal line for a reset operation is added to each of the shift register circuits, and all stages can be reset at an arbitrary timing, and can return to the initial state before the operation of the final stage. In the case where the shift register circuit is used as a driving circuit for a display device, for example, it is advantageous to stop the operation of the shift register circuit and not use the pixels of the region to be unused by arranging only the pixels in a part of the display region, which leads to the advantage of reduced power consumption.

[0167] In addition, when a pulse is input to the signal line RES, the floating electrode SR is charged, so that a decrease in the potential of the electrode SR due to a leakage current can be prevented. Specifically, the transistor having its gate electrode connected to the electrode SR can easily maintain the advantage of being in the on state.

[0168] Note that the present embodiment mode can be freely combined with another embodiment mode.

[0169] Embodiment Mode 3

[0170] A voltage is applied between the gate electrode and the source electrode to turn on the transistor. Here, if a voltage is continuously applied to the gate electrode of the transistor, charges are trapped in the energy level region between the source electrode or the drain electrode and the gate electrode due to impurities or the like, and the trapped charges form an internal electric field; thus, a change in characteristics over time is caused. In particular, a shift change in threshold voltage (threshold shift) is caused. As for the change over time, not only a voltage of a polarity for turning on the transistor but also a voltage of an opposite polarity (also referred to as reverse bias) is applied, and thus the trapped charges are discharged and the degree of change is reduced. In a thin film transistor using amorphous silicon in the channel layer, the threshold shift is significantly observed, which has a defect level in the region between the source electrode or the drain electrode and the gate electrode. Therefore, the shift register circuit of the present embodiment mode is significantly advantageous in a thin film transistor using amorphous silicon in the channel layer. However, the present application is not limited to this.

[0171] In the present embodiment mode, an operation of applying a reverse bias to a transistor forming the shift register circuit of the present application is described.

[0172] First, Figures 7A to 7C The function of applying a reverse bias to reduce a change in characteristics over time is added to Figures 1A to 1C The shift register circuit of the circuit shown. Figure 7A is a whole view of the shift register circuit of the present application, Figure 7B The stage of the circuit 30 of the shift register circuit of the present application is described. Figure 7C is a time chart of an input signal and an output signal of the shift register circuit of the present application.

[0173] Figure 7B The display shows transistors 39a and 39b, terminal N, and electrode S are applied to... Figure 1B The circuit shown is a circuit diagram. Additionally, transistors 31, 32, 35, 36, and 37 and capacitor element 34 correspond to... Figure 1B Transistors 11, 12, 15, 16, and 17 and capacitor 14 are connected to... Figure 1B Same. Additionally... Figure 7B The gate electrode of transistor 33 is connected to electrode S, one of the source electrode and drain electrode of transistor 33 is connected to terminal G, and the other of the source electrode and drain electrode of transistor 33 is connected to terminal P.

[0174] Additionally, the gate electrode of transistor 37 is connected to electrode S, one of the source and drain electrodes of transistor 37 is connected to terminal G, and the other of the source and drain electrodes of transistor 37 is connected to terminal OUT. The gate electrode of transistor 39a is connected to electrode S, one of the source and drain electrodes of transistor 39a is connected to electrode S, and the other of the source and drain electrodes of transistor 39a is connected to terminal N. Similarly, the gate electrode of transistor 39b is connected to terminal N, one of the source and drain electrodes of transistor 39b is connected to electrode S, and the other of the source and drain electrodes of transistor 39b is connected to terminal R.

[0175] Figure 7A This indicates that in each stage, the signal line RB connecting terminal N of circuit 30 is added to... Figure 1A The circuit shown. Additionally, transistor 38 corresponds to... Figure 1A The transistor 18 in the middle is connected similarly.

[0176] Here, refer to Figure 7C describe Figure 7A and 7B The circuit operation is shown. When a pulse is input to the start pulse terminal SP at time T0, the shift register circuit is activated, and output signals are sequentially output from the output terminal L(l). The period during which the output signal is output to the output terminal L(n) is called the normal operation cycle. During the normal operation cycle, a potential of level H is input to the signal line RB. Here, transistor 39b is in the on state, and transistor 39a is in the off state. Specifically, terminals R and electrode S are in a conductive state, and terminals N and electrode S are in a non-conductive state; therefore, Figure 7B Connection status and Figure 1B Similar, therefore Figures 7A to 7C The shift register circuit with Figures 1A to 1C It runs in the same way as shown.

[0177] Then, as Figure 7C As shown, when the output signal is output to Figure 7A After the output terminal L(n) of the shift register circuit is displayed, the potential of signal line RB can be reduced between time T1 and time T2. This period is called the reverse bias application period. Therefore, Figure 7B Transistor 39b is turned off, and transistor 39a is turned on. That is, the electrical connection between terminal R and electrode S is lost, while the electrical connection between terminal N and electrode S remains; therefore, the potential of electrode S decreases. Then, when the potential of electrode S exceeds the potential of electrode N by a threshold voltage of transistor 39a, transistor 39a turns off, and the decrease in the potential of electrode S stops. Here, the potential of signal line RB can be lower than the potential of power line Vss. When the low potential of signal line RB is lower than the potential of power line Vss, the potential of electrode S can be further reduced during the reverse bias application cycle. Therefore, a potential of opposite polarity to that in the on-state can be applied to the gate electrodes of transistors 33 and 37, thus helping to reduce the threshold shift of the transistors.

[0178] Here, transistor 39b is a transistor that provides an electrical connection between terminal R and electrode S during normal operation and interrupts the electrical connection between terminal R and electrode S during reverse bias application cycles. Without providing transistor 39b and continuously establishing conductive continuity between terminal R and electrode S, the circuit size is reduced, resulting in reduced power consumption due to the reduced parasitic capacitance of the connection signal line RB.

[0179] In addition, when Figure 7B When transistor 39b is configured as shown, lowering the potential of N via signal line RB prevents the potential of terminal R from decreasing simultaneously with lowering the potential of electrode S. Here, considering the case where an electrical connection is established between terminal R and electrode S during a reverse bias application cycle, the potential of terminal R also decreases as the potential of electrode S decreases. Terminal R is connected to terminal F of the preceding circuit 30 via electrode SR; therefore, when the potential of terminal R drops to a level lower than or equal to the potential of power line Vss minus the threshold voltage of transistor 36 in the preceding stage, transistor 36 in the preceding stage turns on; thus, a constant current flows through signal line RB and power line Vss. Furthermore, terminal R is also connected to the next stage circuit 30 via electrode SR; therefore, when the potential of terminal R decreases, transistors 35 and 32 in the next stage turn on; thus, a constant current is considered to flow through the clock signal line of the next stage, transistors 32 and 35, and the current stage transistor 39a and signal line RB. Therefore, during the reverse bias application cycle, the electrical connection between terminal R and electrode S is interrupted, thereby preventing the formation of a current path including terminal R due to the potential drop of terminal R. Thus, sufficient reverse bias is applied to transistors 33 and 37 while reducing power consumption.

[0180] Note that in the present embodiment mode, an example is described in which a reverse bias is applied to the gate electrodes of the transistors 33 and 37 during the reverse bias application period; however, the present application is not limited to this. The reverse bias can be applied to any transistor. However, the transistors 33 and 37 are in the on state during most of the period in which the output terminal L should output the L level, and the above-described transistor that is in the on state most of the time causes a large threshold shift. Therefore, as shown in FIG. 6, it is effective and more preferable to reduce the threshold shift by connecting the transistors 39a and 39b to the gate electrodes of the transistors 33 and 37, and providing a reverse bias application period. Figure 7B

[0181] First, Figures 8A to 8C the function in which a reverse bias is applied to reduce the characteristic change over time is explained with reference to Figures 2A to 2C the circuit of the shift register circuit shown in FIG. 5. Figure 8A is a full view of the shift register circuit of the present application, Figure 8B the single stage of the circuit 40 of the shift register circuit of the present application is explained, Figure 8C is another full view of the shift register circuit of the present application.

[0182] Figure 8B the circuit in which the transistors 49a, 49b, 49c, and 49d, the terminal N, the electrode S, and the electrode U are added to Figure 2B the circuit of the circuit shown in FIG. 5. In addition, the transistors 41, 42, 45, 46, 47b, and 47c and the capacitor element 44 correspond to the transistors 21, 22, 25, 26, 27b, and 27c and the capacitor element 24 in Figure 2B , respectively, and the connections are the same as in Figure 2B . In addition, Figure 8B the gate electrode of the transistor 43 in is connected to the electrode S, one of the source electrode and the drain electrode of the transistor 43 is connected to the terminal G, and the other of the source electrode and the drain electrode of the transistor 43 is connected to the terminal P.

[0183] ​Additionally, transistor 47a has its gate electrode connected to electrode U, one of its source and drain electrodes connected to terminal G, and the other of its source and drain electrodes connected to terminal OUT. Transistor 49a has its gate electrode connected to electrode S, one of its source and drain electrodes connected to electrode S, and the other of its source and drain electrodes connected to terminal N. Similarly, transistor 49b has its gate electrode connected to terminal N, one of its source and drain electrodes connected to electrode R, and the other of its source and drain electrodes connected to terminal S. Transistor 49c has its gate electrode connected to terminal U, one of its source and drain electrodes connected to electrode U, and the other of its source and drain electrodes connected to terminal N. Furthermore, transistor 49d has its gate electrode connected to terminal N, one of its source and drain electrodes connected to electrode Q, and the other of its source and drain electrodes connected to terminal U.

[0184] here, Figure 8A This indicates that in each stage, the signal line RB connecting terminal N of circuit 40 is added to... Figure 2A The circuit shown is the circuit diagram. Additionally, transistor 48 corresponds to... Figure 2A The transistor 28 is connected similarly. Additionally, Figure 8C The power supply line Vdd is connected to... Figure 8A The circuit shown is the circuit of the circuit, and the power line Vdd is connected to the terminal V of the circuit 40 of the entire stage.

[0185] Here, according to Figure 7C The displayed timeline is running Figure 8A The circuits shown are 8B and 8C. According to... Figure 7C The displayed timing table is running. Figure 8A In the case of the circuits shown in 8B and 8C, during the normal operating cycle, a potential of level H is input to signal line RB. Here, transistors 49b and 49d are in the on state, and transistors 49a and 49c are in the off state. Specifically, terminals R and electrode S, and terminals Q and electrode U are in the conductive state, while terminals N and electrode S, and electrodes N and U are in the non-conductive state; therefore, Figure 8B Connection status and Figure 2B Similar, thus with Figures 2A to 2C Run in the same way as shown Figures 8A to 8C The shift register circuit in the middle.

[0186] Then, during the reverse bias application cycle, in Figure 8B The transistors 49b and 49d are turned off and the transistors 49a and 49c are turned on. That is, the terminals R and S, the terminals Q and U are in a non-conductive state, and the terminals N and S, and the terminals N and U are in a conductive state; thus, the potentials of the electrodes S and U are lowered. Then, when the potentials of the electrodes S and U exceed the potential of the electrode N by a threshold voltage of the transistors 49a and 49c, the transistors 49a and 49c are turned off and the lowering of the potentials of the electrodes S and U is stopped. Here, the potential of the signal line RB can be lower than the potential of the power supply line Vss. When the low potential of the signal line RB is lower than the potential of the power supply line Vss, the potentials of the electrodes S and U can be further lowered during the reverse bias application period. Thus, a potential of the opposite polarity to the on state case can be applied to the gate electrodes of the transistors 43 and 47a, thus, contributing to reduction of threshold shift of the transistors.

[0187] Here, the transistors 49b and 49d are transistors having a function of providing a conductive state of the terminals R and S, the electrodes Q and U during the normal operation period, and providing a non-conductive state of the terminals R and S, the electrodes Q and U during the reverse bias application period. In a case where the transistors 49b and 49d are not provided and the terminals R and S, the electrodes Q and U are in a continuously conductive state, the circuit scale is made smaller, resulting in reduction of power consumption due to reduction of a parasitic capacitance value of the signal line RB.

[0188] Further, when the transistors 49b and 49d are configured as shown in Figure 8B by lowering the potential of the terminal N through the signal line RB, lowering of the potentials of the terminals R and Q while lowering the potentials of the electrodes S and U can be prevented.

[0189] Here, considering a case where the terminals R and S are in a conductive state during the reverse bias application period, the potential of the terminal R is also reduced as the potential of the electrode S is lowered. The terminal R is connected to the terminal F of the preceding stage circuit 40 through the electrode SR; thus, when the potential of the terminal R is lowered to a potential lower than or equal to the potential of the power supply line Vss minus the threshold voltage of the transistor 46 in the preceding stage, the transistor 46 of the preceding stage is turned on; thus, a constant current flows through the signal line RB and the power supply line Vss. Further, the terminal R is also connected to the transistor 45 of the succeeding stage circuit 40 through the electrode SR; thus, when the potential of the terminal R is lowered, the transistors 45 and 42 of the succeeding stage are turned on; thus, a constant current is considered to flow through the clock signal line of the succeeding stage, the transistor 42, and the transistor 45, and the transistors 49a and the signal line RB of the present stage.

[0190] In addition, considering the case where the terminal Q and the electrode U are in the conductive state during the reverse bias application period, the potential of the terminal Q also decreases with the decrease in the potential of the electrode U. Since the electrode Q is connected to the source electrode or the drain electrode of the transistors 47b and 47c, when the potential of the electrode Q decreases, the transistors 47b and 47c are in the on state so that a constant current flows from the terminal G and the terminal V through the electrode Q, the transistor 49d, the electrode U, the transistor 49c, and the terminal N.

[0191] Therefore, during the reverse bias application period, the terminal R and the electrode S, the electrode Q and the electrode U are in the non-conductive state with the transistors 49b and 49d, thereby preventing the formation of a current path including the terminal R and the electrode Q due to the decrease in the potential of the terminal R and the electrode Q. Thus, sufficient reverse bias can be applied to the transistors 43 and 47a while reducing power consumption. Note that the transistors 49b and 49d can be provided, only one of them can be provided, or none of them can be provided.

[0192] Note that in the present embodiment mode, an example is described in which reverse bias is applied to the gate electrodes of the transistors 43 and 47a during the reverse bias application period; however, the present application is not limited to this. Reverse bias can be applied to any transistor. However, the transistors 43 and 47a are in the on state during most of the period in which the output terminal L outputs the L level, and the above-described transistor that is in the on state most of the time causes large threshold shift. Therefore, as shown in FIG. 6, it is effective and preferable to reduce threshold shift by connecting the transistors 49a, 49b, 49c, and 49d to the gate electrodes of the transistors 43 and 47a, and providing a reverse bias application period. Figure 8B

[0193] As described above, in the present embodiment mode, threshold shift of the transistors 33, 37, and 43, 43a can be reduced by connecting the transistors 39a, 39b, 49a, 49b, 49c, and 49d for applying reverse bias to the gate electrodes of the transistors 33, 37, 43, and 47a. In addition, the gate electrode of any transistor of any circuit other than the circuit shown in the present embodiment mode can be connected to the circuit shown in FIG. 5, thereby applying reverse bias to the transistor. Since the circuit shown in FIG. 5 is a circuit in which the gate electrode of the transistor is connected to the circuit, the potential of any electrode in the circuit other than the gate electrode of the transistor does not change; thus, threshold shift of the transistor can be reduced without constant current flowing or malfunction. Figures 9A to 9D Figures 9A to 9D

[0194] Figures 9A to 9D The circuits shown in FIGS. 5 and 6 each have a signal terminal SIG, a bias terminal BIAS, a target terminal GATE, a cutoff transistor SIG-Tr, and a bias transistor BIAS-Tr. Here, the signal terminal SIG is a terminal to which a signal is input, the bias terminal BIAS is a terminal to which bias is input, the target terminal GATE is a terminal to which a signal is output, the cutoff transistor SIG-Tr is a transistor that is in the off state when the signal terminal SIG is in the high state, and the bias transistor BIAS-Tr is a transistor that is in the on state when the bias terminal BIAS is in the high state. Figures 9A to 9D Figures 10A to 10H ​​​​The bias transistor BIAS-Tr in each circuit shown is used as a rectifier element.

[0195] exist Figure 9A In the circuits shown in 9B, 9C, and 9D, the gate electrode of the cutoff transistor SIG-Tr is connected to the bias terminal BIAS, one of the source and drain electrodes of the cutoff transistor SIG-Tr is connected to the signal terminal SIG, and the other of the source and drain electrodes of the cutoff transistor SIG-Tr is connected to the target terminal GATE.

[0196] exist Figure 9A and 9D In the circuit shown, the gate electrode of the bias transistor SIG-Tr is connected to the target terminal GATE, one of the source and drain electrodes of the bias transistor BIAS-Tr is connected to the target terminal GATE, and the other of the source and drain electrodes of the bias transistor BIAS-Tr is connected to the bias terminal BIAS.

[0197] exist Figure 9B and 9C In the circuit shown, the gate electrode of the bias transistor BIAS-Tr is connected to the bias terminal BIAS, one of the source and drain electrodes of the bias transistor BIAS-Tr is connected to the target terminal GATE, and the other of the source and bias electrodes of the bias transistor BIAS-Tr is connected to the bias terminal BIAS.

[0198] The target terminal GATE is connected to a transistor that is reverse-biased. This is suitable for applying a reverse bias between the gate and source electrodes of the transistor, and between the gate and drain electrodes of the transistor. Therefore, it is preferable to connect the target terminal GATE to the gate electrode of the reverse-biased transistor. However, the invention is not limited thereto; the target terminal GATE can be connected to either the source or drain electrode of the reverse-biased transistor. In this case, the polarity of the reverse bias applied can be opposite to the case where the target terminal GATE is connected to the gate electrode. Note that the number of transistors connected to the target terminal GATE is arbitrary.

[0199] When the transistor is operating normally, the signal terminal SIG is connected to either the signal line or the power supply line input to the transistor. The bias terminal BIAS is a signal line used to select whether to apply a reverse bias to the transistor, or to transfer the potential of the electrode connected to the signal terminal SIG to the target terminal GATE.

[0200] Here, the polarity classification is relative to the cutoff transistor SIG-Tr and the bias transistor BIAS-Tr. Figure 9A The circuits for displays 9B, 9C, and 9D.

[0201] Figure 9A and 9B The circuit shown is one in which a potential of the time H level is applied to the bias terminal BIAS during normal operation, and a potential of the time L level is applied to the bias terminal BIAS during application of the reverse bias. This circuit can be used, for example, when the electrode to which the reverse bias is applied is the gate electrode of an n-channel transistor.

[0202] Figure 9C and 9D The circuit shown is one in which a potential of the time L level is applied to the bias terminal BIAS during normal operation, and a potential of the time H level is applied to the bias terminal BIAS during application of the reverse bias. This circuit can be used, for example, when the electrode to which the reverse bias is applied is the gate electrode of a p-channel transistor. Thus, the circuit shown in this embodiment mode Figures 9A to 9D The circuit shown is one in which a potential of the time L level is applied to the bias terminal BIAS during normal operation, and a potential of the time H level is applied to the bias terminal BIAS during application of the reverse bias. This circuit can be used, for example, when the electrode to which the reverse bias is applied is the gate electrode of a p-channel transistor. Thus, the circuit shown in this embodiment mode

[0203] Next, with reference to Figures 10A to 10H the transistor to which the reverse bias is applied is included in Figures 9A to 9D the circuit of the circuit shown.

[0204] Figure 10A The circuit shown is one in which a potential of the time L level is applied to the bias terminal BIAS during normal operation, and a potential of the time H level is applied to the bias terminal BIAS during application of the reverse bias. This circuit can be used, for example, when the electrode to which the reverse bias is applied is the gate electrode of a p-channel transistor. Thus, the circuit shown in this embodiment mode Figure 9A The circuit shown is one in which a potential of the time L level is applied to the bias terminal BIAS during normal operation, and a potential of the time H level is applied to the bias terminal BIAS during application of the reverse bias. This circuit can be used, for example, when the electrode to which the reverse bias is applied is the gate electrode of a p-channel transistor. Thus, the circuit shown in this embodiment mode Figure 10A The gate electrodes of the transistors AC-Tr and AC-Tr2 can be connected to the gate terminal GATE of the circuit shown. Figure 9A The gate electrodes of the transistors AC-Tr and AC-Tr2 can be connected to the gate terminal GATE of the circuit shown. Figure 10B The circuit shown is one in which a potential of the time L level is applied to the bias terminal BIAS during normal operation, and a potential of the time H level is applied to the bias terminal BIAS during application of the reverse bias. This circuit can be used, for example, when the electrode to which the reverse bias is applied is the gate electrode of a p-channel transistor. Thus, the circuit shown in this embodiment mode Figure 9A The circuit shown is one in which a potential of the time L level is applied to the bias terminal BIAS during normal operation, and a potential of the time H level is applied to the bias terminal BIAS during application of the reverse bias. This circuit can be used, for example, when the electrode to which the reverse bias is applied is the gate electrode of a p-channel transistor. Thus, the circuit shown in this embodiment mode Figure 10B The gate electrodes of the transistors AC-Tr and AC-Tr2 can be connected to the gate terminal GATE of the circuit shown. Figure 9A The gate electrodes of the transistors AC-Tr and AC-Tr2 can be connected to the gate terminal GATE of the circuit shown.

[0205] Here, the transistors AC-Tr, AC-Trl, and AC-Tr2 form part of a circuit having a certain function, and as a whole are like the transistors 33 and 37 in Figures 7A to 7C or the transistors 33 and 37 in Figures 8A to 8C the transistor 43 and 47a in FIG. 43, the circuit of the present application to which the reverse bias is applied is not dependent on each of the source electrode and each of the drain electrode of the transistors AC-Tr, AC-Trl, and AC-Tr2.

[0206] Further, Figure 10C The circuit to which the reverse bias is applied is included in the circuit shown in FIG. 42. As shown in FIG. 42, the gate electrode of the transistor AC-Tr can be connected to the target terminal GATE of the circuit shown in FIG. 42. Further, Figure 9B The circuit to which the reverse bias is applied is included in the circuit shown in FIG. 42. As shown in FIG. 42, the gate electrode of the transistor AC-Tr can be connected to the target terminal GATE of the circuit shown in FIG. 42. Further, Figure 10C The circuit to which the reverse bias is applied is included in the circuit shown in FIG. 42. As shown in FIG. 42, the gate electrode of the transistor AC-Tr can be connected to the target terminal GATE of the circuit shown in FIG. 42. Further, Figure 9B The circuit to which the reverse bias is applied is included in the circuit shown in FIG. 42. As shown in FIG. 42, the gate electrode of the transistor AC-Tr can be connected to the target terminal GATE of the circuit shown in FIG. 42. Further, Figure 10D The circuit to which the reverse bias is applied is included in the circuit shown in FIG. 42. As shown in FIG. 42, the gate electrode of the transistor AC-Tr can be connected to the target terminal GATE of the circuit shown in FIG. 42. Further, Figure 9B The circuit to which the reverse bias is applied is included in the circuit shown in FIG. 42. As shown in FIG. 42, the gate electrode of the transistor AC-Tr can be connected to the target terminal GATE of the circuit shown in FIG. 42. Further, Figure 10D The circuit to which the reverse bias is applied is included in the circuit shown in FIG. 42. As shown in FIG. 42, the gate electrode of the transistor AC-Tr can be connected to the target terminal GATE of the circuit shown in FIG. 42. Further, Figure 9B The circuit to which the reverse bias is applied is included in the circuit shown in FIG. 42. As shown in FIG. 42, the gate electrode of the transistor AC-Tr can be connected to the target terminal GATE of the circuit shown in FIG. 42. Further, Figures 7A to 7C The circuit to which the reverse bias is applied is included in the circuit shown in FIG. 42. As shown in FIG. 42, the gate electrode of the transistor AC-Tr can be connected to the target terminal GATE of the circuit shown in FIG. 42. Further, Figures 8A to 8C The circuit to which the reverse bias is applied is included in the circuit shown in FIG. 42. As shown in FIG. 42, the gate electrode of the transistor AC-Tr can be connected to the target terminal GATE of the circuit shown in FIG. 42. Further,

[0207] Further, the transistors AC-Tr, AC-Trl, and AC-Tr2 are N-channel transistors. Thus, in the period in which H level is input to the bias terminal BIAS, the signal input to the signal terminal SIG is input to the transistors AC-Tr, AC-Trl, and AC-Tr2, and in the period in which L level is input to the bias terminal BIAS, the potential depending on the potential of L level is applied to the gate electrode of the transistors AC-Tr, AC-Trl, and AC-Tr2; thus, the reverse bias is applied.

[0208] Further, Figure 10E The circuit to which the reverse bias is applied is included in the circuit shown in FIG. 42. As shown in FIG. 42, the gate electrode of the transistor AC-Tr can be connected to the target terminal GATE of the circuit shown in FIG. 42. Further, Figure 9C The circuit to which the reverse bias is applied is included in the circuit shown in FIG. 42. As shown in FIG. 42, the gate electrode of the transistor AC-Tr can be connected to the target terminal GATE of the circuit shown in FIG. 42. Further, Figure 10E The gate electrode of the transistor AC-Tr can be connected to the target terminal GATE of the circuit shown. Figure 9C The gate electrode of the transistor AC-Tr can be connected to the target terminal GATE of the circuit shown. Figure 10F The transistors AC-Tr1 and AC-Tr2 to which a reverse bias is applied are included in the circuit shown. Figure 9C The gate electrode of the transistor AC-Tr can be connected to the target terminal GATE of the circuit shown. Figure 10F The gate electrode of the transistor AC-Tr can be connected to the target terminal GATE of the circuit shown. Figure 9C The gate electrode of the transistor AC-Tr can be connected to the target terminal GATE of the circuit shown.

[0209] Here, the transistors AC-Tr, AC-Tr1, and AC-Tr2 constitute a part of a circuit having a certain function, as a whole like the transistors 33 and 37 in FIG. 1 or the transistors 43 and 47a in FIG. 2, in which the circuit of the present application to which a reverse bias is applied does not depend on one of each source electrode and each drain electrode of the transistors AC-Tr, AC-Tr1, and AC-Tr2. Figures 7A to 7C Figures 8A to 8C In addition, the transistors AC-Tr, AC-Tr1, and AC-Tr2 are P-channel transistors. Thus, in a period in which an L level is input to the bias terminal BIAS, a signal input to the signal terminal SIG is input to the transistors AC-Tr, AC-Tr1, and AC-Tr2, and in a period in which an H level is input to the bias terminal BIAS, a potential depending on the H level is applied to the gate electrodes of the transistors AC-Tr, AC-Tr1, and AC-Tr2; thus, a reverse bias is applied.

[0210] In addition, the transistors AC-Tr, AC-Tr1, and AC-Tr2 are P-channel transistors. Thus, in a period in which an L level is input to the bias terminal BIAS, a signal input to the signal terminal SIG is input to the transistors AC-Tr, AC-Tr1, and AC-Tr2, and in a period in which an H level is input to the bias terminal BIAS, a potential depending on the H level is applied to the gate electrodes of the transistors AC-Tr, AC-Tr1, and AC-Tr2; thus, a reverse bias is applied.

[0211] In addition, the transistors AC-Tr, AC-Tr1, and AC-Tr2 are P-channel transistors. Thus, in a period in which an L level is input to the bias terminal BIAS, a signal input to the signal terminal SIG is input to the transistors AC-Tr, AC-Tr1, and AC-Tr2, and in a period in which an H level is input to the bias terminal BIAS, a potential depending on the H level is applied to the gate electrodes of the transistors AC-Tr, AC-Tr1, and AC-Tr2; thus, a reverse bias is applied. Figure 10G In addition, the transistors AC-Tr, AC-Tr1, and AC-Tr2 are P-channel transistors. Thus, in a period in which an L level is input to the bias terminal BIAS, a signal input to the signal terminal SIG is input to the transistors AC-Tr, AC-Tr1, and AC-Tr2, and in a period in which an H level is input to the bias terminal BIAS, a potential depending on the H level is applied to the gate electrodes of the transistors AC-Tr, AC-Tr1, and AC-Tr2; thus, a reverse bias is applied. Figure 9D The gate electrode of the transistor AC-Tr can be connected to the target terminal GATE of the circuit shown. Figure 10G The gate electrode of the transistor AC-Tr can be connected to the target terminal GATE of the circuit shown. FIG. 9D The gate electrode of the transistor AC-Tr can be connected to the target terminal GATE of the circuit shown.

[0212] In addition, the transistors AC-Tr, AC-Tr1, and AC-Tr2 are P-channel transistors. Thus, in a period in which an L level is input to the bias terminal BIAS, a signal input to the signal terminal SIG is input to the transistors AC-Tr, AC-Tr1, and AC-Tr2, and in a period in which an H level is input to the bias terminal BIAS, a potential depending on the H level is applied to the gate electrodes of the transistors AC-Tr, AC-Tr1, and AC-Tr2; thus, a reverse bias is applied. FIG. 10H The transistors AC-Tr1 and AC-Tr2 to which a reverse bias is applied are included in the circuit shown. FIG. 9D The gate electrode of the transistor AC-Tr can be connected to the target terminal GATE of the circuit shown. FIG. 10H The gate electrode of the transistor AC-Tr can be connected to the target terminal GATE of the circuit shown. FIG. 9D The gate electrode of the transistor AC-Tr can be connected to the target terminal GATE of the circuit shown. FIG. 7A to 7C Here, the transistors AC-Tr, AC-Tr1, and AC-Tr2 constitute a part of a circuit having a certain function, as a whole like the transistors 33 and 37 in FIG. 1 or the transistors 43 and 47a in FIG. 2, in which the circuit of the present application to which a reverse bias is applied does not depend on one of each source electrode and each drain electrode of the transistors AC-Tr, AC-Tr1, and AC-Tr2. FIG. 8A to 8C ​transistors 43 and 47a in which reverse bias is applied, the circuit of the present application does not depend on one of each source electrode and each drain electrode of the transistors AC-Tr, AC-Trl, and AC-Tr2.

[0213] In addition, the transistors AC-Tr, AC-Trl, and AC-Tr2 are P-channel transistors. Thus, in a period in which an L level is input to the bias terminal BIAS, a signal input to the signal terminal SIG is input to the transistors AC-Tr, AC-Trl, and AC-Tr2, and in a period in which an H level is input to the bias terminal BIAS, a potential depending on the H level is applied to the gate electrodes of the transistors AC-Tr, AC-Trl, and AC-Tr2; thus, reverse bias is applied.

[0214] Then, referring to FIG. 11A to 11C and FIG. 12 , the circuit of the present application is described in which the signal line for the reset operation is added to the circuit in which reverse bias is applied. FIG. 7A , FIG. 8A and FIG. 8C illustrate the shift register circuit of the present application.

[0215] FIG. 11A , 11B and 11C each illustrate a configuration in which the signal line RES for the reset operation and the transistor RE(k) (k is an integer from 1 to n (including n)) connecting the signal line RES are added to FIG. 7A , FIG. 8A , and FIG. 8C show a configuration of each of the configurations. The gate electrode of the transistor RE(k) is connected to the signal line RES, one of the source electrode and the drain electrode of the transistor RE(k) is connected to the signal line RES, and the other of the source electrode and the drain electrode of the transistor RE(k) is connected to the electrode SR(k).

[0216] FIG. 11A to 11C The shift register circuit is described in which the transistor RE(k) is additionally connected to each stage, so that all stages can be reset at an arbitrary time, which can return to the initial state before the operation of the final stage. However, the present application is not limited to this, and the number of the transistors RE(k) is arbitrary. For example, the transistor RE is provided only in the final stage, the transistor RE is provided only on the odd-numbered stages or only on the even-numbered stages, or the transistor RE is provided only on the upper half stages or only on the lower half stages. There is an advantage in reducing the number of the transistors RE, so that the circuit scale is smaller; thus, the percentage of the circuit occupying the substrate is reduced. In addition, when the number of the transistors RE is reduced, the load of driving the signal line RES and the power consumption can be reduced, which is advantageous.

[0217] Here, referring to FIG. 12 , the operation of the shift register circuit of the present application in which a signal line for a reset operation is added is described. FIG. 12 is a time chart of the changes in the potential of the input signal SP, the terminal P (not shown in the time chart), and the output terminal L at the time Tl when a pulse is input to the signal line RES to reset all stages and at the time T2 when the potential of the signal line RB is decreased to perform a reverse bias application operation. When a start pulse is input at the time TO, the same operation as FIG. 1C is performed until a pulse is input to the signal line RES. However, when a pulse is input to the signal line RES at the time Tl, the potential of the electrode SR of all stages is at the H level; thus, the output terminal L and the terminal P are fixed at the L level. Here, the transistor 36 or 46 for changing the potential of the electrode SR to the L level is turned off because the potential of the terminal P becomes the L level. Therefore, a path through which current flows from the signal line RES to the power supply line Vss when a pulse is input to the signal line RES is not formed.

[0218] Then, during the period between the time T2 and the time T3, a reverse bias is applied by decreasing the potential of the signal line RB. Here, the potential of the signal line RB is preferably lower than the potential of the power supply line Vss. In addition, during the period between the time T3 and the time T4, the potentials of the signal line RB and the signal line RES can be set at the H level for subsequently performing a reset operation again. When another reset operation is performed after the application of the reverse bias, the potentials of the electrode S, the terminal R, and the electrode SR are set at the H level; thus, the potential of the output terminal L is fixed at the L level, so that the period during which the change in the potential of the output is suppressed can be extended.

[0219] Thus, as for the shift register circuit of the present application in FIG. 11A to 11C , a signal line for a reset operation is added in each shift register circuit, all stages can be reset at any time, it can return to the initial state before the operation of the final stage is performed and a reverse bias can be applied at any time. In the case where the shift register circuit is used as a drive circuit of a display device, for example, it is advantageous to stop the operation of the shift register circuit by not using the pixels of the area which is not to be used by arranging only the pixels in a part of the display area, which results in the advantages of reduced power consumption and reduced threshold voltage drift of the transistors. In addition, when a pulse is input to the signal line RES, the floating electrode SR is charged, so that the decrease in the potential of the electrode SR due to a leakage current can be prevented. In particular, the transistor having the gate electrode connected to the electrode SR can easily maintain the advantage of being in the on state.

[0220] Then, with reference to FIG. 13A to 13C , a circuit which performs a reset operation other than a reverse bias operation by adding only one signal line to the shift register circuit shown in FIG. 7A to 7C is described.

[0221] FIG. 13A This is a general diagram of the shift register circuit of the present invention. FIG. 13B This describes a single stage of the shift register circuit of the present invention. FIG. 13C This is a timing diagram of the input and output signals of the shift register circuit of the present invention.

[0222] FIG. 13B This explains the changes made to the connection of transistor 39a (corresponding to transistor 59a) and the addition of terminal M. FIG. 7B The circuit shown is a circuit diagram. Here, transistors 51, 52, 53, 55, 56, 57, and 59b and capacitor element 54 correspond to respectively FIG. 7B Transistors 31, 32, 33, 35, 36, 37, and 39b and capacitor 34 are connected in the following manner: FIG. 7B The display is the same. Additionally, the connection relationships have been changed. FIG. 13B The gate electrode of transistor 59a is connected to terminal M, one of the source electrode and drain electrode of transistor 59a is connected to terminal S, and the other of the source electrode and drain electrode of transistor 59a is connected to terminal N.

[0223] FIG. 13A The instruction specifies that the signal line BL should be replaced. FIG. 7A The signal line RB of the displayed circuit and the signal line BE connected to terminal M of circuit 50 in each stage are added to... FIG. 7A The circuit shown is the circuit diagram. Additionally, transistor 58 corresponds to... FIG. 7A The transistors 38 have similar connections.

[0224] Here, refer to FIG. 13C describe FIG. 13A and 13B The circuit operation is shown. During normal operation, a potential of level H is input to signal line BL, and a potential of level L is input to signal line BE. Here, transistor 59b is in the on state, and transistor 59a is in the off state. Specifically, terminal R and electrode S are in a conductive state, and terminal N and electrode S are in a non-conductive state; therefore... FIG. 13B Connection status and FIG. 1B Similar, therefore FIG. 13A to 13C The shift register circuit with FIG. 1A to 1C It runs in the same way as shown.

[0225] Then, as FIG. 13C As shown, after completion FIG. 13A The potential of the signal line BE can be raised between time Tl and time T4 after the normal operation period of the shift register shown in FIG. 6. This period is called a biasing start period. During the biasing start period, the transistor 59a is in an on state. The period in the biasing start period in which the potential of the signal line BL is at the H level (between time Tl and time T2, and between time T3 and T4) is called a reset period. During the reset period, the transistors 59a and 59b are in on states, and the potential of the terminal N is at the H level; thus, the potentials of the electrode S, the terminal R, and the electrode SR connected to the terminal R become the H level. That is, a reset operation can be performed. Also, the period in the biasing start period in which the potential of the signal line BL is at the L level (between time T2 and time T3) is a reverse bias application period. During the reverse bias application period, the transistor 59b is off, and the transistor 59a is on. Specifically, the terminal R and the electrode S are in a non-conductive state, and the terminal N and the electrode S are in a conductive state, so that the potential of the electrode S becomes the L level in accordance with the potential of the electrode N. Thus, since the transistor 59b is in a non-conductive state, the potential of the terminal N is not transmitted to the terminal R. Here, the potential of the signal line BL is lower than the potential of the power supply line Vss. If the low potential of the signal line RB is lower than the potential of the power supply line Vss, the potential of the electrode S can be further lowered during the reverse bias application period. Thus, a potential of an opposite polarity in an on state can be applied to the gate electrodes of the transistors 53 and 57, so that the threshold shift of the transistors can be reduced. FIG. 13B

[0226] As described above, as for the shift register circuit of the present application shown in FIG. 6, the normal operation period and the biasing start period can be arbitrarily provided by the signal line BE. Also, during the biasing start period, if the potential of the signal line BL is at the H level, the circuit 50 is subjected to a reset operation; at the same time, if the potential of the signal line BL is at the L level, a reverse bias can be applied to the transistors 53 and 57. Moreover, lowering the potential of the signal line BL does not change the potentials of the other electrodes compared to the electrode S; thus, the occurrence of a failure such as a constant current flow and an accident can be reduced. Note that the potential of the electrode S can be freely set during the biasing start period. FIG. 13A to 13C

[0227] Then, with reference to FIG. 7, a circuit in which a reset operation in addition to a reverse bias operation is performed by adding only one signal line to the shift register circuit shown in FIG. 6 will be described. FIG. 14A to 14C FIG. 8A to 8C A circuit in which a reset operation in addition to a reverse bias operation is performed by adding only one signal line to the shift register circuit shown in FIG. 6 will be described. FIG. 8A to 8C

[0228] FIG. 14A is a full circuit diagram of the shift register circuit of the present application, FIG. 14B FIG. 6 is a single-stage circuit diagram of the shift register circuit of the present application, FIG. 14C ​​​​This is another full diagram of the shift register circuit of the present invention. FIG. 14B This explains the changes in the connection of transistor 39a (corresponding to transistor 59a) and the direction... FIG. 7B The circuit shown includes terminal M. Additionally, transistors 61, 62, 63, 65, 66, 67a, 67b, 67c, 69b, and 69d, and capacitor 64 correspond to... FIG. 8B The transistors 41, 42, 43, 45, 46, 47a, 47b, 47c, 49b, and 49d, and capacitor 44 are connected in the following manner: FIG. 8B same.

[0229] in addition, FIG. 14B In transistor 69a, the gate electrode is connected to terminal M, one of the source and drain electrodes of transistor 69a is connected to terminal S, and the other of the source and drain electrodes of transistor 69a is connected to terminal N. Similarly, in transistor 69c, the gate electrode is connected to terminal M, one of the source and drain electrodes of transistor 69a is connected to terminal U, and the other of the source and drain electrodes of transistor 69a is connected to terminal N.

[0230] here, FIG. 14A This indicates that the signal line RB connecting terminal N of circuit 40 in each stage is applied to... FIG. 8A The circuit shown is the circuit diagram. Additionally, transistor 68 corresponds to... FIG. 8A The transistor 48 has a similar connection. Additionally, FIG. 14C The power supply line Vdd is connected to... FIG. 14A The circuit shown is connected to the power supply line Vdd, which is connected to the terminal V of the circuit of all stages of the circuit 60.

[0231] Here, according to FIG. 13C The displayed timeline is running FIG. 14A The circuits shown are 14B and 14C. According to... FIG. 13C The displayed schedule runs FIG. 14A In the case of the circuits shown in 14B and 14C, during the normal operating cycle, a potential of level H is input to signal line BL, and a potential of level L is input to signal line BE. Here, transistors 69b and 69d are in the on state, and transistors 69a and 69c are in the off state. Specifically, terminals R and electrode S, and terminals Q and electrode U are in the conductive state, while terminals N and electrode S, and terminals N and electrode U are in the non-conductive state; therefore, FIG. 14B Connection status and FIG. 2B Similar, therefore FIG. 14A to 14C shift register circuit with FIG. 2A to 2C It runs in the same way as shown.

[0232] Then, during the biasing-on period, a reset period can be provided by raising the potential of the signal line BL to the H level, and a reverse bias application period can be provided by lowering the potential of the signal line BL to the L level. In the reset period, the transistors 69a, 69b, 69c, and 69d are all turned on, and the terminal N is at the H level; thus, the circuit 60 is reset. On the other hand, in the reverse bias application period, the transistors 69b and 69d are turned off, and the transistors 69a and 69c are turned on. That is, the terminals R and S, the terminals Q and U are in a non-conductive state, and the terminals N and S, and the terminals N and U are in a conductive state; thus, the potentials of the electrodes S and U are lowered because the potential of the terminal N is low. Here, the potential of the signal line BL can be lower than the potential of the power supply line Vss. When the low potential of the signal line BL is lower than the potential of the power supply line Vss, the potential of the electrode S can be further lowered during the reverse bias application period. Thus, a potential of the opposite polarity to the case of the on state can be applied to the gate electrodes of the transistors 63 and 67a, and thus the threshold shift of the transistors can be reduced. FIG. 14B

[0233] As described above, as for the shift register circuit of the present application shown in FIG. 14A to 14C , the normal operation period and the biasing-on period can be arbitrarily provided by the signal line BE. In addition, in the biasing-on period, if the potential of the signal line BL is at the H level, the circuit 60 is subjected to the reset operation; at the same time, if the potential of the signal line BL is at the L level, a reverse bias can be applied to the transistors 63 and 67a. Further, lowering the potential of the signal line BL does not change the potentials of the other electrodes than the electrodes S and U; thus, the flow of a constant current and the occurrence of a failure can be reduced. Note that in the biasing-on period, the potentials of the electrodes S and U can be freely set.

[0234] Here, any of the gate electrodes of any of the transistors of any circuit other than the circuits shown in FIG. 13A to 13C and 14A to 14C can be connected to the circuit shown in FIG. 15A to 15D , so that a forward bias is applied to the transistors instead of a reverse bias. Since the circuit shown in FIG. 15A to 15D does not change the potentials of any of the electrodes in the circuit other than the gate electrodes of the transistors when a reverse bias is applied; thus, the threshold shift of the transistors can be reduced without the flow of a constant current or the occurrence of a failure. When a forward bias is applied, the turned-off transistor SIG-Tr is turned on; thus, the potential of the electrode connected to the signal terminal SIG and the signal terminal SIG can be initialized or reset.

[0235] FIG. 15A to 15D The circuits shown in 14A to 14C each have a signal terminal SIG, a bias terminal BIAS, a target terminal GATE, a turned-off transistor SIG-Tr, and a bias transistor BIAS-Tr. In the circuit shown in 14A, the gate electrode of the transistor 63 is connected to the signal line BE, and the gate electrode of the transistor 67a is connected to the signal line BL. In the circuit shown in 14B, the gate electrode of the transistor 63 is connected to the signal line BL, and the gate electrode of the transistor 67a is connected to the signal line BE. In the circuit shown in 14C, the gate electrode of the transistor 63 is connected to the signal line BE, and the gate electrode of the transistor 67a is connected to the signal line BE.​ FIG. 15A In the circuit shown in FIG. 15B, 15C, and 15D, the gate electrode of the cutoff transistor SIG-Tr is connected to the bias terminal BIAS, one of the source electrode and the drain electrode of the cutoff transistor SIG-Tr is connected to the signal terminal SIG, and the other of the source electrode and the drain electrode of the cutoff transistor SIG-Tr is connected to the target terminal GATE.

[0236] In FIG. 15A In the circuit shown in FIG. 15B, 15C, and 15D, the gate electrode of the bias transistor BIAS-Tr is connected to the selection terminal BE-SW, one of the source electrode and the drain electrode of the bias transistor BIAS-Tr is connected to the target terminal GATE, and the other of the source electrode and the drain electrode of the bias transistor BIAS-Tr is connected to the bias terminal BIAS.

[0237] The target terminal GATE is connected to a transistor to which a reverse bias is applied. It is suitable to apply a reverse bias between the gate electrode and the source electrode of the transistor and between the gate electrode and the drain electrode of the transistor. Therefore, it is preferable to connect the target terminal GATE to the gate electrode of the transistor to which a reverse bias is applied. However, the present application is not limited to this, and the target terminal GATE can be connected to the source electrode or the drain electrode of the transistor to which a reverse bias is applied. At this time, the polarity of the bias to which a reverse bias is applied can be opposite to the case where the target terminal GATE is connected to the gate electrode. Note that the number of transistors to which the target terminal GATE is connected is arbitrary.

[0238] The signal terminal SIG is connected to a signal line or a power supply line input to the transistor when the transistor is normally operated. The selection terminal BE-SW is a signal line for selecting whether or not the potential of the bias terminal BIAS is transmitted to the target terminal GATE. The bias terminal BIAS is a signal line for controlling the potential applied to the target terminal GATE when the bias transistor BIAS-Tr is in an on state. The bias terminal BIAS is a signal line for controlling whether or not the signal terminal SIG and the target terminal GATE are connected or disconnected when the bias transistor BIAS-Tr is in an off state.

[0239] Here, the polarity of the cutoff transistor SIG-Tr and the polarity of the bias transistor BIAS-Tr are classified FIG. 15A In the circuit shown in FIG. 15B, 15C, and 15D.

[0240] FIG. 15A A circuit in which a potential of the H level is applied to the bias terminal BIAS and a potential of the H level is applied to the selection terminal BE-SW at the time of normal operation, a potential of the H level is applied to the bias terminal BIAS and a potential of the L level is applied to the selection terminal BE-SW at the time of reset operation, and a potential of the L level is applied to the bias terminal BIAS and a potential of the H level is applied to the selection terminal BE-SW at the time of application of reverse bias is described. This circuit can be used, for example, when the electrode on which reverse bias is applied is the gate electrode of an n-channel transistor.

[0241] FIG. 15B A circuit in which a potential of the H level is applied to the bias terminal BIAS and a potential of the H level is applied to the selection terminal BE-SW at the time of normal operation, a potential of the H level is applied to the bias terminal BIAS and a potential of the L level is applied to the selection terminal BE-SW at the time of reset operation, and a potential of the L level is applied to the bias terminal BIAS and a potential of the H level is applied to the selection terminal BE-SW at the time of application of reverse bias is described. This circuit can be used, for example, when the electrode on which reverse bias is applied is the gate electrode of an n-channel transistor.

[0242] FIG. 15C A circuit in which a potential of the H level is applied to the bias terminal BIAS and a potential of the H level is applied to the selection terminal BE-SW at the time of normal operation, a potential of the H level is applied to the bias terminal BIAS and a potential of the L level is applied to the selection terminal BE-SW at the time of reset operation, and a potential of the L level is applied to the bias terminal BIAS and a potential of the H level is applied to the selection terminal BE-SW at the time of application of reverse bias is described. This circuit can be used, for example, when the electrode on which reverse bias is applied is the gate electrode of an n-channel transistor.

[0243] FIG. 15D A circuit in which a potential of the H level is applied to the bias terminal BIAS and a potential of the H level is applied to the selection terminal BE-SW at the time of normal operation, a potential of the H level is applied to the bias terminal BIAS and a potential of the L level is applied to the selection terminal BE-SW at the time of reset operation, and a potential of the L level is applied to the bias terminal BIAS and a potential of the H level is applied to the selection terminal BE-SW at the time of application of reverse bias is described. This circuit can be used, for example, when the electrode on which reverse bias is applied is the gate electrode of an n-channel transistor.

[0244] Thus, using the embodiment mode shown FIG. 15A to 15D The circuit shown, without changing the potentials of the other electrodes in the circuit, can apply reverse bias to the gate electrode of any transistor in any circuit. In addition, forward bias can be applied to the signal terminal SIG and the target terminal GATE.

[0245] Then, referring to FIG. 16A to 16H the transistor on which the reverse bias is applied is included in FIG. 15A to 15D the circuit shown.

[0246] FIG. 16A the circuit including the transistor AC-Tr on which the reverse bias is applied is added to FIG. 15A the circuit shown. As FIG. 16A shown, the gate electrode of the transistor AC-Tr can be connected to FIG. 15A the target terminal GATE of the circuit shown. FIG. 16B the circuit including the transistors AC-Trl and AC-Tr2 on which the reverse bias is applied is added to FIG. 15A the circuit shown. As FIG. 16B shown, the gate electrodes of the transistors AC-Trl and AC-Tr2 can be connected to FIG. 15A the target terminal GATE of the circuit shown.

[0247] Here, the transistors AC-Tr, AC-Trl, and AC-Tr2 constitute a part of the circuit having a certain function, and as a whole are like the transistors 53 and 57 in FIG. 13A to 13C and the transistors 63 and 67a of FIG. 14A to 14C wherein the circuit of the present application on which the reverse bias is applied does not depend on one of each source electrode and each drain electrode of the transistors AC-Tr, AC-Trl, and AC-Tr2.

[0248] In addition, the transistors AC-Tr, AC-Trl, and AC-Tr2 are N-channel transistors. Thus, in the period in which the H level is input to the bias terminal BIAS and the L level is input to the selection terminal BE-SW, the signal input to the signal terminal SIG is input to the transistors AC-Tr, AC-Trl, and AC-Tr2, and in the period in which the L level is input to the bias terminal BIAS and the H level is input to the selection terminal BE-SW, the potential depending on the potential of the electric potential of the L level of the bias terminal BIAS is applied to the gate electrodes of the transistors AC-Tr, AC-Trl, and AC-Tr2; thus, the reverse bias is applied. In addition, in the period in which the H level is input to the bias terminal BIAS and the H level is input to the selection terminal BE-SW, the potential depending on the potential of the electric potential of the H level of the bias terminal BIAS can be applied to the gate electrodes of the transistors AC-Tr, AC-Trl, and AC-Tr2.

[0249] In addition, FIG. 16C the circuit including the transistor AC-Tr on which the reverse bias is applied is added to FIG. 15B the circuit shown. As FIG. 16C shown, the gate electrode of the transistor AC-Tr can be connected to FIG. 15B The gate terminal GATE of the circuit shown.

[0250] Further, FIG. 16D The transistors AC-Tr1 and AC-Tr2 on which the reverse bias is applied are included in the circuit of the FIG. 15B circuit shown. As shown in FIG. 16D the gate electrode of the transistor AC-Tr1 and AC-Tr2 can be connected to the FIG. 15B gate terminal GATE of the circuit shown. Here, for example, the transistors AC-Tr, AC-Tr1, and AC-Tr2 constitute a part of the circuit having a certain function as a whole like the transistors 53 and 57 in FIG. 13A to 13C or the transistors 63 or 67a of FIG. 8A to 8C the present application, the circuit on which the reverse bias is applied does not depend on one of each source electrode and each drain electrode of the transistors AC-Tr, AC-Tr1, and AC-Tr2.

[0251] Further, the transistors AC-Tr, AC-Tr1, and AC-Tr2 are N-channel transistors. Thus, in the period in which H level is input to the bias terminal BIAS and H level is input to the selection terminal BE-SW, the signal input to the signal terminal SIG is input to the transistors AC-Tr, AC-Tr1, and AC-Tr2, and in the period in which L level is input to the bias terminal BIAS and L level is input to the selection terminal BE-SW, the potential depending on the L level of the bias terminal BIAS is applied to the gate electrode of the transistors AC-Tr, AC-Tr1, and AC-Tr2; thus, the reverse bias is applied. Further, in the period in which H level is input to the bias terminal BIAS and L level is input to the selection terminal BE-SW, the potential of the potential depending on the H level of the bias terminal BIAS can be applied to the gate electrode of the transistors AC-Tr, AC-Tr1, and AC-Tr2.

[0252] Further, FIG. 16E The transistor AC-Tr on which the reverse bias is applied is added to the circuit of the FIG. 15C circuit shown. As shown in FIG. 16E the gate electrode of the transistor AC-Tr can be connected to the FIG. 15C gate terminal GATE of the circuit shown.

[0253] Further, FIG. 16F The transistors AC-Tr1 and AC-Tr2 on which the reverse bias is applied are included in the circuit of the FIG. 15C circuit shown. As shown in FIG. 16F the gate electrode of the transistors AC-Tr1 and AC-Tr2 can be connected to the FIG. 15C gate terminal GATE of the circuit shown.

[0254] Here, transistors AC-Tr, AC-Tr1, and AC-Tr2 form part of a circuit with a specific function, and as a whole, they are like... FIG. 13A to 13C Transistors 53 and 57 in FIG. 14A to 14C The transistors 63 and 67a, wherein the circuit of the present invention with reverse bias applied does not depend on one of the source electrodes and one of the drain electrodes of transistors AC-Tr, AC-Tr1, and AC-Tr2.

[0255] Furthermore, transistors AC-Tr, AC-Tr1, and AC-Tr2 are P-channel transistors. Therefore, during the cycles of L-level input to the bias terminal BIAS and L-level input to the select terminal BE-SW, the signal input to the signal terminal SIG is applied to transistors AC-Tr, AC-Tr1, and AC-Tr2. During the cycles of H-level input to the bias terminal BIAS and H-level input to the select terminal BE-SW, a potential depending on the H-level potential of the bias terminal BIAS is applied to the gate electrodes of transistors AC-Tr, AC-Tr1, and AC-Tr2; thus, a reverse bias is applied. Additionally, during the cycles of L-level input to the bias terminal BIAS and H-level input to the select terminal BE-SW, a potential depending on the L-level potential of the bias terminal BIAS can be applied to the gate electrodes of transistors AC-Tr, AC-Tr1, and AC-Tr2.

[0256] in addition, FIG. 16G The description includes the AC-Tr transistor with reverse bias applied to it. FIG. 15D The circuit shown is the circuit of the circuit. For example... FIG. 16G As shown, the gate electrode of transistor AC-Tr can be connected to FIG. 15D The target terminal GATE of the circuit is shown.

[0257] in addition, FIG. 16H This indicates that the transistors AC-Tr1 and AC-Tr2, which are reverse biased, are contained within... FIG. 15D The circuit shown is the circuit of the circuit. For example... FIG. 16H As shown, the gate electrodes of transistors AC-Tr1 and AC-Tr2 can be connected to FIG. 15D The target terminal GATE of the circuit is shown. Here, transistors AC-Tr, AC-Tr1, and AC-Tr2 form part of a circuit with a specific function, and as a whole, they are like... FIG. 13A to 13C Transistors 53 and 57 in FIG. 14A to 14C The transistors 63 and 67a, wherein the circuit of the present invention with reverse bias applied does not depend on one of the source electrodes and one of the drain electrodes of transistors AC-Tr, AC-Tr1, and AC-Tr2.

[0258] Further, the transistors AC-Tr, AC-Trl, and AC-Tr2 are P-channel transistors. Thus, in a period in which an L level is input to the bias terminal BIAS and an H level is input to the selection terminal BE-SW, a signal input to the signal terminal SIG is input to the transistors AC-Tr, AC-Trl, and AC-Tr2, and in a period in which an H level is input to the bias terminal BIAS and an L level is input to the selection terminal BE-SW, a potential depending on the potential of the H level of the bias terminal BIAS is applied to the gate electrodes of the transistors AC-Tr, AC-Trl, and AC-Tr2; thus, reverse bias is applied. Further, in a period in which an L level is input to the bias terminal BIAS and an L level is input to the selection terminal BE-SW, a potential depending on the potential of the L level of the bias terminal BIAS can be applied to the gate electrodes of the transistors AC-Tr, AC-Trl, and AC-Tr2.

[0259] Note that the present embodiment mode can be freely combined with any of the other embodiment modes.

[0260] Embodiment Mode 4

[0261] In the present embodiment mode, a top view and sectional views of a case where a shift register circuit of the present application is formed by manufacturing elements on a substrate will be described with reference to the drawings. FIG. 17 The circuit 10 formed as an example of the shift register circuit of the present application using a top gate transistor as a transistor will be described. In FIG. 17 In the present embodiment mode, only the circuit 10 of the kth stage (shown as 10k) and the circuit 10 of the (k+l)th stage (shown as 10k+1) will be described. However, the present application is not limited to this, and the circuit 10 can have many stages. Further, FIG. 17 The transistors 11, 12, 13, 15, 16, and 17, the capacitor element 14, and the terminal P in the circuit 10 of FIG. 1A correspond to FIG. 1B The transistors 11, 12, 13, 15, 16, and 17, the capacitor element 14, and the terminal P in the circuit 10 of FIG. 1A. In order to reduce the layout area, the electrodes SR and the output terminal L arranged outside the circuit 10 of FIGs. 1A to 1C are arranged inside the circuit 10 of FIG. 1B. FIG. 17 Note that in the top view of the present embodiment mode, the area indicated by a broken line is an area in which another layer is present in the layer above the area.

[0262] In FIG. 17 In this embodiment mode, the power supply line Vss, the first clock signal line CLK1, and the second clock signal line CLK2 are provided outside the elements forming the circuit 10. Further, the power supply line Vss can be provided opposite the first clock signal line CLK1 and the second clock signal line CLK2. Thus, the power supply line Vss can be prevented from crossing the first clock signal line CLK1 and the second clock signal line CLK2; thus, the power supply line can be prevented from being affected by external noise, and the malfunction can be reduced.

[0263] In this embodiment mode, the power supply line Vss, the first clock signal line CLK1, and the second clock signal line CLK2 are provided outside the elements forming the circuit 10. Further, the power supply line Vss can be provided opposite the first clock signal line CLK1 and the second clock signal line CLK2. Thus, the power supply line Vss can be prevented from crossing the first clock signal line CLK1 and the second clock signal line CLK2; thus, the power supply line can be prevented from being affected by external noise, and the malfunction can be reduced.

[0264] Here, in the embodiment mode, a region in which the active layer region of the transistor overlaps with the gate electrode region is also referred to as a channel region. Further, one of the source and drain electrodes of the transistor separated by the channel region of the transistor is referred to as "one of the source and drain electrodes", and the other region separated by the channel region is referred to as "the other of the source and drain electrodes". Further, a direction of a tangent line of a boundary between one of the source and drain electrodes of the transistor or the other and the channel region of the transistor is referred to as a "channel width direction". Further, a direction perpendicular to the channel width direction is referred to as a "channel length direction". For example, in the transistor of the embodiment mode, when the boundary line between one of the source and drain electrodes of the transistor or the other and the channel region of the transistor is a curved line, the channel width direction and the channel length direction are changed depending on the boundary point.

[0265] In FIG. 17 In this embodiment mode, the channel length direction of the transistor 11 (indicated by Chl) and the channel length direction of the transistor 12 (indicated by Ch2) can be substantially perpendicular. With this structure, the area of the substrate occupied by the transistors 11 and 12 can be minimized, and the circuit size can be reduced.

[0266] Further, the channel length direction of the transistors 13 and 16 (indicated by Chl) can be substantially parallel to each other. They can share one source electrode or one drain electrode. Thus, the area of the substrate occupied by the transistors 13 and 16 can be minimized, and the circuit size can be reduced. Further, the channel length direction of the transistors 15 and 17 (indicated by Ch2) can be substantially parallel to each other, and they can share one source electrode or one drain electrode. Thus, the area of the substrate occupied by the transistors 15 and 17 can be minimized, and the circuit size can be reduced.

[0267] In addition, one of the electrodes in the capacitor element 14, the terminal P, can be composed of a gate electrode, and the other electrode in the capacitor element 14, the electrode connected to the output terminal L, can be composed of a wiring layer. In addition, in the case where the transistor is an n-channel transistor, the active layer of the transistor and the wiring layer connected to the output terminal L can be connected to each other, and the gate electrode composing the terminal P can be interposed between the active layer and the wiring layer to form the capacitor element 14. When the terminal P is composed of a gate electrode, when the potential of the terminal P becomes high, carriers are generated in the active layer connected to the output terminal L. Thus, the capacitance value of the capacitor element 14 formed of the active layer and the gate electrode can be increased.

[0268] Then, reference will be made to FIG. 18 A cross-sectional view along the line A-A' in FIG. 1 is shown. FIG. 17 The structure shown has a substrate 100, a base film 101, an active layer 102, an insulating film 103, gate electrodes 104 and 105, an interlayer film 106, and a wiring layer 108. In addition, the structure shown has a contact 107a and 107b connecting the wiring layer 108 and the active layer 102, and a contact 107c connecting the wiring layer 108 and the gate electrode 104. The structure shown will be described step by step. FIG. 18 The structure shown has a substrate 100, a base film 101, an active layer 102, an insulating film 103, gate electrodes 104 and 105, an interlayer film 106, and a wiring layer 108. In addition, the structure shown has a contact 107a and 107b connecting the wiring layer 108 and the active layer 102, and a contact 107c connecting the wiring layer 108 and the gate electrode 104. The structure shown will be described step by step. FIG. 18 The structure shown has a substrate 100, a base film 101, an active layer 102, an insulating film 103, gate electrodes 104 and 105, an interlayer film 106, and a wiring layer 108. In addition, the structure shown has a contact 107a and 107b connecting the wiring layer 108 and the active layer 102, and a contact 107c connecting the wiring layer 108 and the gate electrode 104. The structure shown will be described step by step. FIG. 18 The structure shown has a substrate 100, a base film 101, an active layer 102, an insulating film 103, gate electrodes 104 and 105, an interlayer film 106, and a wiring layer 108. In addition, the structure shown has a contact 107a and 107b connecting the wiring layer 108 and the active layer 102, and a contact 107c connecting the wiring layer 108 and the gate electrode 104. The structure shown will be described step by step.

[0269] First, the substrate 100 can be a glass substrate formed of barium borosilicate glass, aluminum borosilicate glass, or the like, a quartz substrate, a silicon substrate, a metal substrate, a stainless steel substrate, or a plastic substrate. In addition, the substrate 100 can be polished by CMP or the like to planarize the surface of the substrate 100.

[0270] Then, the base film 101 is formed on the substrate 100. The base film 101 can be formed by a single layer or a stack of layers of aluminum nitride (AIN), silicon oxide (SiO2), silicon oxynitride (SiOxNy), or the like by a known method such as CVD, plasma CVD, sputtering, or spin coating. Note that the base film 101 has a function of blocking the entry of impurities such as contaminants into the substrate 100. When the base film 101 is not formed, the manufacturing process is simplified, and the cost is reduced.

[0271] Then, the active layer 102 is formed on the substrate 100 or the base film 101. Here, the active layer 102 can be formed of polycrystal silicon (p-Si). The active layer 102 can be selectively formed into a desired shape by a photolithography method, a droplet discharge method, a printing method, or the like.

[0272] Then, an insulating film 103 is formed on the substrate 100, the base film 101, or the active layer 102. Here, the insulating film 103 can be formed of silicon oxide (SiO2) or silicon oxynitride (SiOxNy).

[0273] Then, gate electrodes 104 and 105 are formed on the substrate 100, the base film 101, the active layer 102, or the insulating film 103. Here, the gate electrodes 104 and 105 can be selectively formed of various metals in a desired shape by photolithography, a droplet discharge method, a printing method, or the like. Thus, in the case where the gate electrodes 104 and 105 are processed by etching using photolithography or the like, etching is performed so as to obtain etching selectivity between the gate electrodes 104 and 105; thus, the gate electrode 104 and the gate electrode 105 can be formed to have different areas without changing a photomask. Thus, in the case where the conductivity of the active layer 102 is controlled by adding charged particles to the active layer 102, an LDD region can be formed in the active layer 102 without changing a photomask. Therefore, a transistor in which a high electric field is hardly applied and degradation due to a hot carrier is small can be manufactured.

[0274] Then, an interlayer film 106 is formed on the substrate 100, the base film 101, the active layer 102, the insulating film 103, or the gate electrodes 104 and 105. Here, the interlayer film 106 can be formed of an insulating material such as silicon oxide, silicon resin nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, or another inorganic insulating material; acrylic acid or methacrylic acid, or a derivative thereof; a heat-resistant polymer such as polyimide, aramid, polybenzimidazole; or a silicone resin. Note that the silicone resin relates to a resin having a Si-O-Si bond. The skeleton structure of the silicone is formed of a bond of silicon (Si) and oxygen (O). An organic group (e.g., an alkyl group or an aromatic hydrocarbon) containing at least hydrogen is used as a substituent. A fluoro group can also be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group can be used as a substituent. When the interlayer film is formed of a photosensitive or non-photosensitive material such as acrylic acid or polyimide, the interlayer film has a curved side surface in which a radius of curvature continuously changes, and the film formed thereon is preferably formed without being separated. In addition, the interlayer film 106 can be formed in a desired shape by photolithography, a droplet discharge method, a printing method, or the like. Here, the interlayer film 106 can be processed by etching so as to stop etching before the insulating film 103 is processed like the contact 107a and 107b while etching the gate electrodes 104 and 105 like the contact 107c. Then, a wiring layer 108 is formed so that the active layer 102 is connected to the gate electrodes 104 and 105.

[0275] A wiring layer 108 is formed on the substrate 100, the base film 101, the active layer 102, the insulating film 103, the gate electrodes 104 and 105, or the interlayer film 106. Here, a composition containing a metal particle such as Ag (silver), Au (gold), Cu (copper), W (tungsten), or Al (aluminum) as a main component is used as a material for forming the wiring layer 108. In addition, a light-transmissive material such as indium tin oxide (ITO), ITO containing silicon oxide (ITSO), organic indium, organic tin, zinc oxide, titanium nitride can be combined. In addition, the wiring layer 108 can be formed into a desired shape by a photolithography method, a droplet discharge method, a printing method, or the like.

[0276] Then, a case where the shapes of the transistors 13 and 17 are designed to keep the potential of the electrode SR at the H level according to the FIG. 19 top view of the circuit 10 is described. FIG. 19 The circuit 10 shown in the top view of the FIG. 17 has the transistors 11, 12, 13, 15, 16, and 17, and the capacitor element 14, the connection relationship is also similar; however, the areas of the channel regions of the transistors 13 and 17 are different. Thus, when the average of the areas of the gate electrodes of the transistors 13 and 17 is made larger than that of the transistor 12 of the circuit 10, the value of the parasitic capacitance associated with the electrode SR can be made larger; thus, the potential of the electrode SR can be maintained at the H potential even after the reset operation. In addition, as shown in the FIG. 19 , the electrode SR is made into a curved line so as not to form a line shape in the circuit 10. Thus, the length of the electrode SR can be made longer than the interval between the k-th stage circuit 10 and the (k+l)-th stage circuit 10. Therefore, the value of the parasitic capacitance associated with the electrode SR can be increased so that the potential of the electrode SR is maintained at the H level even after the reset operation.

[0277] Then, a case where the cross capacitance of the clock signal line and the output terminal L is removed so that the output terminal L is not affected by the change in the potential of the clock signal line is described with reference to the FIG. 20 top view. FIG. 20 The circuit 10 shown in the top view of the FIG. 17 and FIG. 19 has the transistors 11, 12, 13, 15, 16, and 17, the capacitor element 14, the terminal P, the electrode SR, and the output terminal L, the connection relationship is also similar; however, the first clock signal line CLK1, the second clock signal line CLK2, and the arrangement of the transistors 11 and 12 are different from those of the FIG. 17 and FIG. 19 .

[0278] In the FIG. 20 In this case, the power supply line Vss, the first clock signal line CLK1, and the second clock signal line CLK2 are formed by the wiring layer, and are provided in a direction extending substantially in parallel to the circuit 10 (shown as 10ext). Thus, in the case where a plurality of circuits 10 are provided, the length of the wiring leading to the power supply line increases and thus the wire resistance increases, and thus malfunction and an increase in power consumption due to a voltage drop in the power supply line can be prevented. In addition, malfunction due to distortion of the signal waveform can be suppressed, and the reduction in the operating voltage range in which the circuit normally operates can be suppressed.

[0279] The power supply line Vss, the first clock signal line CLK1, and the second clock signal line CLK2 can be provided outside the elements forming the circuit 10. In addition, the power supply line Vss, the first clock signal line CLK1, and the second clock signal line CLK2 can be provided on the same side as the side on which the output terminal L is provided, with respect to the first transistor, the third transistor, the second transistor, and the fourth transistor. Thus, the output terminal L can be prevented from crossing the first clock signal line CLK1 and the second clock signal line CLK2; thus, the power supply line can be prevented from being affected by noise from the clock signal lines and malfunction can be reduced.

[0280] In addition, the channel length direction of the transistor 11 (shown as Chl) and the channel length direction of the transistor 12 (shown as Ch2) can be substantially parallel. With this structure, the area of the substrate occupied by the transistors 11 and 12 can be minimized, and the circuit size can be reduced, and the generation of an area in which the output terminal L crosses the first clock signal line CLK1 and the second clock signal line CLK2 can be prevented.

[0281] A top view of the shift register circuit of the present application in the case where the bottom gate transistor is used as the transistor and the active layer is processed into a desired shape using the wiring layer as a mask will be described below with reference to FIG. 21 A top view of the shift register circuit of the present application in the case where the bottom gate transistor is used as the transistor and the active layer is processed into a desired shape using the wiring layer as a mask will be described below with reference to FIG. 21 In this case, only the circuit 10 of the kth stage (shown as 10k) and the circuit 10 of the (k+1)th stage (shown as 10k+1) are described; however, the present application is not limited to this, and the circuit 10 has a plurality of stages. In addition, FIG. 21 The transistors 11, 12, 13, 15, 16, and 17, the capacitor element 14, and the terminal P in the circuit 10 in FIG. 1B The transistors 11, 12, 13, 15, 16, and 17, the capacitor element 14, and the terminal P in the circuit 10 in FIG. 1A to 1C The electrodes SR and the output terminal L provided outside the circuit 10 in FIG. 21 are arranged inside the circuit 10 in

[0282] A top view of the shift register circuit of the present application in the case where the bottom gate transistor is used as the transistor and the active layer is processed into a desired shape using the wiring layer as a mask will be described below with reference to FIG. 22A and 22B The cross-sectional view along the lines a-a' and b-b' in FIG. 1 is described below. FIG. 21 FIG. 22A and 22B The structure shown has a substrate 110, a base film 111, a first wiring layer 112, an insulating film 113, active layers 114 and 115, a second wiring layer 116, an interlayer film 117, and a third wiring layer 119. In addition, the structure shown has a contact 118a connecting the third wiring layer 119 and the second wiring layer 116, and a contact 118b connecting the third wiring layer 119 and the first wiring layer 112. The structure shown will be described step by step. FIG. 22A and 22B The structure shown has a contact 118a connecting the third wiring layer 119 and the second wiring layer 116, and a contact 118b connecting the third wiring layer 119 and the first wiring layer 112. The structure shown will be described step by step. FIG. 22A and 22B The structure shown.

[0283] First, the substrate 110 can be a glass substrate formed of barium borosilicate glass, aluminum borosilicate glass, or the like, a quartz substrate, a silicon substrate, a metal substrate, a stainless steel substrate, or a plastic substrate. In addition, the substrate 110 can be polished by CMP or the like to planarize the surface of the substrate 110.

[0284] Then, the base film 111 is formed on the substrate 110. The base film 111 can be formed by a known method such as CVD, plasma CVD, sputtering, or spin coating from a single layer of aluminum nitride (AIN), silicon oxide (Si02), silicon oxynitride (SiOxNy), or the like, or a stack thereof. Note that the base film 111 has the function of blocking the entry of impurities such as contaminants into the substrate 110. When the base film 101 is not formed, the manufacturing process is simplified, and the cost is reduced.

[0285] Then, the first wiring layer 112 is formed on the substrate 110 or the base film 111. Here, the first wiring layer 112 can be processed into a desired shape by photolithography, a droplet discharge method, a printing method, or the like.

[0286] Then, the insulating film 113 is formed on the substrate 110, the base film 101, or the first wiring layer 112. Here, the insulating film 113 can be formed of silicon oxide (Si02) or silicon oxynitride (SiOxNy).

[0287] ​Then, active layers 114 and 115 are formed on the substrate 110, the base film 111, the first wiring layer 112, or the insulating film 113. Here, the active layers 114 and 115 can be formed of amorphous silicon (a-Si), and the active layers 114 and 115 can be formed continuously in the same thin film forming apparatus. The active layer 115 has a higher conductivity than the active layer 114. Note that the region near the interface between the channel region, the active layer 114, and the insulating film 113 can be denser than other regions of the active layer 114. Thus, degradation of the transistor can be suppressed, and thin film formation of the active layer 114 can be accelerated; thus, yield can be improved.

[0288] The second wiring layer 116 can be formed on the substrate 110, the base film 111, the first wiring layer 112, the insulating film 113, or the active layers 114 and 115. Here, a composition containing metal particles such as Ag (silver), Au (gold), Cu (copper), W (tungsten), or Al (aluminum) as a main component can be used as a material for forming the second wiring layer 116. In addition, a light-transmissive material such as indium tin oxide (ITO), ITO containing indium tin oxide and silicon oxide (ITSO), organic indium, organic tin, zinc oxide, titanium nitride can be combined. In addition, the wiring layer 116 can be formed into a desired shape by photolithography, a droplet discharge method, a printing method, or the like.

[0289] Then, the interlayer thin film 117 can be formed on the substrate 110, the base film 111, the first wiring layer 112, the insulating film 113, or the active layers 114 and 115, or the second wiring layer 116. Here, the interlayer thin film 117 can be formed of an insulating material such as silicon oxide, silicon resin nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, or other inorganic insulating materials; acrylic acid or methacrylic acid, or a derivative thereof; a heat-resistant polymer such as polyimide, aromatic polyamide, polybenzimidazole; or a silicone resin. In addition, the interlayer thin film 117 can be processed into a desired shape by photolithography, a droplet discharge method, a printing method, or the like. When the interlayer thin film is formed of a photosensitive or non-photosensitive material such as acrylic acid or polyimide, the interlayer thin film has a curved side surface in which the radius of curvature continuously changes, and the thin film formed thereon is preferably formed without being separated. In addition, the interlayer thin film 117 can be processed into a desired shape by photolithography, a droplet discharge method, a printing method, or the like. Here, the interlayer thin film 117 is processed so as to end etching at the same time as etching the wiring layer 116 like the contact 118a, before processing the insulating film 113 at the same time as the contact 118b. Then, the second wiring layer 116 is formed so that the second wiring layer 116 is connected to the first wiring layer 112.

[0290] The third wiring layer 119 can be formed on the substrate 110, the base film 111, the first wiring layer 112, the insulating film 113, the active layers 114 and 115, the second wiring layer 116, or the interlayer thin film 117. Here, a composition containing metal particles such as Ag (silver), Au (gold), Cu (copper), W (tungsten), or Al (aluminum) as a main component is used as a material for forming the wiring layer 119. In addition, a light-transmissive material such as indium tin oxide (ITO), ITO containing indium tin oxide and silicon oxide (ITSO), organic indium, organic tin, zinc oxide, titanium nitride can be combined. In addition, the third wiring layer 119 can be formed into a desired shape by photolithography, a droplet discharge method, a printing method, or the like.

[0291] Note that in FIG. 22A , reference numeral Ctftl7 denotes a parasitic capacitance element of the transistor 17, Cclkl denotes a parasitic capacitance element of the output terminal L and the first clock signal line CLKl, and Cclk2 denotes a parasitic capacitance element of the output terminal L and the second clock signal line CLK2. FIG. 22A Reference numeral x in denotes the width of the first wiring layer on which the active layer exists in the parasitic capacitance element Ctftl7. Reference numeral y denotes the distance between the upper end of the first wiring layer and the lower end of the second wiring layer in the parasitic capacitance elements Cclkl and Cclk2.

[0292] Here, in FIG. 21 , since the active layer is formed using the second wiring layer as a mask, they are formed in a shape following the second wiring layer. Therefore, the active layer is formed to have a shape, for example, surrounding the second wiring layer. Thus, the coverage of the third wiring layer covering the second wiring layer is improved, and disconnection of the third wiring layer can be prevented. That is, since, for example, when the shape of the periphery of the active layer and the shape of the periphery of the second wiring layer are the same or almost the same, or when the second wiring layer surrounds the active layer, the taper angle of the interlayer thin film on the second wiring layer is sharper than the case where the active layer is formed to have a shape, for example, surrounding the second wiring layer.

[0293] In addition, in FIG. 21 , each of the power supply line Vss, the first clock signal line CLKl, and the second clock signal line CLK2 is formed of a wiring layer and an active layer, which are provided in a direction extending substantially in parallel to the circuit 10 (shown as 10ext). Thus, in the case where a plurality of circuits 10 are provided, the length of the wiring increases and thus the wire resistance increases, and thus malfunction and increase in power consumption due to voltage drop of the power supply line can be prevented. In addition, malfunction due to distortion of a signal waveform can be suppressed, and reduction in the range of the operating voltage in which the circuit normally operates.

[0294] The power supply line Vss, the first clock signal line CLK1, and the second clock signal line CLK2 can be provided outside the elements forming the circuit 10. Further, the power supply line Vss is provided opposite the first clock signal line CLK1 and the second clock signal line CLK2. Thus, the power supply line can be prevented from crossing the first clock signal line CLK1 and the second clock signal line CLK2; thus, the power supply line can be prevented from being affected by the noise of the clock signal lines and malfunction can be reduced.

[0295] In FIG. 21 , the channel length direction of the transistor 11 (shown as Chl) and the channel length direction of the transistor 12 (shown as Ch2) can be substantially perpendicular. With this structure, the area of the substrate occupied by the transistors 11 and 12 can be minimized, and the circuit scale can be reduced. Further, the channel length direction of the transistors 13 and 16 (shown as Chl) can be substantially parallel to each other. They can share one source electrode or one drain electrode. Thus, the area of the substrate occupied by the transistors 13 and 16 can be minimized, and the circuit scale can be reduced.

[0296] Further, the channel length direction of the transistors 15 and 17 (shown as Ch2) can be substantially parallel to each other, and they can share one source electrode or one drain electrode. Thus, the area of the substrate occupied by the transistors 15 and 17 can be minimized, and the circuit scale can be reduced.

[0297] Then, the shape of the transistors 13 and 17 is described to keep the potential of the electrode SR at the H level so that the circuit 10 operates according to FIG. 23 the potential of the fixed terminal P and the output terminal L. FIG. 23 The circuit 10 shown in the top view of FIG. 21 has the same connection relationship as the transistors 11, 12, 13, 15, 16, and 17, the capacitor element 14, the terminal P, the electrode SR, and the output terminal L in ; however, the first wiring layer shape of the transistors 13 and 17 is different. Thus, when the average of the area of the first wiring layer of the transistors 13 and 17 is made larger than that of the first wiring layer of the transistor 12 of the circuit 10, the value of the parasitic capacitance associated with the electrode SR can be made large; thus, it is preferable that the potential of the electrode SR can be maintained at the H level even after the reset operation.

[0298] FIG. 23 Further, as shown in FIG. 23 , the electrode SR is made into a curved line so as not to form a line shape in the circuit 10. Thus, the length of the electrode SR is made larger than the distance between the circuit 10 of the kth stage (shown as 10k) and the circuit 10 of the (k+1)th stage (shown as 10k+1). Therefore, the value of the parasitic capacitance associated with the electrode SR can be increased so that the potential of the electrode SR is maintained at the H level even after the reset operation. Further, FIG. 23 The circuit 10 shown in a top view has a structure of an area in which the output terminal L crosses the clock signal line, which is different from that in FIG. 21 FIG. 23 In the circuit 10 shown in

[0299] Then, referring to FIG. 24A and 24B described are cross-sectional views along lines a-a' and b-b' in FIG. 23 FIG. 24A and 24B The structure shown in has a substrate 110, a base film 111, a first wiring layer 112, an insulating film 115, a second wiring layer 116, an interlayer film 117, and a third wiring layer 119, as shown in FIG. 22A and 22B The structure shown in has a contact 118a connecting the third wiring layer 119 and the second wiring layer 116, and a contact 118b connecting the third wiring layer 119 and the first wiring layer 112. FIG. 24A and 24B

[0300] Note that, in FIG. 24A the reference numeral Ctftl7 represents a parasitic capacitance element of the transistor 17, Cclkl represents a parasitic capacitance element of the output terminal L and the first clock signal line CLKl, and Cclk2 represents a parasitic capacitance element of the output terminal L and the second clock signal line CLK2. FIG. 24A The reference numeral x in represents the width of the first wiring layer on which the active layer exists in the parasitic capacitance element Ctftl7. The reference numeral y represents the distance between the upper end of the first wiring layer and the lower end of the second wiring layer in the parasitic capacitance elements Cclkl and Cclk2.

[0301] Here, the capacitance value of the parasitic capacitance element Ctftl7 becomes larger as x becomes larger. At the same time, the capacitance values of the parasitic capacitance elements Cclkl and Cclk2 become smaller as y becomes larger. When the capacitance value of the parasitic capacitance element Ctftl7 is increased by making x larger as shown in FIG. 24A the parasitic capacitance value related to the electrode SR increases; thus, the potential of the electrode SR is maintained at the H level. In addition, when the capacitance value of the parasitic capacitance element Cclk2 is increased by making y smaller as shown in FIG. 24B ​​​When the capacitance values of the parasitic capacitance elements Cclki and Cclk2 are reduced by increasing y, the potential change of the output terminal L due to the potential changes of the first clock signal line CLK1 and the second clock signal line CLK2 through the parasitic capacitance elements Cclki and Cclk2 can be reduced. Therefore, the first clock signal line CLK1 and the second clock signal line CLK2 can be formed with the first wiring layer.

[0302] Then, referring to FIG. 25 a top view of the case where the cross capacitance of the clock signal lines and the output terminal L is removed so that the output terminal L is not affected by the potential changes of the clock signal lines will be described. FIG. 25 The top view of the circuit 10 shown in FIG. 10 has the same configuration as FIG. 21 and FIG. 23 except that the transistors 11, 12, 13, 15, 16, and 17, the capacitance element 14, the terminal P, the electrode SR, and the output terminal L, the connection relationship are also similar; however, the first clock signal line CLK1, the second clock signal line CLK2, and the arrangement of the transistors 11 and 12 are different from FIG. 21 and FIG. 23

[0303] In FIG. 25 , the power supply line Vss, the first clock signal line CLK1, and the second clock signal line CLK2 are formed by the second wiring layer and the active layer, and are provided in a direction extending substantially parallel to the circuit 10 (shown as 10ext). Thus, in the case where a plurality of circuits 10 are provided, the length of the lead wiring increases and thus the wire resistance increases, and thus, malfunction and an increase in power consumption due to the voltage drop of the power supply line can be prevented. In addition, malfunction due to distortion of the signal waveform can be suppressed, and the reduction in the normal operating voltage range of the circuit can be prevented.

[0304] The power supply line Vss, the first clock signal line CLK1, and the second clock signal line CLK2 can be provided outside the elements forming the circuit 10. In addition, the power supply line Vss, the first clock signal line CLK1, and the second clock signal line CLK2 can be provided on the same side as the side on which the output terminal L is provided with respect to the first transistor, the third transistor, the second transistor, and the fourth transistor. Thus, the output terminal L can be prevented from crossing the first clock signal line CLK1 and the second clock signal line CLK2; thus, the power supply line can be prevented from being affected by the noise of the clock signal lines and malfunction can be reduced.

[0305] ​In addition, the channel length direction of the transistor 11 (indicated as Chl) and the channel length direction of the transistor 12 (indicated as Ch2) can be substantially parallel. With this structure, the area of the substrate occupied by the transistors 11 and 12 can be minimized, and the circuit size can be reduced, and generation of an area in which the output terminal L crosses the first clock signal line CLKl and the second clock signal line CLK2 can be prevented.

[0306] Next, a cross-sectional view along the line a-a' in FIG. 1A is described with reference to FIG. 1B. FIG. 26 A top view of the shift register circuit of the present application in the case where the bottom-gate transistor is used as the transistor and the active layer and the wiring layer are processed into desired shapes, respectively, is described. In FIG. 26 In FIG. 1C, only the circuit 10 of the kth stage (indicated as 10k) and the circuit 10 of the (k+l)th stage (indicated as 10k+1) are described; however, the present application is not limited thereto, and the circuit 10 has a plurality of stages. In addition, FIG. 26 The transistors 11, 12, 13, 15, 16, and 17, the capacitor element 14, and the terminal P in FIG. 1C correspond to the transistors 11, 12, 13, 15, 16, and 17, the capacitor element 14, and the terminal P in FIG. 1A, respectively. In order to reduce the layout area, the electrode SR and the output terminal L arranged outside the circuit 10 in FIG. 1A are arranged inside the circuit 10 in FIG. 1C. FIG. 1B The transistors 11, 12, 13, 15, 16, and 17, the capacitor element 14, and the terminal P in FIG. 1C correspond to the transistors 11, 12, 13, 15, 16, and 17, the capacitor element 14, and the terminal P in FIG. 1A, respectively. In order to reduce the layout area, the electrode SR and the output terminal L arranged outside the circuit 10 in FIG. 1A are arranged inside the circuit 10 in FIG. 1C. FIG. 1A to 1C The transistors 11, 12, 13, 15, 16, and 17, the capacitor element 14, and the terminal P in FIG. 1C correspond to the transistors 11, 12, 13, 15, 16, and 17, the capacitor element 14, and the terminal P in FIG. 1A, respectively. In order to reduce the layout area, the electrode SR and the output terminal L arranged outside the circuit 10 in FIG. 1A are arranged inside the circuit 10 in FIG. 1C. FIG. 26 The transistors 11, 12, 13, 15, 16, and 17, the capacitor element 14, and the terminal P in FIG. 1C correspond to the transistors 11, 12, 13, 15, 16, and 17, the capacitor element 14, and the terminal P in FIG. 1A, respectively. In order to reduce the layout area, the electrode SR and the output terminal L arranged outside the circuit 10 in FIG. 1A are arranged inside the circuit 10 in FIG. 1C.

[0307] Next, a cross-sectional view along the line a-a' in FIG. 1A is described with reference to FIG. 1B. FIG. 27A and 27B A cross-sectional view along the lines a-a' and b-b' in FIG. 1A is described with reference to FIG. 1B. FIG. 26 A cross-sectional view along the lines a-a' and b-b' in FIG. 1A is described with reference to FIG. 1B. FIG. 27A and 27B The structure shown in FIG. 1D has a substrate 120, a base film 121, a first wiring layer 122, an insulating film 123, active layers 124 and 125, a second wiring layer 126, an interlayer film 127, and a third wiring layer 129. In addition, FIG. 27A and 27B The structure shown in FIG. 1D has a contact 128a connecting the third wiring layer 129 and the second wiring layer 126, and a contact 128b connecting the third wiring layer 129 and the first wiring layer 122. The structure shown in FIG. 27A and 27B The structure shown in FIG. 1D has a contact 128a connecting the third wiring layer 129 and the second wiring layer 126, and a contact 128b connecting the third wiring layer 129 and the first wiring layer 122. The structure shown in

[0308] First, the substrate 120 can be a glass substrate formed of barium borosilicate glass, aluminum borosilicate glass, or the like; a quartz substrate, a silicon substrate, a metal substrate, a stainless steel substrate, or a plastic substrate. In addition, the substrate 120 can be polished by CMP or the like to planarize the surface of the substrate 120.

[0309] Then, a base film 121 is formed on the substrate 120. The base film 121 can be formed by a known method such as CVD, plasma CVD, sputtering, or spin coating from a single layer or a stacked layer of aluminum nitride (AIN), silicon oxide (Si02), silicon oxynitride (SiOxNy), or the like. Note that the base film 121 has a function of blocking the entry of impurities such as contaminants into the substrate 120. When the base film 121 is not formed, the manufacturing process is simplified, and the cost is reduced.

[0310] Then, a first wiring layer 122 is formed on the substrate 120 or the base film 121. Here, the first wiring layer 122 can be formed into a desired shape by photolithography, a droplet discharge method, a printing method, or the like.

[0311] Then, an insulating film 123 is formed on the substrate 120, the base film 121, or the first wiring layer 122. Here, the insulating film 123 can be formed of silicon oxide (Si02) or silicon oxynitride (SiOxNy).

[0312] Then, active layers 124 and 125 are formed on the substrate 120, the base film 121, the first wiring layer 122, or the insulating film 123. Here, the active layers 124 and 125 can be formed of amorphous silicon (a-Si), and the active layers 124 and 125 can be formed continuously in the same thin film formation apparatus. The active layer 125 has a higher conductivity than the active layer 124. Note that the region near the interface between the channel region, specifically, the active layer 124, and the insulating film 123 can be denser than other regions of the active layer 124. Thus, degradation of the transistor can be suppressed, and the thin film formation rate of the active layer 124 can be accelerated; thus, the yield is improved.

[0313] A second wiring layer 126 is formed on the substrate 120, the base film 121, the first wiring layer 122, the insulating film 123, or the active layers 124 and 125. Here, a composition containing metal particles such as Ag (silver), Au (gold), Cu (copper), W (tungsten), or Al (aluminum) as a main component can be used as a material for forming the second wiring layer 126. In addition, a light-transmitting material such as indium tin oxide (ITO), ITO containing silicon oxide and silicon oxynitride (ITSO), organic indium, organic tin, zinc oxide, titanium nitride can be combined. In addition, the second wiring layer 126 can be formed into a desired shape by photolithography, a droplet discharge method, a printing method, or the like.

[0314] Then, an interlayer thin film 127 is formed on the substrate 120, the base film 121, the first wiring layer 122, the insulating film 123, or the active layers 124 and 125, or the second wiring layer 126. Here, the interlayer thin film 127 can be formed of an insulating material such as silicon oxide, silicon resin nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, or other inorganic insulating material; acrylic acid or methacrylic acid, or derivative thereof; heat-resistant polymer such as polyimide, aromatic polyamide, polybenzimidazole; or silicone resin. In addition, the interlayer thin film 127 can be processed into a desired shape by photolithography, droplet discharge method, printing method, or the like. When the interlayer thin film is formed of a photosensitive or non-photosensitive material such as acrylic acid or polyimide, the interlayer thin film has a curved side surface in which the radius of curvature continuously changes, preferably formed on the thin film formed thereon without being separated. In addition, the interlayer thin film 127 can be processed into a desired shape by photolithography, droplet discharge method, printing method, or the like. Here, the interlayer thin film 127 can be processed so as to end etching at the same time as etching the wiring layer 126 as the contact 128a and also processing the insulating film 123 as the contact 128b. Then, the second wiring layer 126 is formed so that the second wiring layer 126 is connected to the first wiring layer 122.

[0315] A third wiring layer 129 is formed on the substrate 120, the base film 121, the first wiring layer 122, the insulating film 123, the active layers 124 and 125, the second wiring layer 126, or the interlayer thin film 127. Here, a composition containing a metal particle such as Ag (silver), Au (gold), Cu (copper), W (tungsten), or Al (aluminum) as a main component is used as a material for forming the third wiring layer 129. In addition, a light-transmitting material such as indium tin oxide (ITO), ITO containing silicon oxide (ITSO), organic indium, organic tin, zinc oxide, titanium nitride can be combined. In addition, the third wiring layer 129 can be formed into a desired shape by photolithography, droplet discharge method, printing method, or the like.

[0316] Note that, in FIG. 27A , reference numeral ctftl7 denotes a parasitic capacitance element of the transistor 17, Cclkl denotes a parasitic capacitance element of the output terminal L and the first clock signal line CLKl, and Cclk2 denotes a parasitic capacitance element of the output terminal L and the second clock signal line CLK2. FIG. 27A Reference numeral x in indicates the width of the first wiring layer on which the active layer exists in the parasitic capacitance element Ctftl7. Reference numeral y indicates the distance between the upper end of the first wiring layer and the lower end of the second wiring layer in the parasitic capacitance elements Cclkl and Cclk2. Here, in order to increase y, in the region in which the output terminal L intersects the first clock line CLKl and the second clock signal line CLK2 in the cross-sectional view of the line b-b', the active layers 124 and 125 can be formed.

[0317] Since the active layer and the second wiring layer are formed separately using different masks in FIG. 26 , the region having the active layer does not have to be formed in the second wiring layer other than the transistor region therein. In addition, as in FIG. 26 , the active layer can be formed in the second wiring layer other than the transistor region.

[0318] In addition, in FIG. 26 , each of the power supply line Vss, the first clock signal line CLK1, and the second clock signal line CLK2 is formed of a wiring layer and an active layer, and is provided in a direction substantially parallel to the extension of the circuit 10 (shown as 10ext). Thus, in the case where a plurality of circuits 10 are provided, the length of the lead wiring increases and thus the wire resistance increases, so that malfunction and increase in power consumption due to voltage drop in the power supply line can be prevented. In addition, malfunction due to distortion of a signal waveform can be suppressed, and the reduction in the operating voltage range in which the circuit normally operates.

[0319] The power supply line Vss, the first clock signal line CLK1, and the second clock signal line CLK2 can be provided outside the elements forming the circuit 10. In addition, the power supply line Vss is provided opposite to the first clock signal line CLK1 and the second clock signal line CLK2. Thus, the power supply line can be prevented from crossing the first clock signal line CLK1 and the second clock signal line CLK2; thus, the power supply line can be prevented from being affected by noise of the clock signal line and malfunction can be reduced.

[0320] In FIG. 26 , the channel length direction of the transistor 11 (shown as Chl) and the channel length direction of the transistor 12 (shown as Ch2) can be substantially perpendicular. With this structure, the area of the substrate occupied by the transistors 11 and 12 can be minimized, and the circuit size can be reduced.

[0321] In addition, the channel length direction of the transistors 13 and 16 (shown as Chl) can be substantially parallel to each other; they can share one source electrode or one drain electrode. Thus, the area of the substrate occupied by the transistors 13 and 16 can be minimized, and the circuit size can be reduced. In addition, the channel length direction of the transistors 15 and 17 (shown as Ch2) can be substantially parallel to each other, and they can share one source electrode or one drain electrode. Thus, the area of the substrate occupied by the transistors 15 and 17 can be minimized, and the circuit size can be reduced.

[0322] Then, referring to FIG. 28 A top view of the circuit 10 is described in which the shapes of the transistors 13 and 17 are designed to keep the potential of the electrode SR at the H level so as to fix the potentials of the terminal P and the output terminal L. FIG. 28 The circuit 10 shown in the top view of FIG. 43 has the same connection relationship as the circuit 10 shown in FIG. 42. FIG. 26 The transistors 11, 12, 13, 15, 16, and 17, the capacitor element 14, the terminal P, the electrode SR, and the output terminal L in the circuit 10 shown in FIG. 43 are similar to those in the circuit 10 shown in FIG. 42; however, the shapes of the first wiring layers of the transistors 13 and 17 are different. Thus, when the average of the areas of the first wiring layers of the transistors 13 and 17 is made larger than that of the transistor 12 in the circuit 10, the value of the parasitic capacitance associated with the electrode SR can be made larger; thus, it is preferable that the potential of the electrode SR can be maintained at the H level even after the reset operation.

[0323] In addition, as shown in FIG. 44, in the circuit 10, the electrode SR is made into a curved line so as not to form a line shape. Thus, the length of the electrode SR is made longer than the distance between the circuit 10 of the kth stage (shown as 10k) and the circuit 10 of the (k + 1)th stage (shown as 10k+1). Therefore, the value of the parasitic capacitance associated with the electrode SR can be increased so that the potential of the electrode SR is maintained at the H level even after the reset operation. FIG. 28 In addition, as shown in FIG. 45, the circuit 10 shown in FIG. 44 has a structure in which the output terminal L crosses the region of the clock signal line.

[0324] In the circuit 10 shown in FIG. 45, in the region in which the output terminal L crosses the clock signal line, the output terminal L is formed by the third wiring layer, and the clock signal line can be formed by the second wiring layer. FIG. 28 FIG. 26 Then, with reference to FIGS. 46 and 47, cross-sectional views along the lines a-a' and b-b' in FIG. 45 are described in the case where thin film transistors are used as the transistors. FIG. 28 The structure shown in FIGS. 46 and 47 has a substrate 120, a base film 121, a first wiring layer 122, an insulating film 123, active layers 124 and 125, a second wiring layer 126, an interlayer film 127, and a third wiring layer 129 as shown in FIGS. 48 and 49.

[0325] The structure shown in FIGS. 46 and 47 has a contact 128a connecting the third wiring layer 129 and the second wiring layer 126, and a contact 128b connecting the third wiring layer 129 and the first wiring layer 122. FIG. 29A 29B Note that in the structure shown in FIGS. 46 and 47, the first wiring layer 122 is formed on the base film 121, and the second wiring layer 126 is formed on the active layers 124 and 125. FIG. 28 FIG. 29A 29B The structure shown in FIGS. 46 and 47 has a substrate 120, a base film 121, a first wiring layer 122, an insulating film 123, active layers 124 and 125, a second wiring layer 126, an interlayer film 127, and a third wiring layer 129 as shown in FIGS. 48 and 49. FIG. 27A 27B The structure shown in FIGS. 46 and 47 has a contact 128a connecting the third wiring layer 129 and the second wiring layer 126, and a contact 128b connecting the third wiring layer 129 and the first wiring layer 122. FIG. 29A Note that in the structure shown in FIGS. 46 and 47, the first wiring layer 122 is formed on the base film 121, and the second wiring layer 126 is formed on the active layers 124 and 125.

[0326] FIG. 29A ​​​​​​In the diagram, reference number ctftl7 represents the parasitic capacitance element of transistor 17, Cclkl represents the parasitic capacitance element of output terminal L and first clock signal line CLK1, and Cclk2 represents the parasitic capacitance element of output terminal L and second clock signal line CLK2. FIG. 29A The reference number x in the figure represents the width of the first wiring layer in parasitic capacitance element Ctftl7, on which an active layer or a second wiring layer exists. The reference number y represents the distance between the upper end of the first wiring layer and the lower end of the second wiring layer in parasitic capacitance elements Cclkl and Cclk2.

[0327] Here, the capacitance of parasitic capacitor Ctftl7 increases with increasing x. Simultaneously, the capacitances of parasitic capacitors Cclkl and Cclk2 decrease with increasing y. When the capacitance of parasitic capacitor Ctftl7 is as... FIG. 29A As shown, the parasitic capacitance associated with electrode SR increases with increasing x; therefore, the potential of electrode SR remains at level H. Furthermore, when... FIG. 29B By increasing y to reduce the capacitance values ​​of parasitic capacitance elements Cclk1 and Cclk2, the potential change at the output terminal L caused by the potential changes of the first clock signal line CLK1 and the second clock signal line CLK2 through the parasitic capacitance elements Cclk1 and Cclk2 can be reduced. Note that, therefore, the active layer and the first wiring layer do not necessarily need to be formed below the first clock signal line CLK1 and the second clock signal line CLK2. Alternatively, the first clock signal line CLK1 and the second clock signal line CLK2 can be formed using the first wiring layer.

[0328] Then, refer to FIG. 30 A top view depicting the removal of the cross capacitance between the clock signal line and the output terminal L so that the output terminal L is unaffected by changes in the potential of the clock signal line. FIG. 30 The top view shows that the circuit 10 has, as FIG. 26 and FIG. 28 The transistors 11, 12, 13, 15, 16, and 17, capacitor 14, terminal P, electrode SR, and output terminal L are connected in a similar manner; however, the arrangement of the first clock signal line CLK1, the second clock signal line CLK2, and transistors 11 and 12 is similar to... FIG. 26 and FIG. 28 different.

[0329] exist FIG. 30 In this case, the power supply line Vss, the first clock signal line CLKl, and the second clock signal line CLK2 are formed by the second wiring layer, and they are provided in a direction extending substantially in parallel to the circuit 10 (shown as 10ext). Thus, in the case where a plurality of circuits 10 are provided, the length of the lead wiring increases and thus the wire resistance increases, and thus, malfunction and an increase in power consumption due to a voltage drop in the power supply line can be prevented. In addition, malfunction due to distortion of the signal waveform can be suppressed, and the reduction in the range of the operating voltage can be prevented.

[0330] The power supply line Vss, the first clock signal line CLKl, and the second clock signal line CLK2 can be provided outside the elements forming the circuit 10. In addition, the power supply line Vss, the first clock signal line CLKl, and the second clock signal line CLK2 can be provided on the same side as the side on which the output terminal L is provided, with respect to the first transistor, the third transistor, the second transistor, and the fourth transistor. Thus, the output terminal L can be prevented from crossing the first clock signal line CLKl and the second clock signal line CLK2; thus, the power supply line can be prevented from being affected by noise of the clock signal line and malfunction can be reduced.

[0331] In addition, the channel length direction of the transistor 11 (shown as Chl) and the channel length direction of the transistor 12 (shown as Ch2) can be substantially parallel. With this structure, the area of the substrate occupied by the transistors 11 and 12 can be minimized, and the circuit scale can be reduced, and the generation of an area in which the output terminal L crosses the first clock signal line CLKl and the second clock signal line CLK2 can be prevented.

[0332] Embodiment Mode 5

[0333] In this embodiment mode, a configuration example of a display panel using the shift register circuit of the present application described in Embodiment Modes 1 to 4, and an overall display device using the shift register circuit of the present application are described. Note that in the specification, a display panel refers to a device for displaying a still image or a moving image, which has an area in which pixels (pixel regions) are arranged on a substrate such as a glass substrate, a plastic substrate, a quartz substrate, or a silicon substrate. In addition, a display device refers to a systematized device for displaying an image on a display panel, which has a circuit for converting a conductive signal input from the outside into a data signal for individually controlling the optical state of a pixel, and a driver circuit for dividing the data signal by time and writing them into the pixel. In addition, the display device includes a circuit for processing the data signal so that an image is optimally displayed on the display panel.

[0334] The shift register circuit of the present application is used as part of a driver circuit forming a display device. In addition, considering productivity, production cost, reliability, and the like, a variety of methods are used to provide the shift register circuit of the present application to a display device. Here, reference is made to FIG. 31A to 31E An example of a method for setting the shift register circuit of the present application to a display device is described.

[0335] FIG. 31A A display panel that illustrates a case where a data line driver and a scan line driver that are peripheral driver circuits are combined with a substrate having a pixel region. FIG. 31A The display panel 200a of the display includes a pixel region 201a, a data line driver 202a, a scan line driver 203a, and a connection line substrate 204a. The pixel region 201a is a region in which pixels are arranged; the pixel array can be of the strip type or the delta type. In addition, the pixel region 201a can include data signal lines that are wiring for writing data signals that respectively control optical states to the pixels. In addition, the pixel region 201a can include scan lines that are wiring for selecting pixel columns to data signals that respectively control optical states.

[0336] The data line driver 202a illustrates a circuit for controlling the electrical state of the data signal lines in accordance with an image to be displayed on the pixel region 201a. The data line driver 202a can have the shift register circuit of the present application to control a number of signal data lines by being divided in accordance with time.

[0337] The scan line driver 203a is a circuit for controlling the electrical state of the scan lines that are wiring for selecting pixel columns to data signals that respectively control optical states. The scan line driver 203a can have the shift register circuit of the present application for sequentially scanning a number of scan lines, selecting pixel columns to data signals that respectively control optical states, writing data signals to the pixels, thereby displaying an image on the pixel region 201a.

[0338] The connection wiring substrate 204a is a substrate that has wiring for connecting the display panel 200a to external circuits for driving the display panel 200a. When the connection wiring substrate 204a is formed of a flexible substrate such as polyimide, it is easier to set the display panel 200a in a housing that has a movable portion. In addition, when the housing having the display panel 200a is subjected to a strong impact, if the connection wiring substrate 204a is flexible, the impact is absorbed by the connection wiring substrate 204a; thus, there is a reduced risk of disconnection caused by peeling of the connection portion 205a.

[0339] In FIG. 31A In the display panel 200a of the display, the data line driver 202a and the scan line driver 203a are combined with the substrate having the pixel region 201a; thus, the production cost can be reduced, and the impact resistance can be increased because the number of connection points is small.

[0340] FIG. 31B The display panel is a display panel in which a scan line driver of a peripheral driver circuit is combined with a substrate having a pixel region; a data line driver is provided on the substrate as an IC manufactured on a single crystal substrate (this method is also called COG). FIG. 31B The display panel 200b includes a pixel region 201b, a data line driver 202b, a scan line driver 203b, and a connection wiring substrate 204b.

[0341] The pixel region 201b is a region in which pixels are arranged; the pixel array can be of a strip type or a delta type. In addition, the pixel region 201b can include data signal lines which are wirings for writing data signals for respectively controlling optical states to the pixels. In addition, the pixel region 201b can include scan lines which are wirings for selecting pixel columns to data signals for respectively controlling optical states. The data line driver 202b is a circuit for controlling the electrical state of the data signal lines in accordance with an image to be displayed on the pixel region 201b. The data line driver 202b can have the shift register circuit of the present application in order to control a plurality of signal data lines by dividing them in accordance with time.

[0342] The scan line driver 203b is a circuit for controlling the electrical state of the scan lines which are wirings for selecting pixel columns to data signals for respectively controlling optical states. The scan line driver 203b can have the shift register circuit of the present application for continuously scanning a plurality of scan lines, selecting pixel columns to data signals for respectively controlling optical states, and writing data signals to pixels, thereby displaying an image on the pixel region 201b.

[0343] The connection wiring substrate 204b is a substrate having wirings for connecting the display panel 200b to external circuits for driving the display panel 200b. When the connection wiring substrate 204b is formed of a flexible substrate such as polyimide, it is easier to set the display panel 200b in a housing having a movable portion. In addition, when the housing having the display panel 200b is subjected to a strong impact, if the connection wiring substrate 204b is flexible, the impact is absorbed by the connection wiring substrate 204b; thus, the danger of disconnection due to peeling by the connection portion 205b is reduced.

[0344] In FIG. 31B In the display panel 200b, the scan line driver 203b is combined with the substrate having the pixel region 201b; thus, the production cost can be reduced, and the impact resistance can be increased because the number of connection points is small. In addition, since an IC manufactured using a single crystal substrate is provided as the data line driver 202b, it is possible to manufacture the display panel with very small variations in transistor characteristics; thus, the yield of the display device can be improved. In addition, since the operating voltage is reduced, the power consumption can be reduced.

[0345] FIG. 31C The display panel 200c is a display panel in which a data line driver and a scan line driver, which are peripheral driver circuits, are manufactured on a substrate having a pixel region as an IC on a single crystal substrate, thereby implementing COG. FIG. 31C The display panel 200c of the display includes a pixel region 201c, a data line driver 202c, a scan line driver 203b, and a connection wiring substrate 204c.

[0346] The pixel region 201c is a region in which pixels are arranged; the pixel array can be a strip type or a delta type. In addition, the pixel region 201c can include a data signal line which is a wiring for writing a data signal for individually controlling an optical state to a pixel. In addition, the pixel region 201c can include a scan line which is a wiring for selecting a pixel column to a data signal for individually controlling an optical state.

[0347] The data line driver 202c is a circuit for controlling an electrical state of a data signal line according to an image to be displayed on the pixel region 201c. The data line driver 202c can have a shift register circuit of the present application in order to control a plurality of signal data lines by dividing them according to time.

[0348] The scan line driver 203c is a circuit for controlling an electrical state of a scan line which is a wiring for selecting a pixel column to a data signal for individually controlling an optical state. The scan line driver 203c can have a shift register circuit of the present application for continuously scanning a plurality of scan lines, selecting a pixel column to a data signal for individually controlling an optical state, and writing a data signal to a pixel, thereby displaying an image on the pixel region 201c.

[0349] The connection wiring substrate 204c is a substrate having a wiring for connecting the display panel 200c to an external circuit for driving the display panel 200c. When the connection wiring substrate 204c is formed of a flexible substrate such as polyimide, it is easier to set the display panel 200c in a housing having a movable portion. In addition, when the housing having the display panel 200c is subjected to a strong impact, if the connection wiring substrate 204c is flexible, the impact is absorbed by the connection wiring substrate 204c; thus, the danger of disconnection due to peeling of the connection portion 205c is reduced.

[0350] In addition, since the connection wiring substrate 204c is set to be flexible, the display panel 200c can be set in a housing having a movable portion. FIG. 31C The display panel of the display can be manufactured by making the IC as the data line driver 202c and the scan line driver 203c using a single crystal substrate; thus, the transistor characteristics can be made to vary very little, thereby improving the yield of the display device. In addition, since the operating voltage is reduced, the power consumption can be reduced.

[0351] FIG. 31D The display panel is a case where a scan line driver which is a peripheral driver circuit is combined with a flexible substrate having a pixel region, and a data line driver is provided on the flexible substrate as an IC fabricated on a single crystal substrate and connected thereto (this method is also called TAB). FIG. 31D The display panel 200d of the display includes a pixel region 201d, a data line driver 202d, a scan line driver 203b, and a connection wiring substrate 204d.

[0352] The pixel region 201d is a region in which pixels are arranged; the pixel array can be of a strip type or a delta type. In addition, the pixel region 201d can include a data signal line which is a wiring for writing a data signal for individually controlling an optical state to a pixel. In addition, the pixel region 201d can include a scan line which is a wiring for selecting a pixel column to a data signal for individually controlling an optical state.

[0353] The data line driver 202c represents a circuit for controlling an electrical state of a data signal line according to an image to be displayed on the pixel region 201d. The data line driver 202d has a shift register circuit of the present application in order to control a plurality of signal data lines separated by time intervals.

[0354] The scan line driver 203d is a circuit for controlling an electrical state of a scan line which is a wiring for selecting a pixel column to a data signal for individually controlling an optical state. The scan line driver 203d has a shift register of the present application for sequentially continuously scanning a plurality of scan lines, selecting a pixel column to a data signal for individually controlling an optical state, and bending and moving the data signal into a pixel, thereby displaying an image on the pixel region 201d.

[0355] The connection wiring substrate 204d is a substrate provided with a wiring for connecting the display panel 200d to an external circuit for driving the display panel 200d, and when the connection wiring substrate 204d is formed of a flexible substrate of polyimide or the like, it is easier to mount the display panel 200d in a housing having a movable member. Also, when a housing having the display panel 200d is impacted violently, if the connection wiring substrate 204d is flexible, the impact can be absorbed by the connection wiring substrate 204d; thus, the danger of disconnection due to peeling of the connection portion 205d is reduced.

[0356] In FIG. 31D In the display panel 200d shown, the scan line driver 203c is combined with the substrate having the pixel region 201b; thus, the production cost can be reduced, and the impact resistance can be increased because the number of connection points is small. Further, since the IC manufactured using a single crystal substrate is provided as the data line driver 202d, a display panel can be manufactured with very small variations in transistor characteristics; thus, the yield of the display device can be improved. Further, since the operating voltage is reduced, the power consumption can be reduced. Further, since the data line driver 202d is connected to the connection wiring substrate 204d, the area of the display panel 200d other than the pixel region 201d (also referred to as a frame) can be reduced, and thus the display device can have a higher added value. Further, if the connection wiring substrate is flexible, when the housing having the display panel 200d is subjected to a strong impact, the connection wiring substrate 204d absorbs the impact on the data line driver 204d; thus, the risk of disconnection due to peeling of the data line driver 202d from the connection wiring substrate 204d is reduced.

[0357] FIG. 31E It is described that a data line driver and a scan line driver which are peripheral driver circuits are manufactured as ICs on a single crystal substrate on a substrate having a pixel region called a TAB. FIG. 31E The display panel 200e shown includes a pixel region 201e, a data line driver 202e, a scan line driver 203e, and a connection wiring substrate 204e.

[0358] The pixel region 201e is a region in which pixels are arranged; the pixel array can be of a strip type or a delta type. Further, the pixel region 201e can include a data signal line which is a wiring for writing a data signal for individually controlling an optical state to a pixel. Further, the pixel region 201e can include a scan line which is a wiring for selecting a pixel column to a data signal for individually controlling an optical state.

[0359] The data line driver 202e describes a circuit for controlling the electrical state of a data signal line in accordance with an image to be displayed on the pixel region 201e. The data line driver 202e can have a shift register circuit of the present application to control a plurality of signal data lines by dividing them in accordance with time.

[0360] The scan line driver 203e is a circuit for controlling the electrical state of a scan line which is a wiring for selecting a pixel column to a data signal for individually controlling an optical state. The scan line driver 203e can have a shift register circuit according to the present application for continuously scanning a plurality of scan lines, selecting a pixel column to a data signal for individually controlling an optical state, and writing a data signal to a pixel, thereby displaying an image on the pixel region 201e.

[0361] The connection wiring substrate 204e is a substrate having wirings for connecting the display panel 200e to an external circuit for driving the display panel 200e. When the connection wiring substrate 204e is formed of a flexible substrate of polyimide or the like, it is easier to set the display panel 200e in a housing having a movable portion. In addition, when the housing having the display panel 200e is subjected to a strong impact, if the connection wiring substrate 204e is flexible, the impact is absorbed by the connection wiring substrate 204e; thus, the danger of disconnection due to peeling of the connection portion 205e is reduced.

[0362] Since the IC manufactured using a single crystal substrate is provided as the FIG. 31E The data line driver 202e and the scan line driver 203e in the display panel 200e shown can be manufactured with very small variations in transistor characteristics; thus, the yield of the display device can be improved. In addition, since the operating voltage is reduced, the power consumption can be reduced. In addition, since the data line driver 202e is connected to the connection wiring substrate 204e, the frame of the display panel 200e can be reduced; thus, the display device can have a higher added value. In addition, if the connection wiring substrate 204e is flexible, when the housing having the display panel 200e is subjected to a strong impact, the connection wiring substrate 204e absorbs the impact on the data line driver 204e; thus, the danger of disconnection due to peeling of the data line driver 202e and the scan line driver 203e from the connection wiring substrate 204e is reduced.

[0363] Thus, the transistor of the present application can be any kind of transistor and formed on any kind of substrate. The shift register circuit of the present application can be formed on a glass substrate, a plastic substrate, a single crystal substrate, an SOI substrate, or any other substrate. A part of the shift register circuit of the present application can be formed on one substrate while another part of the shift register circuit of the present application can be formed on another substrate. That is, it is not required that the entire shift register circuit of the present application is formed on the same substrate.

[0364] Then, referring to FIG. 32 An example of the configuration of a display device including the shift register circuit of the present application is described. FIG. 32 The display device 220 shown has Figures 31A to 31E a display panel 200, an external drive circuit 221, and a connection wiring substrate 204.

[0365] The display panel 200 has a pixel region 201, a data line driver 202, and a scan line driver 203. Since the display panel 200 has been described above, the details are not described here. However, naturally, the display panel 200 can be provided in accordance with a variety of methods. Figure 32 The display device 220, data line driver 202, and scan line driver 203 are shown.

[0366] The external drive circuit 221 includes a control circuit 210, an image data conversion circuit 211, and a power supply circuit 212. Additionally, the power supply circuit 212 may have a power supply CV for the control / image data conversion circuit, a power supply DV for the driver, and a power supply PV for the pixel circuit. Note that the power supply PV for the pixel circuit does not need to be provided to the power supply circuit 212 according to the configuration of the pixel region 201.

[0367] The connection wiring substrate 204 can be electrically connected to the display panel 200 through the connection portion 205, and can be electrically connected to the external driving circuit 221 through the connector 213.

[0368] In addition, in order to correspond to such Figure 33 The display panel shown has a large pixel area. Multiple data line drivers 202 (202-1, 202-2, 202-3, and 202-4), multiple scan line drivers 203 (203-1, 203-2, 203-3, and 203-4), and multiple connection wiring substrates 204 (204-1, 204-2, 204-3, 204-4, 204-5, 204-6, 204-7, and 204-8) can be used for a display panel 200 and a pixel area 201. Here, in Figure 33 The example shown uses four data line drivers 202 and four scan line drivers 203; however, there is no specific limitation on the number of data line drivers 202 and scan line drivers 203, and any number can be used. When the number of data line drivers 202 and scan line drivers 203 is small, the number of ICs and connection points is small; therefore, reliability can be improved and production costs reduced. When the number of data line drivers 202 and scan line drivers 203 is large, the performance required for each driver decreases, thus increasing yield.

[0369] Note that the number of connecting wiring substrates 204 is preferably two or more, while the number of data line drivers 202 and scan line drivers is relatively small. When the number of connecting wiring substrates 204 is greater than the number of drivers, the number of contact points increases; therefore, when the number of contact points increases, the defects of disconnection at the contact points increase.

[0370] exist Figure 32 The control circuit 210 is connected to the image data conversion circuit 211 and the power supply circuit 212. In addition, the control circuit 210 is connected to the data line driver 202 and the scan line driver 203 through the connector 213, the connection wiring substrate 204, and the connection portion 205. In addition, the image data conversion circuit 211 is connected to an input terminal of input image data. In addition, the image data conversion circuit 211 is connected to the data line driver 202 through the connector 213, the connection wiring substrate 204, and the connection portion 205.

[0371] In addition, the power supply circuit 212 supplies power to each circuit, and a power supply CV for the control / image data conversion circuit is connected to the control circuit 210 and the image data conversion circuit 211, a power supply DV for the driver is connected to the data line driver 202 and the scan line driver 203 through the connector 213, the connection wiring substrate 204, and the connection portion 205, and a power supply PV for the pixel circuit is connected to the pixel region 201 through the connector 213, the connection wiring substrate 204, and the connection portion 205.

[0372] The voltage supplied from the power supply CV to the control circuit 210 and the image data conversion circuit 211 is preferably as low as possible because they control the circuit 210 and the image data conversion circuit 211 performs logical operation, and thus, it is desirable to be about 3 V. In addition, in order to reduce power consumption, the voltage from the power supply DV for the driver is preferably as low as possible, for example, when the IC is used for the data line driver 202 and the scan line driver 203. It is desirable to be about 3 V. In addition, the data line driver 202 and the scan line driver 203 are combined with the display panel 200, and it is desirable to apply a voltage having a boost of about two to three times as high as the transistor threshold voltage. Thus, it is possible to safely operate the circuit while suppressing an increase in power consumption.

[0373] The control circuit 210 can have a configuration to perform an operation of generating a clock supplied to the data line driver 202 and the scan line driver 95, an operation of generating and supplying a timing pulse. In addition, the control circuit 210 can have a configuration to perform an operation of generating a clock supplied to the image data conversion circuit, an operation of generating a timing pulse to output converted image data to the data line driver 202, and the like. The power supply circuit 212 can have a configuration to stop the operation of supplying a voltage to each circuit when, for example, the image data conversion circuit 211, the data line driver 202, and the scan line driver 203 are not required to be operated, thereby reducing power consumption.

[0374] When the image data is input to the image data conversion circuit 211, the image data conversion circuit 211 converts the image data into data input to the data line driver 202 according to the time at which the signal is supplied from the control circuit 210, and then outputs the data to the data line driver circuit 202. Specifically, a configuration in which the image data having an analog signal is input to the image data conversion circuit 211 to be converted into digital signal, and then the digital signal image data is output to the data line driver 202 can be used.

[0375] The data line driver 202 can have a configuration such that the shift register of the present application operates according to a clock signal and a timing pulse from the control circuit 210; image data input to the data line driver 202 is accepted with time division; and a data voltage or a data current having an analog value is output to a plurality of data lines according to the data that has been accepted. The update of the data voltage or the current output to the data line can be performed in accordance with a latch pulse from the control circuit 210. In addition, a signal for a reset operation can be input in order to reset the shift register circuit of the present application. Furthermore, a signal for applying a reverse bias can be input in order to apply a reverse bias to a transistor in the shift register circuit of the present application.

[0376] According to the update of the data voltage or the data current output to the data line, the scan line driver 203 operates the shift register of the present application in response to a clock signal and a timing pulse from the control circuit 210 to continuously scan the scan line 29. Here, a signal for a reset operation can be input in order to reset the shift register circuit of the present application. Furthermore, a signal for applying a reverse bias can be input in order to apply a reverse bias to a transistor in the shift register circuit of the present application.

[0377] Note Figure 32 and Figure 33 The example in which the scan line driver 203 is configured on one side is described in Embodiment Mode 5; however, the scan line driver 203 can be configured on each side instead of one side. In the case where the scan line driver 203 is configured on each side, the left-right balance of the display device is completed when set on an electronic device, and thus it is advantageous to increase the degree of freedom of arrangement.

[0378] Embodiment Mode 6

[0379] In this embodiment mode, reference is made to Figures 34A to 34H to describe an electronic device obtained by using the shift register of the present application.

[0380] The present application can be used for various electronic devices. Specifically, the present application can be used for display devices of electronic devices. As the electronic devices, there can be listed cameras such as video cameras and digital cameras; head-up displays; navigation systems; audio reproducing devices (car audio, audio components, etc.); computers; game machines; portable information terminals (mobile computers, cellular phones, portable game machines, electronic books, etc.); image reproducing devices including recording media (specifically, devices capable of reproducing the contents of recording media such as digital versatile disks (DVDs) and having display devices that can display data images); and the like.

[0381] Figure 34A A television receiver including a housing 3001, a stand 3002, a display area 3003, a speaker unit 3004, a video input terminal 3005, and the like is shown. The display device of the present application can be used for the display area 3003. For example, since a television receiver requires a large display area, the display device of the present application can be used for the display area 3003, thereby obtaining a very reliable electronic device that hardly has a failure even when subjected to noise such as external electromagnetic waves, in which a reverse bias application can be operated. Figure 33 A display device. Note that the display device includes, in particular, all light emitting devices for displaying information, for example, for personal computers, for TV broadcast reception, or for advertisement displays. The display device using the shift register circuit of the present application can be used for the display area 3003, thereby obtaining a very reliable electronic device that hardly has a failure even when subjected to noise such as external electromagnetic waves, in which a reverse bias application can be operated.

[0382] Figure 34B A digital camera including a main body 3101, a display area 3102, an image receiving section 3103, an operation key 3104, an external connection port 3205, a shutter 3106, and the like is shown. The display device using the shift register circuit of the present application can be used for the display area 3102, thereby obtaining a very reliable digital camera that hardly has a failure even when subjected to noise such as external electromagnetic waves, in which a reverse bias application can be operated.

[0383] Figure 34C A computer including a main body 3201, a housing 3202, a display area 3203, a keyboard 3204, an external connection port 3205, a click mouse 3206, and the like is shown. The display device using the shift register circuit of the present application can be used for the display area 3203, thereby obtaining a very reliable computer that hardly has a failure even when subjected to noise such as external electromagnetic waves, in which a reverse bias application can be operated.

[0384] Figure 34D A mobile computer is shown which includes a main body 3301, a display area 3302, a switch 3303, operation keys 3304, an infrared port 3305, and the like. A display device using the shift register circuit of the present application can be used for the display area 3302, thereby obtaining a very reliable mobile computer which has almost no malfunction even when disturbed by noise such as an external electromagnetic wave, in which a reverse bias application can be executed.

[0385] Figure 34E A mobile image reproducing apparatus (particularly, a DVD reproducing apparatus) loaded with a recording medium (DVD, etc.) is shown which includes a main body 3401, a housing 3402, a display area A 3403, a display area B 3404, a recording medium reading section 3405, operation keys 3406, a speaker unit 3407, and the like. The display area A 3403 mainly displays image information, while the display area B mainly displays text information. A display device using the shift register circuit of the present application can be used for the display area A 3403 and the display area B 3404, thereby obtaining a very reliable image reproducing apparatus which has almost no malfunction even when disturbed by noise such as an external electromagnetic wave, in which a reverse bias application can be executed.

[0386] Figure 34F A goggle-type display is shown which includes a main body 3501, a display area 3502, and a support section 3503. The goggle-type display can be manufactured by applying the display device described in any one of the above-described embodiment modes to the display area 3502. A display device using the shift register circuit of the present application can be used for the display area 3502, thereby obtaining a very reliable goggle-type display which has almost no malfunction even when disturbed by noise such as an external electromagnetic wave, in which a reverse bias application can be executed.

[0387] Figure 34G A video camera is shown which includes a main body 3601, a display area 3602, a housing 3603, an external connection port 3604, a remote controller receiving section 3605, an image receiving section 3606, a battery 3607, an audio input section 3608, operation keys 3609, and the like. A display device using the shift register circuit of the present application can be used for the display area 3602, thereby obtaining a very reliable video camera which has almost no malfunction even when disturbed by noise such as an external electromagnetic wave, in which a reverse bias application can be executed.

[0388] Figure 34H A cellular phone is shown including a main body 3701, a housing 3702, a display area 3703, an audio input portion 3704, an audio output portion 3705, an operation key 3706, an external connection port 3707, an antenna 3708, and the like. A display device using the shift register circuit of the present application can be used for the display area 3703, thereby obtaining a very reliable cellular phone having almost no malfunction even when subjected to noise such as external mobile phone interference, in which a reverse bias application can be operated.

[0389] Thus, the present application can be used for electronic devices in all fields.

[0390] This application is based on Japanese Patent Application Serial No. 2005-378262 filed in the Japan Patent Office on December 28, 2005, the entire contents of which are incorporated herein by reference.< / vss> < / vss> < / vss> < / vss> < / vss> < / vss> < / vss> < / vss> < / vdd> < / vdd> < / vdd> < / vss> < / vss> < / vss> < / vss> < / vss> < / vdd> < / vss> < / vss> < / vdd> < / vss>

Claims

1. A semiconductor device comprising: a drive circuit including a first stage and a second stage, wherein the first stage includes first to seventh transistors, one of a source and a drain of the first transistor is electrically connected to a clock signal line, the other of the source and the drain of the first transistor is electrically connected to an output signal line of the first stage, one of a source and a drain of the second transistor is electrically connected to the output signal line of the first stage, the other of the source and the drain of the second transistor is electrically connected to a power supply line, a gate of the second transistor is electrically connected to one of a source and a drain of the third transistor and one of a source and a drain of the fourth transistor, the other of the source and the drain of the third transistor is directly connected to a gate of the third transistor, the other of the source and the drain of the third transistor is electrically connected to a first wiring, the other of the source and the drain of the fourth transistor is electrically connected to the power supply line, the gate of the fourth transistor is electrically connected to a gate of the first transistor, one of a source and a drain of the fifth transistor is electrically connected to the power supply line, the other of the source and the drain of the fifth transistor is electrically connected to a second wiring, the gate of the fifth transistor is electrically connected to the gate of the first transistor, one of a source and a drain of the sixth transistor is electrically connected to the gate of the first transistor, the other of the source and the drain of the sixth transistor is directly connected to a gate of the sixth transistor, one of a source and a drain of the seventh transistor is electrically connected to the gate of the first transistor, the other of the source and the drain of the seventh transistor is electrically connected to the power supply line, and the gate of the sixth transistor is electrically connected to an output signal line of the second stage.

2. A semiconductor device comprising: a drive circuit including a first stage and a second stage, wherein the first stage includes first to seventh transistors, one of a source and a drain of the first transistor is electrically connected to a clock signal line, the other of the source and the drain of the first transistor is electrically connected to an output terminal of the first stage, one of a source and a drain of the second transistor is electrically connected to the output terminal of the first stage, the other of the source and the drain of the second transistor is electrically connected to a power supply line, a gate of the second transistor is electrically connected to a first wiring, one of a source and a drain of the third transistor is electrically connected to an input terminal of the first stage, the other of the source and the drain of the third transistor is electrically connected to a gate of the first transistor, a gate of the third transistor is directly connected to the one of the source and the drain of the third transistor, one of a source and a drain of the fourth transistor is directly connected to the gate of the first transistor, the other of the source and the drain of the fourth transistor is electrically connected to the power supply line, a gate of the fourth transistor is electrically connected to the first wiring, one of a source and a drain of the fifth transistor is electrically connected to the gate of the second transistor, the other of the source and the drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor, a gate of the fifth transistor is electrically connected to the first wiring, the one of the source and the drain of the sixth transistor is directly connected to one of a source and a drain of the seventh transistor, the other of the source and the drain of the sixth transistor is electrically connected to a second wiring, a gate of the sixth transistor is directly connected to the other of the source and the drain of the sixth transistor, a signal output from an output terminal of the second stage is supplied to the input terminal of the first stage, and the gate of the first transistor is located between the clock signal line and the power supply line.

3. The semiconductor device according to claim 2, further comprising: an eighth transistor, wherein one of a source and a drain of the eighth transistor is directly connected to the gate of the second transistor; the other of the source and the drain of the eighth transistor is electrically connected to the first wiring, and a gate of the eighth transistor is electrically connected to a third wiring.

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