Gate driving circuit and display panel

Abstract

The present disclosure relates to the technical field of display, and provides a gate driving circuit and a display panel. The gate driving circuit can include a plurality of repeating units, each of the repeating units including a first shift register unit and a second shift register unit connected in cascade, in the same repeating unit, a feedback end of the first shift register unit is connected to a first output end of the second shift register unit, a first output end of the first shift register unit is connected to an input end of the second shift register unit, and a second output end of the first shift register unit is connected to a feedback end of the second shift register unit; in the same shift register unit, the input end can be used to input a signal in response to a signal of the first selection end or a signal of the feedback end in response to a signal of the second selection end through an input selection module; and the output selection module can be used to output a signal through the first output end in response to a signal of the first selection end or output a signal through the second output end in response to a signal of the second selection end.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a gate driving circuit and a display panel. Background Art

[0002] The current market's pursuit of increasingly higher PPI and narrower bezels means that current designs cannot be further narrowed. Furthermore, as resolution increases, the number of Gate Driver on Array (GOA) groups also increases, indirectly impacting signal stability. Furthermore, the increased number of components increases the RC load of the circuit, impacting product reliability. Summary of the Invention

[0003] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and to provide a gate driving circuit and a display panel.

[0004] According to one aspect of the present disclosure, a gate drive circuit is provided, comprising a plurality of repeating units, wherein the repeating unit comprises a first shift register unit and a second shift register unit connected in cascade, wherein the first shift register unit and the second shift register unit each comprise an input selection module, an output selection module, an input terminal, a feedback terminal, and two output terminals, and the first shift register unit and the second shift register unit are respectively connected to a first clock signal terminal and a second clock signal terminal; in the same repeating unit, the feedback terminal of the first shift register unit is connected to the first output terminal of the second shift register unit, the first output terminal of the first shift register unit is connected to the input terminal of the second shift register unit, and the second output terminal of the first shift register unit is connected to the feedback terminal of the second shift register unit; in two adjacent repeating units, the second output terminal of the second shift register unit in the previous repeating unit is connected to the input terminal of the first shift register unit in the next repeating unit; in the same shift register unit, the input selection module is connected to the input terminal, the first selection terminal, the second selection terminal, the second selection terminal, the second selection terminal, the second selection terminal, the second selection terminal, the first ... two selection terminals and a feedback terminal, the input selection module is used to respond to the signal of the first selection terminal and use the signal of the input terminal for input, or respond to the signal of the second selection terminal and use the signal of the feedback terminal for input; the output selection module is connected to the first output terminal, the second output terminal, the first selection terminal and the second selection terminal, and the output selection module is used to respond to the signal of the first selection terminal and output through the first output terminal, or respond to the signal of the second selection terminal and output through the second output terminal; wherein, in the same shift register unit, the signal of the first selection terminal and the signal of the second selection terminal have opposite polarity, and the conduction levels of the first selection terminals of the two shift register units in the same repeating unit partially overlap and the conduction levels of the second selection terminals partially overlap; the signal of the first clock signal terminal is inverted to the signal of the second clock signal terminal, and the signals of the first clock signal terminal and the second clock signal terminal of the first shift register unit are correspondingly inverted to the signals of the first clock signal terminal and the second clock signal terminal of the second shift register unit.

[0005] In an exemplary embodiment of the present disclosure, in any repeating unit, the first output end of the first shift register unit serves as the nth output end of the gate drive circuit, and the second output end of the first shift register unit serves as the (n+2)th output end of the gate drive circuit; the first output end of the second shift register unit serves as the (n+1)th output end of the gate drive circuit, and the second output end of the second shift register unit serves as the (n+3)th output end of the gate drive circuit, where n is a natural number greater than or equal to 1.

[0006] In an exemplary embodiment of the present disclosure, when the first selection end of the first shift register unit outputs a conduction level with a conduction duration of T, the first selection end of the second shift register unit sequentially outputs a conduction level and a non-conduction level with a duration of T / 2; when the second selection end of the first shift register unit outputs a conduction level with a conduction duration of T, the second selection end of the second shift register unit sequentially outputs a non-conduction level and a conduction level with a duration of T / 2.

[0007] In an exemplary embodiment of the present disclosure, the conduction level durations of the first clock signal terminal and the second clock signal terminal are both t, where t=T / 2.

[0008] In an exemplary embodiment of the present disclosure, when the input terminal of the first shift register unit is at a conduction level, the first clock signal terminal of the first shift register unit is at a conduction level, and the second clock signal terminal is at a non-conduction level.

[0009] In an exemplary embodiment of the present disclosure, the input selection module is also connected to the first node, and the input selection module is also used to transmit the signal of the input end to the first node in response to the signal of the first selection end, or to transmit the signal of the feedback end to the first node in response to the signal of the second selection end; the output selection module is also connected to the fifth node, and the output selection module is also used to transmit the signal of the fifth node to the first output end in response to the signal of the first selection end, or to transmit the signal of the fifth node to the second output end in response to the signal of the second selection end.

[0010] In an exemplary embodiment of the present disclosure, the input selection module and the output selection module both include transistors, and the polarities of the transistors are the same.

[0011] In an exemplary embodiment of the present disclosure, the input selection module includes: a first selection transistor, having a first electrode connected to the input terminal, a second electrode connected to the first node, and a gate connected to the first selection terminal, the first selection transistor being configured to transmit the signal from the input terminal to the first node in response to a signal from the first selection terminal; a second selection transistor, having a first electrode connected to the feedback terminal, a second electrode connected to the first node, and a gate connected to the second selection terminal, the second selection transistor being configured to transmit the signal from the feedback terminal to the first node in response to a signal from the second selection terminal; the output selection module includes: a third selection transistor, having a first electrode connected to the fifth node, a second electrode connected to the first output terminal, and a gate connected to the first selection terminal, the third selection transistor being configured to transmit the signal from the fifth node to the first output terminal in response to a signal from the first selection terminal; and a fourth selection transistor, having a first electrode connected to the fifth node, a second electrode connected to the second output terminal, and a gate connected to the second selection terminal, the fourth selection transistor being configured to transmit the signal from the fifth node to the second output terminal in response to a signal from the second selection terminal; wherein the first to fourth selection transistors are all P-type transistors.

[0012] In an exemplary embodiment of the present disclosure, the first shift register unit and the second shift register unit each include: an input module connected to the first node, the third node, and the first clock signal terminal, the input module being configured to transmit the signal of the first node to the third node in response to the signal of the first clock signal terminal; a first control module connected to the second node and the first clock signal terminal and receiving a first level signal, the first control module being configured to pull down the second node using the first level signal in response to the signal of the first clock signal terminal; a second control module connected to the second node, the third node, and the first clock signal terminal, the second control module being configured to pull up the second node using the signal of the first clock signal terminal in response to the signal of the third node; and a reset module connected to the second node, the third node, and the second clock signal terminal and receiving the second level signal. The reset module is used to respond to the signal of the second node and the signal of the second clock signal end and reset the third node using the second level signal; the protection module is connected to the third node and the fourth node and receives the first level signal, and the protection module is used to transmit the signal of the third node to the fourth node in response to the first level signal or to shut down in response to the voltage difference between the first level signal and the signal of the fourth node; the first output module is connected to the second node, the first output end, and the second output end and receives the second level signal, and the first output module is used to transmit the second level signal to the first output end and the second output end in response to the signal of the second node; the second output module is connected to the fifth node, the fourth node and the second clock signal end, and the second output module is used to transmit the signal of the second clock signal end to the fifth node in response to the signal of the fourth node.

[0013] In an exemplary embodiment of the present disclosure, the input module, the first control module, the second control module, the reset module, the protection module, the first output module, and the second output module all include transistors, and the polarity of each transistor is the same.

[0014] In an exemplary embodiment of the present disclosure, the input module includes: a first transistor, a first electrode connected to the first node, a second electrode connected to the third node, and a gate connected to the first clock signal terminal, the first transistor being used to transmit the signal of the first node to the third node in response to the signal of the first clock signal terminal; a first control transistor, a first electrode receiving the first level signal, a second electrode connected to the second node, and a gate connected to the first clock signal terminal, the first control transistor being used to transmit the first level signal to the second node in response to the signal of the first clock signal terminal; the second control module includes: a second control transistor, a first electrode connected to the second node, a second electrode connected to the first clock signal terminal, and a gate connected to the third node, the second control transistor being used to pull down the second node using the signal of the first clock signal terminal in response to the signal of the third node; the reset module includes: a first reset transistor, a first electrode connected to receive the second level signal, a second electrode connected to the sixth node, and a gate connected to the second node, the first reset transistor being used to transmit the second level signal to the sixth node in response to the signal of the second node; a second reset transistor, a first electrode connected to the third node, a second electrode connected to the sixth node, and a gate connected to the second clock signal terminal, the second reset transistor being used to transmit the second level signal to the sixth node in response to the signal of the second node; The transistor is configured to transmit the signal of the sixth node to the third node in response to the signal of the second clock signal terminal to reset the third node; the protection module includes: a second transistor, a first electrode connected to the third node, a second electrode connected to the fourth node, and a gate receiving the first level signal, the second transistor being configured to transmit the signal of the third node to the fourth node in response to the first level signal or to be turned off in response to a voltage difference between the first level signal and the signal of the fourth node; the first output module includes: a first output transistor, a first electrode receiving the second level signal, a second electrode connected to the first output terminal, and a gate connected to the second node, the first output transistor being configured to transmit the second level signal to the first output terminal in response to the signal of the second node; a second output transistor, a first electrode receiving the second level signal, a second electrode connected to the second output terminal, and a gate connected to the second node, the second output transistor being configured to transmit the second level signal to the second output terminal in response to the signal of the second node; the second output module includes: a third output transistor, a first electrode connected to the fifth node, a second electrode connected to the second clock signal terminal, and a gate connected to the fourth node, the third output transistor being configured to transmit the signal of the second clock signal terminal to the fifth node in response to the signal of the fourth node.

[0015] In an exemplary embodiment of the present disclosure, the first transistor, the first control transistor, the second control transistor, the first reset transistor, the second reset transistor, the second transistor, the first output transistor, the second output transistor and the third output transistor are all P-type transistors.

[0016] In an exemplary embodiment of the present disclosure, the first shift register unit and the second shift register unit also include: a first storage module, connected to the second node and receiving the second level signal, the first storage module being used to maintain the potential of the second node stable; a second storage module, connected to the fourth node and the fifth node, the second storage module being used to bootstrap the fourth node when the signal at the fifth node has the same polarity as the signal at the fourth node.

[0017] In an exemplary embodiment of the present disclosure, the first storage module includes: a first capacitor, a first electrode connected to the second node, and a second electrode receiving the second level signal; the second storage module includes: a second capacitor, a first electrode connected to the fourth node, and a second electrode connected to the fifth node.

[0018] According to a second aspect of the present disclosure, a display panel is further provided, comprising the gate driving circuit described in any embodiment of the present disclosure.

[0019] In the gate drive circuit disclosed herein, by cascading the shift register units according to the above relationship, one repeating unit can output four rows of gate signals. Compared with the prior art, the circuit structure of the gate drive circuit is simplified, thereby reducing the RC load in the circuit. The space saved by the simplified circuit structure can also reduce the size of the side frame, thereby improving the competitiveness of the product.

[0020] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0022] Figure 1 is a structural block diagram of a gate drive circuit according to an embodiment of the present disclosure;

[0023] Figure 2 1 is a schematic structural diagram of a gate driving circuit according to another embodiment of the present disclosure;

[0024] Figure 3 for Figure 1 The structural block diagram of a shift register unit in FIG;

[0025] Figure 4 1 is a schematic structural diagram of a shift register unit according to another embodiment of the present disclosure;

[0026] Figure 5 for Figure 3 Timing diagram of each node in;

[0027] Figure 6 is an equivalent circuit diagram of the first shift register unit in the first stage;

[0028] Figure 7 is an equivalent circuit diagram of the second shift register unit in the first stage;

[0029] Figure 8 is an equivalent circuit diagram of the first shift register unit in the second stage;

[0030] Figure 9 is an equivalent circuit diagram of the second shift register unit in the second stage;

[0031] Figure 10 is an equivalent circuit diagram of the first shift register unit in the third stage;

[0032] Figure 11 is an equivalent circuit diagram of the second shift register unit in the third stage;

[0033] Figure 12 is an equivalent circuit diagram of the first shift register unit in the fourth stage;

[0034] Figure 13 is an equivalent circuit diagram of the second shift register unit in the fourth stage;

[0035] Figure 14 is an equivalent circuit diagram of the first shift register unit in the fifth stage;

[0036] Figure 15 FIG. 4 is an equivalent circuit diagram of the second shift register unit in the fifth stage. DETAILED DESCRIPTION

[0037] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, may, however, be implemented in many different forms and should not be construed as limited to the implementations set forth herein; rather, these implementations are provided as non-limiting examples so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the figures, and thus a detailed description of the same will not be repeated. In addition, the drawings are only schematic and the dimensions are not necessarily to scale.

[0038] Although relative terms such as "on", "under", "lower", "upper" and the like can be used herein to describe one element's relationship to another element as the device is oriented in the figures, such terms are used on the drawings and / or in the specification solely to illustrate the particular aspects of the example, and do not limit the position, location and / or orientation of the device. It will be understood that the device can be oriented differently (e.g., rotated 90 degrees, inverted, etc.) and that the descriptors used herein are not intended to be limiting.

[0039] The terms "a", "an", "the" and "at least one" are used to mean one or more of something; the terms "comprises", "comprising", "includes", "including" and the like can mean including but not limited to; the term "first", "second", "third" and the like can be used to mean various ordinal numbers and do not indicate a quantity or a particular ordering, but are used to distinguish one element from another.

[0040] Figure 1 A structural block diagram of a gate driving circuit according to an embodiment of the present disclosure is shown in FIG. 1. Figure 1As shown, the gate drive circuit may include a plurality of repeating units Q, the repeating unit Q including a first shift register unit GOA1 and a second shift register unit GOA2 connected in cascade, the first shift register unit GOA1 and the second shift register unit GOA2 each including an input selection module 11, an output selection module 20, an input terminal Input, a feedback terminal FB and two output terminals; in the same repeating unit Q, the feedback terminal FB of the first shift register unit GOA1 is connected to the first output terminal Out1 of the second shift register unit GOA2, the first output terminal Out1 of the first shift register unit GOA1 is connected to the input terminal Input of the second shift register unit GOA2, and the second output terminal Out2 of the first shift register unit GOA1 is connected to the feedback terminal FB of the second shift register unit GOA2; in two adjacent repeating units Q, the second output terminal Out2 of the second shift register unit GOA2 in the previous repeating unit Q is connected to the input terminal Input of the first shift register unit GOA1 in the next repeating unit Q; in the same shift register unit, the input selection module 11 is connected to the input terminal In put, a first selection terminal Odd_A, a second selection terminal Odd_B and a feedback terminal FB, the input selection module 11 is used to respond to the signal of the first selection terminal Odd_A and use the signal of the input terminal Input for input, or respond to the signal of the second selection terminal Odd_B and use the signal of the feedback terminal FB for input; the output selection module 20 is connected to the first output terminal Out1, the second output terminal Out2, the first selection terminal Odd_A and the second selection terminal Odd_B, and the output selection module 20 is used to respond to the signal of the first selection terminal Odd_A and output through the first output terminal Out1 or respond to the signal of the second selection terminal Odd_B and output through the second output terminal Out2; wherein, in the same shift register unit, the polarity of the signal of the first selection terminal Odd_A is opposite to that of the second selection terminal Odd_B; the signal of the first clock signal terminal CK is inverted with the signal of the second clock signal terminal CB, and the signals of the first clock signal terminal CK and the second clock signal terminal CB of the first shift register unit GOA1 are correspondingly inverted with the signals of the first clock signal terminal CK and the second clock signal terminal CB of the second shift register unit GOA2.

[0041] In the gate drive circuit disclosed herein, by cascading the shift register units according to the above relationship, one repeating unit Q can output four rows of gate signals. Compared with the existing technology, the circuit structure of the gate drive circuit is simplified, thereby reducing the RC load in the circuit. The space saved by the simplified circuit structure can also reduce the size of the side frame, thereby improving the competitiveness of the product.

[0042] The input selection module 11 is connected with the first selection end Odd_A and the second selection end Odd_B, so that when the first selection end Odd_A is at an on level, the input selection module 11 can input the signal of the input end Input, i.e., transmit the signal of the input end Input to the internal circuit of the shift register unit. When the second selection end Odd_B is at an on level, the input selection module 11 can input the signal of the feedback end FB, i.e., transmit the signal of the feedback end FB to the internal circuit of the shift register unit. Similarly, the output selection module 20 is connected with the first selection end Odd_A and the second selection end Odd_B, when the first selection end Odd_A is at an on level, the output selection module 20 can output through the first output end Out1, and when the second selection end Odd_B is at an on level, the output selection module 20 can output through the second output end Out2. The specific circuit structure of the input selection module 11 and the output selection module 20 can be referred to the introduction of subsequent embodiments, which is not expanded here.

[0043] The on level output by a certain signal end in the present disclosure can be understood as that the level output by the signal end can turn on or open the circuit structure connected with the signal end. Correspondingly, the level output by a certain signal end is at a non-on level, i.e., the level signal output by the signal end can control the circuit structure connected with the signal end to be closed.

[0044] The signal of the first clock signal end CK and the signal of the second clock signal end CB are opposite, which means that when the first clock signal end CK outputs a high level signal, the second clock signal end CB outputs a low level signal, or when the first clock signal end CK is at a low level signal, the second clock signal end CB is at a high level signal.

[0045] It should be noted that the high level and the low level in the present disclosure refer to two logic states represented by the potential range of the circuit node. The high level can specifically refer to a level higher than the voltage of the common end, and the low level can specifically refer to a level lower than the voltage of the common end. The specific potential range can be set according to the needs in specific application scenarios, which is not limited in the present disclosure.

[0046] The signals at the first clock signal terminal CK and the second clock signal terminal CB of the first shift register unit GOA1 are inverted in phase with the signals at the first clock signal terminal CK and the second clock signal terminal CB of the second shift register unit GOA2, that is, the first clock signal terminal CK of the first shift register unit GOA1 is inverted in phase with the signal at the first clock signal terminal CK of the second shift register unit GOA2, and the second clock signal terminal CB of the first shift register unit GOA1 is inverted in phase with the signal at the second clock signal terminal CB of the second shift register unit GOA2. For example, when the first clock signal terminal CK of the first shift register unit GOA1 is at a high level, the second clock signal terminal CB of the first shift register unit GOA1 is at a low level, and the first clock signal terminal CK of the second shift register unit GOA2 is at a low level and the second clock signal terminal CB is at a high level.

[0047] In any repeating unit of the present disclosure, the first output terminal Out1 of the first shift register unit GOA1 serves as the nth output terminal G-out(n) of the gate drive circuit, and the second output terminal Out2 of the first shift register unit GOA1 serves as the (n+2)th output terminal G-out(n+2) of the gate drive circuit; the first output terminal Out1 of the second shift register unit GOA2 serves as the (n+1)th output terminal G-out(n+1) of the gate drive circuit, and the second output terminal Out2 of the second shift register unit GOA2 serves as the (n+3)th output terminal G-out(n+3) of the gate drive circuit, where n is a natural number greater than or equal to 1. That is, the first output terminal Out1 and the second output terminal Out2 of the first shift register unit GOA1 are used to output the nth row gate signal and the (n+2)th row gate signal, respectively, and the first output terminal Out1 and the second output terminal Out2 of the second shift register unit GOA2 are used to output the (n+1)th row gate signal and the (n+3)th row gate signal, respectively. It can be seen that the same shift register unit is used to output gate signals to two pixel rows separated by one row in the display area to drive two sub-pixels separated by one row. Thus, a repeating unit Q can sequentially output four consecutive rows of gate signals to the display area to sequentially drive four consecutive rows of sub-pixels. Compared with the gate drive circuit in the prior art, the circuit structure of the gate drive circuit of the present disclosure outputting the same number of gate signals is simplified, thereby saving the space occupied by the gate drive circuit, and the saved space is conducive to reducing the frame size. It can also be understood that the gate drive circuit is usually composed of transistors. By simplifying the circuit structure of the gate drive circuit, the number of transistors used in the gate drive circuit can be reduced, thereby reducing the RC load in the circuit.

[0048] The specific structure of the gate drive circuit disclosed in the present invention is introduced below with reference to the accompanying drawings.

[0049] Figure 2 FIG. 1 is a schematic structural diagram of a gate drive circuit according to another embodiment of the present disclosure, as shown in FIG. Figure 2 As shown, both the input selection module and the output selection module can be implemented by transistors. The input selection module can include a first selection transistor TS1 and a second selection transistor TS2. The first electrode of the first selection transistor TS1 is connected to the input terminal, the second electrode is connected to the first node N1, and the gate is connected to the first selection terminal. The first selection transistor TS1 can be used to transmit the signal of the input terminal to the first node N1 in response to the signal of the first selection terminal; the first electrode of the second selection transistor TS2 is connected to the feedback terminal FB, the second electrode is connected to the first node N1, and the gate is connected to the second selection terminal. The second selection transistor TS2 can be used to transmit the signal of the feedback terminal FB to the first node N1 in response to the signal of the second selection terminal; the output selection module can include a third selection transistor TS3 and a fourth selection transistor TS4. The first electrode of the third selection transistor TS3 is connected to the fifth node N5, the second electrode is connected to the first output terminal, and the gate is connected to the first selection terminal. The third selection transistor TS3 can be used to transmit the signal of the fifth node N5 to the first output terminal in response to the signal of the first selection terminal; the first electrode of the fourth selection transistor TS4 is connected to the fifth node N5, the second electrode is connected to the second output terminal, and the gate is connected to the second selection terminal. The fourth selection transistor TS4 can be used to transmit the signal of the fifth node N5 to the second output terminal in response to the signal of the second selection terminal.

[0050] Among them, the first selection transistor TS1 to the fourth selection transistor TS4 are all P-type transistors. When the first selection terminal is at a low level and the second selection terminal is at a high level, the first selection transistor TS1 and the third selection transistor TS3 are turned on, and the second selection transistor TS2 and the fourth selection transistor TS4 are turned off. At the input terminal, the shift register unit uses the signal at the input terminal as input, and at the output terminal, the first output terminal of the shift register unit outputs the signal of the fifth node N5. When the first selection terminal is at a high level and the second selection terminal is at a low level, the first selection transistor TS1 and the third selection transistor TS3 are turned off, and the second selection transistor TS2 and the fourth selection transistor TS4 are turned on. At the input terminal, the signal at the feedback terminal FB is used as input. At the output terminal, the second output terminal outputs the signal of the fifth node N5.

[0051] The shift register unit works through the specific structure of the input selection module and the output selection module and the above-mentioned cascade relationship, and cooperates with the timing of each node to achieve a repeating unit composed of the first shift register unit GOA1 and the second shift register unit GOA2 to output four rows of gate signals.

[0052] Figure 3 for Figure 1 The structural block diagram of a shift register unit in Figure 3As shown, the first shift register unit GOA1 and the second shift register unit GOA2 can further include an input module 12, a first control module 14, a second control module 13, a reset module 15, a protection module 16, a first output module 21, a second output module 22, a first storage module 31 and a second storage module 32. The input module 12 is connected to the first node N1, the third node N3 and the first clock signal terminal CK. The input module 12 can be configured to transmit the signal of the first node N1 to the third node N3 in response to the signal of the first clock signal terminal CK. For example, when the first clock signal terminal CK is at a low level, the input module 12 is turned on to transmit the signal of the first node N1 to the third node N3.

[0053] The first control module 14 is connected to the second node N2, the first clock signal terminal CK and receives the first level signal VGL. The first control module 14 can be configured to pull down the second node N2 using the first level signal VGL in response to the signal of the first clock signal terminal CK. The first level signal VGL can be a low level signal. When the first clock signal terminal CK is at a low level, the first control module 14 is turned on to pull down the second node N2 using the first level signal VGL.

[0054] The second control module 13 is connected to the second node N2, the third node N3 and the first clock signal terminal CK. The second control module 13 can be configured to pull up the second node N2 using the signal of the first clock signal terminal CK in response to the signal of the third node N3. The second control module 13 is controlled by the third node N3. When the third node N3 is at a low level, the second control module 13 is turned on. At this time, if the first clock signal terminal CK is at a high level signal, the second control module 13 can pull up the second node N2; if the first clock signal terminal CK is at a low level signal, the second control module 13 can pull down the second node N2.

[0055] It should be understood that the "pull up" in the present disclosure refers to pulling the potential at the corresponding circuit node to a high level, and the "pull down" refers to pulling the potential at the corresponding circuit node to a low level. It can be understood that the "pull up" and "pull down" described above can be realized by the directional movement of electric charge, and therefore can be realized by electronic components or combinations thereof having corresponding functions, which are not limited in the present disclosure.

[0056] The reset module 15 is connected to the second node N2, the third node N3, and the second clock signal terminal CB and receives the second level signal VGH. The reset module 15 can be configured to respond to the signal of the second node N2 and the signal of the second clock signal terminal CB and reset the third node N3 using the second level signal VGH. The reset module 15 can perform a reset before any signal input. For example, when the second clock signal terminal CB and the second node N2 are both at a low level, the reset module 15 can be controlled to conduct and the third node N3 can be pulled high using the second level signal VGH, thereby resetting the third node N3.

[0057] The protection module 16 is connected to the third node N3 and the fourth node N4 and receives the first level signal VGL. The protection module 16 can be configured to transmit the signal from the third node N3 to the fourth node N4 in response to the first level signal VGL, or to shut down in response to the voltage difference between the first level signal VGL and the signal from the fourth node N4. The protection module 16 can be shut down when the potential difference between the first level signal VGL and the fourth node N4 is large, thereby preventing the potential of the third node N3 from being affected. In other words, the protection module 16 can prevent the potential of the fourth node N4 from affecting the potential of the third node N3, maintaining the potential of the third node N3 stable. This protects the input module 12, the second control module 13, and the reset module 15 from maintaining stable operation.

[0058] The first storage module 31 is connected to the second node N2 and receives the second level signal VGH. The first storage module 31 can be used to maintain the stability of the potential of the second node N2; the second storage module 32 is connected to the fourth node N4 and the fifth node N5. The second storage module 32 can be used to bootstrap the fourth node N4 when the signal of the fifth node N5 has the same polarity as the signal of the fourth node N4.

[0059] Figure 4 FIG. 1 is a structural diagram of a shift register unit according to another embodiment of the present disclosure, as shown in FIG. Figure 4As shown, the first storage module and the second storage module in the gate drive circuit of the present disclosure can be implemented by storage capacitors, and the other functional modules can be implemented by transistors. In an exemplary embodiment, the input module 12 may include a first transistor T1, wherein the first electrode of the first transistor T1 is connected to the first node N1, the second electrode is connected to the third node N3, and the gate is connected to the first clock signal terminal CK. The first transistor T1 can be used to transmit the signal of the first node N1 to the third node N3 in response to the signal of the first clock signal terminal CK. The first control module 14 may include a first control transistor TD, wherein the first electrode of the first control transistor TD receives the first level signal VGL, the second electrode is connected to the second node N2, and the gate is connected to the first clock signal terminal CK. The first control transistor TD can be used to transmit the first level signal VGL to the second node N2 in response to the signal of the first clock signal terminal CK. The second control module 13 may include a second control transistor TU, wherein the first electrode of the second control transistor TU is connected to the second node N2, the second electrode is connected to the first clock signal terminal CK, and the gate is connected to the third node N3. The second control transistor TU can be used to pull down the second node N2 using the signal of the first clock signal terminal CK in response to the signal of the third node N3. The reset module 15 may include a first reset transistor TR1 and a second reset transistor TR2. The first reset transistor TR1 has a first electrode connected to receive a second level signal VGH, a second electrode connected to the sixth node, and a gate connected to the second node N2. The first reset transistor TR1 may be configured to transmit the second level signal VGH to the sixth node in response to a signal at the second node N2. The second reset transistor TR2 has a first electrode connected to a third node N3, a second electrode connected to the sixth node, and a gate connected to the second clock signal terminal CB. The second reset transistor TR2 may be configured to transmit a signal at the sixth node to the third node N3 in response to a signal at the second clock signal terminal CB, thereby resetting the third node N3. The protection module 16 may include a second transistor T2. The second transistor T2 has a first electrode connected to the third node N3, a second electrode connected to the fourth node N4, and a gate connected to receive a first level signal VGL. The second transistor T2 may be configured to transmit a signal at the third node N3 to the fourth node N4 in response to the first level signal VGL, or to be turned off in response to a voltage difference between the first level signal VGL and the signal at the fourth node N4. The first output module 21 may include a first output transistor TO1 and a second output transistor TO2. The first electrode of the first output transistor TO1 receives the second level signal VGH, the second electrode is connected to the first output end, and the gate is connected to the second node. The first output transistor TO1 can be used to transmit the second level signal VGH to the first output end in response to the signal of the second node; the first electrode of the second output transistor TO2 receives the second level signal VGH, the second electrode is connected to the second output end, and the gate is connected to the second node. The second output transistor TO2 can be used to transmit the second level signal VGH to the second output end in response to the signal of the second node.The second output module 22 may include a third output transistor TO3, a first electrode of the third output transistor TO3 is connected to the fifth node, a second electrode is connected to the second clock signal terminal CB, and a gate is connected to the fourth node. The third output transistor TO3 can be used to transmit the signal of the second clock signal terminal CB to the fifth node in response to the signal of the fourth node.

[0060] The aforementioned transistors may be P-type transistors, such as P-type low-temperature polysilicon transistors. Of course, in other embodiments, the aforementioned transistors may also be N-type transistors. This disclosure only uses P-type transistors as an example for illustrative description.

[0061] Figure 5 for Figure 3 The timing diagram of each node in Figure 6 is the equivalent circuit diagram of the first shift register unit in the first stage, Figure 7 FIG1 is an equivalent circuit diagram of the second shift register unit in the first stage. It should be understood that for the convenience of explaining the working principle of the shift register unit, Figure 6 The first-stage shift register unit is used as an example for illustrative description. The input terminal of the first-stage shift register unit is connected to the start signal STV. In addition, because the first selection terminal and the second selection terminal in the first shift register unit GOA1 and the second shift register unit GOA2 are distinguished, Odd_A represents the first selection terminal in the first shift register unit GOA1, Odd_B represents the second selection terminal in the first shift register unit GOA1, Even_A represents the first selection terminal in the second shift register unit GOA2, and Even_B represents the second selection terminal in the second shift register unit GOA2.

[0062] In addition, if Figure 5 As shown, when the first selection terminal Odd_A of the first shift register unit GOA1 outputs a conduction level with a conduction duration of T, the first selection terminal Even_A of the second shift register unit GOA2 sequentially outputs a conduction level and a non-conduction level with a duration of T / 2; when the second selection terminal Odd_B of the first shift register unit GOA1 outputs a conduction level with a conduction duration of T, the second selection terminal Even_B of the second shift register unit GOA2 sequentially outputs a non-conduction level and a conduction level with a duration of T / 2.

[0063] Furthermore, the conduction level durations of the first clock signal terminal CK and the second clock signal terminal CB are both t, where t=T / 2.

[0064] Furthermore, when the input terminal Input of the first shift register unit GOA1 is at a conducting level, the first clock signal terminal CK of the first shift register unit GOA1 is at a conducting level, and the second clock signal terminal CB is at a non-conducting level.

[0065] like Figure 5 As shown, in the first gating stage T1, the first selection terminal Odd_A of the first shift register unit GOA1 is at a low level, the second selection terminal Odd_B is at a high level, the first selection transistor TS1 and the third selection transistor TS3 in the first shift register unit GOA1 are turned on, and the second selection transistor TS2 and the fourth selection transistor TS4 are turned off.

[0066] like Figure 5 and Figure 6 As shown, in the first phase t1, in the first shift register unit GOA1, the input terminal Input is at a low level, so that the first selection transistor TS1 transmits the low-level signal of the input terminal Input to the first node N1, causing the first node N1 to be at a low level. At the same time, in this first phase t1, the first clock signal terminal CK of the first shift register unit GOA1 is at a low level and the second clock signal terminal CB is at a high level, so that the first transistor T1 is turned on, transmitting the low-level signal of the first node N1 to the third node N3, causing the third node N3 to become a low level.

[0067] like Figure 6 As shown, under the control of the low-level signal of the first clock signal terminal CK, the first control transistor TD is turned on, and the first-level signal VGL pulls down the second node N2, that is, the second node N2 becomes low. Under the control of the low-level signal of the second node N2, the first output transistor TO1 and the second output transistor TO2 are turned on, transmitting the second-level signal VGH to the first output terminal Out1 and the second output terminal Out2, so that the first output terminal Out1 and the second output terminal Out2 of the first shift register unit GOA1 both output high-level signals at this stage, that is, the first output terminal G-out1 and the third output terminal G-out3 of the gate drive circuit both output high-level signals.

[0068] At the same time, in the first stage t1, if Figure 7 As shown, in the second shift register unit GOA2, the first selection terminal Even_A is at a high level, the second selection terminal Even_B is at a low level, the first clock signal terminal CK is at a high level, and the second clock signal terminal CB is at a low level. At this time, the first selection transistor TS1 and the third selection transistor TS3 are turned off, the second selection transistor TS2 and the fourth selection transistor TS4 are turned on, and the second selection transistor TS2 transmits the feedback terminal FB, i.e., the signal of the second output terminal Out2 of the first shift register unit GOA1, to the first node N1, so that the first node N1 of the second shift register unit GOA2 is at a high level. At the same time, the first transistor T1 and the first control transistor TD are turned off, the second node N2 maintains the low level signal of the previous stage, and the third node N3 maintains the high level signal of the previous stage.

[0069] like Figure 7 As shown, under the control of the low-level signal of the second node N2, the first output transistor TO1 and the second output transistor TO2 in the second shift register unit GOA2 are turned on, and the second-level signal VGH is transmitted to the first output terminal Out1 and the second output terminal Out2, so that the second output terminal G-out2 and the fourth output terminal G-out4 of the gate drive circuit both output high-level signals at this stage.

[0070] In the second phase t2, in the first shift register unit GOA1, the first selection terminal Odd_A is at a low level, the second selection terminal Odd_B is at a high level, the first clock signal terminal CK is at a high level, and the second clock signal terminal CB is at a low level. In the second shift register unit GOA2, the first selection terminal Even_A is at a low level, the second selection terminal Even_B is at a high level, the first clock signal terminal CK is at a low level, and the second clock signal terminal CB is at a high level. Figure 8 is the equivalent circuit diagram of the first shift register unit in the second stage, Figure 9 FIG. 4 is an equivalent circuit diagram of the second shift register unit in the second stage.

[0071] like Figure 8 As shown, the first selection transistor TS1 and the third selection transistor TS3 are turned on, and the second selection transistor TS2 and the fourth selection transistor TS4 are turned off. The first transistor T1 and the first control transistor TD are turned off, the third node N3 maintains the low-level signal of the previous stage, and the second control transistor TU is turned on to transmit the high-level signal of the first clock signal terminal CK to the second node N2, so that the second node N2 now becomes a high level.

[0072] like Figure 8 As shown, the second transistor T2 is turned on, making the fourth node N4 and the third node N3 equal in potential and both at a low level. Under the control of the low-level signal at the fourth node N4, the third output transistor T03 is turned on, transmitting the low-level signal from the second clock signal terminal CB to the fifth node N5, causing the fifth node N5 to change to a low level. Moreover, at this time, the fourth node N4 and the second clock signal terminal CB are both at a low level, and the second capacitor C2 performs a bootstrap operation, further lowering the potential of the fourth node N4. At this time, the gate-source voltage Vgs of the second transistor T2 is greater than Vth, and the second transistor T2 is turned off.

[0073] like Figure 8As shown, under the control of the low-level signal at the first selection terminal Odd_A, the third selection transistor TS3 is turned on, transmitting the low-level signal at the fifth node N5 to the first output terminal Out1, so that the first output terminal Out1 now outputs a low-level signal. The second output transistor TO2 and the fourth selection transistor TS4 are both turned off, so that the second output terminal Out2 maintains the output of the high-level signal. In this way, the first output G-out1 of the gate drive circuit now outputs a low-level signal, realizing the first shift signal output.

[0074] In the second stage t2, as Figure 9 As shown, in the second shift register unit GOA2, the first selection terminal Even_A is at a low level, the second selection terminal Even_B is at a high level, the first clock signal terminal CK is at a low level, and the second clock signal terminal CB is at a high level. The first selection transistor TS1 and the third selection transistor TS3 are turned on, and the second selection transistor TS2 and the fourth selection transistor TS4 are turned off, thereby transmitting the low-level signal at the input terminal Input, i.e., the first output terminal Out1 of the first shift register unit GOA1, to the first node N1, causing the first node N1 to become a low level at this time.

[0075] like Figure 9 As shown, under the control of the low level signal of the first clock signal terminal CK, the first transistor T1 and the first control transistor TD are turned on, so that the second node N2 and the third node N3 are both at a low level.

[0076] like Figure 9 As shown, under the control of the low-level signal of the second node N2, the first output transistor TO1 and the second output transistor TO2 are turned on, so that the first output terminal Out1 and the second output terminal Out2 in the second shift register unit GOA2 both output high levels, that is, the second output terminal G-out2 and the fourth output terminal G-out4 of the gate drive circuit output high-level signals at this time.

[0077] In the second selection phase T2, the first selection terminal Odd_A of the first shift register unit GOA1 is at a high level, the second selection terminal Odd_B is at a low level, the first selection transistor TS1 and the third selection transistor TS3 of the first shift register unit GOA1 are turned off, and the second selection transistor TS2 and the fourth selection transistor TS4 are turned on.

[0078] Figure 10 is the equivalent circuit diagram of the first shift register unit in the third stage, Figure 11 is an equivalent circuit diagram of the second shift register unit in the third stage.

[0079] like Figure 10As shown, in the third phase t3, in the first shift register unit GOA1, the first clock signal terminal CK is at a low level and the second clock signal terminal CB is at a high level, thereby turning on the first transistor T1 and the first control transistor TD. The third node N3 and the first node N1 are at the same potential, and both are high-level signals output by the second output terminal G-out2 of the gate drive circuit. The second node N2 is pulled down to a low level by the first level signal VGL.

[0080] like Figure 10 As shown, under the control of the low-level signal at the second node N2, the first output transistor TO1 and the second output transistor TO2 are turned on, so that the first output terminal Out1 and the second output terminal Out2 both output the second-level signal VGH. That is, the first output terminal G-out1 and the third output terminal G-out3 of the gate drive circuit both output high-level signals. The second transistor T2 is still in the off state at this time. During this process, the second-level signal VGH charges the fifth node N5 through the fourth selection transistor TS4, so that the potential of the fifth node N5 gradually decreases.

[0081] At the same time, in the third stage t3, as Figure 11 As shown, in the second shift register unit GOA2, the first selection terminal Even_A is at a low level, the second selection terminal Even_B is at a high level, the first clock signal terminal CK is at a high level, and the second clock signal terminal CB is at a low level. As a result, the first selection transistor TS1 and the third selection transistor TS3 are turned on, and the second selection transistor TS2 and the fourth selection transistor TS4 are turned off. The first clock signal terminal CK is at a high level, causing the first transistor T1 and the first control transistor TD to turn off, and the third node N3 maintains the low level of the previous stage. The second control transistor TU is turned on under the control of the low level signal of the third node N3, transmitting the high level signal of the first clock signal terminal CK to the second node N2, causing the second node N2 to become a high level at this time, and the first output transistor TO1 and the second output transistor TO2 are both turned off.

[0082] In addition, if Figure 10 As shown, the third output transistor TO3 is turned off, and the fifth node N5 maintains the low level of the previous stage.

[0083] like Figure 11As shown, the second transistor T2 is turned on, causing the fourth node N4 to be at a low level. Under the control of the low-level signal at the fourth node N4, the third output transistor TO3 is turned on, transmitting the low-level signal at the second clock signal terminal CB to the fifth node N5, that is, the fifth node N5 becomes low. At this time, the turned-on third selection transistor TS3 transmits the low-level signal at the fifth node N5 to the first output terminal Out1, so that the first output terminal Out1 now outputs a low-level signal, that is, the second output terminal G-out2 of the gate drive circuit outputs a low level, and the fourth output terminal outputs a high level, realizing the second shift signal output.

[0084] In the fourth stage t4, in the first shift register unit GOA1, the first selection terminal Odd_A is at a high level, the second selection terminal Odd_B is at a low level, the first clock signal terminal CK is at a high level, and the second clock signal terminal CB is at a low level. In the second shift register unit GOA2, the first selection terminal Even_A is at a high level, the second selection terminal Even_B is at a low level, the first clock signal terminal CK is at a low level, and the second clock signal terminal CB is at a high level. Figure 12 is the equivalent circuit diagram of the first shift register unit in the fourth stage, Figure 13 is an equivalent circuit diagram of the second shift register unit in the fourth stage.

[0085] like Figure 13 As shown, the first selection transistor TS1 and the third selection transistor TS3 are turned off, while the second selection transistor TS2 and the fourth selection transistor TS4 are turned on. Both the first transistor T1 and the first control transistor TD are turned off. During this process, the potential of the fifth node N5 decreases, causing the potential of the fourth node N4 to decrease, thereby turning on the second transistor T2 and transmitting the low-level signal of the fourth node N4 to the third node N3, causing the third node N3 to be at a low level. Under the control of the low level of the third node N3, the second control transistor TU is turned on, pulling up the second node N2, causing the second node N2 to become a high level, thereby turning off the first output transistor TO1 and the second output transistor TO2.

[0086] At the same time, under the low level control of the fourth node N4, the third output transistor TO3 is turned on, and the low level signal of the second clock signal terminal CK is transmitted to the fifth node N5, so that the fourth selection transistor TS4 outputs the low level signal of the fifth node N5, that is, the third output terminal G-out3 of the gate drive circuit outputs a low level signal at this time, realizing the third shift signal output.

[0087] like Figure 13As shown, in the second phase t4, in the second shift register unit GOA2, the first selection terminal Even_A becomes high, the second selection terminal Even_B becomes low, the first clock signal terminal CK is low, and the second clock signal terminal CB is high.

[0088] like Figure 13 As shown, the first selection transistor TS1 and the third selection transistor TS3 are turned off, the second selection transistor TS2 and the fourth selection transistor TS4 are turned on, and the first transistor T1 and the first control transistor TD are turned on. The second selection transistor TS2 transmits the low-level signal from the feedback terminal FB, i.e., the third output terminal Out3 of the gate drive circuit, to the first node N1, causing the first node N1 to be at a low level. The first transistor T1 transmits the low-level signal from the first node N1 to the third node N3, causing the third node N3 to be at a low level. The first control transistor TD is turned on and transmits the first-level signal VGL to the second node N2, causing the second node N2 to be at a low level.

[0089] like Figure 14 As shown, under the control of the low-level signal of the second node N2, the first output transistor TO1 and the second output transistor TO2 are turned on, and the second-level signal VGH is transmitted to the first output terminal Out1 and the second output terminal Out2 for output, so that the first output terminal Out1 and the third output terminal Out3 of the gate drive circuit both output a high level at this time.

[0090] In the third selection phase T3, in the first shift register unit GOA1, the first selection terminal Odd_A is at a low level and the second selection terminal Odd_B is at a high level, so that the first selection transistor TS1 and the third selection transistor TS3 are turned on and the second selection transistor TS2 and the fourth selection transistor TS4 are turned off.

[0091] Figure 15 is the equivalent circuit diagram of the first shift register unit in the fifth stage, Figure 14 FIG. 4 is an equivalent circuit diagram of the second shift register unit in the fifth stage.

[0092] like Figure 14 As shown, in the fifth stage t5, in the first shift register unit GOA1, the first clock signal terminal CK is at a low level and the second clock signal terminal CB is at a high level, so that the first transistor T1 and the first control transistor TD are turned on. The first transistor T1 is turned on and uses the high-level signal of the first node N1 to pull up the third node N3, so that the third node N3 is now at a high level. The first control transistor TD is turned on and uses the first-level signal VGL to pull down the second node N2, so that the second node N2 is now at a low level.

[0093] like Figure 15As shown, under the control of the low-level signal of the second node N2, the first output transistor TO1 and the second output transistor TO2 are both turned on, so that the first output terminal Out1 and the second output terminal Out2 both output the second-level signal VGH, that is, the first output terminal G-out1 and the third output terminal G-out3 of the gate drive circuit both output a high level at this time.

[0094] like Figure 15 As shown, in the second shift register unit GOA2, the first selection terminal Even_A is at a high level and the second selection terminal Even_B is at a low level, thereby turning off the first selection transistor TS1 and turning on the second selection transistor TS2. Simultaneously, the first clock signal terminal CK is at a high level and the second clock signal terminal CB is at a low level, thereby turning off both the first transistor T1 and the first control transistor TD. The third node N3 maintains the low-level signal from the previous stage. Under the control of the low-level signal at the third node N3, the second control transistor TU is turned on, transmitting the high-level signal from the first clock signal terminal CK to the second node N2, causing the second node N2 to become high. Consequently, both the first output transistor TO1 and the second output transistor TO2 are turned off.

[0095] like ​ As shown, the fourth node N4 is at a low level, so the third transistor TO3 is turned on, transmitting the low level signal of the second clock signal terminal CB to the fifth node N5, that is, the fifth node N5 is at a low level at this time. The turned-on fourth selection transistor TS4 transmits the low level signal of the fifth node N5 to the second output terminal Out2, so that the fourth output terminal G-out4 of the gate drive circuit outputs a low level, realizing the fourth shift output of the shift register unit.

[0096] Thus, after a complete cycle from the first stage t1 to the fifth stage t5, the gate drive circuit's first output terminal Out1, second output terminal Out2, third output terminal Out3, and fourth output terminal sequentially output low-level signals, shifting the signal at the input terminal Input in sequence. Thereafter, the gate drive circuit repeats the above process, outputting the shifted signal step by step.

[0097] It can be seen that in the gate drive circuit disclosed herein, the first shift register unit GOA1 and the second shift register unit GOA2 can both output two rows of gate signals, and a first shift register unit GOA1 and a second shift register unit GOA2 constitute a repeating unit Q, so that a repeating unit Q can output four rows of gate signals to the display area.

[0098] According to a second aspect of the present disclosure, a display panel is further provided, comprising the gate driving circuit described in any embodiment of the present disclosure.

[0099] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow from the generality of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

Claims

1. A gate drive circuit, characterized in that: The device comprises a plurality of repeating units, wherein the repeating units include a first shift register unit and a second shift register unit connected in cascade, wherein the first shift register unit and the second shift register unit each include an input selection module, an output selection module, an input terminal, a feedback terminal, and two output terminals, and the first shift register unit and the second shift register unit are respectively connected to a first clock signal terminal and a second clock signal terminal; In the same repeating unit, the feedback end of the first shift register unit is connected to the first output end of the second shift register unit, the first output end of the first shift register unit is connected to the input end of the second shift register unit, and the second output end of the first shift register unit is connected to the feedback end of the second shift register unit; In two adjacent repeating units, the second output end of the second shift register unit in the previous repeating unit is connected to the input end of the first shift register unit in the next repeating unit; In the same shift register unit, the input selection module is connected to the input terminal, the first selection terminal, the second selection terminal, and the feedback terminal, and is configured to respond to a signal from the first selection terminal and use the signal from the input terminal for input, or respond to a signal from the second selection terminal and use the signal from the feedback terminal for input; the output selection module is connected to the first output terminal, the second output terminal, the first selection terminal, and the second selection terminal, and is configured to respond to a signal from the first selection terminal and output through the first output terminal, or respond to a signal from the second selection terminal and output through the second output terminal; Wherein, in the same shift register unit, the polarity of the signal at the first selection end is opposite to that of the signal at the second selection end, and the conduction levels of the first selection ends and the conduction levels of the second selection ends of the two shift register units in the same repeating unit partially overlap; The signal at the first clock signal end is inverted with the signal at the second clock signal end, and the signals at the first clock signal end and the second clock signal end of the first shift register unit are correspondingly inverted with the signals at the first clock signal end and the second clock signal end of the second shift register unit.

2. The gate drive circuit according to claim 1, wherein: In any repeating unit, the first output end of the first shift register unit serves as the nth output end of the gate driving circuit, and the second output end of the first shift register unit serves as the (n+2)th output end of the gate driving circuit; The first output end of the second shift register unit serves as the (n+1)th output end of the gate drive circuit, and the second output end of the second shift register unit serves as the (n+3)th output end of the gate drive circuit, where n is a natural number greater than or equal to 1.

3. The gate drive circuit according to claim 1, wherein: When the first selection end of the first shift register unit outputs a conduction level with a conduction duration of T, the first selection end of the second shift register unit sequentially outputs a conduction level and a non-conduction level with a duration of T / 2; When the second selection end of the first shift register unit outputs a conduction level with a conduction duration of T, the second selection end of the second shift register unit sequentially outputs a non-conduction level and a conduction level with a duration of T / 2.

4. The gate driving circuit according to claim 3, wherein: The conduction level durations of the first clock signal terminal and the second clock signal terminal are both t, where t=T / 2.

5. The gate driving circuit according to claim 1, wherein: When the input terminal of the first shift register unit is at a conducting level, the first clock signal terminal of the first shift register unit is at a conducting level, and the second clock signal terminal is at a non-conducting level.

6. The gate driving circuit according to claim 1, wherein: The input selection module is further connected to the first node, and is further configured to transmit the signal of the input terminal to the first node in response to the signal of the first selection terminal, or to transmit the signal of the feedback terminal to the first node in response to the signal of the second selection terminal; The output selection module is also connected to the fifth node, and is further used to transmit the signal of the fifth node to the first output end in response to the signal of the first selection end, or to transmit the signal of the fifth node to the second output end in response to the signal of the second selection end.

7. The gate driving circuit according to claim 6, wherein: The input selection module and the output selection module both include transistors, and the polarities of the transistors are the same.

8. The gate driving circuit according to claim 6, wherein: The input selection module includes: a first selection transistor, having a first electrode connected to the input terminal, a second electrode connected to the first node, and a gate connected to the first selection terminal, the first selection transistor being configured to transmit a signal from the input terminal to the first node in response to a signal from the first selection terminal; a second selection transistor, having a first electrode connected to the feedback terminal, a second electrode connected to the first node, and a gate connected to the second selection terminal, the second selection transistor being configured to transmit a signal from the feedback terminal to the first node in response to a signal from the second selection terminal; The output selection module includes: a third selection transistor, having a first electrode connected to the fifth node, a second electrode connected to the first output terminal, and a gate connected to the first selection terminal, the third selection transistor being configured to transmit a signal from the fifth node to the first output terminal in response to a signal from the first selection terminal; a fourth selection transistor, having a first electrode connected to the fifth node, a second electrode connected to the second output terminal, and a gate connected to the second selection terminal, the fourth selection transistor being configured to transmit the signal of the fifth node to the second output terminal in response to a signal of the second selection terminal; Wherein, the first to fourth selection transistors are all P-type transistors.

9. The gate driving circuit according to claim 1, wherein: The first shift register unit and the second shift register unit both include: an input module connected to the first node, the third node, and the first clock signal terminal, the input module being configured to transmit the signal of the first node to the third node in response to the signal of the first clock signal terminal; a first control module connected to the second node and the first clock signal terminal and receiving a first level signal, wherein the first control module is configured to pull down the second node using the first level signal in response to a signal at the first clock signal terminal; a second control module connected to the second node, the third node, and the first clock signal terminal, the second control module being configured to respond to a signal from the third node and pull up the second node using a signal from the first clock signal terminal; a reset module connected to the second node, the third node, and the second clock signal terminal and receiving a second level signal, the reset module being configured to reset the third node using the second level signal in response to a signal of the second node and a signal of the second clock signal terminal; a protection module connected to the third node and the fourth node and receiving the first level signal, the protection module being configured to transmit the signal of the third node to the fourth node in response to the first level signal or to be shut down in response to a voltage difference between the first level signal and the signal of the fourth node; a first output module connected to the second node, the first output terminal, and the second output terminal and receiving a second level signal, wherein the first output module is configured to transmit the second level signal to the first output terminal and the second output terminal in response to the signal of the second node; The second output module is connected to the fifth node, the fourth node and the second clock signal end, and is used for transmitting the signal of the second clock signal end to the fifth node in response to the signal of the fourth node.

10. The gate driving circuit according to claim 9, wherein: The input module, the first control module, the second control module, the reset module, the protection module, the first output module, and the second output module all include transistors, and the polarities of the transistors are the same.

11. The gate driving circuit according to claim 9, wherein: The input module includes: a first transistor, having a first electrode connected to the first node, a second electrode connected to the third node, and a gate connected to the first clock signal terminal, the first transistor being configured to transmit a signal from the first node to the third node in response to a signal from the first clock signal terminal; The first control module includes: a first control transistor, having a first electrode receiving the first level signal, a second electrode connected to the second node, and a gate connected to the first clock signal terminal, and the first control transistor is configured to transmit the first level signal to the second node in response to a signal at the first clock signal terminal; The second control module includes: a second control transistor, having a first electrode connected to the second node, a second electrode connected to the first clock signal terminal, and a gate connected to the third node, the second control transistor being configured to respond to a signal at the third node and pull down the second node using a signal at the first clock signal terminal; The reset module includes: a first reset transistor, having a first electrode connected to receive the second level signal, a second electrode connected to the sixth node, and a gate connected to the second node, and the first reset transistor is configured to transmit the second level signal to the sixth node in response to the signal at the second node; a second reset transistor, having a first electrode connected to the third node, a second electrode connected to the sixth node, and a gate connected to the second clock signal terminal, the second reset transistor being configured to transmit a signal from the sixth node to the third node in response to a signal from the second clock signal terminal to reset the third node; The protection module includes: a second transistor, having a first electrode connected to the third node, a second electrode connected to the fourth node, a gate receiving the first level signal, and the second transistor configured to transmit the signal of the third node to the fourth node in response to the first level signal or be turned off in response to a voltage difference between the first level signal and the signal of the fourth node; The first output module includes: a first output transistor, having a first electrode receiving the second level signal, a second electrode connected to the first output terminal, and a gate connected to the second node, and the first output transistor is configured to transmit the second level signal to the first output terminal in response to the signal of the second node; a second output transistor, having a first electrode receiving the second level signal, a second electrode connected to the second output terminal, and a gate connected to the second node, and the second output transistor is configured to transmit the second level signal to the second output terminal in response to the signal of the second node; The second output module includes: A third output transistor has a first electrode connected to the fifth node, a second electrode connected to the second clock signal terminal, and a gate connected to the fourth node. The third output transistor is used to transmit the signal of the second clock signal terminal to the fifth node in response to the signal of the fourth node.

12. The gate driving circuit according to claim 11, wherein: The first transistor, the first control transistor, the second control transistor, the first reset transistor, the second reset transistor, the second transistor, the first output transistor, the second output transistor, and the third output transistor are all P-type transistors.

13. The gate driving circuit according to claim 1, wherein: The first shift register unit and the second shift register unit both further include: a first storage module connected to the second node and receiving a second level signal, wherein the first storage module is used to maintain a stable potential of the second node; The second storage module is connected to the fourth node and the fifth node, and is used for bootstrapping the fourth node when the polarity of the signal of the fifth node is the same as that of the signal of the fourth node.

14. The gate driving circuit according to claim 13, wherein: The first storage module includes: a first capacitor, a first electrode connected to the second node, and a second electrode receiving the second level signal; The second storage module includes: The second capacitor has a first electrode connected to the fourth node and a second electrode connected to the fifth node.

15. A display panel, characterized in that: The gate drive circuit comprises the gate drive circuit according to any one of claims 1 to 14.

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