Solder-based hybrid bonding for fine pitch and thin blt interconnects

Abstract

The present disclosure relates to solder-based hybrid bonding for fine pitch and thin BLT interconnects. A semiconductor device assembly includes a first semiconductor device including a first substrate having a front side surface, a plurality of solder bumps on the front side surface of the first substrate, and a first polymer layer on the front side surface. The semiconductor device assembly also includes a second semiconductor device including a second substrate having a back side surface, a plurality of TSVs protruding from the back side surface of the second substrate, and a second polymer layer on the back side surface of the first substrate, the second polymer layer having a plurality of openings corresponding to the plurality of TSVs. The first and second semiconductor devices are bonded such that the first polymer layer contacts the second polymer layer, and each of the plurality of solder bumps extends into a corresponding one of the plurality of openings and contacts a corresponding one of the plurality of TSVs.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices, and more specifically, to solder-based hybrid semiconductor device bonding incorporating fine-pitch and thin-bond-line-thickness (BLT) interconnects therein. Background Technology

[0002] Microelectronic devices generally have a die (i.e., a chip) containing an integrated circuit system with a high density of extremely small components. Typically, a die contains an array of tiny bonding pads electrically coupled to the integrated circuit system. The bonding pads are external electrical contacts through which power supply voltages, signals, etc., are transmitted to and emitted from the integrated circuit system. After the die is formed, it is "packaged" to couple the bonding pads to a larger array of electrical terminals that can be more easily coupled to various power lines, signal lines, and ground lines. Conventional processes for packaging dies involve electrically coupling the bonding pads on the die to an array of leads, ball pads, or other types of electrical terminals, and encapsulating the die to protect it from environmental factors such as moisture, particles, static electricity, and physical impact. Summary of the Invention

[0003] One aspect of this disclosure provides a semiconductor device assembly comprising: a first semiconductor device including: a first substrate having a front surface, a plurality of solder bumps located on the front surface of the first substrate, and a first polymer layer on the front surface of the first substrate; and a second semiconductor device including: a second substrate having a back surface, a plurality of through-silicon vias (TSVs) protruding from the back surface of the second substrate, and a second polymer layer on the back surface of the first substrate, the second polymer layer having a plurality of openings corresponding to the plurality of TSVs, each opening having a volume larger than the volume of the plurality of solder bumps, wherein the first semiconductor device and the second semiconductor device are coupled such that the first polymer layer contacts the second polymer layer, and each of the plurality of solder bumps extends into a corresponding one of the plurality of openings and contacts a corresponding one of the plurality of TSVs.

[0004] Another aspect of this disclosure provides a semiconductor device assembly comprising: a plurality of semiconductor devices, each of the plurality of semiconductor devices comprising: a substrate having a front surface and a back surface; a plurality of solder bumps located on the front surface of the substrate; a first polymer layer on the front surface of the substrate; a plurality of through-silicon vias (TSVs) protruding from the back surface of the substrate; and a second polymer layer on the back surface of the substrate, the second polymer layer having a plurality of openings corresponding to the plurality of TSVs, each opening having a volume larger than the volume of the plurality of solder bumps.

[0005] Another aspect of this disclosure provides a method of manufacturing a semiconductor device assembly, comprising: processing a first semiconductor device to form a cavity in a first polymer layer around a protruding through-silicon via (TSV) on a back surface of the first semiconductor device; processing a second semiconductor device to generate a second polymer layer and solder bumps on a front surface of the second semiconductor device; bonding the first semiconductor device to the second semiconductor device such that the first polymer layer contacts the second polymer layer and the solder bumps extend into the cavity and contact the TSVs; and reflowing the solder bumps to wet the protruding TSVs within the cavity. Attached Figure Description

[0006] Figure 1A-1D A cross-sectional view of a first semiconductor device at various manufacturing steps according to an embodiment of the present invention;

[0007] Figure 2A-2D Cross-sectional views of a second semiconductor device at various manufacturing steps according to an embodiment of the present invention;

[0008] Figure 3 Cross-sectional views depicting solder-based hybrid bonding of first and second semiconductor devices according to embodiments of the present invention;

[0009] Figure 4 A cross-sectional view depicting a semiconductor device assembly with hybrid bonding interconnects according to an embodiment of the present invention;

[0010] Figure 5 A cross-sectional view of a third semiconductor device according to an embodiment of the present invention;

[0011] Figure 6 This is a flowchart illustrating a method for assembling a semiconductor device assembly with hybrid bonding according to an embodiment of the present invention;

[0012] Figure 7 This is a flowchart illustrating a method for manufacturing a first semiconductor device for a semiconductor device assembly according to an embodiment of the present invention; and

[0013] Figure 8 This is a flowchart illustrating a method for manufacturing a second semiconductor device for semiconductor device assembly according to an embodiment of the present invention.

[0014] The drawings are merely illustrative of exemplary embodiments and should therefore not be considered as limiting the scope. Elements and features shown in the drawings are not necessarily scaled, but rather the emphasis is on clearly illustrating the principles of the exemplary embodiments. Additionally, specific dimensions or placements may be exaggerated to aid in visually expressing such principles. In the drawings, the same reference numerals used in different embodiments denote similar or corresponding, but not necessarily identical, elements. Detailed Implementation

[0015] 3D semiconductor device integration, encompassing die-to-die, die-to-wafer, and wafer-to-wafer bonding, perpetuates Moore's Law to achieve smaller and faster semiconductor devices. Solder bumps and through-silicon via (TSV) pitch in semiconductor device assemblies enable high-density interconnects between two or more semiconductor devices for different applications. However, the mechanical stability of solder bumps, solder bump non-wetting, and TSV recesses are concerns for finer pitch semiconductor assemblies (e.g., 10µm and below). For example, solder bridging and non-wetting issues exist in conventional interconnect technologies with tight TSV pitches. Furthermore, openings in copper-copper joints challenge the yield of copper hybrid bonding-based interconnects and require very tight control over copper pad recesses at pitches of 5nm and below. In addition, 3D semiconductor device integration requires a minimized and constant BLT (Block Least Trace) to achieve uniform and reliable performance of the assembled semiconductor device.

[0016] To address these and other drawbacks, this disclosure discloses a solder-based hybrid bonding method for semiconductor device assemblies, comprising polymer-polymer bonding and solder-TSV bonding at the interface of stacked semiconductor devices. Specifically, the disclosed semiconductor device interconnect includes a first semiconductor device having a first polymer layer, a TSV as under-bump metallization (UBM), and a cavity created around the TSV. The hybrid semiconductor device interconnect further includes a second semiconductor device having a second polymer layer and solder bumps formed thereon. The first and second semiconductor devices can be bonded via polymer-polymer bonding between the first and second polymer layers and solder bump-TSV bonding by extending solder bumps into the cavity to contact the TSV. The semiconductor device assembly disclosed in this disclosure accommodates solder bumps within the cavity around the TSV, thus eliminating BLT between stacked semiconductor devices.

[0017] In this disclosure, a first semiconductor device may be processed to create a cavity in its first polymer layer and around a protruding TSV on the back surface of the first semiconductor device. Figure 1A-1D Cross-sectional views of a first semiconductor device 100 at various manufacturing steps according to an embodiment of the present invention are shown. Figure 1AAs shown, TSV 104 can be fabricated to protrude from the back side surface of substrate 102 of semiconductor device 100. In this example, TSV 104 can be fabricated using a post-via method, i.e., TSV 104 is formed from the back side of substrate 102 by etching the back side of substrate 102, shallow trench isolation (STI) pads, and the interlayer dielectric above the STI pads to expose metal pads (not shown) through corresponding TSV openings. Here, TSV 104 can be filled with any suitable conductive material, such as copper, tungsten, molybdenum, nickel, titanium, tantalum, platinum, silver, gold, ruthenium, iridium, rhenium, rhodium, or alloys thereof. Alternatively, TSV 104 can be formed using a pre-via method, wherein a wafer thinning process can be performed using grinding or lapping tools to expose TSV 104 from the back side of substrate 102. In another example embodiment, TSV 104 can be fabricated to protrude from and penetrate through the back side surface of substrate 102. For example, TSV 104 can be formed by etching through substrate 102 and then filling it with any conductive material. Furthermore, TSV 104 may have a height in the range of 2µm to 5µm and a diameter in the range of 2µm to 4µm above substrate 102.

[0018] The passivation liner 106 may be further deposited on the back side surface of the substrate 102 of the first semiconductor device 100. For example... Figure 1B As shown, the liner 106 can also be conformally coated on the protruding sidewalls and top surface of the TSV 104. The deposition of the liner 106 can be performed using any suitable technique, including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or gas cluster ion beam (GCIB) deposition. In this example, the passivation liner 106 can be an insulating dielectric material, such as silicon oxide (SiO), silicon nitride (SiN), silicon boron carbonitride (SiBCN), silicon oxycarbonitride (SiOCN), silicon carbonitride (SiOC), silicon carbonitride (SiCN), silicon boron nitride (SiBN), low-k dielectric materials, or combinations thereof. Here, the liner 106 can have a thickness in the range of 1 μm to 3 μm.

[0019] In the next step, the back surface of the semiconductor device 100 can be planarized to expose the top surface of the TSV 104. Polarization can be achieved by applying TBM material 108 as an aid, followed by a rapid dicing process. In another embodiment, polarization can be achieved by a chemical mechanical polishing (CMP) process utilizing end-point detection technology. Specifically, the CMP process can be performed using chemical or granular slurry and mechanical force to gradually remove the TBM material 108. The CMP process can further remove the liner 106 from the top surface of the TSV 104 and stop on the top surface.

[0020] Once the top surface of TSV 104 is exposed, the TBM material can be removed from the back side of the semiconductor device 100. The removal of the TBM material 108 can be accomplished using wet etching techniques or anisotropic etching techniques (such as reactive ion etching (RIE) processes). Figure 1D As shown, a polymer layer 110 may be further deposited on the back surface of substrate 102 to assist in the semiconductor device assembly. Here, the polymer layer 110 can be deposited using vapor deposition techniques such as CVD or PVD processes. In this example, the polymer layer 110 can be further planarized using a planarization technique such as CMP. Furthermore, a cavity 112 can be created by patterning the polymer layer 110 using a hard mask and then etching away the patterned polymer using a dry etching or wet etching technique. Specifically, a cavity 112 with a diameter in the range of 5 μm to 10 μm can be formed around the protruding TSV 104. Due to process tolerances, the polarization of the polymer layer may not stop exactly on the top surface of TSV 104, resulting in a difference between the top surface of the polymer layer and the top surface of TSV 104. Figure 1D As can be seen, after the cavity 112 is formed around the protruding TSV 104, the top surface of the planarized polymer layer 110 can be higher than the top surface of the TSV 104.

[0021] In another embodiment, a passivation layer may be deposited on the back side of the substrate 102 based on the exposure of the top surface of the TSV 104 and the removal of the TBM material 108. The passivation layer may be made of an insulating dielectric material, such as silicon oxide (SiO), silicon nitride (SiN), silicon boron carbonitride (SiBCN), silicon oxycarbonitride (SiOCN), silicon carbonoxylate (SiOC), silicon carbonitride (SiCN), silicon boron nitride (SiBN), or combinations thereof. Similarly, the passivation layer may be planarized and patterned to form cavities 112 therein and around the protruding TSV 104. Furthermore, processing of the semiconductor device 200 may include removing the liner 106 from the sidewalls of the protruding TSV 104 after patterning the cavities 112 in the polymer / passivation layer 110, which can be accomplished by wet or dry etching techniques.

[0022] In another embodiment, the semiconductor device 100 may include a plurality of TSVs protruding from the back surface of the semiconductor device 100, each of the plurality of TSVs having a cavity surrounding it. The process of the plurality of TSVs and the corresponding cavities can be consistent with... Figure 1A-1D The process is the same as that described for TSV 104. In this example, multiple TSVs can have a pitch distance of less than 10µm.

[0023] In this disclosure, a second semiconductor device may be processed to produce a second polymer layer and solder bumps on the front surface of the second semiconductor device. Figure 2A-2D A cross-sectional view of a second semiconductor device 200 after manufacturing operations, according to an embodiment of the present invention. Figure 2A As shown, solder bumps 204 can be fabricated on the front surface of a substrate 202 of a second semiconductor device 200. The solder bumps 204 can be processed by patterning a hard mask on the front side of the substrate 204 and subsequently performing solder plating. The hard mask can then be peeled off, causing the solder bumps 204 to protrude from the front surface of the semiconductor device 200. In this example, the solder bumps 204 can be made of a material comprising nickel, copper, gold, palladium, silver, or alloys thereof. In another embodiment, the solder bumps 204 can comprise various materials. For example, the solder bumps 204 can comprise nickel pillars capped with a solder alloy, copper pillars capped with a solder alloy, or only a solder alloy. In another example embodiment, the solder bumps 204 can be fabricated on and penetrate the front surface of the substrate 202. For example, the substrate 202 can have hard masks on its front and back surfaces. The solder bumps 204 can be processed by fully patterning the front surface and the hard mask film on the substrate 202, followed by a solder plating process. Here, the solder bumps 204 may have a diameter in the range of 2µm to 5µm. Although not described, those skilled in the art will understand that the solder bumps 204 can be connected to an integrated circuit system within or on the substrate 202 via one or more vias, traces, pads, etc.

[0024] In the next step, a polymer layer 206 may be deposited on the front surface of the substrate 202, such as... Figure 2B As shown in the diagram. Similar to polymer layer 110, polymer layer 206 can be deposited using vapor deposition techniques such as CVD or PVD processes. Figure 2C As shown, polymer layer 206 can be further planarized using planarization techniques such as CMP, polishing, or etching processes to expose solder bumps 204. In this example, the planarization process can continue until solder bumps 204 protrude a few micrometers from the top surface of polymer layer 206. In another example embodiment, polymer layer 110 can be etched back, for example, using wet or dry etching techniques, to highlight solder bumps 204 thereon.

[0025] After the solder bump 204 is exposed from the polymer layer 206, as Figure 2D As shown, a reflow process can be performed on solder bump 204 to form solder balls and assist in the assembly of a semiconductor device. The purpose of reflowing solder bump 204 is to increase the bump height by reshaping the exposed solder bumps into spheres and to facilitate solder-TSV bonding as described later in this disclosure. Reflow solder balls over the planarized polymer layer 206 offer better reliability and can be performed in a nitrogen atmosphere during rapid thermal processing (RTP).

[0026] In another embodiment, the semiconductor device 200 may include a plurality of solder bumps located on its front surface. The process of the plurality of solder bumps may be consistent with... Figure 2A-2D The process for solder bump 204 described herein is the same.

[0027] Figure 3 A cross-sectional view depicting a solder-based hybrid bonding of a first semiconductor device 100 and a second semiconductor device 200 according to an embodiment of the present invention is shown. The bonding of the semiconductor devices may involve flipping the second semiconductor device 200 and aligning its front surface with the back surface of the first semiconductor device 100. Additionally, the solder bumps 204 of the semiconductor device 200 may be aligned with the TSV 104 of the first semiconductor device 100 for solder-TSV bonding. In this example, the semiconductor devices 100 and 200 can be stacked by contacting the polymer layer 206 of the second semiconductor device 200 and the solder bumps 204 with the polymer layer 110 and the TSV 104 of the first semiconductor device 100, respectively. Specifically, the semiconductor device stacking can be accomplished by polymer-to-polymer bonding (e.g., bonding between polymer layers 206 and 110 at less than 200°C without any underfill). As previously discussed, the polymer layers of the first semiconductor device 100 and the second semiconductor device 200 may be made of thermosetting or thermoplastic materials, such as epoxy resins, silicones, acrylic resins, bismaleimides, and polyimides. These polymer layers are cross-linked and become harder when they come into contact and are subjected to high temperatures after stacking. Once the semiconductor devices 100 and 200 are stacked, a final large-scale reflow can be performed to form solder wetting, wherein the solder bumps 204 become fluid-molten and properly adhere to the conductive top surface of the TSV 104 for solder-TSV bonding. In this example, the cavity 112 may have a volume larger than the protruding solder bumps 204, such that it can accommodate all solder material after the solder-TSV bonding process.

[0028] Turning Figure 4 Cross-sectional views of stacked semiconductor devices 100 and 200 with hybrid bonding interconnects according to embodiments of the present invention are depicted. During semiconductor device stacking, the solder bumps 204 are soft rather than molten. Therefore, and as Figure 4As shown, the bulk of solder bump 204 is contactable with TSV 104 and accommodated within cavity 112 of semiconductor device 100. In this manner, the solder balls of solder bump 204 do not flow into the interface between the first semiconductor device 100 and the second semiconductor device 200, thus eliminating any BLT between them. In this example, the hybrid bonding between the stacked first semiconductor device 100 and second semiconductor device 200 includes a polymer-polymer bonding between polymer layer 206 and polymer layer 110, and a solder-TSV bonding between solder bump 204 and TSV 104 and within cavity 112 of the first semiconductor device 100. This hybrid bonding for semiconductor device assemblies effectively reduces device yield losses due to solder bridging and non-wetting issues. Furthermore, in the example embodiment, wetted solder balls may adhere to protruding TSV 104 but may not completely fill cavity 112. This may leave gaps in cavity 112, but will not cause reliability issues for the stacked semiconductor device because the polymer layers are well bonded therebetween.

[0029] In another embodiment, the semiconductor device assembly described herein includes bonding a first semiconductor device 100 and a second semiconductor device 200 such that a polymer layer 206 contacts a polymer layer 110, and each of a plurality of solder bumps located on a front surface of the semiconductor device 200 extends into a corresponding one of a plurality of TSVs projecting from a back surface of the second semiconductor device 200. In another embodiment, TSV 104 and solder bump 204 penetrate substrate 102 and substrate 202, respectively, in a hybrid bonding interconnect.

[0030] In an exemplary embodiment, this disclosure reveals a third semiconductor device assembly by stacking multiple semiconductor devices one on top of the other. Figure 5 A cross-sectional view of this type of semiconductor device according to an embodiment of the present invention is depicted. In this example, the semiconductor device 500 may include a front surface and a back surface, each containing different materials and structures for hybrid bonding of semiconductor device components. Figure 5 As shown, a TSV 508 may be fabricated and protrude on the front surface. The sidewalls of the TSV 508 may be encapsulated by a passivated liner 512, and the top surface of the TSV 508 may be exposed. Specifically, a polymer layer 510 may be deposited on the front surface of the semiconductor device 500, and cavities 514 may be patterned thereon. Specifically, cavities 514 having a diameter in the range of 5 μm to 10 μm may be formed around the protruding TSV 508. In this example, the material selection and fabrication process for the polymer layer 510, TSV 508, liner 512, and cavity 514 may be consistent with those for the semiconductor device 100. Figure 1A-1D The material selection and manufacturing procedures described herein are the same.

[0031] Furthermore, the semiconductor device 500 may include solder bumps 504, a polymer layer 506, and a pad layer 516 located on the back surface of the substrate 502. For example... Figure 5 As shown, polymer layer 506 may encapsulate the back side surface, and solder bump 504 may be located on pad layer 516 and protrude above polymer layer 506. Here, TSV 508 extends completely through substrate 502 and contacts solder bump 504. In this example, the material selection and fabrication process for polymer layer 506 and solder bump 504 can be compared with that for semiconductor device 200. Figure 2A-2D The material selection and manufacturing procedures described herein are the same.

[0032] In this example embodiment, semiconductor devices (e.g., multiple semiconductor devices 500) can be stacked one on top of the other using hybrid bonding for semiconductor device assemblies. For example, the back surface of a first semiconductor device 500 can be etched onto and bonded to the front surface of a second semiconductor device 500' using both polymer-polymer bonding and solder-TSV bonding. Here, a polymer-polymer bonding can be formed between the polymer layer 506 of the first semiconductor device 500 and the polymer layer 510' of the second semiconductor device 500'. On the other hand, a solder-TSV bonding can be formed between the solder bump 504 of the first semiconductor device 500 and the TSV 508' of the second semiconductor device 500'. Specifically, the bulk of the solder bump 504 of the first semiconductor device 500 can contact the TSV 104' of the semiconductor device 500' and can be accommodated within the cavity 514' of the semiconductor device 500'. In this assembly, the solder balls of the solder bump 504 are confined within the cavity 512' and do not flow into the interface between the first semiconductor device 500 and the second semiconductor device 500', thus eliminating any BLT therebetween. The manufacturing process described above can be repeated to further stack more semiconductor devices 500 in the semiconductor device assembly.

[0033] In another embodiment, one or more of the semiconductor devices 500 may be connected to other circuit systems of the device. For example, the TSV 508 of the semiconductor device 500 may be connected to another circuit system of the device for electrical connection via its exposed top surface. In another example, the solder bump 504 of the semiconductor device 500 may be connected to another circuit system of the device.

[0034] Figure 6This is a flowchart illustrating a method 600 for a semiconductor device assembly having a solder-based hybrid bonding according to an embodiment of the present invention. Referring to Figures 1-5, method 600 includes processing a first semiconductor device at 602 to create a cavity in a first polymer layer around a protruding TSV on the back surface of the first semiconductor device. For example, TSV 104 may be fabricated on and protrude thereon on the back surface of semiconductor device 100. Specifically, cavity 112 may be formed by patterning polymer layer 110 of semiconductor device 100 and located around protruding TSV 104.

[0035] Method 600 further includes processing the second semiconductor device in 604 to generate a second polymer layer and solder bumps on the front surface of the second semiconductor device. For example, the second semiconductor device 200 may be processed to deposit a polymer layer 206 on its front surface and expose solder bumps 204 over the polymer layer 206.

[0036] Furthermore, method 600 includes bonding a first semiconductor device to a second semiconductor device at 606, such that a first polymer layer contacts a second polymer layer, and solder bumps extend into the cavity and contact the TSV. For example, the first semiconductor device 100 and the second semiconductor device 200 may be stacked to form a hybrid bond therebetween. Specifically, a polymer-polymer bond may be formed between polymer layer 206 and polymer layer 110. Additionally, a solder-TSV bond may be formed within the cavity 112 of the first semiconductor device 100 between solder bump 204 and TSV 104.

[0037] Finally, method 600 includes 608 reflowing solder bumps to wet the protruding TSV within the cavity. For example, after bonding the first semiconductor device 100 and the second semiconductor device 200, a large-scale reflow process can be performed to form solder wetting, wherein the solder bumps 204 become fluid-molten and properly adhere to the top surface of the TSV 104 for conductive solder-TSV bonding.

[0038] Turn now Figure 7 , Figure 7 This is a flowchart illustrating a method 700 for manufacturing a first semiconductor device for a semiconductor device assembly according to an embodiment of the present invention. (See also...) Figure 1A-1DMethod 700 includes etching the back surface of the first semiconductor device in 702 to expose a TSV protruding therefrom. For example, the back surface of the substrate 102 of the semiconductor device 100 may be thinned to expose the TSV 104 thereon. Method 700 also includes depositing a liner on the back surface of the first semiconductor device and on the protruding TSV in 704. For example, the liner 106 may be deposited and conformally coated on the back surface of the substrate 102 and on the sidewalls and top surface of the protruding TSV 104. Additionally, method 700 includes planarizing the back surface of the first semiconductor device in 706 to expose the top surface of the TSV. For example, the liner 106 may be further planarized with the aid of TBM material 108 to expose the top surface of the TSV 104. Furthermore, method 700 includes depositing a first polymer layer on the back surface of the first semiconductor device in 708. For example, a polymer layer 110 may be deposited on the back surface of the substrate 102. Finally, method 700 includes patterning the first polymer layer in 710 to create cavities around the protruding TSV. For example, the polymer layer 110 can be patterned to form a cavity 112 therein, and the cavity 112 may be around the protruding TSV 104.

[0039] Figure 8 This is a flowchart illustrating a method 800 for manufacturing a second semiconductor device for a semiconductor device assembly according to an embodiment of the present invention. (See also...) Figure 2A-2D Method 800 includes processing solder bumps on the front surface of a second semiconductor device in 802. For example, solder bumps 204 may be fabricated on the front surface of a substrate 202 of the semiconductor device 200. Method 800 also includes depositing a second polymer layer on the front surface of the second semiconductor device in 804. For example, polymer layer 206 may be deposited on the back surface of the substrate 202. Furthermore, method 800 includes planarizing the second polymer layer in 806 to expose the top portion of the solder bumps. For example, polymer layer 206 may be polarized to expose the solder bumps 204 thereover. In another example embodiment, a reflow process may be further performed on the semiconductor device. For example, the semiconductor device 200 may be reflowed to reshape the exposed solder bumps 204 into spheres to facilitate solder-TSV bonding in downstream processes of the semiconductor device assembly.

[0040] The semiconductor device interconnects described herein may be implemented in wafer-to-wafer bonding, die-to-die bonding, die-to-wafer bonding, or any combination thereof.

[0041] The following describes several embodiments of semiconductor devices and specific details of associated systems and methods. Those skilled in the art will recognize that suitable stages of the methods described herein can be performed at the wafer level or the die level. Therefore, depending on the context of use, the term "substrate" can refer to a wafer-level substrate or a single die-level substrate. Furthermore, unless the context otherwise indicates, conventional semiconductor manufacturing techniques can be used to form the structures disclosed herein. For example, chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, electroless plating, spin coating, and / or other suitable techniques can be used to deposit materials. Similarly, for example, plasma etching, wet etching, chemical mechanical planarization, or other suitable techniques can be used to remove materials.

[0042] According to one aspect of this disclosure, the semiconductor device described above may be a memory die, such as a dynamic random access memory (DRAM) die, a NAND memory die, a NOR memory die, a magnetic random access memory (MRAM) die, a phase-change memory (PCM) die, a ferroelectric random access memory (FeRAM) die, a static random access memory (SRAM) die, etc. In embodiments where multiple dies are provided in a single component, the semiconductor device may be memory dies of the same type (e.g., two NAND, two DRAM, etc.) or memory dies of different types (e.g., one DRAM and one NAND, etc.). According to another aspect of this disclosure, the semiconductor die of the component described above may be a logic die (e.g., a controller die, a processor die, etc.), or a mixture of logic and memory dies (e.g., a memory controller die and memory dies controlled by it).

[0043] The devices containing memory devices discussed herein can be formed on a semiconductor substrate or die, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by using doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0044] The functionality described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of this disclosure and the appended claims. Features implementing the functionality may also be physically located in various locations, including distributed implementations such that portions of the functionality are implemented in different physical locations.

[0045] As used herein, the word "or," as used in the claims, or as in a list of items (e.g., a list followed by phrases such as "at least one of" or "one or more of"), indicates a list of inclusion, such that a list of at least one of, for example, A, B, or C, means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0046] As used herein, the terms “top,” “bottom,” “up,” “down,” “above,” and “below” can refer to a relative orientation or position in a semiconductor device given the orientation shown in the figures. However, these terms should be broadly understood to include semiconductor devices having other orientations, such as inverted or tilted orientations, wherein top / bottom, up / down, above / below, up / down, and left / right may be interchanged depending on the orientation.

[0047] It should be noted that the methods described above depict possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more embodiments from the methods may be combined.

[0048] As should be understood from the foregoing, specific embodiments of the invention have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of the invention. Specifically, numerous specific details have been set forth in the foregoing description to provide a thorough and illustrative description of embodiments of the invention. However, those skilled in the art will recognize that this disclosure may be practiced without one or more of the specific details. In other instances, well-known structures or operations typically associated with memory systems and devices have not been shown or described in detail to avoid obscuring other aspects of the technology. Generally, it should be understood that various other devices, systems, and methods besides those specific embodiments disclosed herein are within the scope of the invention.

Claims

1. A semiconductor device assembly comprising: A first semiconductor device, comprising: A first substrate having a front surface. Multiple solder bumps are located on the front surface of the first substrate, and A first polymer layer, which is on the front surface of the first substrate; and A second semiconductor device comprising: The second substrate has a back-side surface. Multiple through-silicon vias (TSVs) protrude from the back surface of the second substrate, and A second polymer layer, located on the back surface of the first substrate, has a plurality of openings corresponding to the plurality of TSVs, each opening having a volume larger than the volume of the plurality of solder bumps. The first semiconductor device and the second semiconductor device are coupled such that the first polymer layer contacts the second polymer layer, and each of the plurality of solder bumps extends into a corresponding one of the plurality of openings and contacts a corresponding one of the plurality of TSVs.

2. The semiconductor device assembly of claim 1, wherein a gap exists within one or more of the plurality of openings.

3. The semiconductor device assembly of claim 1, wherein the first polymer layer is bonded to the second polymer layer.

4. The semiconductor device assembly of claim 1, wherein the spacing between the plurality of TSVs is less than 10 μm.

5. The semiconductor device assembly of claim 1, wherein the diameter of the plurality of TSVs is in the range of 2 μm to 4 μm, and the diameter of the plurality of openings is in the range of 5 μm to 10 μm.

6. The semiconductor device assembly of claim 1, wherein the top surface of each of the plurality of TSVs is recessed below the top surface of the second polymer layer.

7. The semiconductor device assembly of claim 1, further comprising a dielectric layer encapsulating the back surface of the second substrate and the protruding sidewalls of the plurality of TSVs.

8. The semiconductor device assembly of claim 1, wherein the first polymer layer and the second polymer layer are made of a material comprising at least one of epoxy resin, silicone, acrylic resin, bismaleimide, or polyimide.

9. The semiconductor device assembly of claim 1, wherein the plurality of TSVs are made of a conductive material comprising at least one of copper, tungsten, molybdenum, nickel, titanium, tantalum, platinum, silver, gold, ruthenium, iridium, rhenium, rhodium, or alloys thereof.

10. The semiconductor device assembly of claim 1, wherein each of the plurality of solder bumps comprises a nickel pillar capped with solder material.

11. A semiconductor device assembly comprising: A plurality of semiconductor devices, each of the plurality of semiconductor devices comprising: A substrate having a front surface and a back surface, Multiple solder bumps are located on the front surface of the substrate. A first polymer layer, on the front surface of the substrate, Multiple through-silicon vias (TSVs) protrude from the back surface of the substrate, and A second polymer layer is provided on the back surface of the substrate, the second polymer layer having a plurality of openings corresponding to the plurality of TSVs, each opening having a volume larger than the volume of the plurality of solder bumps. The first semiconductor device and the second semiconductor device of the plurality of semiconductor devices are coupled such that: The first polymer layer of the first semiconductor device contacts the second polymer layer of the second semiconductor device, and Each of the plurality of solder bumps of the first semiconductor device extends into a corresponding one of the plurality of openings of the second semiconductor device and contacts a corresponding one of the plurality of TSVs of the second semiconductor device.

12. A method for manufacturing a semiconductor device assembly, comprising: The first semiconductor device is processed to form a cavity in a first polymer layer around a protruding through-silicon via (TSV) on the back side surface of the first semiconductor device. The second semiconductor device is processed to generate a second polymer layer and solder bumps on the front surface of the second semiconductor device; The first semiconductor device is bonded to the second semiconductor device such that the first polymer layer contacts the second polymer layer, and the solder bump extends into the cavity and contacts the TSV; as well as The solder bumps are reflowed to wet the protruding TSV within the cavity.

13. The method of claim 12, wherein processing the first semiconductor device comprises: The back surface of the first semiconductor device is etched to expose the TSV protruding therefrom. A liner is deposited on the back surface of the first semiconductor device and on the protruding TSV. The back surface of the first semiconductor device is planarized to expose the top surface of the TSV. The first polymer layer is deposited on the back surface of the first semiconductor device, and The first polymer layer is patterned to create the cavity around the protruding TSV.

14. The method of claim 13, wherein planarizing the back surface of the first semiconductor device includes a rapid dicing process, and wherein the exposed top surface of the TSV is recessed below the top surface of the patterned first polymer layer.

15. The method of claim 13, further comprising removing the liner from the sidewall of the protruding TSV after patterning the first polymer layer to form the cavity.

16. The method of claim 12, wherein processing the second semiconductor device comprises: Process the solder bumps on the front surface of the second semiconductor device. Deposit the second polymer layer on the front surface of the second semiconductor device, and The second polymer layer is planarized to expose the top portion of the solder bump.

17. The method of claim 16, wherein planarizing the second polymer layer comprises at least one of a chemical mechanical planarization (CMP) process, a polishing process, or an etching process.

18. The method of claim 16, further comprising reflowing the solder bumps to form solder balls over the planarized second polymer layer.

19. The method of claim 12, wherein bonding the first semiconductor device to the second semiconductor device comprises bonding the first polymer layer and the second polymer layer.

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