A SiN stress-based stepped structure GeSn laser and a preparation method thereof

Abstract

The application relates to a SiN stress-based ladder-shaped structure GeSn laser and a preparation method, and the laser comprises a substrate layer, a buffer layer arranged on the substrate layer, an N-type Ge layer arranged on the buffer layer, a DBR mirror and a DBR mirror arranged at two ends of the N-type Ge layer respectively, a ladder-shaped structure arranged on the N-type Ge layer, a P-type Ge layer arranged on the ladder-shaped structure, a P-type heavily-doped ohmic contact region arranged in the P-type Ge layer, a Si3N4 stress layer arranged on the ladder-shaped structure and the N-type Ge layer, an electrode arranged in a first groove penetrating through the Si3N4 stress layer and above the P-type heavily-doped ohmic contact region, and an N-type heavily-doped ohmic contact region arranged below the metal electrode and in the N-type Ge layer. The application can effectively improve the light-emitting efficiency of the Ge laser, reduce the threshold current density of the Ge laser, and provides a feasible scheme for high-efficiency group-IV material integrated light sources.

Description

TECHNICAL FIELD

[0001] The application relates to the field of semiconductor optoelectronics, in particular to a stepped structure GeSn laser based on SiN stress and a preparation method. BACKGROUND

[0002] The integrated circuit industry, as the cornerstone of the information society, has made great progress in the past decades. However, with the continuous reduction of integrated circuit manufacturing, the traditional micro-nano electronic chip is facing more and more challenges. The decline of integrated circuit manufacturing inevitably brings problems such as RC delay, electromagnetic interference and increased energy consumption. Silicon-based optoelectronic integrated technology uses optical interconnection to replace electrical interconnection for intra-chip or inter-chip signal transmission, providing a solution to the problems encountered by traditional integrated circuits in development. At present, more than 90% of circuits and discrete components on the market are made of Si material. Due to the low cost and mature production chain of Si material, the devices and circuits made of Si material can balance the advantages of cost and performance. As a latecomer in the integrated circuit industry, optoelectronic integrated circuit has shown good strength in the field of optical communication and has broad application prospects in the field of future optical computers. Optoelectronic integrated circuit combines the logic computing function of electronic devices with the high-speed and low-loss transmission capability of optical devices to realize information processing and transmission between chips and within chips, which can make optoelectronic integrated chips break through the challenges and bottlenecks faced by traditional electronic chips and continue Moore's law. Intel first proposed the preliminary architecture of optoelectronic integrated chips, and semiconductor industry giants such as IBM followed suit. Today, optoelectronic integrated technology has become a hot spot for competition among many high-tech companies and a focus of great power game.

[0003] In the photoelectric integration technology, high-efficiency and CMOS process compatible light source is an important part of monolithic photoelectric integration, and the photoelectric integrated chips which have been put into the market mostly use III-V materials to prepare integrated light source, although III-V materials can realize high-efficiency light emission due to the characteristics of direct band gap, but there is a large lattice mismatch and thermal mismatch between silicon material and III-V material, and the price of InP and GaAs materials is also relatively high, so it undoubtedly greatly increases the preparation cost of photoelectric integrated chip to prepare III-V light source on the silicon-based chip by means of heteroepitaxy, wafer bonding and the like. Using group IV materials to prepare integrated light source may be an important means to solve the problem, although group IV materials such as Si and Ge are non-direct band gap semiconductors, which are accompanied by phonon emission in the light emission process, which makes the IV group material light source unable to realize the high-efficiency light emission of III-V material light source. But the energy difference between the Γ energy valley and the L energy valley of the direct band gap of Ge material is only 136meV, and the band gap difference between the Γ energy valley and the L energy valley can be effectively reduced by doping Sn which is also a group IV element through applying tensile stress. Experiments have proved that the Ge can be converted into a direct band gap semiconductor by applying a biaxial tensile strain of 1.8% on the Ge or doping more than 9% of Sn component, so as to realize high-efficiency light emission.

[0004] In recent years, how to prepare high-efficiency Ge-based laser has become a topic of common concern for researchers at home and abroad, and a series of works on modified Ge materials and device structures have jointly promoted the continuous development of Ge-based light source. SUMMARY

[0005] In order to solve the above problems existing in the prior art, the application provides a stepped structure GeSn laser based on SiN stress and a preparation method. The technical problems to be solved by the application are solved by the following technical scheme:

[0006] A stepped structure GeSn laser based on SiN stress, the laser comprises:

[0007] a substrate layer;

[0008] a buffer layer arranged on the substrate layer;

[0009] an N-type Ge layer arranged on the buffer layer;

[0010] a front-end DBR mirror and a rear-end DBR mirror arranged on the upper surfaces of the two ends of the N-type Ge layer, respectively;

[0011] a plurality of stepped structures of GeSn material arranged on the N-type Ge layer in the width direction and located between the front-end DBR mirror and the rear-end DBR mirror;

[0012] a P-type Ge layer disposed on each of the stepped structures;

[0013] a P-type heavily doped ohmic contact region disposed in the P-type Ge layer;

[0014] a Si3N4 stress layer disposed on the stepped structures and the N-type Ge layer, an upper surface of the Si3N4 stress layer being flush with an upper surface of the P-type Ge layer;

[0015] a metal electrode disposed in a first trench penetrating the Si3N4 stress layer and on the P-type heavily doped ohmic contact region;

[0016] an N-type heavily doped ohmic contact region disposed below the metal electrode and in the N-type Ge layer.

[0017] In an embodiment of the present application, the substrate layer comprises a silicon substrate.

[0018] In an embodiment of the present application, the buffer layer comprises Si 0.5 Ge 0.5 a buffer layer.

[0019] In an embodiment of the present application, the stepped structures comprise a first stepped sub-structure and a second stepped sub-structure symmetrically disposed, each of the first stepped sub-structure and the second stepped sub-structure comprising a multi-stage stepped structure.

[0020] In an embodiment of the present application, each of the front-end DBR mirror and the back-end DBR mirror comprises a plurality of optical waveguide structures spaced apart along a width direction and disposed on the N-type Ge layer.

[0021] In an embodiment of the present application, the optical waveguide structure comprises:

[0022] a Si layer, the Si layer being provided with a plurality of second trenches spaced apart and penetrating the Si layer, the second trenches extending in a direction perpendicular to the extending direction of the metal electrode, an upper surface of the Si layer being flush with an upper surface of the stepped structure;

[0023] a SiO2 layer filled in the second trenches.

[0024] In an embodiment of the present application, the front-end DBR mirror has a smaller number of second trenches than the back-end DBR mirror.

[0025] The embodiments of the present application also provide a preparation method of a stepped structure GeSn laser based on SiN stress, for preparing the laser of any of the above embodiments, the preparation method comprising:

[0026] selecting a substrate layer;

[0027] growing a buffer layer on the substrate layer;

[0028] growing an N-type Ge layer on the buffer layer by using low-temperature MBE technology;

[0029] growing a GeSn layer on the N-type Ge layer by using low-temperature MBE technology;

[0030] growing a P-type Ge layer on the GeSn layer by using low-temperature MBE technology;

[0031] etching the P-type Ge layer and the GeSn layer to form a stepped groove by using reactive ion etching technology, etching the GeSn layer into a plurality of stepped structures arranged along the width direction, and retaining a P-type Ge layer on each of the stepped structures;

[0032] growing a Si3N4 stress layer in the stepped groove and on the P-type Ge layer by using PECVD technology;

[0033] etching away the excess Si3N4 stress layer on the surface by using plasma etching technology to expose the upper surface of the P-type Ge layer;

[0034] etching away the Si3N4 stress layer at both ends by using plasma etching technology to expose the N-type Ge layer at both ends;

[0035] preparing a front DBR mirror and a rear DBR mirror at both ends of the N-type Ge layer, respectively;

[0036] forming a first groove through the Si3N4 stress layer by using plasma etching technology;

[0037] performing ion implantation on the P-type Ge surface below the first groove by using ion implantation technology to form a P-type heavily doped ohmic contact region, and performing ion implantation on the P-type Ge layer surface to form an N-type heavily doped ohmic contact region;

[0038] filling the first groove with a metal material by using sputtering deposition technology to form a metal electrode.

[0039] In an embodiment of the present application, the preparation of the front DBR mirror and the rear DBR mirror at both ends of the N-type Ge layer, respectively, comprises:

[0040] preparing an optical waveguide structure arranged along the width direction at both ends of the N-type Ge layer, respectively.

[0041] In an embodiment of the present application, the preparation of the optical waveguide structure arranged along the width direction at both ends of the N-type Ge layer, respectively, comprises:

[0042] depositing a Si layer on both ends of the upper surface of the N-type Ge layer by using ultra-vacuum chemical vapor deposition technology;

[0043] etching the Si layer by using plasma etching technology to form a plurality of second grooves arranged at intervals and penetrating through the Si layer, wherein the extending direction of the second grooves is perpendicular to the extending direction of the metal electrode, and the upper surface of the Si layer is flush with the upper surface of the stepped structure;

[0044] filling the second grooves with a SiO2 layer by using ultra-vacuum chemical vapor deposition technology;

[0045] etching the overall structure of the Si layer and the SiO2 layer into a discrete optical waveguide structure.

[0046] Compared with the prior art, the present application has the following beneficial effects:

[0047] The present application sets a plurality of stepped structures of GeSn material arranged at intervals along the width direction on the N-type Ge layer between the front-end DBR mirror and the rear-end DBR mirror, thereby being able to introduce greater SiN stress on the surface of the device, so as to reduce the energy difference between the Γ energy valley and the L energy valley of the Ge material, improve the light-emitting efficiency of the Ge laser, reduce the threshold current density of the Ge laser, and improve the conventional SiN stress technology. Meanwhile, the preparation process of the GeSn laser of the present application is compatible with the CMOS process, thereby reducing the preparation cost of the silicon-based light source. The stepped structure GeSn laser based on SiN stress of the present application combines the GeSn alloy technology and the SiN film technology, and is able to avoid the problems of Sn segregation and stress relaxation of the SiN film.

[0048] Generally, 9%-10% of Sn needs to be doped to make Ge into a direct band gap, but the solid solubility of Sn in Ge is limited, and when 6%-7% of Sn is doped in Ge, serious segregation phenomenon will occur. Therefore, the present application makes the Ge doped with 6%-7% of Sn also into a direct band gap, and introduces external stress, i.e. SiN film stress. Similarly, Ge can also be converted into a direct band gap semiconductor by externally applying a biaxial tensile strain of 1.8% without doping Sn, but such a large stress is very difficult to achieve. In summary, the present application dopes 6% of Sn in Ge, thereby avoiding the segregation phenomenon of Sn, and introducing high-stress SiN film to introduce tensile stress, and only about 0.8% of biaxial tensile strain is needed to make the Ge doped with 6% of Sn into a direct band gap. 0.8% is undoubtedly much smaller than 1.8%, which greatly reduces the difficulty of the process. The present application will be further described in detail below in combination with the drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0049] Figure 1is a three-dimensional structure schematic diagram of a ladder-shaped structure GeSn laser based on SiN stress provided by an embodiment of the present application;

[0050] Figure 2 is a two-dimensional structure schematic diagram of a ladder-shaped structure GeSn laser based on SiN stress provided by an embodiment of the present application;

[0051] Figure 3 is a front view of an active region provided by an embodiment of the present application;

[0052] Figure 4 is a top view of a ladder-shaped structure GeSn laser based on SiN stress provided by an embodiment of the present application;

[0053] Figure 5a is a distribution schematic diagram of a ladder-shaped structure SiN film exerting tensile stress in Ge material provided by an embodiment of the present application;

[0054] Figure 5b is a distribution schematic diagram of a ladder-shaped structure SiN film exerting tensile stress in Ge material provided by an embodiment of the present application;

[0055] Figures 6a-6d is a band structure diagram of four semiconductor materials provided by an embodiment of the present application;

[0056] Figure 7a is a band structure schematic diagram of 1.8% biaxial tensile strain Ge and unstrained Ge provided by an embodiment of the present application;

[0057] Figure 7b is a band structure schematic diagram of Ge 0.91 Sn 0.09 and Ge provided by an embodiment of the present application;

[0058] Figure 7c is a result schematic diagram of influence of biaxial tensile strain on Ge band structure provided by an embodiment of the present application;

[0059] Figure 7d is a result schematic diagram of influence of Sn component on Ge band structure provided by an embodiment of the present application;

[0060] Figures 8a-8m is a process schematic diagram of a preparation method of a ladder-shaped structure GeSn laser based on SiN stress provided by an embodiment of the present application. DETAILED DESCRIPTION

[0061] The present application will be further described below in conjunction with specific embodiments, but the embodiments of the present application are not limited thereto.

[0062] Embodiment one

[0063] At present, the direct band gap of Ge material is reduced to improve the light emitting efficiency of the laser by doping Sn in Ge to form GeSn alloy or introducing mechanical stress. However, although the SiN film technology can introduce stress on the surface of the device, due to the existence of stress relaxation, the stress will be concentrated on the surface of the material and cannot act on the inside of the device. The solid solubility of Sn in Ge is relatively low, and when the Sn component is higher than 6%, there will be serious segregation phenomenon, which makes the quality of GeSn material become very poor.

[0064] Based on this, see Figure 1 , Figure 2 , Figure 3 and Figure 4 , Figure 1 is a three-dimensional structure schematic diagram of a ladder-shaped structure GeSn laser based on SiN stress provided by an embodiment of the present application, Figure 2 is a two-dimensional structure schematic diagram of a ladder-shaped structure GeSn laser based on SiN stress provided by an embodiment of the present application, Figure 3 is a front view of an active region provided by an embodiment of the present application, Figure 4 is a top view of a ladder-shaped structure GeSn laser based on SiN stress provided by an embodiment of the present application. The present application provides a ladder-shaped structure GeSn laser based on SiN stress, which comprises:

[0065] a substrate layer 1;

[0066] a buffer layer 2 arranged on the substrate layer 1;

[0067] an N-type Ge layer 3 arranged on the buffer layer 2;

[0068] a front DBR mirror (Front DBR) and a back DBR mirror (Back DBR) arranged on the upper surfaces of the two ends of the N-type Ge layer 3, respectively;

[0069] a plurality of ladder-shaped structures 6 of GeSn material arranged on the N-type Ge layer 3 in the width direction and located between the front DBR mirror and the back DBR mirror;

[0070] a P-type Ge layer 5 arranged on each ladder-shaped structure 6;

[0071] a P-type heavily doped ohmic contact region 13 arranged in the P-type Ge layer 5;

[0072] a Si3N4 stress layer 7 arranged on the ladder-shaped structure 6 and the N-type Ge layer 3, and the upper surface of the Si3N4 stress layer 7 is flush with the upper surface of the P-type Ge layer 5;

[0073] The metal electrode 14 is arranged in the first groove penetrating the Si3N4 stress layer 7 and on the P-type heavily doped ohmic contact region 13.

[0074] The N-type heavily doped ohmic contact region 12 is arranged below the metal electrode 8 and in the N-type Ge layer 3.

[0075] Optionally, the substrate layer comprises a silicon substrate.

[0076] Optionally, the buffer layer comprises Si 0.5 Ge 0.5 The buffer layer can reduce the impact of the lattice mismatch between Si and Ge.

[0077] Optionally, the stepped structure comprises a first stepped sub-structure and a second stepped sub-structure arranged symmetrically, and the first stepped sub-structure and the second stepped sub-structure comprise a plurality of stepped structures.

[0078] Optionally, the front DBR mirror and the rear DBR mirror each comprise a plurality of optical waveguide structures arranged at intervals along the width direction on the N-type Ge layer.

[0079] Further, the optical waveguide structure comprises:

[0080] The Si layer is provided with a plurality of second grooves arranged at intervals and penetrating the Si layer, the extension direction of the second grooves is perpendicular to the extension direction of the metal electrode, and the upper surface of the Si layer is flush with the upper surface of the stepped structure.

[0081] The SiO2 layer is filled in the second grooves.

[0082] Further, the number of the second grooves of the front DBR mirror is less than that of the rear DBR mirror, because the reflectivity of the resonant cavity needs to be high at one end close to total reflection, and the reflectivity of the other end, that is, the light emitting surface, needs to be small so as to facilitate light transmission, and the reflectivity of the DBR for specific wavelength light increases with the increase of the number of layers, so the number of the second grooves of the front DBR mirror is less than that of the rear DBR mirror, for example, the number of the second grooves of the front DBR mirror is 6, and the number of the second grooves of the rear DBR mirror is 12.

[0083] When the contact surface between the SiN thin film and the Ge material is a plane, stress is accumulated at the contact surface, and the stress gradually decays with the increase of the distance into the material. Therefore, the present application considers introducing a stepped structure at the contact surface between Ge and SiN, which can accumulate stress at the corners of the steps, not only can introduce greater stress, but also can effectively relieve the relaxation phenomenon of stress. Figure 5a 、 5bAs shown, the Ge material surface after the introduction of the stepped structure introduces greater tensile stress, especially at the corners of the stepped structure, there is a stress accumulation phenomenon, and the distance of the tensile stress into the Ge material is also longer than that without the stepped structure.

[0084] Unlike GaAs, InP, and other III-V materials, Ge material, like Si material, belongs to indirect band gap semiconductor, and the energy band structures of Si, Ge, GaAs, and InP materials are as shown in Figures 6a-6d As shown, Figure 6a The energy band structure corresponding to the Si material, Figure 6b The energy band structure corresponding to the Ge material, the energy band structure corresponding to the GaAs material is shown in FIG. 6, and the energy band structure corresponding to the InP material is shown in FIG. 6. GaAs, InP, and other III-V materials are direct semiconductors, and the minimum of the conduction band and the maximum of the valence band are at the same k value in k space. In the process of electron and hole recombination, no momentum exchange occurs, and the light-emitting efficiency is high. Although III-V materials can prepare high-efficiency integrated light sources, their preparation process is not compatible with CMOS process, and there is a large lattice mismatch and thermal mismatch between the Si substrate, which leads to some unavoidable difficulties in the development of heterogeneous integration. With the continuous progress of optoelectronic integration, Si, Ge, and other group IV materials have become an important choice for silicon-based monolithic optoelectronic integration technology. However, although Si, Ge, and other group IV materials can be prepared using CMOS process and have a small lattice mismatch and thermal mismatch with the Si substrate, their non-direct band gap semiconductor characteristics result in the emission of phonons in addition to photons during the recombination process, which makes their light-emitting efficiency much lower than that of III-V material light sources.

[0085] As a group IV material, although Ge is also an indirect band gap semiconductor, the energy difference between the direct band gap Γ energy valley and the L energy valley at the minimum of the conduction band is only 134 meV. Through energy band engineering, Ge material can be modified to become a direct band gap semiconductor, which is an effective solution for preparing group IV material light sources. Researchers have found that by introducing tensile strain in Ge material or doping Sn in Ge to form GeSn alloy, the band gap of Ge material can be narrowed, and the direct band gap narrows faster than the indirect band gap. When 1.8% biaxial tensile strain is introduced or the Sn component exceeds 9%, the direct band gap of Ge will be equal to the indirect band gap, and it will become a direct band gap semiconductor. The effects of Sn component and tensile strain on the energy band of Ge material are shown in Figures 7a-7d .

[0086] But at present, it is difficult to introduce tensile stress greater than 1GPa on the surface of Ge by SiN high stress film technology in engineering, and the introduction of excessive stress will lead to an increase in the number of defects in Ge material, thereby leading to the deterioration of device characteristics. At the same time, the solid solubility of Sn in Ge at room temperature is extremely low, although high Sn component GeSn alloy can be grown by low temperature MBE technology, but when the Sn component exceeds 6%, there will be serious segregation phenomenon, which leads to the difficulty of realizing the conversion of Ge material from non-direct band gap semiconductor to direct band gap semiconductor when the two methods are used alone, but if the two modification methods can be used at the same time, the process can be realized with lower technical difficulty. Therefore, when the stepped structure capable of introducing higher SiN film stress is proposed, the GeSn alloy technology can be combined, and the two methods can be used to realize the efficient modification of Ge material. The reason why the laser of the application adopts DBR (distributed Bragg reflector) laser is: DBR laser can usually realize single mode output, which means that they can emit a very narrow light beam with high focusing ability. In contrast, the output of FP laser is usually multimode, so their light beam is wider and the focusing effect is not as good as that of DBR laser. DBR laser has higher spectral purity, which means that there is less stray light and noise in its output spectrum, making it more suitable for applications such as optical fiber communication and optical storage. DBR lasers can achieve wavelength tuning by changing the period of the reflection grating, so their tuning range is wider than that of FP lasers. This makes them more widely used in sensing and optical communication systems. The output linewidth of DBR laser is relatively narrow, which means that its spectral resolution is higher. This makes it more suitable for applications such as spectral analysis and optical measurement. In summary, DBR laser has better single mode output, higher spectral purity, wider tuning range and narrower linewidth. Therefore, DBR laser has been widely used in the fields of optical communication, optical interconnection, sensing, optical storage and other fields.

[0087] Example two

[0088] Please refer to Figures 8a-8m , Figures 8a-8m is a process diagram of a preparation method of a stepped structure GeSn laser based on SiN stress provided by the embodiment of the application, and the application provides a preparation method of a stepped structure GeSn laser based on SiN stress on the basis of the above-mentioned embodiment, and the preparation method comprises the following steps:

[0089] Step 1, selecting a substrate layer 1.

[0090] Step 2, please refer to Figure 8a , a buffer layer 2 is grown on the substrate layer 1 by using PECVD technology.

[0091] Specifically, using ultra-vacuum chemical vapor deposition (EVD), SiH4 and GeH4 gases are introduced into the reaction chamber in a 1:1 ratio. The substrate temperature is maintained at 400°C, and a 300nm thick Si layer is deposited. 0.5 Ge 0.5 Buffer layer, deposited Si 0.5 Ge 0.5 The buffer layer will reduce the impact of lattice mismatch between Si and Ge.

[0092] Step 3, please refer to Figure 8b An N-type Ge layer 3 was grown on the buffer layer 2 using low-temperature MBE (molecular beam epitaxy) technology.

[0093] Specifically, a low-temperature MBE technique is used to grow a doping concentration of 4×10⁻⁶. 18 cm -3 A 500nm thick N-type Ge material is used as the N-region of the device, namely the N-type Ge layer 3, and the growth temperature is 300℃.

[0094] Step 4, please refer to Figure 8c GeSn layer 4 was grown on N-type Ge layer 3 using low-temperature MBE technology.

[0095] Specifically, a 400nm thick GeSn material with a Sn composition of 6% was grown using low-temperature MBE technology. This GeSn layer 4 served as the laser emitting region, and the growth temperature was 90℃.

[0096] Step 5, please refer to Figure 8d A P-type Ge layer 5 was grown on GeSn layer 4 using low-temperature MBE technology.

[0097] Specifically, a low-temperature MBE technique is used to grow a doping concentration of 1×10⁻⁶. 19 cm -3 A 200nm thick P-type Ge material is used as the P-region of the device, namely the P-type Ge layer 5, and the growth temperature is 300℃.

[0098] Step 6, please refer to Figure 8e The P-type Ge layer 5 and GeSn layer 4 are etched using reactive ion etching technology to form stepped trenches. The GeSn layer is etched into multiple stepped structures 6 spaced apart along the width direction. The P-type Ge layer 5 is retained on each stepped structure 6.

[0099] Specifically, the reactive ion etching technology is used to etch the trench on the structure described in step 5, Si3N4 is used as the barrier layer, the etchant formula is potassium hydroxide: isopropyl alcohol: water = 1:2:2, the etching temperature is 80℃, for example, for a three-layer trench, first etch a trench with a spacing of 200nm, a width of 1.6μm and a depth of 300nm on the surface of the P-type Ge layer. In the first layer trench, a trench with a width of 1.4μm and a depth of 100nm is etched. In the second layer trench, a trench with a width of 1.2μm and a depth of 100nm is etched. In the third layer trench, a trench with a width of 1μm and a depth of 100nm is etched.

[0100] Step 7, please refer to Figure 8f Si3N4 stress layer 7 is grown in the stepped trench and on the P-type Ge layer 5 by using the PECVD technology.

[0101] Specifically, Si3N4 stress layer 7 is grown in the stepped trench and on the P-type Ge layer 5 obtained in step 6, and SiH4 (diluted by N2 gas, concentration 12%) and NH3 gas are used, and the gas flow ratio is 1. The growth temperature is 350℃, the radio frequency is 15MHz, the power is 100W, and the reaction pressure is 250Pa.

[0102] Step 8, the surface excess Si3N4 stress layer is etched away by using the plasma etching technology to expose the upper surface of the P-type Ge layer.

[0103] Step 9, the Si3N4 stress layer at both ends is etched away by using the plasma etching technology to expose the N-type Ge layer at both ends.

[0104] Step 10, front DBR mirror and rear DBR mirror are respectively prepared at both ends of the N-type Ge layer 3.

[0105] Specifically, optical waveguide structures are respectively prepared at both ends of the N-type Ge layer 3 and arranged along the width direction.

[0106] In this embodiment, optical waveguide structures are respectively prepared at both ends of the N-type Ge layer 3 and arranged along the width direction, which comprises:

[0107] Step 10.1, please refer to Figure 8g Si layer 8 is deposited on the upper surface of the N-type Ge layer at both ends by using the ultrahigh vacuum chemical vapor deposition technology, which is used for preparing the DBR mirror.

[0108] Step 10.2, please refer to Figure 8h The Si layer is etched by using the plasma etching technology to form a plurality of second trenches 9 arranged at intervals and penetrating through the Si layer 8, wherein the extension direction of the second trench 9 is perpendicular to the extension direction of the metal electrode, and the upper surface of the Si layer is flush with the upper surface of the stepped structure.

[0109] Specifically, the second grooves 9 with a width of 300 nm and a spacing of 180 nm are etched on the Si layer at the front end and the rear end of the active region by using a plasma etching technique, the number of the second grooves 9 at the front end is 6, and the number of the second grooves 9 at the rear end is 12.

[0110] Step 10.3, please refer to Figure 8i The SiO2 layer 10 is filled in the second grooves by using an ultra-vacuum chemical vapor deposition technique.

[0111] Specifically, the SiO2 layer 10 is grown at 500°C by using an ultra-vacuum chemical vapor deposition technique, the SiH4 gas and the O2 gas are introduced into the reaction chamber, and the SiO2 material is filled in the second grooves obtained in step 10.2.

[0112] Step 10.4, please refer to Figure 8j The whole structure of the Si layer and the SiO2 layer is etched into a discrete optical waveguide structure.

[0113] Step 11, please refer to Figure 8k The first grooves 11 for depositing metal electrodes are etched through the Si3N4 stress layer by using a plasma etching technique.

[0114] Step 12, please refer to Figure 8l The ion implantation is performed on the P-type Ge surface below the first grooves by using an ion implantation technique to form a P-type heavily doped ohmic contact region 12, and the ion implantation is performed on the N-type Ge surface to form an N-type heavily doped ohmic contact region 13.

[0115] Specifically, the P-type heavily doped ohmic contact region 12 with a doping concentration of 1×1019cm-2 is formed on the P-type Ge surface by using an ion implantation technique. The N-type heavily doped ohmic contact region 13 with a doping concentration of 1×1019cm-2 is formed on the N-type Ge surface. 20 -3 20 -3

[0116] Step 13, please refer to Figure 8m The metal material is filled in the first grooves 11 by using a sputtering deposition technique to form a metal electrode 14.

[0117] Optionally, the metal electrode 14 is, for example, an Al metal electrode.

[0118] ​​​​In the description of the present application, the terms "first", "second", "third", etc. are used only to describe the purpose and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified.

[0119] In the description of the present application, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and integrate different embodiments or examples described in the present specification.

[0120] Although the present application is described herein in conjunction with various embodiments, those skilled in the art, with the benefit of the drawings, the disclosure, and the appended claims, can understand and appreciate other variations of the disclosed embodiments in implementing the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. Measures recited in mutually different dependent claims can be combined and can be realized by a combination of measures.

[0121] The above is a further detailed description of the present application in conjunction with specific preferred embodiments, and the specific implementation of the present application cannot be limited to these descriptions. Modifications made by those skilled in the art without departing from the concept of the present application should be considered within the scope of protection of the present application.

Claims

1. A SiN-stress-based stepped-structure GeSn laser, characterized in that, The laser comprises: a substrate layer; a buffer layer disposed on the substrate layer; an N-type Ge layer disposed on the buffer layer; a front DBR mirror and a rear DBR mirror respectively disposed on the upper surface of both ends of the N-type Ge layer; a plurality of stepped structures of GeSn material disposed on the N-type Ge layer in a width direction and between the front DBR mirror and the rear DBR mirror, and the component of Sn is 6%; a P-type Ge layer disposed on each of the stepped structures; a P-type heavily doped ohmic contact region disposed in the P-type Ge layer; a Si3N4 stress layer disposed on the stepped structures and the N-type Ge layer, and the upper surface of the Si3N4 stress layer is flush with the upper surface of the P-type Ge layer; a metal electrode disposed in a first trench penetrating the Si3N4 stress layer and on the P-type heavily doped ohmic contact region; an N-type heavily doped ohmic contact region disposed below the metal electrode and in the N-type Ge layer.

2. The staircase structure GeSn laser of claim 1, wherein, The substrate layer comprises a silicon substrate.

3. The stepped structure GeSn laser of claim 1, wherein, The buffer layer includes Si 0.5 Ge 0.5 Buffer layer.

4. The stepped structure GeSn laser of claim 1, wherein, The stepped structures comprise a first stepped substructure and a second stepped substructure symmetrically disposed, and each of the first stepped substructure and the second stepped substructure comprises a multi-stage stepped structure.

5. The stepped structure GeSn laser of claim 1, wherein, The front DBR mirror and the rear DBR mirror each comprise a plurality of optical waveguide structures disposed on the N-type Ge layer in a width direction.

6. The stepped structure GeSn laser of claim 5, wherein, The optical waveguide structure comprises: a Si layer provided with a plurality of second trenches penetrating the Si layer and arranged in a space, the extension direction of the second trenches is perpendicular to the extension direction of the metal electrode, and the upper surface of the Si layer is flush with the upper surface of the stepped structure; a SiO2 layer filled in the second trenches.

7. The stepped structure GeSn laser of claim 6, wherein, The number of the second trenches of the front DBR mirror is less than that of the rear DBR mirror. 8.A method for fabricating a SiN-stress-based stepped-structure GeSn laser, characterized in that, A method for preparing the laser of any one of claims 1 to 7, the method comprising: selecting a substrate layer; growing a buffer layer on the substrate layer; growing an N-type Ge layer on the buffer layer by using a low-temperature MBE technique; growing a GeSn layer on the N-type Ge layer by using a low-temperature MBE technique; growing a P-type Ge layer on the GeSn layer by using a low-temperature MBE technique; etching the P-type Ge layer and the GeSn layer to form stepped trenches by using a reactive ion etching technique, and the GeSn layer is etched into a plurality of stepped structures disposed in a width direction, and the P-type Ge layer is also retained on each of the stepped structures; growing a Si3N4 stress layer in the stepped trenches and on the P-type Ge layer by using a PECVD technique; etching away the excess Si3N4 stress layer on the surface by using a plasma etching technique to expose the upper surface of the P-type Ge layer; etching away the Si3N4 stress layer at both ends by using a plasma etching technique to expose the N-type Ge layer at both ends; preparing a front DBR mirror and a rear DBR mirror at both ends of the N-type Ge layer respectively; etching a first trench penetrating the Si3N4 stress layer by using a plasma etching technique; Ion implantation technology is used to perform ion implantation on the N-type Ge surface below the first groove to form an N-type heavily doped ohmic contact region, and ion implantation is performed on the P-type Ge layer surface to form a P-type heavily doped ohmic contact region; Sputtering deposition technology is used to fill the metal material in the first groove to form a metal electrode.

9. The production method according to claim 8, characterized by, Front DBR reflectors and rear DBR reflectors are respectively prepared at both ends of the N-type Ge layer, including: Light waveguide structures are respectively prepared at both ends of the N-type Ge layer and are arranged along the width direction.

10. The method of claim 9, wherein, Light waveguide structures are respectively prepared at both ends of the N-type Ge layer and are arranged along the width direction, including: Ultra-high vacuum chemical vapor deposition technology is used to deposit a Si layer on the upper surface of the N-type Ge layer; Plasma etching technology is used to etch the Si layer to form a plurality of second grooves arranged at intervals and penetrating through the Si layer, wherein the extension direction of the second grooves is perpendicular to the extension direction of the metal electrode, and the upper surface of the Si layer is flush with the upper surface of the stepped structure; Ultra-high vacuum chemical vapor deposition technology is used to fill a SiO2 layer in the second grooves; The overall structure of the Si layer and the SiO2 layer is etched into discrete light waveguide structures.

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