A fractional error estimation circuit applied to a fully digital phase-locked loop

Abstract

The application discloses a decimal error estimation circuit applied to a full-digital phase-locked loop, comprising a time-to-digital converter and an encoding circuit, a period average module, a period normalization module, a first multiplier and a complement circuit; wherein the time-to-digital converter and the encoding circuit, the period average module, the period normalization module, the first multiplier and the complement circuit are sequentially connected. The application realizes the calculation of the decimal phase error in the full-digital phase-locked loop through the time-to-digital converter and the encoding circuit, the period average module, the period normalization module, the first multiplier and the complement circuit. The main advantages of the application are that the circuit structure is simple, the portability is strong, the design is flexible and the cost is low.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology, specifically relating to a fractional error estimation circuit applied to an all-digital phase-locked loop. Background Technology

[0002] A phase-locked loop (PLL) is a circuit with a feedback mechanism. In a PLL, the oscillator output is compared with a reference signal, and the oscillator is calibrated based on the difference. Ideally, when the PLL is locked, the oscillator output frequency is the same as the expected oscillation frequency, and the phase error with the reference signal is maintained within a set range. With the development of digital circuit technology, PLLs are evolving towards digitization, generalization, and integration, and the all-digital phase-locked loop (ADPLL) has become a new research focus. ADPLLs use digital circuits to implement the functions of analog circuits. Compared to analog PLLs, ADPLLs are more portable and programmable, and their phase and frequency adjustments are easier to implement, simplifying the structure of high-performance receivers.

[0003] The difference between the ADPLL output and the reference signal is calculated jointly by the integer error estimation circuit and the fractional error estimation circuit. Traditional fractional error estimation circuits either do not perform periodic averaging or use a summation and averaging method when calculating the average period of the oscillator, requiring a large memory to store multiple data points, resulting in a complex structure. When calculating the normalized period, a lookup table is generally used to avoid division operations, requiring many gates and flip-flops, which occupies a large area on the chip and increases cost.

[0004] Patent CN111077760B lists the reciprocals of all possible period values ​​and stores them in RAM when calculating the normalized period of the oscillator. Then, it reads the data from RAM and outputs it. This method is relatively easier to implement than division, but it requires storing a large number of data with a wide bit width. Furthermore, it does not perform period averaging and cannot reduce random errors caused by clock jitter and metastability of D flip-flops.

[0005] The fractional error estimation circuit proposed in this invention can effectively overcome these shortcomings. Summary of the Invention

[0006] The purpose of this invention is to solve the problems in the background art. By adopting a period averaging module, the random error caused by clock jitter and metastability of D flip-flops is reduced. Furthermore, by using a period normalization module, the use of D flip-flops and gate circuits is reduced, thus providing a fractional error estimation circuit applicable to all-digital phase-locked loops.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: a fractional error estimation circuit applied to an all-digital phase-locked loop, characterized in that it includes: a time-to-digital converter and encoding circuit, a period averaging module, a period normalization module, a first multiplier, and a complement circuit;

[0008] The error Δt and period T output by the time-to-digital converter and encoding circuit v The components are respectively connected to the first multiplier and the periodic averaging module, and the average value of the output of the periodic averaging module is... Access the period normalization module, the reciprocal output by the period normalization module The first multiplier is connected, and the first multiplier outputs the product. Connect to the complement circuit;

[0009] The time-to-digital converter and encoding circuit are used to generate the error Δt between the rising edge of the variable clock CKV and the rising edge of the reference clock FREF. r And the period T of CKV v ;

[0010] The period averaging module is used to calculate the average value of a variable clock cycle over multiple reference clock cycles.

[0011] The period normalization module is used to calculate the reciprocal of the average period.

[0012] The complement circuit is used to calculate the complement of the output of the first multiplier.

[0013] Furthermore, the periodic averaging module uses the exponential moving average method to calculate the average period, and includes a first adder, a shift circuit, a second adder, and a first D flip-flop;

[0014] The period T output by the time-to-digital converter and encoding circuit v The output Q of the first D flip-flop is connected to the input of the first adder. The output of the first adder is connected to a shift circuit. The output of the shift circuit and the output Q of the first D flip-flop are connected to the input of the second adder. The output of the second adder is connected to the data terminal D of the first D flip-flop. The output Q of the first D flip-flop is connected to a period normalization module. The clock terminal clk of the first D flip-flop is connected to the global clock CKR. The reset terminal rst of the first D flip-flop is connected to the reset signal Rst.

[0015] Furthermore, the period normalization module uses the Newton-Raphson algorithm to calculate the average period reciprocal, and includes a second multiplier, a third adder, a third multiplier, a second D flip-flop, and a third D flip-flop;

[0016] The output of the periodic averaging module The output Q of the third D flip-flop is connected to the input of the second multiplier. The input of the third adder is connected to the output of the second multiplier and the value 2. The output of the third adder and the output Q of the third D flip-flop are connected to the input of the third multiplier. The output of the third multiplier is connected to the data terminal D of the second D flip-flop. The output Q of the second D flip-flop is connected to the data terminal D of the third D flip-flop. The output Q of the third D flip-flop is connected to the input of the first multiplier. The clock terminals clk of the second and third D flip-flops are both connected to the global clock CKR. The reset terminals rst of the second and third D flip-flops are both connected to the reset signal Rst.

[0017] Beneficial effects:

[0018] 1. The present invention provides a fractional error estimation circuit for a fully digital phase-locked loop. It uses a period averaging module to calculate the average clock period after frequency division of the digitally controlled oscillator, which reduces the random error caused by clock jitter and metastability of D flip-flops, improves accuracy, and has a relatively simple circuit structure.

[0019] 2. This invention provides a fractional error estimation circuit for all-digital phase-locked loops, which uses a period normalization module to calculate the reciprocal of the average period, compared to existing methods that use lookup tables. The calculations used fewer D flip-flops and gate circuits, saving resources.

[0020] 3. The present invention provides a fractional error estimation circuit for all-digital phase-locked loops, which has the advantages of strong portability and flexible circuit design. Attached Figure Description

[0021] Figure 1 This is a circuit diagram of the all-digital phase-locked loop in an embodiment of the present invention;

[0022] Figure 2 This is a schematic diagram of the circuit structure of the present invention;

[0023] Figure 3 This is a schematic diagram of the circuit structure of the periodic averaging module in this invention;

[0024] Figure 4 This is a schematic diagram of the circuit structure of the period normalization module in this invention. Detailed Implementation

[0025] The invention will now be further explained with reference to the accompanying drawings.

[0026] like Figure 1As shown, the all-digital phase-locked loop in this embodiment of the invention includes a phase detection module composed of an integer error estimation circuit and a fractional error estimation circuit, a digital loop filter, a digitally controlled oscillator (DCO), a frequency divider, and a retiming circuit. The phase detection module, digital loop filter, and DCO are connected in sequence, forming a loop. The retiming circuit provides a global clock for both the phase detection module and the digital loop filter. In use, the reference clock FREF and the frequency control word FCW are input into the entire all-digital phase-locked loop for processing, and a variable-frequency oscillation waveform is output.

[0027] like Figure 2 As shown, this embodiment provides a fractional error estimation circuit for an all-digital phase-locked loop, including a time-to-digital converter (TDC) and coding circuit, a period averaging module, a period normalization module, a first multiplier, and a complement circuit. The error Δt and period T output by the time-to-digital converter and coding circuit are... v The components are respectively connected to the first multiplier and the periodic averaging module, and the average value of the output of the periodic averaging module is... Connect to the period normalization module; the reciprocal output of the period normalization module. The first multiplier is connected, and the first multiplier outputs the product. Connect to the compensation circuit.

[0028] The time-to-digital converter and encoding circuit are used to generate the error Δt between the rising edge of the variable clock CKV and the rising edge of the reference clock FREF. r And the period T of CKV v .

[0029] The period averaging module is used to calculate the average value of a variable clock cycle over multiple reference clock cycles.

[0030] The period normalization module is used to calculate the reciprocal of the average period.

[0031] The complement circuit is used to calculate the complement of the output of the first multiplier.

[0032] The time-to-digital converter and encoding circuit are used to generate the error Δt between the rising edge of the variable clock CKV and the rising edge of the reference clock FREF. r And the period T of CKV v .

[0033] The time-to-digital converter (TD-SCDMA) consists of a delay chain of 64 inverters and 64 D flip-flops for sampling. The rising edges of the variable clock CKV and the reference clock FREF are connected to the TD-SCDMA, which outputs the sampling result Q[63:0]. The encoding circuit calculates and outputs the rising edge error t by finding the positions of the 0→1 and 1→0 transitions in Q[63:0]. r [5:0] and CKV period T v [5:0].

[0034] The period averaging module is used to calculate the average value of a variable clock cycle over multiple reference clock cycles. Its structure is as follows Figure 3 As shown, it includes a first adder, a shift circuit, a second adder, and a first D flip-flop. The input of the first adder is connected to the period T output by the time-to-digital converter and the encoding circuit. v The difference between [5:0] and the output Q of the first D flip-flop is subtracted and then divided using a shift circuit. The shifted result and the output Q of the first D flip-flop are connected to the input of the second adder. The sum of the two is connected to the data input D of the first D flip-flop, and the output Q of the first D flip-flop outputs the average value. average value The access period normalization module is connected. The clock input clk of the first D flip-flop is connected to the global clock CKR, and the reset input rst is connected to the reset signal Rst.

[0035] The period normalization module is used to calculate the reciprocal of the average period. Its structure is as follows Figure 4 As shown, it includes a second multiplier, a third adder, a third multiplier, a second D flip-flop, and a third D flip-flop. The output of the periodic averaging module... The output Q of the third D flip-flop is connected to the input of the second multiplier. The product of the two, plus the value 2, is connected to the input of the third adder. The subtraction of the two, plus the output Q of the third D flip-flop, is connected to the input of the third multiplier. The product of the two is connected to the data terminal D of the second D flip-flop. The output Q of the second D flip-flop is connected to the data terminal D of the third D flip-flop. The output Q of the third D flip-flop outputs the reciprocal of the average period. Furthermore, the clock inputs clk of the second and third D flip-flops are connected to the global clock CKR, and the reset inputs rst of the second and third D flip-flops are connected to the reset signal Rst.

[0036] Rising edge error t of the time-to-digital converter and encoding circuit output r [5:0] and the reciprocal of the average period output by the period normalization module. The result of multiplying the two components is sent to the complement circuit, where it is inverted and then incremented by 1 to obtain the final decimal error ε.

[0037] In this embodiment, the averaging method used by the periodic averaging module is the exponential moving average, which is an averaging method that gives higher weight to recent data. Its formula is as follows:

[0038] V n =β·V n-1 +(1-β)·θ n (1)

[0039] Among them, V n V0 represents the average of the first n data points (V0 = 0), and β is the weighting value (generally set to 0.9-0.999). We take β = 1-2. -7 , θ n =Tv n Then equation (1) can be expressed as follows:

[0040]

[0041] The division operation is implemented by a shift circuit.

[0042] The principle of the periodic normalization module is to use the Newton-Raphson algorithm for approximate division calculations. The Newton-Raphson algorithm is a root-finding algorithm. Its principle is to start from an initial point, draw a tangent line at that point, and find the coordinates of the next iteration point by the intersection of the tangent line and the X-axis. This process is repeated until a satisfactory approximate solution is found. The formula is as follows:

[0043]

[0044] Where, f'(x) n Let f(x) be the function f(x) in x. n The first derivative at that point is the tangent line at that point. In this embodiment, we assume... Then the roots of f(x) are Equation (3) can be rewritten as follows:

[0045]

[0046] Considering the input average period of the period normalization module The range is from 48 to 64, so let the initial value x0 = 1 / 64, and the fixed-point number representation is 0000_0011_1111_1111. All other data are also represented using fixed-point numbers. When performing multiplication and addition, the multiplication and addition of fixed-point numbers need to be considered.

[0047] To further prevent the multiplier's bit width from increasing, the output of the second D flip-flop was truncated.

[0048] In summary, the fractional error estimation circuit for all-digital phase-locked loops provided by this invention calculates the fractional phase error in all-digital phase-locked loops through a time-to-digital converter and encoding circuit, a period averaging module, a period normalization module, a first multiplier, and a complement circuit.

[0049] This invention provides a fractional error estimation circuit for all-digital phase-locked loops. It employs a period averaging module to calculate the average clock period after frequency division of the digitally controlled oscillator, reducing the random errors caused by clock jitter and the metastability of the D flip-flop, thus improving accuracy. Simultaneously, it uses a period normalization module to calculate the reciprocal of the average period, which is superior to existing methods using lookup tables. The calculation uses fewer D flip-flops and gate circuits, saving resources, and the circuit structure is relatively simple, with the advantages of strong portability and flexible circuit design.

[0050] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A fractional error estimation circuit applied to an all-digital phase-locked loop, characterized in that, include: It includes a time-to-digital converter and encoding circuit, a period averaging module, a period normalization module, a first multiplier, and a complement circuit; The error Δt and period T output by the time-to-digital converter and encoding circuit v The components are respectively connected to the first multiplier and the periodic averaging module, and the average value of the output of the periodic averaging module is... Access the period normalization module, the reciprocal output by the period normalization module The first multiplier is connected, and the first multiplier outputs the product. Connect to the complement circuit; The time-to-digital converter and encoding circuit are used to generate the error Δt between the rising edge of the variable clock CKV and the rising edge of the reference clock FREF. r And the period T of CKV v ; The period averaging module is used to calculate the average value of a variable clock cycle over multiple reference clock cycles. ; The period normalization module is used to calculate the reciprocal of the average period. ; The complement circuit is used to calculate the complement of the output of the first multiplier.

2. The fractional error estimation circuit applied to an all-digital phase-locked loop according to claim 1, characterized in that, The periodic averaging module uses the exponential moving average method to calculate the average period, and includes a first adder, a shift circuit, a second adder, and a first D flip-flop. The period T output by the time-to-digital converter and encoding circuit v The output Q of the first D flip-flop is connected to the input of the first adder. The output of the first adder is connected to a shift circuit. The output of the shift circuit and the output Q of the first D flip-flop are connected to the input of the second adder. The output of the second adder is connected to the data terminal D of the first D flip-flop. The output Q of the first D flip-flop is connected to a period normalization module. The clock terminal clk of the first D flip-flop is connected to the global clock CKR. The reset terminal rst of the first D flip-flop is connected to the reset signal Rst.

3. The fractional error estimation circuit applied to an all-digital phase-locked loop according to claim 1, characterized in that, The period normalization module uses the Newton-Raphson algorithm to calculate the average reciprocal of the period, and includes a second multiplier, a third adder, a third multiplier, a second D flip-flop, and a third D flip-flop. The output Tv of the periodic averaging module and the output Q of the third D flip-flop are connected to the input of the second multiplier. The input of the third adder is connected to the output of the second multiplier and the value 2. The output of the third adder and the output Q of the third D flip-flop are connected to the input of the third multiplier. The output of the third multiplier is connected to the data D of the second D flip-flop. The output Q of the second D flip-flop is connected to the data D of the third D flip-flop. The output Q of the third D flip-flop is connected to the input of the first multiplier. The clock terminals clk of the second and third D flip-flops are both connected to the global clock CKR. The reset terminals rst of the second and third D flip-flops are both connected to the reset signal Rst.

Images