Dynamic metadata relocation in memory

Abstract

Metadata is dynamically relocated in DRAM from a virtual page that is not mapped to the same DRAM row where associated data is located to the same DRAM row. If a data access request targets a location in a first page that is configured to store metadata instead of data, a second location in a second page can be determined and the requested data can be accessed at the second location. The associated metadata can be accessed at a location in the first page that is configured in the virtual domain to store data but is configured in the physical domain to store metadata associated with the data in the first page.

Description

Background Art

[0001] A computing device may include multiple subsystems that communicate with each other via a bus or other interconnects. Such computing devices may be, for example, portable computing devices ("PCDs"), such as laptop computers or palmtop computers, cellular phones or smart phones, portable digital assistants, portable game consoles, etc. The communication subsystem may be included in the same integrated circuit chip or in different chips. "System on chip" or "SoC" is an example of such a chip that integrates many components to provide system-level functionality. For example, an SoC may include one or more types of processors, such as a central processing unit ("CPU"), a graphics processing unit ("GPU"), a digital signal processor ("DSP"), and a neural processing unit ("NPU"). The SoC may include other subsystems, such as a transceiver or "modem" subsystem that provides wireless connectivity, a memory subsystem, etc. The SoC may be coupled to one or more memory chips via a data communication link. Various processing engines may perform memory transactions with memory. The main memory or system memory in PCDs and other computing devices typically includes dynamic random access memory ("DRAM"). DRAM is organized into an array of rows and columns. A row must be opened before its data can be accessed. Only one row can be opened at any time. DRAM rows are sometimes called (physical) pages.

[0002] The term "conflict" refers to a memory transaction that points to a closed DRAM row while another row (the row that the transaction is not pointing to) is open. If there is a conflict in a memory transaction, the open row must be closed first, and then the row that the transaction points to must be opened. Conflicts increase memory latency, which is the amount of time it takes to complete a memory transaction in response to a transaction request from a processing engine. Memory latency has the potential to impact computing device performance and ultimately the user experience. Minimizing memory latency can also be an important goal in mission-critical or safety-critical computing devices, such as those used to control autonomous vehicles, drones, and the like.

[0003] Some types of data have metadata associated with them. For example, a "syndrome" is metadata associated with data that has been subjected to an error correction algorithm. Flags and other metadata may be associated with data that has been subjected to a compression algorithm. Signatures, hashes, etc. may be associated with data that has been subjected to an authentication algorithm. Still other types of metadata are known, such as Memory Tag Extension ("MTE"). Metadata is typically stored in memory in such a way that it can be accessed when the associated data is accessed. Summary of the invention

[0004] Systems, methods, computer-readable media, and other examples of metadata relocation in DRAM are disclosed. Metadata can be dynamically relocated from virtual pages that are not mapped to the same DRAM row as associated data.

[0005] An exemplary method of metadata relocation in DRAM may include receiving a first request to access data at a first data location in a first memory page of the DRAM and associated metadata at a first metadata location in a second memory page of the DRAM. The method may include determining whether the first data location in the first memory page is configured to store metadata. The method may also include accessing the data at the first data location in the first memory page if the first data location in the first memory page is not configured to store metadata. The method may further include determining the metadata location in the first memory page if the first data location in the first memory page is not configured to store metadata. The method may further include accessing the associated metadata at the metadata location in the first memory page if the first data location in the first memory page is not configured to store metadata. The method may include determining the second data location in the second memory page if the first data location in the first memory page is configured to store metadata. The method may further include accessing the data at the second data location in the second memory page if the first data location in the first memory page is configured to store metadata. The method may still additionally include accessing associated metadata at the first data location in the first memory page if the first data location in the first memory page is configured to store metadata.

[0006] An exemplary system for metadata relocation may include a DRAM and a processor. The processor may be configured to receive a first request for accessing data at a first data location in a first memory page and associated metadata at a first metadata location in a second memory page. The processor may also be configured to determine whether the first data location in the first memory page is configured to store metadata. If the first data location in the first memory page is not configured to store metadata, the processor may be further configured to access the data at the first data location in the first memory page. If the first data location in the first memory page is not configured to store metadata, the processor may be further configured to determine the metadata location in the first memory page. If the first data location in the first memory page is not configured to store metadata, the processor may be further configured to access the associated metadata at the metadata location in the first memory page. If the first data location in the first memory page is configured to store metadata, the processor may be further configured to determine the second data location in the second memory page. If the first data location in the first memory page is configured to store metadata, the processor may be further configured to access the data at the second data location in the second memory page. If the first data location in the first memory page is configured to store metadata, the processor may additionally be configured to access the associated metadata at the first data location in the first memory page.

[0007] Another exemplary system for metadata relocation in DRAM may include a component for receiving a first request for accessing data at a first data location in a first memory page of the DRAM and associated metadata at a first metadata location in a second memory page of the DRAM. The system may include a component for determining whether the first data location in the first memory page is configured to store metadata. The system may also include a component for accessing the data at the first data location in the first memory page if the first data location in the first memory page is not configured to store metadata. The system may further include a component for determining the metadata location in the first memory page if the first data location in the first memory page is not configured to store metadata. The system may further include a component for accessing the associated metadata at the metadata location in the first memory page if the first data location in the first memory page is not configured to store metadata. The system may include a component for determining a second data location in a second memory page if the first data location in the first memory page is configured to store metadata. The system may further include a component for accessing the data at the second data location in the second memory page if the first data location in the first memory page is configured to store metadata. The system may still further include means for accessing associated metadata at the first data location in the first memory page if the first data location in the first memory page is configured to store metadata.

[0008] An exemplary computer-readable medium for metadata relocation in DRAM may include a non-transitory computer-readable medium having instructions stored thereon in a computer-executable form. When the instructions are executed by a processor, the processor may be configured to receive a first request for accessing data at a first data location in a first memory page and associated metadata in a second memory page. The instructions may configure the processor to determine whether the first data location in the first memory page is configured to store metadata. If the first data location in the first memory page is not configured to store metadata, the instructions may also configure the processor to access the data at the first data location in the first memory page. If the first data location in the first memory page is not configured to store metadata, the instructions may further configure the processor to determine the metadata location in the first memory page. If the first data location in the first memory page is not configured to store metadata, the instructions may further configure the processor to access the associated metadata at the metadata location in the first memory page. If the first data location in the first memory page is configured to store metadata, the instructions may further configure the processor to determine the second data location in the second memory page. If the first data location in the first memory page is configured to store metadata, the instructions may additionally configure the processor to access data at the second data location in the second memory page. If the first data location in the first memory page is configured to store metadata, the instructions may additionally configure the processor to access the associated metadata at the first data location in the first memory page. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In the drawings, like reference numerals refer to like parts in the various views unless otherwise specified. For reference numerals with letter character designations, such as "102A" or "102B", the letter character designations may distinguish between two similar parts or elements appearing in the same drawing. When a reference numeral is intended to encompass all parts having the same reference numeral in all drawings, the letter character designations for the reference numeral may be omitted.

[0010] Figure 1 is a block diagram conceptually illustrating metadata relocation in a dynamic random access memory (DRAM) according to an exemplary embodiment.

[0011] Figure 2 is a block diagram of a metadata relocation system in a DRAM according to an exemplary embodiment.

[0012] Figure 3 is a memory map diagram illustrating the conventional location of data and associated metadata in DRAM.

[0013] Figure 4is a memory map diagram illustrating relocation of metadata in a DRAM according to an exemplary embodiment.

[0014] Figure 5 is a memory map diagram illustrating data locations without associated metadata according to an exemplary embodiment.

[0015] Figure 6 is a flow chart illustrating a method of metadata relocation in a DRAM according to an exemplary embodiment.

[0016] Figure 7 is a diagram illustrating a method of Figure 6 An address diagram showing an example of converting data addresses in the relocation method.

[0017] Figure 8 It is a graphic Figure 7 A memory map of the conversion aspects.

[0018] Fig. 9 Similar to Figure 8 , showing an example of actual memory addresses.

[0019] Fig.10 is a diagram illustrating a method of Figure 6 An address map of an example of translating metadata addresses in the relocation method.

[0020] Fig.11 is a memory map diagram illustrating relocation of metadata in a DRAM according to an exemplary embodiment, wherein the DRAM includes a plurality of memory bank groups.

[0021] Fig.12 is another memory map illustrating relocation of metadata in a DRAM according to an exemplary embodiment, wherein the DRAM includes a plurality of memory bank groups.

[0022] Fig.13 is a block diagram of a computing device according to an exemplary embodiment. DETAILED DESCRIPTION

[0023] As used herein, the word "exemplary" means "serving as an example, instance, or illustration." The word "illustrative" may be used herein as a synonym for "exemplary." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0024] like Figure 1, in system 100, client 102 may issue a memory transaction request directed to dynamic random access memory ("DRAM") 104. Although not shown for clarity, system 100 may be included in any type of computing device. Client 102 may also be of any type. As one of ordinary skill in the art will appreciate, client 102 may be implemented by execution of an application, thread, etc. on a processor. Client 102 may also be referred to as a processing engine or bus master. As one of ordinary skill in the art will appreciate, a bus master is any device that initiates a bus transaction with a system resource, of which DRAM 104 is an example. DRAM 104 may be of any type, such as double data rate synchronous DRAM ("DDR-SDRAM"), sometimes referred to as "DDR" for simplicity. As DDR technology has evolved, DDR versions such as fourth generation low power DDR ("LPDDR4") and fifth generation low power DDR ("LPDDR5") have been developed. DRAM 104 may be, for example, LPDDR4, LPDDR5, etc.

[0025] The various memory transaction requests that client 102 may issue may include requests to read data from DRAM 104 and requests to write data (i.e., store data) to DRAM 104. Memory transaction requests may also be referred to as requests to access DRAM 104. Each memory transaction request may include a virtual address or location. When the data that is the subject of the read transaction request has been returned to client 102, the read transaction is completed. When the data that is the subject of the write transaction request has been written to DRAM 104, the write transaction is completed.

[0026] Certain types of data that may be stored in DRAM 104 have metadata associated with the data. Metadata processor 106 may receive a memory transaction request with client 102 and determine whether the data that is the subject of the transaction request has associated metadata. Metadata processor 106 may determine whether the data has associated metadata based on a virtual address. For example, if the virtual address is within a first address range, metadata processor 106 may determine that the data has associated metadata, and if the virtual address is within a second address range, metadata processor 106 may determine that the data does not have associated metadata. Different address ranges may correspond to different types of metadata. Depending on whether the data has associated metadata and the type of metadata, metadata processor 106 may process the data accordingly. For example, if the virtual address corresponds to data of a type that has been subjected to error correction features, metadata processor 106 may generate syndrome metadata to be stored in DRAM 104 in association with the data in the case of a write access, or may perform an error correction algorithm on the data using the associated syndrome metadata read from DRAM 104 in the case of a read access. The problem addressed by the embodiments described herein is how to efficiently access metadata as well as data.

[0027] Data and associated metadata may be stored in a first region (i.e., address range) 108 of DRAM 104. Dashed arrow 110 conceptually indicates an association between an exemplary line of data and its metadata. Data of a type that does not have any associated metadata may be stored in a second region 112 of DRAM 104. Although for purposes of illustration, the first region 108 of DRAM 104 may be stored in a second region 112 of DRAM 104. Figure 1 Only one such "first" region 108 and one such "second" region 112 are shown, but there may be more than one region storing data and associated metadata, and more than one region storing data without any associated metadata. Figure 1 Not shown in FIG. 1 , a virtual address (in the virtual domain) provided by a memory transaction request is translated or mapped to a physical address in DRAM 104 (in the physical domain).

[0028] It should be understood that data locations and metadata locations in the virtual domain refer to, sometimes colloquially, the locations of data and metadata that client 102 "sees" or "perceives" being stored. As described in additional detail below, from the client's perspective (i.e., in the virtual domain), portions of DRAM 104 may be configured to store data, while other portions of DRAM 104 may be configured to store metadata. In other words, the virtual or client domain refers to the addressing scheme used by client 102 to indirectly reference data and metadata storage locations in DRAM 104. In contrast, the physical domain refers to the addressing scheme used in DRAM 104 to physically access storage locations where data and metadata may be stored. Correspondingly, it can be noted that in the physical domain, portions of DRAM 104 may be configured to store data, while other portions of DRAM 104 may be configured to store metadata.

[0029] like Figure 2 As shown, the system 200 may include a client 202, a system cache 204, a coprocessor 206, a memory controller 208, and a DRAM 210. The system 200 may be the system 100 ( Figure 1 ). Client 202, coprocessor 206, and DRAM 210 may be examples of the above-mentioned client 102, metadata processor 106, and DRAM 104, respectively. System cache 204 may be inserted in the data flow between client 202 and coprocessor 206. As understood by those of ordinary skill in the art, system cache 204 may operate in a conventional manner. Therefore, some memory transaction requests may be completed using system cache 204, thereby avoiding the need to access DRAM 210. System cache 204 may organize data in units referred to as cache lines or, for brevity, "lines." Using system cache 204 instead of DRAM 210 to complete memory transaction requests is not directly relevant to the present disclosure. Instead, the present disclosure relates to memory transaction requests completed by accessing DRAM 210. However, it should be understood that the client 202, the system cache 204, and the coprocessor 206 all process data in the virtual domain, and therefore address data by virtual page addresses (i.e., page codes) and virtual row addresses (i.e., row numbers) rather than physical addresses in the DRAM 210. The client 202 issues memory transaction requests that indicate virtual addresses by virtual page codes and row numbers within virtual pages.

[0030] Among other functions, the coprocessor 206 may process metadata, such as one or more of error correction, memory tagging, DRAM authentication, DRAM freshness, DRAM compression, and the like. The coprocessor 206 may determine whether a client is requesting access to data of a type that has associated metadata. A request to access data having associated metadata may generate a request to also access the associated metadata. The coprocessor 206 may therefore provide a request to the memory controller 208 to access not only the data requested by the client 202 but also the associated metadata. For example, in response to a request from the client 202 to write data of a type that has been error corrected to the DRAM 210, the coprocessor 206 may generate syndrome metadata and a request to the memory controller 208 to store the syndrome metadata in association with the data in the DRAM 210. Similarly, in response to a request to read data of a type that has been error corrected from the DRAM 210, the coprocessor 206 may generate a request to the memory controller 208 to read the associated syndrome metadata from the DRAM 210. Coprocessor 206 may then perform error correction algorithms on the data using the syndrome metadata read from DRAM 210 .

[0031] Among other functions, the memory controller 208 can convert memory transaction requests into DRAM transactions, including DRAM commands and physical addresses in a conventional manner. Since such conventional functions and related functions of the memory controller 208 are well understood by those of ordinary skill in the art, these aspects of the memory controller 208 are not described herein.

[0032] DRAM 210 may have a conventional structure and operate in a conventional manner. DRAM 210 may be, for example, LPDDR4, LPDDR5, etc. Although the structure and operation of such DRAMs are well understood by those of ordinary skill in the art, the following brief description is provided as background.

[0033] DRAM 210 may include one or more memory banks 212. For example, DRAM 210 may have M memory banks 212, which may be referred to as "Bank_0" through "Bank_M-1". Each memory bank 212 may include a two-dimensional array 213 of storage locations, where a storage location in the array is accessed by selecting a row and a column. For clarity, array 213 is referred to as Figure 2 Array 213 may have more rows and columns than shown, and each storage location may be configured to store a certain amount of data, such as a byte ("B"). Figure 2, exemplary rows and columns are highlighted (indicated by cross-hatching). Thus, the DRAM physical address provided by the memory controller 208 may include a row address, a column address, and a bank address. In response to the bank address, the bank address decoding logic (not shown) may select one of the banks 212. In response to the row address, the row address decoder 214 may select one of the rows in the selected bank 212. Similarly, in response to the column address, the column address decoder 216 may select one of the columns in the selected bank 212. The read latch 218 may buffer read data, and the write latch 220 may buffer write data. The input / output ("I / O") logic 222 may direct the reading of data from the selected memory location and the writing of data to the selected memory location.

[0034] Each memory bank 212 may have a row buffer 224. The row buffer 224 stores the contents of a selected row (sometimes referred to as a physical "page"). Before writing or reading a row, the row must be activated or "opened". Once the row is opened, the DRAM 210 can read from or write to any number of columns in the row buffer 224 in response to a read or write command. After a read or write command, data is transferred serially between the memory controller 208 and the DRAM 210 in a unit called a "burst", which includes a predetermined number of columns of data. The burst size may be, for example, the same as the row size described above. After writing to or reading from the row buffer 224, the row must be restored or "closed". Only one row in each memory bank 212 may remain open at a time.

[0035] The memory controller 208 can identify each transaction as a "hit", "miss", or "conflict" based on the current state of the DRAM memory bank 212. A hit is a read or write transaction to a row (in the memory bank 212) that the memory controller 208 determines to be open when the memory controller 208 processes the transaction request. A hit has low latency. That is, a hit transaction can be completed in a relatively short time. A miss is a read or write transaction to a row (in the memory bank 212) that the memory controller 208 determines to be closed when the memory controller 202 processes the transaction request. If the memory controller 208 identifies a read or write transaction as a miss, the memory controller 208 must first open the row before reading from or writing to the row. A miss has a higher latency than a hit. That is, a miss transaction takes more time to complete than a hit transaction. A conflict is a read or write transaction to a row (in a memory bank 212) that the memory controller 208 determines is closed when the memory controller 208 processes the transaction request, and the memory controller 208 determines that another row to the same memory bank (not targeted by the memory transaction) is open at that time. If the memory controller 208 identifies the read or write transaction as a conflict, the memory controller 208 must first close the open row in that memory bank 212 and then open the row targeted by the transaction before reading from or writing to that row. A conflict has a higher latency than a miss. That is, a transaction that is a conflict takes more time to complete than a transaction that is a miss or a hit.

[0036] If the data and its associated metadata are not stored in the same row of DRAM 210, memory accesses can result in conflicts, resulting in high latency. Exemplary embodiments of the systems, methods, computer-readable media, etc. described herein relate to dynamically mapping or relocating metadata in a manner that maximizes the likelihood that memory accesses of data and associated metadata will not result in conflicts. By storing the data and its associated metadata in the same DRAM row, when the DRAM row is opened, the data and metadata can be accessed simultaneously, thereby avoiding conflicts.

[0037] like Figure 3 As shown, a conventional addressing scheme or configuration 300 may configure a memory address range or region 302 to include a data region 304 and a metadata region 306. That is, region 302 is configured to store data in data region 304 and store its associated metadata in metadata region 306. Data region 304 may be configured as two or more data pages 308A (“Pages”). D0 ”), 308B(“P D1”), and so on, until the last data page (not shown). (The ellipsis (“…”) following data page 308B indicates that there may be any number of additional data pages.) Similarly, metadata area 306 may be configured as one or more metadata pages 310.

[0038] Each of the data pages 308A, 308B, etc. may be configured as a plurality ("Z") of data rows: a first data row L 0 , the second data line L 1 Wait until the last data row L Z-1 Similarly, each metadata page in the one or more metadata pages 310 may be configured as Z metadata rows: a first metadata row L 0 , the second metadata line L 1 etc., until the last metadata line L Z-1 All metadata associated with the data stored in the first data page 308A may be stored in the first metadata row L of the metadata page 310. 0 (“P MD0 ”). Similarly, all metadata associated with the data stored in the second data page 308B may be stored in the second metadata row L of the metadata page 310. 1 The same relative positions of data and associated metadata as described above with respect to the first two data pages 308A and 308B apply to all additional data pages (not shown), and thus metadata associated with data stored in the last data page (not shown) may be stored in the last row L of metadata page 310. Z-1 Each data page 308A, 308B, etc., and each metadata page 310 may have a page size (“S P ") and row size ("S L ”), examples of which are described below. Each of the pages in the virtual domain can be converted (e.g., by the memory controller 208) into a different DRAM row in the physical domain. Each of the rows of pages in the virtual domain can be converted into a group of one or more DRAM columns in the row corresponding to the page.

[0039] In order to access data and its associated metadata, a client may issue a transaction request that includes a virtual address that identifies the request target by a page code and a row number. That is, the client may use a virtual domain address scheme that addresses data in data pages 308A, 308B, etc., and addresses associated metadata in metadata page 310. In exemplary configuration 300, each of data pages 308A, 308B, etc., and metadata page 310 are mapped or converted to different DRAM rows in the physical domain. It can be understood from exemplary configuration 300 that because data and its associated metadata are not stored in the same DRAM row, memory accesses may result in conflicts.

[0040] like Figure 4 As shown, the exemplary addressing scheme or configuration 400 may configure an address range or region 402 to include a data region 404 and a pseudo metadata region 406. To access the data and its associated metadata, the client may follow the same procedures as described above with respect to Figure 3 The transaction request is issued in the same manner as described above, the transaction request including a virtual address in area 402, which identifies the target of the request by a page code and a row number. That is, the client can use a virtual domain address scheme that addresses the data in data pages 408A, 408B, etc., and addresses the associated metadata in metadata page 410 of pseudo metadata area 406. In the exemplary configuration 400, each of the data pages 408A, 408B, etc., and the metadata page 410 are mapped or converted to different DRAM rows in the physical domain. However, unlike the conventional configuration 300 (described above), Figure 3 ), the pseudo metadata area 406 is configured as a metadata area in the virtual (ie, client) domain, but as Figure 4 As shown, the physical (i.e., memory controller and DRAM) domain is configured as a supplemental data area to store data that has been "relocated" from data area 404. In other words, client 202 is configured as described above with respect to Figure 3 The same manner described “sees” or “perceives” metadata as stored in pseudo metadata area 406 , even though the metadata is not actually stored (in the physical domain) in the DRAM row mapped to pseudo metadata area 406 .

[0041] In contrast, in the physical domain, metadata may be stored in a predetermined row (e.g., the last row) of each of the data pages 408A, 408B, etc. in the data area 404. In other words, the exemplary embodiments described herein operate in the physical domain as if the last row of a data page is swapped with the rows of a metadata page that includes metadata for the data page in the virtual domain. For example, in the physical domain, the first to second to last rows (i.e., data rows L) stored in the first data page 408A are swapped with the rows of a metadata page that includes metadata for the data page in the virtual domain. 0 To L Z-2 ) can be stored in the last row of the first data page 408A. Similarly, in the physical domain, metadata associated with the first to second to last rows (i.e., data rows L) stored in the second data page 408B 0 To L Z-2 ) can be stored in the last row of the second data page 408B. The same relative positions of data and associated metadata as described above with respect to the first two data pages 408A and 408B apply to all additional data pages (not shown), so that in the physical domain, the first to second to last rows (i.e., data rows L) stored in the last data page (not shown) are identical. 0 To L Z-2 ) can be stored in the last row of the last data page.

[0042] The pseudo metadata area 406 may be configured in the physical domain as one or more supplemental data pages 410 to store the last row (i.e., data row L) of each data page stored in (i.e., what the client "sees" or "perceives" as stored in) data pages 408A, 408B, etc. in the virtual domain. Z-1 ) instead of metadata. For example, the first row of the supplemental data page 410 can be configured in the physical domain to store data associated with the last row of the first data page 408A in the virtual domain, the second row of the supplemental data page 410 can be configured to store data associated with the last row of the second data page 408B in the virtual domain, and so on.

[0043] In summary, in a virtual domain, or from client 202 ( Figure 2 ), the last row of each of the data pages 408A, 408B, etc. is configured to store data, but in the physical domain, or from the perspective of the memory controller 208 and the DRAM 210 ( Figure 2 ), the last row of each of the data pages 408A, 408B, etc. is configured to store all metadata associated with that one of the pages 408A, 408B, etc. In addition, in the virtual domain, or from the client 202 ( Figure 2 ), but in the physical domain, or from the perspective of the memory controller 208 and the DRAM 210, the pseudo metadata area 406 is configured to store metadata associated with the data pages 408A, 408B, etc., but in the physical domain, or from the perspective of the memory controller 208 and the DRAM 210, the pseudo metadata area 406 is configured to store metadata received from the client 202 ( Figure 2 ) from the perspective of the first row of each data page in data pages 408A, 408B, etc. In other words, the last row of each data page in data pages 408A, 408B, etc. is a virtual domain data location and is also a physical domain metadata location configured to store all metadata associated with one of the data pages 408A, 408B, etc. In addition, each row of supplemental data pages 410 (in pseudo metadata area 406) is a virtual domain metadata location and is also a physical domain data location corresponding to the last row of each data page in data pages 408A, 408B, etc. It should be understood that the last row is an example of a predetermined row in which metadata can be stored, and in other embodiments, metadata can be stored in any other predetermined row. For example, in another embodiment (not shown), the first row can be a row configured to store metadata. In yet another embodiment (not shown), the second row can be a row configured to store metadata, etc.

[0044] like Figure 5 As shown, it can be noted that the above-mentioned addressing scheme or configuration 400 ( Figure 4 ) can coexist with an addressing scheme or configuration 500 for data without any associated metadata. Configuration 500 can configure an address range or region 502 of DRAM 210 to consist of only a data region 504 without an associated metadata region. Address ranges or regions 502 and 402 ( Figure 4 ) may be the same DRAM 210 ( Figure 2 ) two address ranges or regions. The data region 504 may be configured as two or more DRAM data pages 508A, 508B, etc.

[0045] like Figure 6 As shown, the exemplary method 600 for metadata relocation in a DRAM system may include the events or actions described below with respect to blocks 602-614. The method 600 reflects the above Figure 4 The mapping or relocation of the described data and metadata may occur dynamically, i.e., in response to a request from client 202 ( Figure 2) memory transaction request. The method 600 may be executed or otherwise controlled by, for example, the above-mentioned coprocessor 206 or by a combination of the coprocessor 206 and the memory controller 208. The coprocessor 206, the memory controller 208, or a combination of the coprocessor 206 and the memory controller 208 may be examples of means for performing the functions described below with respect to the method 600. In the following description of the method 600, the terms "first", "second", etc. may be used to distinguish between elements or steps, rather than to describe or imply any order, sequence, rank, etc. For example, references to the "first" and "second" pages in the method 600 are not limited to the above reference pages. Figure 4 The corresponding data pages 408A and 408B described may be any other pages that are consecutive, but may refer to any two of the data pages 408A, 408B, etc., or any other two pages. Similarly, references to the "first" and "second" data locations are not limited to the corresponding rows L. 0 and L 1 or any other possibly consecutive data locations, but can refer to any two locations.

[0046] As shown in block 602, method 600 may include receiving a request to access data at a first data location in a first page and associated metadata at a first metadata location in a second page. The request may include two access requests: one request to access the data and another request to access metadata associated with the data. The access request may be received by, for example, a portion of coprocessor 206.

[0047] As shown in block 604, it may be determined whether the first data location in the first page is configured to store metadata. Figure 4 As described above, the last row of each of the data pages 408A, 408B, etc. may be configured to store metadata. Therefore, in an exemplary embodiment where the last row of each data page is configured to store metadata rather than data, it may be determined (block 604) whether the first data location is the last row of the data page. In other words, it may be determined whether the target of the data access request is the last row of the data page. It should be understood that in the exemplary embodiments described herein, the coprocessor 206 is configured to use the above referenced Figure 4 The mapping or configuration 400 described above can be used to determine whether a particular physical domain data location is configured to store metadata (rather than data) or is configured to store data (rather than metadata). That is, in an exemplary embodiment, the coprocessor 206 can determine whether the target of the data access request is the last row of the data page. The first data location configured to store metadata can also be referred to as a second metadata location.

[0048] As shown in block 606, if it is determined (block 604) that the first data location in the first page is not configured to store metadata, the data at the first data location in the first page may be accessed. For example, the memory controller 208 ( Figure 2 ) can access data by issuing commands to DRAM 210, communicating data with DRAM 210, etc., as described above with respect to Figure 2 Again, refer to the above Figure 4 As described in the mapping or configuration 400, if the first data location corresponds to the first to second to last row (ie, data row L) of one of the data pages 408A, 408B, etc. 0 To L Z-2 ) in the physical domain data location.

[0049] As shown in block 612, if it is determined (block 604) that the first data location in the first page is not configured to store metadata, then a ("second") metadata location in the first page may be determined. Figure 4 In the example described, each row of the supplemental data page 410 of the pseudo metadata area 406 is mapped to the last row of one of the data pages 408A, 408B, etc. Thus, in this example, the "second" metadata location in the first page is the last row of the first page. For example, if the first page is data page 408A, the second metadata location can be determined as the last row of data page 408A. Similarly, if the first page is data page 408B, the second metadata location can be determined as the last row of data page 408B. The second metadata location is the location of metadata that has been "relocated" from the pseudo metadata area 406. As shown in box 613, after the ("second") metadata location in the first page is determined (box 612), the associated metadata can be accessed at that metadata location in the first page.

[0050] Accessing a data location according to block 606 may include converting (e.g., by the memory controller 208) a virtual domain data location to a physical domain data location. A request to access data may provide a first data location in the form of a virtual page number and a row number. Similarly, a request to access metadata may provide a first metadata location in the form of a virtual page number and a row number. A page number in the virtual domain may correspond to a DRAM row in the physical domain, and thus be converted (e.g., by the memory controller 208) to a DRAM row in the physical domain. A row number in the virtual domain may correspond to, and thus be converted to, a group of one or more DRAM columns in the row. (The number of DRAM columns per data row may be predetermined, i.e., constant throughout the operation of an embodiment.)

[0051] As shown in block 608, if it is determined (block 604) that the first data location in the first page is configured to store metadata, then a second data location in the second page may be determined based on the first data location. Figure 4 In the example mapping or configuration described above, if it is determined that the requested or target data location is the last row (i.e., data row L) of one of the data pages 408A, 408B, etc. Z-1 ). It can then be determined which row of the supplemental data page 410 in the pseudo metadata area 406 corresponds to the data page. In this example, the supplemental data page 410 is the "second" page mentioned above, and the row in the supplemental data page 410 is the "second" data location.

[0052] As shown in block 610, once the second data location in the second page is determined (block 608), the second data location may be accessed. In the case of a read access, accessing the data at the second data location may include the memory controller 208 ( Figure 2 ) reads data from DRAM 210. In the case of a write access, accessing the data may include ensuring that the data has been written, i.e., stored in DRAM 210 by memory controller 208.

[0053] As shown in block 614, if it is determined (block 604) that the first data location in the first page is configured to store metadata, the associated metadata may be accessed at the first data location. Accessing the associated metadata may include translating (e.g., by the memory controller 208) the first data location in the virtual domain into the physical domain. The page number in the virtual domain may correspond to, and therefore be translated into, a DRAM row in the physical domain. The row number in the virtual domain may correspond to, and therefore be translated into, a group of one or more DRAM columns in the row.

[0054] Note that in the case where the first data location in the first page is configured to store data (ie, not configured to store metadata), then the first data location is in the same DRAM row as the metadata location. Figure 4 , where the target data location is data row L of data page 408A corresponding to the first DRAM row in the physical domain. 0 To L Z-2 In the case of any data row in the memory controller 208 ( Figure 2 ) will not encounter a conflict because the target metadata location is in the same first DRAM row. Similarly, when the target data location is in the data row L corresponding to the data page 408B of the second DRAM row in the physical domain 0 To L Z-2 In the case of any data row in the memory controller 208 ( Figure 2 ) will not encounter a conflict because the target metadata location is in the same second DRAM row. However, in the case where the first data location in the first page is configured to store metadata (i.e., the first data location has been configured as a second metadata location), then the second data location (where the target data has been relocated) will not be in the same DRAM row as the second metadata location. Again referring to Figure 4 , in the case where the translated or relocated data location is in the supplemental DRAM data page 410, then the memory controller 208 encounters a conflict because the translated or relocated metadata location is the last row of one of the data pages 408A, 408B, etc. A conflict is less likely than a hit (i.e., no conflict) because in each DRAM page, only one of the Z rows (e.g., the last row) is relocated to the supplemental DRAM data page 410. On average, only one out of every Z requests to access data and associated metadata will conflict.

[0055] Note that the above method 600 ( Figure 6 ) involves a request to access data with associated metadata. Figure 6 8, but if a request is received to access data without any associated metadata, the location of the data in another memory page, such as page 508A or 508B described above, may be determined and accessed in a conventional manner. Figure 5 ). That is, method 600 may be conditionally executed depending on whether the requested data is of a type that has associated metadata or another type that does not have associated metadata.

[0056] refer to Figure 7 , the method 600( Figure 6 ) in block 608. That is, Figure 7 The data area 404 ( Figure 4 ) is converted into an address in the pseudo metadata area 406. In this example, the DRAM page size S P is 2kB, and the row size is S L In this example, data area 402 ( Figure 4 ) can be 32GB in size, including 16k in the above 2kB page, and the size of metadata area 404 can be 1GB. That is, the ratio of data to metadata of the data type involved in this example is 32:1.

[0057] In this example, the address length is 36 bits. The address bits can be referenced by their position number, from the least significant bit ("LSB") in position "0", or for brevity, "bit 0", to the most significant bit ("MSB") in position "35", or for brevity, "bit 35". The address can be organized in bit groups. The size or number of bits in the lowest bit group is 6 because the size of the bit group is the row size S. L ( Figure 4 ). The size or number of bits in the bit group is 5 because the size of this bit group is the log2 of the number of rows per page, which in this example is the number of 64B rows per 2kB page. The size or number of bits in the next bit group is 25 because the size of this bit group is the log2 of the size of the data area, which is 32GB.

[0058] exist Figure 8 , the data area 404 ( Figure 4 ) is converted to a physical address in the pseudo metadata area 406 of the storage area 402. The memory area 402 can be characterized by a data area start address ("DataStartAddr") and a data area end address ("DataEndAddr") of the data area 404 and a metadata area start address ("MdataStartAddr") and a metadata area end address ("MdataEndAddr") of the metadata area 406. "DataAddr" is a data page 408A, 408B ( Figure 8 The address of a 64B row in one of the above (not shown separately). Figure 8 408A, 408B, etc., may be referred to as "LastLineDataAddr". In the following equations, the arrow symbol "->" may be used to indicate that a result is obtained from the left side of the equation (i.e., the right side of the equation). In some equations, arrows may refer to operations.

[0059] In this example, according to block 604 ( Figure 6 ) can be determined by determining whether bits 6 to 10 of the data address are all 1, that is, whether DataAddr[10:6] = '11111'. If bits 6 to 10 of the data address are '11111', then the row corresponding to the requested or target data location is the last row of one of the data pages 408A, 408B, etc. If bits 6 to 10 of the data address are '11111', then the data area 404 ( Figure 4 ) can be converted into an address in the pseudo metadata area 406.

[0060] Continuing with this example, according to block 608 ( Figure 6 ) can be performed by first determining the address offset of the last line from the start address ("LastLineDataAddrOffset"). The address offset can be determined by subtracting the data area start address from LastLineDataAddr:

[0061] LastDataLineAddr-DataStartAddr->LastLineDataAddrOffset (Equation 1)

[0062] The address offset of the last line within a data page can be determined by LastLineDataAddrOffset:

[0063] LastLineDataAddrOffset->DataPageAddrOffset (Equation 2)

[0064] In the above equation 2, the arrow symbol ("->") means the operation of discarding address bits 6 to 10 (i.e., the row offset within the page). As a result, LastLineDataAddrOffset is the offset address of the data row that needs to be added to the pseudo metadata area start address MdataStartAddr. Then, the address of the relocated data row in the pseudo metadata area 406 ("NewDataAddr") can be determined by adding the address offset of the last row within the data page to the metadata area start address:

[0065] DataPageAddrOffset+MdataStartAddr->NewDataAddr (Equation 3)

[0066] exist Fig. 9 , an example of address values ​​in memory area 402 is shown. Because the value of DataAddr[10:6] is '11111', Equation 1 evaluates to: 0x8_000107C0–0xc000_0000->0x7_4001_07C0. Equation 2 evaluates to: 0x7_4001_07C0->0x3A00_0800. Equation 3 evaluates to: 0x3A00_0800+0x8000_0000->0xBA00_0800. Therefore, in this example, the address of the relocated data row (NewDataAddr) in the pseudo metadata area 406 is 0xBA00_0800.

[0067] refer to Fig.10 , the method 600( Figure 6 ) in block 612. That is, Fig.10An example of converting address 802 in dummy metadata area 406 to address 804 in data area 404 is illustrated. Because DataAddr, which is the requested or target data location, is the last row of one of data pages 408A, 408B, etc., in this example, block 612 ( Figure 6 ) can be determined as Fig.10 and Equation 4 to perform:

[0068] DataAddr->LastLineDataAddrOffset(MdataAddr) (Equation 4)

[0069] In the above equation 4, the arrow symbol ("->") means that address bits 6 to 10 are forced to '11111'. Fig. 9 For the example values ​​described, the address of the associated metadata (MdataAddr) in the data area 404 would be 0x8_0001_07FE.

[0070] The above method 600( Figure 6 ) can also be applied to DRAM 210 ( Figure 2 ) An embodiment organized in multiple bank groups ("BGs") where data is interleaved, such as LPDDR5 configured in "bank group mode" (also called "bank group mask"). Fig.11 As shown, an exemplary memory region 1100 (eg, in DRAM 210) may be organized in a virtual domain as groups of four virtual pages. Fig.11 is referred to as: "virtual page 0", "virtual page 1", "virtual page 2" and "virtual page 3". Figure 4 ) in which DRAM 210 is not organized in multiple BGs, in this embodiment, data can be addressed in the virtual domain by virtual page numbers and row numbers (not shown). For example, client 202 ( Figure 2 ) can request access to data by indicating a virtual page from virtual page 0 to virtual page 3 and the row number within the virtual page.

[0071] In the LPDDR5 addressing scheme, bits 14-13 address the bank, bits [10:8] address the BG, and bits [5:0] address the starting column in the DRAM array ( Fig.11 In the example shown, the DRAM can be configured as four BGs. Fig.11 Each bank group may include four banks. Each virtual page in the virtual page may be organized in rows. Fig.11Different types of shading distinguish memory bank groups from each other, such as Fig.11 Each virtual page and each row may have a size of, for example, 2 kB and 64 B, respectively, as in the previous embodiments described above (e.g., regarding Figure 4 ). Note that the four virtual pages, virtual page 0 - virtual page 3 are virtual or client domain memory areas, while the BG and memory bank are physical or DRAM domain structures.

[0072] Similar to the previous embodiment, each row of data has associated metadata. A virtual metadata page (not shown) may be configured (i.e., in the virtual domain) to store the associated metadata. Thus, a request to access data and associated metadata may address data in one of virtual pages 0-3 and address metadata in the virtual metadata page.

[0073] LPDDR5 bank group mode interleaves the banks (which may be referred to as "B0", "B1", "B2", and "B3") between bank groups. Fig.11 In the , each virtual page column represents a 64B access, addressed by bits [7:6]. Fig.11 The mode in which bank interleaving occurs, i.e., the mode in which consecutive accesses move from one bank to another across BGs, is not indicated, and as will be understood by those skilled in the art, and the mode can be any mode. The question of where to map or relocate metadata presents a challenge because the interleaving is inconsistent with the page size. For example, in an LPDDR5 bank group mode embodiment, where the virtual page size is 2kB, the bank groups are not interleaved at the same size boundary (e.g., 2kB) as the virtual page. The question of where to map or relocate metadata represents a challenge because even if the metadata is relocated to the last row in a virtual data page (similar to LPDDR5), there is no guarantee that the data and metadata will be placed in the same physical bank group page in DDR. When bank groups are interleaved at boundaries that are smaller than the page size, a single virtual page will be mapped to different physical pages in different bank groups.

[0074] Metadata can be stored by configuring one row per bank group (i.e., in the physical domain) (see Fig.11 ) to solve this challenge. Note that in Fig.11 In the example shown, the last row of the memory bank B3 in each of the memory bank groups BG0 , BG1 , BG2 , and BG3 is configured to store metadata.

[0075] exist Fig.12 In this paper, the above mapping is depicted in an alternative way ( Fig.11 ).exist Fig.12, an exemplary mapping between a virtual page 1200 (such as any of the virtual pages 0-3 described above) and a physical or DRAM storage location is indicated by a dashed arrow. Each mapped bank group portion 1202 has a similar structure to that described above with reference to FIG. Figure 2 The memory structure of DRAM 210 described above. That is, each of the memory banks B0-B3 includes an array of memory locations addressed by rows and columns. In each row of the array, a set of a predetermined number of memory locations or columns may correspond to a row (e.g., 64B) in the virtual domain.

[0076] The shaded blocks within the bank groups BG0-BG3 represent the mapping of all four virtual pages, Virtual Page 0-Virtual Page 3, to the physical (DRAM) domain. As a result of the bank group interleaving, in each bank group BG0-BG3, a portion of each virtual page, Virtual Page 0-Virtual Page 3, is mapped to a portion of one of the banks B0-B3, such as the circled portion 1202 of bank B0. It is worth noting that all metadata rows (see Fig.11 ) are mapped to the same DRAM page and are shown in Fig.12 Depicted as the fourth row from the top in bank B0 of each bank group BG0-BG3. However, in other examples, a metadata row may be mapped to any DRAM page.

[0077] exist Figure 11-12 In the example shown, a client request to access data in any row of virtual page 1200 except the last row of bank B3 in the same bank group as the requested data does not result in a conflict, and thus no relocation of the requested data address is performed. Note that although only one page in each of banks B0-B3 in a bank group may be opened at a time, pages in different banks may be opened simultaneously. For example, a page containing a metadata row (e.g., four rows) may be opened at the same time. Fig.12 In the example shown, a data access request may be open and a page containing the requested data row in B0, B1, or B2 may also be open. In the example shown, only a data access request directed to the last row of memory bank B3 will result in a conflict because that row is configured in the physical domain to store metadata rather than data. If it is determined that the data access request is directed to the last row of memory bank B3, a relocation of the requested data address is performed. Since there are 32 rows in each physical page of any memory bank in the example shown, the probability of a data access request becoming a conflict is 1 in 32. In the case where the data to metadata ratio is 1 / 32 (such as Fig.11), 31 of the total 32 accesses to the DRAM physical page have metadata located in the same physical page within the bank group. Any metadata access after the data access to that 31 row will not result in a page conflict, because the metadata access will result in a page hit. The data access to the last row of the page is relocated to a row in the pseudo metadata page (mapped to a different DRAM page), resulting in a page miss / conflict. Therefore, the probability of a page conflict is 1 / 32.

[0078] According to block 604 ( Figure 6 ) can be performed by first determining the address ("DataAddrSwapped") having the bank group mask bits (Addr[10:8]) swapped with the low order page bits (Addr[12:11]). If bits 6 to 10 of DataAddrSwapped are '11111", then the row corresponding to the requested or target data location is the last row of one of the virtual pages Virtual Page 0 - Virtual Page 3. If bits 6 to 10 of the data address are '11111", then according to block 608 ( Figure 6 ) can be performed by translating the requested data address to the last row of the last bank group (see Equation 1 above). The address offset of the last row within the page can be determined by LastLineDataAddrOffset (see Equation 2 above). The address of the relocated data row (NewDataAddr) can then be determined by adding the address offset of the last row within the data page to the metadata area start address (see Equation 3 above).

[0079] use Fig. 9 For the same exemplary address value 0x8_0001_07C0 shown, since the value of DataAddr[10:6] is not '11111' after swapping the bank group bits with the low-order page bits, it can be determined that the data address is not the last row of the bank group page. Therefore, data address relocation is not performed. The metadata address can be determined by swapping the bank group mask bits (Addr[10:8]) with the low-order page bits (Addr[12:11]) to form DataAddrSwapped. Then, the metadata address can be determined (see Equation 4). Using the DataAddr value of 0x8_001_07C0, the relocation address of the associated metadata (MdataAddr) will be 0x8_0001_1FD6.

[0080] In another example, the address value may be 0x0_F000_FFC0. Since the value of DataAddr[10:6] is '11111' after swapping the bank group bits with the low-order page bits, it can be determined that the data address is the last row of the bank group page. Figure 6 ) can be performed by first determining the address offset of the last row from the start address. The address offset can be determined by subtracting the data area start address from LastLineDataAddr (see Equation 1 above). Then, the address offset of the last row within the page can be determined (see Equation 2 above). The address of the relocated data row ("NewDataAddr") can be determined by adding the address offset of the last row within the data page to the metadata area start address (see Equation 3 above). In this example, the address value is 0x0_F000_FFC0, and Equation 1 evaluates to: 0x0_F000_FFC0–0xC000_0000->0x3000_FFC0. Equation 2 evaluates to: 0x3000_FFC0->0x180_07C0. Equation 3 evaluates to: 0x3000_FFC0+0x8000_0000->0x8180_FFC0. Therefore, the address of the relocated data line is 0x8180_FFC0.

[0081] The relocated metadata address can be determined by swapping the bank group mask bits (Addr[10:8]) with the low-order page bits (Addr[12:11]) to form DataAddrSwapped. The metadata address can then be determined (see Equation 4). Using the value of DataAddr of 0x0_F000_FFC0, the relocated address of the associated metadata (MdataAddr) will be 0xF000_FFFE.

[0082] like Fig.13 As shown, an exemplary embodiment of a system and method for metadata relocation in a DRAM system may be provided in a portable computing device (“PCD”) 1300. The PCD 1300 may be a system 100 ( Figure 1 ) or 200( Figure 2 ) example.

[0083] PCD 1300 may include SoC 1302. SoC 1302 may include CPU 1304, GPU 1306, DSP 1307, analog signal processor 1308, or other processors. CPU 1304 may include multiple cores, such as first core 1304A, second core 1304B, and so on, up to Nth core 1304N.

[0084] The PCD 1300 may include a display controller 1310 and a touch screen controller 1312 coupled to the CPU 1304. A touch screen display 1314 external to the SoC 1302 may be coupled to the display controller 1310 and the touch screen controller 1312. The PCD 1300 may also include a video decoder 1316 coupled to the CPU 1304. A video amplifier 1318 may be coupled to the video decoder 1316 and the touch screen display 1314. A video port 1320 may be coupled to the video amplifier 1318. A universal serial bus (“USB”) controller 1322 may also be coupled to the CPU 1304, and a USB port 1324 may be coupled to the USB controller 1322. A subscriber identity module (“SIM”) card 1326 may also be coupled to the CPU 1304.

[0085] One or more memories may be coupled to CPU 1304. The one or more memories may include volatile and non-volatile memories. Examples of volatile memories include static random access memory ("SRAM") 1328 and dynamic RAM ("DRAM") 1330 and 1331. Such memories may be external to SoC 1302 (such as DRAM 1330), or internal to SoC 1302 (such as DRAM 1331). A DRAM controller 1332 coupled to CPU 1304 may control writing data to and reading data from DRAM 1330 and DRAM 1331. In other embodiments, such a DRAM controller may be included in a processor, such as CPU 1304. DRAM controller 1332 may be a memory controller 208 ( Figure 2 ) or an example of a memory controller 208 combined with the coprocessor 206. Any one of the DRAM 1330 and the DRAM 1331 may be the DRAM 210 ( Figure 2 ) example.

[0086] The CPU 1304 may include a processor 1304 that may be coupled to the CPU 1304. A stereo codec 1334 may be coupled to the analog signal processor 1308. Additionally, an audio amplifier 1336 may be coupled to the stereo codec die 1334. First and second stereo speakers 1338 and 1340 may be coupled to the audio amplifier 1336, respectively. Additionally, a microphone amplifier 1342 may be coupled to the stereo codec die 1334, and a microphone 1344 may be coupled to the microphone amplifier 1342. A frequency modulation ("FM") radio tuner 1346 may be coupled to the stereo codec 1334. An FM antenna 1348 may be coupled to the FM radio tuner 1346. Additionally, a stereo headset 1350 may be coupled to the stereo codec 1334. Other devices that may be coupled to the CPU 1304 include one or more digital (e.g., CCD or CMOS) cameras 1352.

[0087] A modem or radio frequency transceiver 1354 can be coupled to the analog signal processor 1308. An RF switch 1356 can be coupled to the RF transceiver 1354 and the RF antenna 1358. Additionally, a keypad 1360, a mono headset 1362 with a microphone, and a vibrator device 1364 can be coupled to the analog signal processor 1308.

[0088] SoC 1302 may have one or more internal or on-chip thermal sensors 1370A and may be coupled to one or more external or off-chip thermal sensors 1370B. An analog-to-digital converter (“ADC”) controller 1372 may convert the voltage drop generated by thermal sensors 1370A and 1370B into a digital signal. A power supply 1374 and a power management integrated circuit (“PMIC”) 1376 may provide power to SoC 1302.

[0089] The firmware or software may be stored in any of the above-described memories, such as DRAM 1330 or 1331, SRAM 1328, etc., or may be stored in local memory that is directly accessible by the processor hardware on which the software or firmware is executed. Execution of such firmware or software may control aspects of any of the above-described methods or configure aspects of any of the above-described systems. Any such memory or other non-transitory storage medium having firmware or software stored therein in a computer-readable form for execution by processor hardware may be an example of a "computer-readable medium," as that term is understood in the patent dictionary.

[0090] For those skilled in the art to which the present invention belongs, alternative embodiments will become apparent without departing from its spirit and scope. Therefore, although selected aspects have been described in detail, it should be understood that various substitutions and changes can be made therein without departing from the spirit and scope of the present invention as defined by the appended claims.

[0091] Examples of implementations are described in the following numbered clauses:

[0092] 1. A method for metadata relocation in a dynamic random access memory (DRAM), comprising:

[0093] receiving a first request to access first data at a first data location in a first memory page of the DRAM and associated metadata in a second memory page of the DRAM;

[0094] determining whether a first data location in a first memory page is configured to store metadata;

[0095] If the first data location in the first memory page is not configured to store metadata, accessing first data at the first data location in the first memory page;

[0096] If the first data location in the first memory page is not configured to store metadata, determining a metadata location in the first memory page;

[0097] If the first data location in the first memory page is not configured to store metadata, accessing associated metadata at the metadata location in the first memory page;

[0098] If the first data location in the first memory page is configured to store metadata, determining a second data location in the second memory page;

[0099] If the first data location in the first memory page is configured to store metadata, accessing the first data at a second data location in the second memory page; and

[0100] If the first data location in the first memory page is configured to store metadata, the associated metadata at the first data location in the first memory page is accessed.

[0101] 2. A method according to clause 1, wherein if the first data location in the first memory page is not configured to store metadata, accessing the associated metadata at the metadata location in the first memory page occurs simultaneously with accessing the first data at the first data location in the first memory page.

[0102] 3. A method according to clause 2, wherein:

[0103] Accessing the associated metadata at the metadata location in the first memory page includes accessing a DRAM row; and

[0104] Accessing first data at a first data location in a first memory page includes accessing a DRAM row.

[0105] 4. The method according to clause 1, further comprising:

[0106] receiving a second request to access second data at a second data location in a third memory page, the second data having no associated metadata; and

[0107] Second data at a second data location in a third memory page is accessed.

[0108] 5. The method of clause 1, wherein determining whether the first data location in the first memory page is configured to store metadata comprises determining whether the first data location is a last row in the first memory page.

[0109] 6. The method of clause 1, wherein accessing the first data at the first data location in the first memory page comprises accessing a last row of the plurality of rows in the first memory page.

[0110] 7. A method according to clause 1, wherein accessing the associated metadata at the metadata location in the first memory page includes accessing a last row of multiple rows in the first memory page, the last row including metadata associated with data in all other rows in the first memory page.

[0111] 8. The method of clause 1, wherein the memory has two or more memory bank groups, each memory bank group including two or more memory banks, and the metadata location in the first memory page is a last row of a last memory bank in each memory bank group.

[0112] 9. A system for metadata relocation, comprising:

[0113] Dynamic random access memory (DRAM); and

[0114] The processor is configured as:

[0115] receiving a first request to access first data at a first data location in a first memory page and associated metadata in a second memory page;

[0116] determining whether a first data location in a first memory page is configured to store metadata;

[0117] If the first data location in the first memory page is not configured to store metadata, accessing first data at the first data location in the first memory page;

[0118] If the first data location in the first memory page is not configured to store metadata, determining a metadata location in the first memory page;

[0119] If the first data location in the first memory page is not configured to store metadata, accessing associated metadata at the metadata location in the first memory page;

[0120] If the first data location in the first memory page is configured to store metadata, determining a second data location in the second memory page;

[0121] If the first data location in the first memory page is configured to store metadata, accessing the first data at a second data location in the second memory page; and

[0122] If the first data location in the first memory page is configured to store metadata, the associated metadata at the first data location in the first memory page is accessed.

[0123] 10. A system according to clause 9, wherein the processor is configured to: if the first data location in the first memory page is not configured to store metadata, access the associated metadata at the metadata location in the first memory page simultaneously with accessing the first data at the first data location in the first memory page.

[0124] 11. A system according to clause 10, wherein:

[0125] The processor is configured to: access the associated metadata at the metadata location in the first memory page by accessing the DRAM row; and

[0126] The processor is configured to access first data at a first data location in a first memory page by accessing a DRAM row.

[0127] 12. A system according to clause 9, wherein the processor is further configured to: receive a second request for accessing second data at a second data location in a third memory page, the second data having no associated metadata; and access the second data at the second data location in the third memory page.

[0128] 13. The system of clause 9, wherein the processor is configured to determine whether the first data location in the first memory page is configured to store metadata by determining whether the first data location is a last row in the first memory page.

[0129] 14. The system of clause 9, wherein the processor is configured to access the first data at the first data location in the first memory page by accessing a last row of the plurality of rows in the first memory page.

[0130] 15. A system according to clause 9, wherein the processor is configured to: access the associated metadata at the metadata location in the first memory page by accessing a last row of multiple rows in the first memory page, the last row including metadata associated with data in all other rows in the first memory page.

[0131] 16. The system of clause 9, wherein the memory has two or more memory bank groups, each memory bank group including two or more memory banks, and the metadata location in the first memory page is a last row of a last memory bank in each memory bank group.

[0132] 17. A system for metadata relocation in a dynamic random access memory (DRAM), comprising:

[0133] means for receiving a first request to access first data at a first data location in a first memory page of the DRAM and associated metadata in a second memory page of the DRAM;

[0134] means for determining whether a first data location in a first memory page is configured to store metadata;

[0135] means for accessing first data at a first data location in a first memory page if the first data location in the first memory page is not configured to store metadata;

[0136] means for determining a metadata location in the first memory page if the first data location in the first memory page is not configured to store metadata;

[0137] means for accessing associated metadata at a metadata location in the first memory page if the first data location in the first memory page is not configured to store metadata;

[0138] means for determining a second data location in a second memory page if the first data location in the first memory page is configured to store metadata;

[0139] means for accessing first data at a second data location in a second memory page if the first data location in the first memory page is configured to store metadata; and

[0140] Means for accessing associated metadata at a first data location in a first memory page if the first data location in the first memory page is configured to store metadata.

[0141] 18. A system according to clause 17, wherein the component for accessing associated metadata at a metadata location in a first memory page includes: if the first data location in the first memory page is not configured to store metadata, the component for accessing the associated metadata is simultaneously with accessing the first data at the first data location in the first memory page.

[0142] 19. A system according to clause 18, wherein:

[0143] The means for accessing the associated metadata at the metadata location in the first memory page includes: means for accessing a DRAM row; and

[0144] Means for accessing first data at a first data location in a first memory page include means for accessing a DRAM row.

[0145] 20. The system according to clause 17, further comprising:

[0146] means for receiving a second request to access second data at a second data location in a third memory page, the second data having no associated metadata; and

[0147] Means for accessing second data at a second data location in a third memory page.

[0148] 21. The system of clause 17, wherein the means for determining whether the first data location in the first memory page is configured to store metadata comprises: means for determining whether the first data location is a last row in the first memory page.

[0149] 22. The system of clause 17, wherein means for accessing the first data at the first data location in the first memory page comprises means for accessing a last row of the plurality of rows in the first memory page.

[0150] 23. A system according to clause 17, wherein the means for accessing associated metadata at a metadata location in a first memory page includes: means for accessing a last row of multiple rows in the first memory page, the last row including metadata associated with data in all other rows in the first memory page.

[0151] 24. The system of clause 17, wherein the memory has two or more memory bank groups, each memory bank group including two or more memory banks, and the metadata location in the first memory page is a last row of a last memory bank in each memory bank group.

[0152] 25. A computer readable medium for metadata relocation in a dynamic random access memory (DRAM), comprising a non-transitory computer readable medium having instructions stored thereon in a computer executable form, the instructions, when executed by a processor, configure the processor to:

[0153] receiving a first request to access first data at a first data location in a first memory page and associated metadata in a second memory page;

[0154] determining whether a first data location in a first memory page is configured to store metadata;

[0155] If the first data location in the first memory page is not configured to store metadata, accessing first data at the first data location in the first memory page;

[0156] If the first data location in the first memory page is not configured to store metadata, determining a metadata location in the first memory page;

[0157] If the first data location in the first memory page is not configured to store metadata, accessing associated metadata at the metadata location in the first memory page;

[0158] If the first data location in the first memory page is configured to store metadata, determining a second data location in the second memory page;

[0159] If the first data location in the first memory page is configured to store metadata, accessing the first data at a second data location in the second memory page; and

[0160] If the first data location in the first memory page is configured to store metadata, the associated metadata at the first data location in the first memory page is accessed.

[0161] 26. A computer-readable medium as described in clause 25, wherein if the first data location in the first memory page is not configured to store metadata, the instructions configure the processor to access the associated metadata at the metadata location in the first memory page while accessing the first data at the first data location in the first memory page.

[0162] 27. The computer-readable medium of clause 26, wherein the instructions configure the processor to:

[0163] accessing the associated metadata at the metadata location in the first memory page by accessing the DRAM row; and

[0164] First data at a first data location in a first memory page is accessed by accessing a DRAM row.

[0165] 28. The computer-readable medium of clause 25, wherein the instructions further configure the processor to:

[0166] receiving a second request to access second data at a second data location in a third memory page, the second data having no associated metadata; and

[0167] Second data at a second data location in a third memory page is accessed.

[0168] 29. The computer-readable medium of clause 25, wherein the instructions configure the processor to determine whether the first data location in the first memory page is configured to store metadata by determining whether the first data location is a last row in the first memory page.

[0169] 30. The computer-readable medium of clause 25, wherein the instructions configure the processor to access the first data at the first data location in the first memory page by accessing a last row of the plurality of rows in the first memory page.

Claims

1. A method for metadata relocation in a dynamic random access memory (DRAM), comprising: receiving a first request to access first data at a first data location in a first memory page of the DRAM and associated metadata in a second memory page of the DRAM; determining whether the first data location in the first memory page is configured to store metadata; If the first data location in the first memory page is not configured to store metadata, accessing the first data at the first data location in the first memory page; If the first data location in the first memory page is not configured to store metadata, determining a metadata location in the first memory page; accessing the associated metadata at the metadata location in the first memory page if the first data location in the first memory page is not configured to store metadata; If the first data location in the first memory page is configured to store metadata, determining a second data location in the second memory page; accessing the first data at the second data location in the second memory page if the first data location in the first memory page is configured to store metadata; as well as If the first data location in the first memory page is configured to store metadata, the associated metadata at the first data location in the first memory page is accessed.

2. The method of claim 1 , wherein if the first data location in the first memory page is not configured to store metadata, accessing the associated metadata at the metadata location in the first memory page occurs simultaneously with accessing the first data at the first data location in the first memory page.

3. The method according to claim 2, wherein: accessing the associated metadata at the metadata location in the first memory page comprises accessing a DRAM row; and Accessing the first data at the first data location in the first memory page includes accessing the DRAM row.

4. The method according to claim 1, further comprising: receiving a second request to access second data at a second data location in a third memory page, the second data having no associated metadata; as well as The second data at the second data location in the third memory page is accessed.

5. The method of claim 1 , wherein determining whether the first data location in the first memory page is configured to store metadata comprises: A determination is made as to whether the first data location is a last row in the first memory page.

6. The method of claim 1 , wherein accessing the first data at the first data location in the first memory page comprises: A last row of the plurality of rows in the first memory page is accessed.

7. The method of claim 1 , wherein accessing the associated metadata at the metadata location in the first memory page comprises: A last row of the plurality of rows in the first memory page is accessed, the last row comprising metadata associated with data in all other rows in the first memory page.

8. The method of claim 1, wherein the memory has two or more memory bank groups, each memory bank group includes two or more memory banks, and the metadata location in the first memory page is the last row of the last memory bank in each memory bank group.

9. A system for metadata relocation, comprising: Dynamic random access memory (DRAM); as well as The processor is configured as: receiving a first request to access first data at a first data location in a first memory page and associated metadata in a second memory page; determining whether the first data location in the first memory page is configured to store metadata; If the first data location in the first memory page is not configured to store metadata, accessing the first data at the first data location in the first memory page; If the first data location in the first memory page is not configured to store metadata, determining a metadata location in the first memory page; accessing the associated metadata at the metadata location in the first memory page if the first data location in the first memory page is not configured to store metadata; If the first data location in the first memory page is configured to store metadata, determining a second data location in the second memory page; accessing the first data at the second data location in the second memory page if the first data location in the first memory page is configured to store metadata; as well as If the first data location in the first memory page is configured to store metadata, the associated metadata at the first data location in the first memory page is accessed.

10. The system of claim 9, wherein the processor is configured to: If the first data location in the first memory page is not configured to store metadata, the associated metadata at the metadata location in the first memory page is accessed concurrently with accessing the first data at the first data location in the first memory page.

11. The system of claim 10, wherein: The processor is configured to: access the associated metadata at the metadata location in the first memory page by accessing a DRAM row; and The processor is configured to access the first data at the first data location in the first memory page by accessing the DRAM row.

12. The system of claim 9, wherein the processor is further configured to: receiving a second request to access second data at a second data location in a third memory page, the second data having no associated metadata; and The second data at the second data location in the third memory page is accessed.

13. The system of claim 9, wherein the processor is configured to determine whether the first data location in the first memory page is configured to store metadata by determining whether the first data location is a last row in the first memory page.

14. The system of claim 9, wherein the processor is configured to access the first data at the first data location in the first memory page by accessing a last row of a plurality of rows in the first memory page.

15. A system according to claim 9, wherein the processor is configured to: access the associated metadata at the metadata location in the first memory page by accessing a last row of multiple rows in the first memory page, wherein the last row includes metadata associated with data in all other rows in the first memory page.

16. The system of claim 9, wherein the memory has two or more memory bank groups, each memory bank group includes two or more memory banks, and the metadata location in the first memory page is a last row of a last memory bank in each memory bank group.

17. A system for metadata relocation in a dynamic random access memory (DRAM), comprising: means for receiving a first request to access first data at a first data location in a first memory page of the DRAM and associated metadata in a second memory page of the DRAM; means for determining whether the first data location in the first memory page is configured to store metadata; means for accessing the first data at the first data location in the first memory page if the first data location in the first memory page is not configured to store metadata; means for determining a metadata location in the first memory page if the first data location in the first memory page is not configured to store metadata; means for accessing the associated metadata at the metadata location in the first memory page if the first data location in the first memory page is not configured to store metadata; means for determining a second data location in the second memory page if the first data location in the first memory page is configured to store metadata; means for accessing the first data at the second data location in the second memory page if the first data location in the first memory page is configured to store metadata; as well as Means for accessing the associated metadata at the first data location in the first memory page if the first data location in the first memory page is configured to store metadata.

18. The system of claim 17, wherein the means for accessing the associated metadata at the metadata location in the first memory page comprises: Means for accessing the associated metadata concurrently with accessing the first data at the first data location in the first memory page if the first data location in the first memory page is not configured to store metadata.

19. The system of claim 18, wherein: The means for accessing the associated metadata at the metadata location in the first memory page comprises: means for accessing a DRAM row; and The means for accessing the first data at the first data location in the first memory page comprises means for accessing the DRAM row.

20. The system of claim 17, further comprising: means for receiving a second request to access second data at a second data location in a third memory page, the second data having no associated metadata; as well as Means for accessing the second data at the second data location in the third memory page.

21. The system of claim 17, wherein the means for determining whether the first data location in the first memory page is configured to store metadata comprises: Means for determining whether the first data location is a last row in the first memory page.

22. The system of claim 17, wherein the means for accessing the first data at the first data location in the first memory page comprises: Means for accessing a last row of a plurality of rows in said first memory page.

23. The system of claim 17, wherein the means for accessing the associated metadata at the metadata location in the first memory page comprises: Means for accessing a last row of a plurality of rows in the first memory page, the last row comprising metadata associated with data in all other rows in the first memory page.

24. The system of claim 17, wherein the memory has two or more memory bank groups, each memory bank group includes two or more memory banks, and the metadata location in the first memory page is a last row of a last memory bank in each memory bank group.

25. A computer readable medium for metadata relocation in a dynamic random access memory (DRAM), comprising a non-transitory computer readable medium having instructions stored thereon in a computer executable form, the instructions, when executed by a processor, configure the processor to: receiving a first request to access first data at a first data location in a first memory page and associated metadata in a second memory page; determining whether the first data location in the first memory page is configured to store metadata; If the first data location in the first memory page is not configured to store metadata, accessing the first data at the first data location in the first memory page; If the first data location in the first memory page is not configured to store metadata, determining a metadata location in the first memory page; accessing the associated metadata at the metadata location in the first memory page if the first data location in the first memory page is not configured to store metadata; If the first data location in the first memory page is configured to store metadata, determining a second data location in the second memory page; accessing the first data at the second data location in the second memory page if the first data location in the first memory page is configured to store metadata; as well as If the first data location in the first memory page is configured to store metadata, the associated metadata at the first data location in the first memory page is accessed.

26. A computer-readable medium according to claim 25, wherein the instructions configure the processor to: if the first data location in the first memory page is not configured to store metadata, access the associated metadata at the metadata location in the first memory page simultaneously with accessing the first data at the first data location in the first memory page.

27. The computer-readable medium of claim 26, wherein the instructions configure the processor to: accessing the associated metadata at the metadata location in the first memory page by accessing a DRAM row; and The first data at the first data location in the first memory page is accessed by accessing the DRAM row.

28. The computer-readable medium of claim 25, wherein the instructions further configure the processor to: receiving a second request to access second data at a second data location in a third memory page, the second data having no associated metadata; and The second data at the second data location in the third memory page is accessed.

29. The computer-readable medium of claim 25, wherein the instructions configure the processor to determine whether the first data location in the first memory page is configured to store metadata by determining whether the first data location is a last row in the first memory page.

30. The computer-readable medium of claim 25, wherein the instructions configure the processor to access the first data at the first data location in the first memory page by accessing a last row of a plurality of rows in the first memory page.

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