An ultra-low temperature drift bandgap reference voltage segmented compensation circuit

Abstract

An ultra-low temperature drift bandgap reference voltage segmented compensation circuit includes a start-up circuit, a reference core circuit and a segmented compensation circuit, the start-up circuit provides a start-up signal for the reference core circuit, the start-up circuit provides a bias signal for the segmented compensation circuit, the reference core circuit has a voltage output port, the voltage output port is used to output a first-order bandgap reference voltage; the segmented compensation circuit has a high-temperature compensation port and a low-temperature compensation port, the segmented compensation circuit provides high-temperature compensation for the first-order bandgap reference voltage through the high-temperature compensation port, and the segmented compensation circuit provides low-temperature compensation for the first-order bandgap reference voltage through the low-temperature compensation port. A small number of compensation elements are used for high and low temperature segmented compensation, the compensation circuit structure is simple and clear, the design complexity is low and the design cost is low. Two nA-level currents are added on the basis of the first-order bandgap reference compensation circuit, thereby reducing the power consumption of the overall circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit power supply, in particular to a kind of ultra-low temperature drift band gap reference voltage segmented compensation circuit. BACKGROUND

[0002] Voltage reference is the basic core module in many integrated circuit chips, widely used in analog integrated circuits, requires that voltage reference can provide stable and efficient bias voltage or bias current.Band gap reference voltage source can usually provide a stable voltage independent of temperature, process and power supply voltage for circuit.

[0003] The traditional first-order compensation band gap reference circuit is as shown in Figure 1 Wherein resistance R1, resistance R2, resistance R3 use the same material, the emitter area of NPN type triode Q1 is 8 times the emitter area of NPN type triode Q2, by introducing an operational amplifier A1, so that X, Y point voltage is the same, then the output voltage V REF of band gap reference voltage source is

[0004] Where T is absolute temperature, k is Boltzmann constant, q is electron charge, V BE2 Is the base-emitter voltage of NPN type triode Q2, R2, R3 are the resistance values of resistance R2, resistance R3 respectively. The resistance values of resistance R2, resistance R3 can be adjusted to realize zero temperature characteristic reference voltage in a certain temperature range.

[0005] And because V BE2 Has temperature nonlinearity, the temperature coefficient of the traditional first-order temperature compensation reference voltage is usually 20-100ppm / ℃, so to further reduce the temperature coefficient, higher-order temperature compensation strategy needs to be introduced. SUMMARY

[0006] The present application aims to provide a segmented compensation circuit with simple circuit structure, low power consumption, temperature coefficient less than 0.6ppm / ℃ in the range of-55℃-125℃, reaching 0.5ppm / ℃.

[0007] An ultra-low temperature drift band gap reference voltage segmented compensation circuit is proposed, and the specific technical solutions are as follows:

[0008] An ultra-low temperature drift band gap reference voltage segmented compensation circuit, comprising a start-up circuit and a reference core circuit, characterized in that: it further comprises a segmented compensation circuit, the start-up circuit provides a start-up signal for the reference core circuit, the start-up circuit provides a bias signal for the segmented compensation circuit, the reference core circuit has a voltage output port, and the voltage output port is used to output a first-order band gap reference voltage.

[0009] The segmented compensation circuit has a high-temperature compensation port and a low-temperature compensation port, the segmented compensation circuit provides high-temperature compensation for the first-order bandgap reference voltage through the high-temperature compensation port, and the segmented compensation circuit provides low-temperature compensation for the first-order bandgap reference voltage through the low-temperature compensation port.

[0010] To better realize the present application, further:

[0011] The segmented compensation circuit comprises MOS tube M14, MOS tube M15, MOS tube M16, MOS tube M17, triode Q6 and triode Q7.

[0012] The source of the MOS tube M14 is connected with the power port VIN, the drain of the MOS tube M14 is connected with the source of the MOS tube M16, and the drain of the MOS tube M16 is the high-temperature compensation port.

[0013] The source of the MOS tube M15 is connected with the power port VIN, the gate of the MOS tube M15 is connected with the gate of the MOS tube M14, and the common terminal formed by the gates of the MOS tube M15 and the MOS tube M14 is connected with the common terminal formed by the gates of the MOS tube M9 and the MOS tube M10.

[0014] The drain of the MOS tube M15 is connected with the source of the MOS tube M17, the gate of the MOS tube M17 is connected with the gate of the MOS tube M16, the drain of the MOS tube M17 is connected with the collector of the triode Q6, the gate of the MOS tube M17 is connected with the drain, the emitter of the triode Q6 is connected with the ground terminal GND through the resistor R8, and the triode Q6 adopts a negative temperature characteristic material.

[0015] One branch of the base of the triode Q6 is connected with the drain of the MOS tube M13, the source of the MOS tube M13 is connected with the power terminal VIN, and the gate of the MOS tube M13 is connected with the common terminal formed by the gates of the MOS tube M15 and the MOS tube M14.

[0016] The other branch of the base of the triode Q6 is connected with the ground terminal GND through the resistor R7.

[0017] The collector of the triode Q7 is connected with the power terminal VIN, the emitter of the triode is connected with the ground terminal through the resistor R10, the base of the triode Q7 is connected with the first terminal of the resistor R9, and the second terminal of the resistor R9 is the low-temperature compensation port.

[0018] Further, the starting circuit comprises MOS tube M1, MOS tube M2, MOS tube M3, MOS tube M4, MOS tube M5, MOS tube M6, triode Q1 and resistor R1.

[0019] The drain of the MOS transistor M1 is connected to the drain of the MOS transistor M2, the gate of the MOS transistor M2 is connected to the gate of the MOS transistor M3, and the source of the MOS transistor M2 and the source of the MOS transistor M3 are both connected to the ground terminal GND;

[0020] The drain of the MOS transistor M3 is connected to the drain of the MOS transistor M4, the gate of the MOS transistor M4 is connected to the gate of the MOS transistor M5, and the source of the MOS transistor M4 and the source of the MOS transistor M5 are both connected to the power terminal VIN;

[0021] The drain of the MOS transistor M5 is connected to the drain of the MOS transistor M6, and the source of the MOS transistor M6 is connected to the collector of the transistor Q1, and the emitter of the transistor Q1 is connected to the ground terminal GND through the resistor R1;

[0022] The drain of the MOS transistor M5 is connected to the drain of the MOS transistor M6, and the source of the MOS transistor M6 is connected to the collector of the transistor Q1, and the emitter of the transistor Q1 is connected to the ground terminal GND through the resistor R1;

[0023] Further, the reference nuclear circuit includes MOS transistors M7, M8, M9, M10, M11, M12, transistors Q2, Q3, Q4, Q5, resistors R2, R3, R4, R5, R6 and R11;

[0024] The gate of the MOS transistor M9 is connected to the gate of the MOS transistor M10, and the source of the MOS transistor M9 and the source of the MOS transistor M10 are connected to the power terminal VIN;

[0025] The drain of the MOS transistor M9 is connected to the drain of the MOS transistor M7, the source of the MOS transistor M7 is connected to the collector of the transistor Q3, and the emitter of the transistor Q3 is connected to the first end of the resistor R2, and the second end of the resistor R2 is connected to the ground terminal GND;

[0026] The drain of the MOS transistor M10 is connected to the drain of the MOS transistor M8, the source of the MOS transistor M8 is connected to the collector of the transistor Q4, the gate of the MOS transistor M8 is connected to the gate of the MOS transistor M7, and the emitter of the transistor Q4 is connected to the first end of the resistor R2;

[0027] The common terminal between the drain of the MOS transistor M10 and the drain of the MOS transistor M8 is connected to the gate of the MOS transistor M12, the source of the MOS transistor M12 is connected to the power terminal VIN, the drain of the MOS transistor M12 is connected to the collector of the transistor Q5 in turn through the resistors R3, R4, R5 and R6, and the emitter of the transistor Q5 is connected to the ground terminal GND through the resistor R11;

[0028] The collector of the triode Q2 is connected between the source of the MOS tube M7 and the collector of the triode Q3, the base of the triode Q2 is connected with the emitter of the triode Q2, and the emitter of the triode Q2 is connected with the common terminal of the resistor R5 and the resistor R6;

[0029] The common terminal of the resistor R3 and the resistor R4 is an output port, and the output port outputs a reference voltage Vref.

[0030] The beneficial effects of the present application are:

[0031] The present application adopts a simple segmented compensation circuit, only introduces nA level compensation current, thereby realizing a bandgap reference voltage with low temperature drift and low power consumption, the temperature drift is less than 0.6ppm / ℃ in the range of-55℃-125℃, and the static power supply current is only 10uA.

[0032] The difference between the base-emitter voltages of the two NPN triodes in the first-order bandgap reference voltage source circuit BE The first-order temperature compensation current I generated on the resistor R6 PTAT The first-order temperature compensation current I PTAT The first-order temperature compensation reference voltage generated on the resistor R4, the resistor R5 and the resistor R6 is superimposed with the base-emitter voltage of the triode Q5 to generate a first-order compensation bandgap reference voltage.

[0033] The low-temperature compensation circuit is arranged to generate a low-temperature compensation voltage on the resistor R5 and the resistor R6 by a low-temperature compensation current.

[0034] The high-temperature compensation circuit is arranged to generate a voltage increasing with temperature on the resistor R12 by a high-temperature compensation current, thereby realizing high-order compensation in the high-temperature section. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 It is a traditional first-order compensation bandgap reference circuit;

[0036] Figure 2 It is a first-order temperature compensation bandgap reference simulation result graph;

[0037] Figure 3 It is a circuit schematic diagram of the present application;

[0038] Figure 4 It is a temperature compensation current simulation result graph of the embodiment of the present application;

[0039] Figure 5 It is a segmented compensation reference voltage simulation result graph of the embodiment of the present application. DETAILED DESCRIPTION

[0040] Clearly, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present application.

[0041] As shown in Figure 3

[0042] A super-low-temperature drift bandgap reference voltage segmented compensation circuit, comprising a starting circuit, a reference core circuit and a segmented compensation circuit, the starting circuit provides a starting signal for the reference core circuit, the starting circuit provides a bias signal for the segmented compensation circuit, the reference core circuit has a voltage output port, and the voltage output port is used to output a first-order bandgap reference voltage;

[0043] The segmented compensation circuit has a high-temperature compensation port and a low-temperature compensation port, the segmented compensation circuit provides high-temperature compensation for the first-order bandgap reference voltage through the high-temperature compensation port, and the segmented compensation circuit provides low-temperature compensation for the first-order bandgap reference voltage through the low-temperature compensation port.

[0044] The specific circuit structure of the starting circuit is described as follows,

[0045] The starting circuit comprises MOS tubes M1, M2, M3, M4, M5, M6, a triode Q1 and a resistor R1.

[0046] The drain of the MOS tube M1 is connected with the drain of the MOS tube M2, the gate of the MOS tube M2 is connected with the gate of the MOS tube M3, and the source of the MOS tube M2 and the source of the MOS tube M3 are both connected with a ground terminal GND.

[0047] The drain of the MOS tube M3 is connected with the drain of the MOS tube M4, the gate of the MOS tube M4 is connected with the gate of the MOS tube M5, and the source of the MOS tube M4 and the source of the MOS tube M5 are both connected with a power terminal VIN.

[0048] The drain of the MOS tube M5 is connected with the drain of the MOS tube M6, and the source of the MOS tube M6 is connected with the collector of the triode Q1, and the emitter of the triode Q1 is connected with the ground terminal GND through the resistor R1.

[0049] The drain of the MOS tube M5 is connected with the drain of the MOS tube M6, and the source of the MOS tube M6 is connected with the collector of the triode Q1, and the emitter of the triode Q1 is connected with the ground terminal GND through the resistor R1.

[0050] The specific circuit structure of the reference core circuit is described as follows,

[0051] ​The reference core circuit comprises MOS transistor M7, MOS transistor M8, MOS transistor M9, MOS transistor M10, MOS transistor M11, MOS transistor M12, triode Q2, triode Q3, triode Q4, triode Q5, resistor R2, resistor R3, resistor R4, resistor R5, resistor R6 and resistor R11.

[0052] The gate of MOS transistor M9 is connected with the gate of MOS transistor M10, and the source of MOS transistor M9 and MOS transistor M10 is connected with power port VIN.

[0053] The drain of MOS transistor M9 is connected with the drain of MOS transistor M7, the source of MOS transistor M7 is connected with the collector of triode Q3, the emitter of triode Q3 is connected with the first end of resistor R2, and the second end of the resistor R2 is connected with ground terminal GND.

[0054] The drain of MOS transistor M10 is connected with the drain of MOS transistor M8, the source of MOS transistor M8 is connected with the collector of triode Q4, the gate of MOS transistor M8 is connected with the gate of MOS transistor M7, and the emitter of triode Q4 is connected with the first end of resistor R2.

[0055] The common terminal between the drain of MOS transistor M10 and the drain of MOS transistor M8 is connected with the gate of MOS transistor M12, the source of MOS transistor M12 is connected with power port VIN, the drain of MOS transistor M12 is connected with the collector of triode Q5 in sequence through resistor R3, resistor R4, resistor R5 and resistor R6, and the emitter of triode Q5 is connected with ground terminal GND through resistor R11.

[0056] The collector of triode Q2 is connected between the source of MOS transistor M7 and the collector of triode Q3, the base of triode Q2 is connected with the emitter of triode Q2, and the emitter of triode Q2 is connected with the common terminal of resistor R5 and resistor R6. The common terminal of resistor R3 and resistor R4 is output port, and the output port outputs reference voltage Vref.

[0057] In the reference core circuit, MOS transistor M9 and MOS transistor M10 are P-type MOS transistors with the same channel width-length ratio, MOS transistor M7 and MOS transistor M8 are N-type MOS transistors with the same channel width-length ratio, triode Q3 and triode Q4 are both NPN type triodes, and the emitter area of triode Q4 is 8 times of the emitter area of triode Q3. Resistor R2, resistor R3, resistor R4, resistor R5 and resistor R6 have the same structure.

[0058] In which, the first-order temperature-compensated bandgap reference voltage V REF1 is,

[0059] wherein k is the Boltzmann constant, T is the absolute temperature, q is the electronic charge, V BE5 is the base-emitter voltage of the NPN transistor Q5, R4-R6 are the resistance values of the resistors R4-R6, and T is the room temperature. r A first-order bandgap reference voltage V REF1 .

[0060] The segmented compensation circuit comprises MOS tubes M14, M15, M16, M17, a transistor Q6 and a transistor Q7.

[0061] The source of the MOS tube M14 is connected to the power port VIN, the drain of the MOS tube M14 is connected to the source of the MOS tube M16, the drain of the MOS tube M16 is the high-temperature compensation port, and the drain of the MOS tube M16 is connected to the emitter of the transistor Q5. The MOS tube M16 provides a high-temperature compensation signal to the transistor Q5.

[0062] The source of the MOS tube M15 is connected to the power port VIN, and the gate of the MOS tube M15 is connected to the gate of the MOS tube M14. The common terminal formed by the gates of the MOS tube M15 and the MOS tube M14 is connected to the common terminal formed by the gates of the MOS tube M9 and the MOS tube M10.

[0063] The drain of the MOS tube M15 is connected to the source of the MOS tube M17, the gate of the MOS tube M17 is connected to the gate of the MOS tube M16, the drain of the MOS tube M17 is connected to the collector of the transistor Q6, the gate of the MOS tube M17 is connected to the drain of the MOS tube M17, the emitter of the transistor Q6 is connected to the ground terminal GND through the resistor R8, and the transistor Q6 adopts a negative temperature characteristic material.

[0064] The base of the transistor Q6 is connected to the drain of the MOS tube M13, the source of the MOS tube M13 is connected to the power terminal VIN, and the gate of the MOS tube M13 is connected to the common terminal formed by the gates of the MOS tube M15 and the MOS tube M14.

[0065] The other branch of the base of the transistor Q6 is connected to the ground terminal GND through the resistor R7.

[0066] The collector of the transistor Q7 is connected to the power terminal VIN, the emitter of the transistor is connected to the ground terminal through the resistor R10, the base of the transistor Q7 is connected to the first terminal of the resistor R9, the second terminal of the resistor R9 is the low-temperature compensation port, the low-temperature compensation port provides a high-temperature compensation signal to the transistor Q5, and the base of the transistor Q7 is further connected to the ground terminal GND through the capacitor C1.

[0067] The working principle of the application is as follows:

[0068] Bandgap reference output voltage V REF At one end of resistor R5, the ratio of the emitter area of transistor Q3 to that of transistor Q4 is 8:1, so that:

[0069]

[0070] The simulation diagram of the first-order bandgap reference output voltage is shown in Figure 2 The output voltage has zero temperature characteristic only at T r = 25℃, and the output voltage decreases when the temperature is lower than T r or higher than T r , and the overall curve is in the shape of a quadratic function.

[0071] As shown in Figure 3 , a segmented compensation circuit is introduced in the embodiment of the present application, when the temperature is lower than T r1 , the collector current of N-transistor Q7 is:

[0072]

[0073] Therefore, the base current of Q7 can be expressed as:

[0074]

[0075] Where β T is the current gain of transistor Q7, which is a temperature-dependent variable, and its formula is:

[0076]

[0077] Where β ∞ is the maximum common-emitter current gain, which is independent of temperature, and ΔE g is the narrowing factor of the bandgap of the emitter, so the expression of the bandgap reference output voltage after low-temperature compensation is:

[0078]

[0079] As can be seen from formula (5), the lower the temperature is when the temperature is lower than T Tr1 , the larger the exponential term is, and the higher the temperature is, the smaller the exponential term is, that is, when the temperature is lower than a certain value, a voltage that increases with the decrease of temperature is added to the first-order bandgap reference, so that the output voltage V REF is curved upward at low temperature, achieving the effect of exponential compensation.

[0080] When the temperature is lower than T r2 , since the base-emitter voltage V BE6 of transistor Q6 is negative temperature characteristic, V BE6When the temperature is higher than a certain value, the collector current I C6 of the triode Q6 gradually increases with the decrease of V BE6 , and the expression of I C6 is:

[0081]

[0082] Therefore, a current gradually increasing with the increase of temperature can be generated at high temperature, and then the collector current of the triode Q6 is mirrored to the emitter of the triode Q5 through the MOS tube M16 and the MOS tube M17, and an additional voltage is generated on the resistor R11, so that the expression of the reference voltage after high-temperature compensation is:

[0083]

[0084] As can be seen from the formula (7), when the temperature is higher than a certain value, an additional current gradually increasing with the increase of temperature is generated, and a voltage gradually increasing with the increase of temperature is generated on the resistor R11, so that the output voltage V REF is curved on the curve at high temperature, and the effect of second-order compensation is achieved.

[0085] Figure 4 The simulation experiment results of the temperature compensation current I C5 and I B7 in the bandgap reference circuit of the embodiment of the present application are shown in Figs. 2 and 3, respectively. Figure 4 As can be seen from the simulation experiment results, I C5 is 0nA at normal temperature and 50nA at 125℃, I B7 gradually increases with the decrease of temperature at low temperature, and the sum of the two added currents is only 100nA, thereby reducing the power consumption of the overall circuit.

[0086] Figure 5 The simulation experiment results of the output voltage varying with temperature in the bandgap reference circuit of the embodiment of the present application are shown in Fig. 4. Figure 5 As can be seen from the simulation experiment results, the output voltage presents the characteristics after high-order compensation, and the temperature drift of the output voltage is effectively reduced. The simulation results show that the temperature drift of the output voltage is less than 0.6ppm / ℃ in the temperature range of-55℃-125℃.

[0087] It will be obvious to a person skilled in the art that the application is not limited to the details of the foregoing exemplary embodiments and can be implemented in other concrete forms without departing from the spirit or essential characteristics of the application. The embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. No reference signs in the claims should be considered as limiting the scope of the claims to the identity of the reference signs therein.

[0088] Furthermore, it should be understood that although the description is made on the basis of the embodiments, not every embodiment contains only one independent technical solution, and the description of the specification is only for the sake of clarity, and those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that those skilled in the art can understand.

Claims

1. An ultra-low temperature drift bandgap reference voltage segmented compensation circuit comprising a start-up circuit and a reference core circuit, characterized in that: The starting circuit provides a starting signal for the reference core circuit, and provides a bias signal for the segmented compensation circuit; the reference core circuit has a voltage output port for outputting a first-order bandgap reference voltage; The segmented compensation circuit has a high-temperature compensation port and a low-temperature compensation port; the segmented compensation circuit provides high-temperature compensation for the first-order bandgap reference voltage through the high-temperature compensation port; and the segmented compensation circuit provides low-temperature compensation for the first-order bandgap reference voltage through the low-temperature compensation port; The segmented compensation circuit comprises MOS tubes M14, M15, M16, M17, a triode Q6 and a triode Q7; The source of the MOS tube M14 is connected with a power supply port VIN, and the drain of the MOS tube M14 is connected with the source of the MOS tube M16, and the drain of the MOS tube M16 is a high-temperature compensation port; The source of the MOS tube M15 is connected with the power supply port VIN, and the gate of the MOS tube M15 is connected with the gate of the MOS tube M14; The common terminal formed by the gates of the MOS tube M15 and the MOS tube M14 is connected with the common terminal formed by the gates of the MOS tube M9 and the MOS tube M10 in the reference core circuit; The drain of the MOS tube M15 is connected with the source of the MOS tube M17, the gate of the MOS tube M17 is connected with the gate of the MOS tube M16, the drain of the MOS tube M17 is connected with the collector of the triode Q6, the gate of the MOS tube M17 is connected with the drain of the MOS tube M17, the emitter of the triode Q6 is connected with a ground terminal GND through a resistor R8, and the triode Q6 adopts a negative temperature characteristic material; One branch of the base of the triode Q6 is connected with the drain of the MOS tube M13, the source of the MOS tube M13 is connected with the power supply port VIN, and the gate of the MOS tube M13 is connected on the common terminal formed by the gates of the MOS tube M15 and the MOS tube M14; The other branch of the base of the triode Q6 is connected with the ground terminal GND through a resistor R7; The collector of the triode Q7 is connected with the power supply port VIN, the emitter of the triode Q7 is connected with the ground terminal GND through a resistor R10, the base of the triode Q7 is connected with the first end of a resistor R9, and the second end of the resistor R9 is a low-temperature compensation port.

2. The segmented compensation circuit of the ultra-low temperature drift bandgap reference voltage according to claim 1, wherein: The starting circuit comprises MOS tubes M1, M2, M3, M4, M5, M6, a triode Q1 and a resistor R1; The drain of the MOS tube M1 is connected with the drain of the MOS tube M2, the gate of the MOS tube M2 is connected with the gate of the MOS tube M3, and the source of the MOS tube M2 and the source of the MOS tube M3 are both connected with a ground terminal GND; The drain of the MOS tube M3 is connected with the drain of the MOS tube M4, the gate of the MOS tube M4 is connected with the gate of the MOS tube M5, and the source of the MOS tube M4 and the source of the MOS tube M5 are both connected with a power supply port VIN; The drain of the MOS tube M3 is connected with the drain of the MOS tube M4, the gate of the MOS tube M4 is connected with the gate of the MOS tube M5, and the source of the MOS tube M4 and the source of the MOS tube M5 are both connected with a power supply port VIN; The drain of the MOS tube M5 is connected with the drain of the MOS tube M6, the source of the MOS tube M6 is connected with the collector of the transistor Q1, the emitter of the transistor Q1 is connected with the ground terminal GND through the resistor R1; The drain of the MOS tube M5 is connected with the drain of the MOS tube M6, the source of the MOS tube M6 is connected with the collector of the transistor Q1, the emitter of the transistor Q1 is connected with the ground terminal GND through the resistor R1; 3. The ultra-low temperature drift bandgap reference voltage segmented compensation circuit according to claim 2, characterized in that: The reference core circuit comprises the MOS tube M7, the MOS tube M8, the MOS tube M9, the MOS tube M10, the MOS tube M11, the MOS tube M12, the transistor Q2, the transistor Q3, the transistor Q4, the transistor Q5, the resistor R2, the resistor R3, the resistor R4, the resistor R5, the resistor R6 and the resistor R11; The gate of the MOS tube M9 is connected with the gate of the MOS tube M10, the source of the MOS tube M9 and the source of the MOS tube M10 are connected with the power terminal VIN; The drain of the MOS tube M9 is connected with the drain of the MOS tube M7, the source of the MOS tube M7 is connected with the collector of the transistor Q3, the emitter of the transistor Q3 is connected with the first terminal of the resistor R2, the second terminal of the resistor R2 is connected with the ground terminal GND; The drain of the MOS tube M10 is connected with the drain of the MOS tube M8, the source of the MOS tube M8 is connected with the collector of the transistor Q4, the gate of the MOS tube M8 is connected with the gate of the MOS tube M7, the emitter of the transistor Q4 is connected with the first terminal of the resistor R2; The common terminal between the drain of the MOS tube M10 and the drain of the MOS tube M8 is connected with the gate of the MOS tube M12, the source of the MOS tube M12 is connected with the power terminal VIN, the drain of the MOS tube M12 is connected with the collector of the transistor Q5 in sequence through the resistor R3, the resistor R4, the resistor R5 and the resistor R6, the emitter of the transistor Q5 is connected with the ground terminal GND through the resistor R11; The collector of the transistor Q2 is connected between the source of the MOS tube M7 and the collector of the transistor Q3, the base of the transistor Q2 is connected with the emitter of the transistor Q2, the emitter of the transistor Q2 is connected with the common terminal of the resistor R5 and the resistor R6; The common terminal of the resistor R3 and the resistor R4 is the output terminal, the output terminal outputs the reference voltage Vref.

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