Power converter control module

Abstract

A power converter control module is disclosed. A control module for controlling a switching buck-boost converter includes: an inductor, a capacitor, a first top switch and a second top switch, a first bottom switch and a second bottom switch, and a diode coupled to the second top switch. The control module controls the switching buck-boost converter to alternate between a first time period and a second time period. In the first time period, the second top switch is open and a cycle of charging and discharging the inductor is performed. During this cycle, the inductor is also energized by current flowing through the diode and charging the capacitor. In the second time period, the first and second top switches are open, and the first and second bottom switches are closed, causing the current in the inductor to recirculate and the capacitor to be discharged by current flowing in the load.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Italian Patent Application No. 102022000004283, filed on 7 March 2022, which is incorporated herein by reference. Technical Field

[0003] This invention relates generally to electronic circuits, and more specifically to a power converter control module. Background Technology

[0004] As is known, there are currently available so-called DC-DC converters, also known as switching converters, which are capable of generating an output voltage from a DC input voltage. This output voltage is of DC type and can be higher or lower than the input voltage. Furthermore, the output voltage can be applied to a load.

[0005] To detect faults, systems for detecting overcurrent are known to be used to activate load protection mechanisms. Specifically, it is known to measure the voltage across a shunt resistor with low resistance (only a few milliohms) to detect overcurrent conditions. However, in many applications, switching converters can remain in a low-power operating mode known as low-power mode, where the converter provides a low regulation current. In this low-power mode, detecting overcurrent conditions requires detecting an extremely low voltage across the shunt resistor, which can be difficult to measure accurately. Summary of the Invention

[0006] According to one embodiment, a control module is used to control a switching buck-boost converter, the switching buck-boost converter including: an input node configured to receive an input voltage; an output node configured to be coupled to a load; an inductor; a capacitor; a first top switch; a second top switch; a first bottom switch; and a second bottom switch, the first top switch and the first bottom switch being connected in series to form a first internal node, the second top switch and the second bottom switch being connected in series to form a second internal node, the inductor being coupled to the first internal node and the second internal node, the first top switch and the second top switch being coupled to the input node and the output node, respectively, and the capacitor being coupled to the output node. The switching buck-boost converter also includes a diode coupled to the on terminal of the second top switch and configured to prevent the capacitor from discharging through the second internal node when the second top switch is off. The control module includes a controller, acquisition circuitry, and overcurrent detection circuitry. The controller is configured to operate in a low-power operating mode when coupled to the switching buck-boost converter, during which the controller causes the switching buck-boost converter to alternate between a first time period and a second time period. During a first time period, the controller is configured to open the second top switch and control the first top switch, first bottom switch, and second bottom switch to perform a charging and discharging cycle of the inductor. During the charging and discharging cycle, the inductor is energized by current flowing through it, wherein the current flows through the diode during each discharge cycle of the inductor and charges the capacitor in such a way that the voltage at the output node increases from a low threshold to a high threshold. During a second time period, the controller is configured to open the first top switch and the second top switch and close the first bottom switch and the second bottom switch. During this period, the current in the inductor recirculates through the first bottom switch and the second bottom switch, and the capacitor is discharged by the current flowing in the load in such a way that the voltage at the output node decreases from a high threshold to a low threshold. An acquisition circuit is configured to generate a digital signal indicating the duration of the second time period; an overcurrent detection circuit is configured to receive the digital signal and includes a first comparison circuit configured to compare the duration of each second time period with a first limit duration and indicate the occurrence of an overcurrent when the duration of the second time period is shorter than the first limit duration.

[0007] According to another embodiment, a method for controlling a switching buck-boost converter includes: an input node configured to receive an input voltage; an output node configured to be coupled to a load; an inductor; a capacitor; a first top switch; a second top switch; a first bottom switch; and a second bottom switch, the first top switch and the first bottom switch being connected in series to form a first internal node, the second top switch and the second bottom switch being connected in series to form a second internal node, the inductor being coupled to the first internal node and the second internal node, the first top switch and the second top switch being coupled to the input node and the output node, respectively, and the capacitor being coupled to the output node. The switching buck-boost converter further includes a diode coupled to the on terminal of the second top switch and configured to prevent the capacitor from discharging through the second internal node when the second top switch is off. The method includes operating the switching buck-boost converter in a low-power operating mode including alternating first and second time periods. Operating the switching buck-boost converter in a low-power operating mode during a first time period includes: opening a second top switch; controlling a first top switch, a first bottom switch, and a second bottom switch to perform a cycle of charging and discharging an inductor, during which current flows through the inductor, wherein the current, during each discharge cycle of the inductor, flows through a diode and charges a capacitor in such a way that the voltage at the output node increases from a low threshold to a high threshold; and operating the switching buck-boost converter in a low-power operating mode during a second time period includes: opening the first top switch and the second top switch; closing the first bottom switch and the second bottom switch, during which current in the inductor recirculates through the first bottom switch and the second bottom switch, and the capacitor is discharged by current flowing in the load in such a way that the voltage at the output node decreases from a high threshold to a low threshold. The method further includes: generating a digital signal indicating the duration of the second time period; and based on the digital signal, comparing the duration of each second time period with a first limit duration, and indicating the occurrence of an overcurrent when the duration of the second time period is shorter than the first limit duration.

[0008] According to another embodiment, a switch-mode power supply includes: a power controller configured to be coupled to a power circuit including a plurality of switches coupled between a power input node and a power output node, and an inductor coupled to the plurality of switches. The power controller is configured to operate the power circuit in a low-power mode including alternating first and second time periods. The power controller is configured to: apply an active switching signal to at least one of the plurality of switches during the first time period when the output voltage of the power output node transitions from a first predetermined voltage threshold to a second predetermined voltage threshold, and apply a static switching signal to each of the plurality of switches during the second time period when the output voltage of the power output node transitions from the second predetermined voltage threshold to the first predetermined voltage threshold. The switch-mode power supply further includes: a voltage measurement circuit configured to be coupled to the power output node; and a first overcurrent measurement circuit coupled to the voltage measurement circuit and configured to indicate a first overcurrent condition when the duration of the first time period is less than the first threshold, or when the duration of the second time period is greater than the second threshold. Attached Figure Description

[0009] To better understand the invention, preferred embodiments are now described by way of non-limiting example with reference to the accompanying drawings, in which:

[0010] Figure 1 The circuit diagram of the converter is shown;

[0011] Figure 2A and Figure 2B It shows Figure 1 The circuit diagram shown is of the converter operating in the first normal operating mode.

[0012] Figure 3A and Figure 3B It shows Figure 1 The circuit diagram shown is for the converter when it is operating in the second normal operating mode.

[0013] Figure 4A and Figure 4B It shows Figure 1 The circuit diagram shown is of the converter operating in the first low-power operation mode.

[0014] Figure 4C It shows Figure 1 The circuit diagram shown is for the converter when it operates in another low-power operating mode.

[0015] Figure 5 , Figure 6 , Figure 11 and Figure 13 A time graph of battery power is shown;

[0016] Figure 7A block diagram of the circuit implemented by this control module is shown;

[0017] Figure 8 , Figure 10 and Figure 12 The timing diagram of the signals generated in this control module is shown;

[0018] Figure 9 It shows Figure 7 A block diagram of a portion of the circuit shown; and

[0019] Figure 14A and Figure 14B It shows Figure 1 The circuit diagram shown is for the converter when operating in the second low-power operation mode. Specific Implementation

[0020] Various embodiments relate to modules for controlling a switching buck-boost converter with overcurrent detection and corresponding methods for controlling the buck-boost converter.

[0021] Figure 1 A converter 1 comprising four NMOS transistors is shown, which are, for example, power MOSFETs formed in a corresponding integrated circuit, and are referred to below as first top transistor 2 and second top transistor 4, and first bottom transistor 6 and second bottom transistor 8, respectively.

[0022] The source terminals of the first top transistor 2 and the second top transistor 4 are respectively connected to the drain terminals of the first bottom transistor 6 and the second bottom transistor 8 to form the first internal node N1 and the second internal node N2, respectively. The source terminals of the first bottom transistor 6 and the second bottom transistor 8 are connected to the first terminal of the resistor 10, and the second terminal of the resistor 10 is grounded. An inductor 12 is also present, with its terminals connected to the first internal node N1 and the second internal node N2, respectively.

[0023] The drain terminal of the first top transistor 2 forms the input node N. IN It is designed to receive DC type input voltage V IN The drain terminal of the second top transistor 4 is connected to the first terminal of the shunt resistor 14, and the second terminal of the shunt resistor 14 forms the output node N. OUT Load 15 is connected to this output node N. OUT In fact, load 15 is connected to output node N. OUT Between and ground. Additionally, capacitor C OUT Connected in parallel with load 15 at output node N OUT Between and ground.

[0024] The first and second terminals of the shunt resistor 14 and the output node N OUT The gate terminals of the first top transistor 2 and the second top transistor 4, as well as the first bottom transistor 6 and the second bottom transistor 8, are connected to the control circuit 17. The drive circuit 19 is also connected to the control circuit 17. The control circuit 17 and the drive circuit 19 constitute the control module 20 of the converter 1.

[0025] Control module 20 can control the first top transistor 2 and the second top transistor 4, as well as the first bottom transistor 6 and the second bottom transistor 8, so that converter 1 operates in a first operating mode, such as... Figure 2A and Figure 2B As shown schematically.

[0026] Specifically, in the first operating mode, the second top transistor 4 is always on to couple the second internal node N2 to the first terminal of the shunt resistor 14. The second bottom transistor 8 is switched off to decouple the second internal node N2 from the resistor 10, and thus from ground.

[0027] Conversely, the first top transistor 2 and the first bottom transistor 6 are controlled alternately by the control module 20. Specifically, for each time period T, also known as the switching cycle T, the first top transistor 2... ON The internal transistor remains on, while the first bottom transistor 6 is off, as shown. Figure 2A As shown. In this way, the current I increases linearly with time. L The current flows in inductor 12; in other words, inductor 12 is gradually charged. Current I L It still flows in the shunt resistor 14 and partially affects the output capacitor C. OUT It charges, and partially charges the load 15. Therefore, during the time interval T... ON During this period, energy is stored in inductor 12 and output capacitor C. OUT middle.

[0028] Once the time interval T ON At the end, the first top transistor 2 is turned off, while the first bottom transistor 6 is turned on. This configuration occurs at time interval T. OFF Maintain this state until the time interval T ends, and as follows: Figure 2B As shown. Ideally, T = T ON +T OFF In this configuration, inductor 12 and output capacitor C OUT Gradual discharge; especially current I L It gradually decreases, possibly until it disappears.

[0029] In fact, in the first operating mode, converter 1 behaves similarly to a so-called buck converter. Therefore, in the following text, the first operating mode will be referred to as buck mode. Thus, inductor 12 undergoes charging and discharging cycles, transferring energy to load 15.

[0030] The control module 20 can also control the first top transistor 2 and the second top transistor 4, as well as the first bottom transistor 6 and the second bottom transistor 8, so that the converter 1 operates in a second operating mode, such as... Figure 3A and Figure 3B As shown schematically.

[0031] Specifically, in the second operating mode, the first top transistor 2 is always on to couple the first internal node N1 to the input node N. IN Instead, the first bottom transistor 6 is turned off to decouple the first internal node N1 from resistor 10, and thus from ground.

[0032] Conversely, the second top transistor 4 and the second bottom transistor 8 are controlled alternately by the control module 20. Specifically, for each time period T', the second bottom transistor 8 remains on for the time interval T'on, while the second top transistor 4 is off, as shown below. Figure 3A As shown; in this way, the current I increases linearly with time. L The current flows through inductor 12 and is guided to ground through resistor 10. Therefore, inductor 12 undergoes a discharge process.

[0033] Once the time interval T' ON At the end, the second bottom transistor 8 is turned off, while the second top transistor 4 is turned on, and this configuration is maintained for time interval T'. OFF until the time interval T' ends, and as follows Figure 3B As shown; ideally, T' = T' ON +T' OFF In this configuration, the current I L After passing through the shunt resistor 14, then partially through the output capacitor C. OUT The capacitor C is charged, and a portion of the charge flows to the load 15, gradually decreasing, possibly until it disappears. OUT In the subsequent time interval T' ON During this period, current is supplied to the load.

[0034] In fact, in the second operating mode, converter 1 behaves similarly to a so-called boost converter. Therefore, in the following text, the second operating mode will be referred to as boost mode. Furthermore, in this case, inductor 12 undergoes charging and discharging cycles, transferring energy to load 15.

[0035] Therefore, converter 1 is a buck-boost converter; therefore, if we take the output node N OUT The voltage present on and therefore on load 15 is expressed as V. OUT Then converter 1 can obtain ratio V OUT / V IN This ratio is either equal to the ratio achieved by the buck converter or equal to the ratio achieved by the boost converter.

[0036] Furthermore, the control module 20 can alternate the switching period T during which converter 1 operates in buck mode and the time period T' during which converter 1 operates in boost mode to obtain a ratio V that is approximately equal to 1. OUT / V IN .

[0037] More specifically, the control circuit 17 is based on the voltage drop across resistor 10, and therefore on the current flowing in resistor 10 (this current is compared with the current I flowing in inductor 12). L (consistent), and further based on voltage V OUT Determine the time interval T ON T OFF and T'on, T' OFF The duration. For this purpose, control circuit 17 receives a reference voltage V. ref and with voltage V OUT Depends on reference voltage V ref It operates in a closed-loop manner. Additionally, although not shown, control circuit 17 is connected to resistor 10.

[0038] More specifically, the control circuit 17 can, for example, implement a control scheme for a so-called current-mode converter 1, wherein the resistor 10 is capable of detecting current I. L This generates current I. L The first control quantity of the function, which is related to the indicated voltage V OUT With reference voltage V ref The difference between the two control quantities is compared, and the duty cycle (understood as T) is used to determine the difference between the two control quantities. ON or T' ON The ratio between I and T is controlled based on the comparison result, so that inductor 12 acts as a voltage-controlled current generator, because current I L The average value is the voltage V. OUT With reference voltage V ref The difference between them is a function. Alternatively, control circuit 17 can implement a control scheme for a so-called voltage-mode converter 1, in which the duty cycle is based solely on voltage V. OUT With reference voltage V refThe difference between them is controlled without implementing another control loop in which the control variable is determined by the current I of inductor 12. L Composition. In both cases, by changing the reference voltage V ref Obtain voltage V OUT The corresponding change (excluding ripple); that is, it is found that at a given reference voltage V ref In the case of a value, converter 1 uses voltage V OUT It is assumed that the corresponding average value works in this way.

[0039] Normally, if we use V c Representing the voltage drop across shunt resistor 14, control circuit 17 can also be configured based on voltage V. c The system detects the occurrence of an overcurrent in load 15, for example, caused by a fault in load 15, where load 15 draws more current than expected. This overcurrent can be detected, for example, using current measurement circuitry known in the art. For instance, the current measurement circuitry may include circuitry that measures the voltage across resistor 14 and compares the measured voltage to a predetermined threshold. In some embodiments, the current measurement circuitry may be implemented using an analog comparator. Once an overcurrent is detected, control module 20 can implement protection mechanisms for converter 1, such as shutting down the transistors of converter 1.

[0040] Regarding overcurrent detection capability, it should be noted how converter 1 regulates the current, typically in the range of several amperes, in both buck and boost modes; therefore, when the current I... L Exceeding a fairly high limit, such as 20A, will result in overcurrent. Therefore, assuming the resistance of shunt resistor 14 is, for example, 1mΩ, the voltage V across shunt resistor 14 will be... c Typically below 20mV; therefore, the occurrence of overcurrent can be detected by implementing a comparator in control circuit 17, which is configured to convert voltage V... c The comparison is made against a threshold equal to, for example, 20mV; the current consumption of the comparator is negligible compared to the voltage and current present within converter 1.

[0041] However, it is well known that in many applications, converter 1 can remain in a low-power operating mode, also known as a low-power mode, in which converter 1 regulates a current much lower than previously described (e.g., less than 1A), and in which the non-strictly necessary function of control circuit 17 is suppressed to reduce power consumption. In this case, the voltage V present across shunt resistor 14... c It can be very low (e.g., in the range of 1mV); therefore, through voltage V cDetecting overcurrent by comparing it to a corresponding threshold (understood as current regulated in low-power mode in the absence of a fault, also known as detection of a "soft short circuit") is far from accurate and / or overly cumbersome in terms of power consumption and area footprint. Furthermore, it is not possible to increase the resistance value of shunt resistor 14, as this would result in excessive power dissipation.

[0042] The control module 120, represented by 120, is described with reference to converter 1 and its differences from the control module 20 described above. The control circuit of control module 120 is represented by 117.

[0043] Specifically, when converter 1 operates in low-power mode, control module 120 keeps the second top transistor 4 off. Furthermore, also in low-power mode, converter 1 can operate in buck or boost mode, which will be referred to below as low-power buck mode and low-power boost mode. In the following text, the symbol T... switching The duration used to indicate the period when converter 1 operates in low-power buck mode is also considered to apply to the case when converter 1 operates in low-power boost mode, even if the same considerations are not taken into account.

[0044] More specifically, when converter 1 operates in low-power buck mode, control module 120 also keeps the second bottom transistor 8 off (during time interval T). ON During and in time interval T OFF During this period, both the first top transistor 2 and the first bottom transistor 6 are controlled simultaneously in the same manner as described with reference to the buck mode above. Therefore, as Figure 4A As shown, in time interval T ON During this period, current I L After passing through the first top transistor 2 and the inductor 12, the flow passes through the body diode (denoted by 24 and not shown in the previous figure) of the second top transistor 4, whose anode and cathode are connected to the source and drain terminals of the second top transistor 4, respectively.

[0045] Specifically, in low-power mode, and regardless of whether converter 1 operates in low-power buck or low-power boost mode, load 15 draws a reduced current (e.g., less than 1A). Therefore, current I L It also shows a tendency to fall below normal operating levels (understood as a reference). Figure 2A , Figure 2B , Figure 3A , Figure 3B The value that occurs during the described operation, wherein load 15 absorbs a current greater than the aforementioned reduced current. Therefore, current I LThe body diode 24 can be passed through without damaging the second top transistor 4, and the power consumption is reduced. In addition, since the second top transistor 4 is turned off, a reduction in power consumption is achieved; in fact, the portion of the drive circuit 19 that drives the second top transistor 4 (not shown) can be disabled.

[0046] In addition, such as Figure 4B As shown, in time interval T OFF During this period, the first top transistor 2 and the first bottom transistor 6 are turned off and turned on respectively, as referenced above. Figure 2B As described. Furthermore, at time interval T... OFF During this period, current I L The current flows through the body diode 24.

[0047] In practice, what happens is Figure 5 In qualitative displays, for example, this refers to the situation where converter 1 implements the so-called "discontinuous conduction mode (DCM)," i.e., current I... L The cases where it disappears during each time period T. Furthermore, Figure 5 The signal PWM generated by the control circuit 117 is shown in such a way that when the signal PWM is equal to "1", the first top transistor 2 and the first bottom transistor 4 are turned on and off, respectively, and when the signal PWM is equal to "0", the first top transistor 2 and the first bottom transistor 4 are turned off and on, respectively.

[0048] In other words, given the time period during which converter 1 operates in low-power buck mode, this includes consecutive time periods T (where two time periods are as follows) Figure 5 As shown in the figure, in each time period, the PWM signal is at time interval T. ON and time interval T OFF The period is equal to "1" and "0".

[0049] Nevertheless, it can be noted that the current I L How does the value of time interval T work? ON Increase during the period, and then at subsequent time intervals T OFF The voltage decreases during this period and disappears before the end of the time interval T. Furthermore, after removing the ripple (not shown), the voltage V... OUT In time interval T ON During and in time interval T OFF The duration increases because body diode 24 blocks output capacitor C. OUT Discharge occurs through the second top transistor 4, and therefore through the second internal node N2. In other words, the voltage V... OUT In time interval T ON During and in time interval T OFF The trend has been increasing throughout the period.

[0050] The control circuit 117 is also configured to detect voltage V OUT When the first voltage threshold TH_HIGH is reached, and used to control converter 1, so that at voltage V OUT Once the first voltage threshold TH_HIGH has been reached, converter 1 will operate in pulse-skipping mode.

[0051] Specifically, when the control circuit 117 controls the converter 1 to operate in pulse frequency hopping mode, it continues to disable the second top transistor 4 and further enables the second bottom transistor 8, as shown below. Figure 4C As shown; the first top transistor 2 and the first bottom transistor 6 are turned off and turned on, respectively. In this way, the current I... L It recirculates in the network formed by inductor 12 and the first bottom transistor 6 and the second bottom transistor 8. Therefore, the output capacitor C OUT It can gradually discharge, and then the voltage V OUT Decrease, such as Figure 6 This is shown in more detail in the text.

[0052] In particular, Figure 6 This illustrates how converter 1 will operate in pulse frequency hopping mode for a period of time with a duration TOV_MODE, which is based on voltage V. OUT The process terminates when a second voltage threshold TH_LOW is reached, which is lower than the first voltage threshold TH_HIGH. Specifically, and without implying any general loss, it is assumed that the first voltage threshold TH_HIGH is lower than the voltage V. OUT The target value V* OUT In other words, assuming that when converter 1 operates in low-power buck mode, the reference voltage V ref Equal to indicates the reference voltage V ref The value of V* ref This ensures that if converter 1 operates in normal operating mode, we will have (ripple removed) V OUT =V* OUT , where V* OUT >TH_HIGH.

[0053] As an example, also in Figure 6 The diagram shows two time periods when converter 1 operates in low-power buck mode, one before and one after the time period when converter 1 operates in pulse hopping mode.

[0054] The duration of the time period during which converter 1 operates in pulse frequency hopping mode, TOV_MODE, is equal to (TH_HIGH - TH_LOW)·C. OUT / ILOAD , among which, I LOAD This represents the current absorbed by load 15 when converter 1 operates in low-power buck mode.

[0055] Once again, refer to Figure 6 And this does not imply any general loss, the start of the time period in which converter 1 operates in pulse-skipping mode is asynchronous with respect to time period T. Again, without implying any general loss, time period T can alternatively be synchronous with respect to the end of the previous time period in which converter 1 operates in pulse-skipping mode.

[0056] Nevertheless, the control circuit 117 uses a time-based T OV_MODE The monitoring low-power mode implements an overcurrent detection mechanism because, as explained earlier, the latter depends on the current I. LOAD .

[0057] More specifically, the control circuit 117 can, for example, implement the monitoring circuit 49, which, as... Figure 7 As shown, it can be activated when the control module 120 controls the converter 1 in low power mode.

[0058] Specifically, the monitoring circuit 49 implements the timing circuit 61, which generates a period of T. clock The clock signal. In addition, the monitoring circuit 49 implements the comparator stage 50 and the synchronous acquisition stage 51.

[0059] Comparator 50 has a connection to output node N OUT The input terminal generates an analog signal OV_COMP_A, when the voltage V OUT When the first voltage threshold TH_HIGH is reached during the rising phase, the signal switches from "0" to "1" (i.e., with a rising edge), and when the voltage V... OUT When the second voltage threshold TH_LOW is reached during the falling phase, the signal switches from "1" to "0" (i.e., with a falling edge), as shown below. Figure 6 As shown. Therefore, the signal OV_COMP_A is equal to "1" during the time period when converter 1 operates in pulse frequency hopping mode, and equal to "0" during the time period when converter 1 operates in low power buck mode.

[0060] Synchronous acquisition stage 51 is connected to comparator stage 50 to receive signal OV_COMP_A and generate digital signal OV_COMP_D, which is synchronized with the clock signal and represents a version of signal OV_COMP_A with edges synchronized with the clock signal. Therefore, each rising / falling edge of signal OV_COMP_A corresponds to a rising / falling edge of signal OV_COMP_D. A delay is introduced between signal OV_COMP_D and signal OV_COMP_A by synchronous acquisition stage 51. Although not shown, synchronous acquisition stage 51 may also include, in a manner known per se, two cascaded flip-flops (not shown) timed based on the clock signal, in addition to possible subsequent digital filters (not shown) for filtering possible glitches that may exist on signal OV_COMP_A.

[0061] In practice, aside from the tolerance introduced by the time discretization of synchronous acquisition, each time interval when signal OV_COMP_D equals "1" (or "0") has the same duration as the corresponding time interval when signal OV_COMP_A equals "1" (or "0"), which is consistent with the time interval when converter 1 operates in pulse hopping mode (or low-power buck mode). In other words, the duration of each time interval when signal OV_COMP_D equals "1" is equal to the duration T of the corresponding time interval when signal OV_COMP_A equals "1". OV_MODE Furthermore, the duration of each time interval when signal OV_COMP_D equals "0" is equal to the duration T of the corresponding time interval when signal OV_COMP_A equals "0". switching Therefore, the signal OV_COMP_D indicates the duration of the time interval between the operation of converter 1 in pulse hopping mode and low-power buck mode.

[0062] The monitoring circuit 49 also implements an edge detection circuit 52, which is coupled to the synchronous acquisition stage 51 to receive the signal OV_COMP_D and is configured to generate a first pulse signal FE_PLS and a second pulse signal RE_PLS that are synchronized with the clock signal and include pulses with a duration equal to the period Tclock.

[0063] like Figure 8 As shown, the first pulse signal FE_PLS generates a pulse whenever the falling edge of the signal OV_COMP_D occurs, and the second pulse signal RE_PLS generates a pulse whenever the rising edge of the signal OV_COMP_D occurs.

[0064] The monitoring circuit 49 also implements the counter 54, the reset circuit 56, the first register 58, the second register 59, and the fault detection circuit 60.

[0065] Counter 54 stores the value of the variable Ncounter, which is an integer and increments at each pulse of the clock signal. At this point, even for the sake of simplicity, in Figure 7 The connections to timing circuit 61 are not shown. Timing circuit 61 is connected not only to counter 54, but also to synchronous acquisition circuit 51, edge detection circuit 52, reset circuit 56, and fault detection circuit 60. Therefore, the clock signal provides timing to counter 54, synchronous acquisition circuit 51, edge detection circuit 52, reset circuit 56, and fault detection circuit 60.

[0066] In addition, the reset circuit 56 receives the first pulse signal FE_PLS and the second pulse signal RE_PLS at the input terminal, and resets the counter 54, i.e. the value of the variable Ncounter, whenever the pulse of the first pulse signal FE_PLS or the second pulse signal RE_PLS appears.

[0067] The control circuit 117 can be programmed to store a first threshold TH_OV and a second threshold TH_SW, each consisting of positive integers, in the first register 58 and the second register 59, respectively, where TH_SW > TH_OV. Furthermore, the counter 54 has a size that causes the maximum value of the variable Ncounter (hereinafter referred to as NMAX) to be greater than the second threshold TH_SW.

[0068] The fault detection circuit 60 is coupled to the counter 54, the first register 58, and the second register 59 to receive the variable Ncounter, the first threshold TH_OV, and the second threshold TH_SW at its input. Furthermore, the fault detection circuit 60 is coupled to the edge detection circuit 52 to receive the first pulse signal FE_PLS and the second pulse signal RE_PLS, and to the synchronous acquisition circuit 51 to receive the signal OV_COMP_D.

[0069] like Figure 9 As shown, the fault detection circuit 60 implements a first comparison circuit 62 and a second comparison circuit 64, which, although not shown, are connected to a timing circuit 61 to receive a clock signal. In various embodiments, comparison circuits 62 and 64 can be implemented using digital comparison circuits or digital comparators known in the art.

[0070] The first comparator circuit 62 also has inputs connected to the first register 58 and the counter 54, respectively, to receive the first threshold TH_OV and the variable Ncounter. Furthermore, although not shown in detail, the first comparator circuit 62 is connected to the edge detection circuit 52 to receive the first pulse signal FE_PLS.

[0071] In practice, the first comparator circuit 62 is configured to detect the corresponding duration T for each time period during which the converter 1 operates in pulse frequency hopping mode. OV_MODE Is it at least equal to the first limit duration Tth_ov? To this end, the first comparison circuit 62 performs a comparison between the first threshold TH_OV and the variable Ncounter at each pulse of the first pulse signal FE_PLS, and therefore whenever the falling edge of the signal OV_COMP_D occurs. This variable Ncounter has been incremented by 1 for each pulse of the clock signal starting from the pulse preceding the second pulse signal RE_PLS. Figure 8 As shown. Therefore, the value of the variable Ncounter makes the product Ncounter Tclock equal to the duration of the time period before the pulse of the first pulse signal FE_PLS when the signal OV_COMP_D is equal to "1", which, as explained above, is equal to the duration T of the corresponding time period when converter 1 operates in pulse hopping mode. OV_MODE .

[0072] If the value of the variable Ncounter is at least equal to the first threshold TH_OV, it means that the duration T of the time period during which converter 1 operates in pulse hopping mode. OV_MODE It is at least equal to the first constraint duration Tth_ov, which is equal to TH_OVTclock. As mentioned before, due to the duration T OV_MODE Equals (TH_HIGH-TH_LOW)·C OUT / I LOAD Therefore, the first threshold TH_OV can be programmed as the current I*. LOAD The function of the current I* LOAD This represents the maximum current that load 15 can absorb in low-power mode, and specifically makes TH_OV·Tclock=(TH_HIGH-TH_LOW)·C OUT / I* LOAD .

[0073] In this way, if the variable Ncounter is at least equal to the first threshold TH_OV, it means that the actual current I absorbed by the load 15 is... LOAD It did not exceed the current I* LOAD For example, such as Figure 6 and Figure 8 As shown, Figure 6 Only the time period during which converter 1 operates in pulse frequency hopping mode is shown in full. Figure 8 The diagram shows three time periods during which converter 1 operates in pulse frequency hopping mode. Otherwise, it indicates that the current I... LOAD It has exceeded the current I* LOAD Therefore, an overcurrent occurs, for example, as... Figure 10 and Figure 11 as shown. Specifically, Figure 10 it shows three time periods during which the converter 1 operates in a pulse frequency hopping mode, and overcurrent starts in the third time period. Similarly, Figure 11 it shows two time periods during which the converter 1 operates in a pulse frequency hopping mode, and overcurrent starts at the beginning of the second time period during which the converter 1 operates in a pulse frequency hopping mode (qualitatively represented by the rising edge of the logic signal sOC).

[0074] As can be seen again in Figure 10 the first comparison circuit 62 can also generate a first comparison signal SS1 at the output, which is initially equal to "0" and is set to be equal to "1" after performing the comparison operation that has generated Ncounter < TH_OV, that is, after detecting overcurrent.

[0075] Without implying any general loss, the first comparison circuit 62 can reset the counter 54 after performing the comparison operation that has generated Ncounter < TH_OV.

[0076] In addition, for example, a variant can be implemented to prevent, after the reset of the counter 54 caused by the pulse of receiving the second pulse signal RE_PLS, before the next pulse of receiving the first pulse signal FE_PLS, the variable Ncounter may reach the maximum value NMAX and subsequent new reset (which may occur in the case of a duration T OV_MODE too long with respect to the size of the counter 54) that would prevent the correct check to be performed. In fact, if it is found that Ncounter < TH_OV when receiving the pulse of the first pulse signal FE_PLS, due to the aforementioned new reset, the first comparison circuit 62 will erroneously detect overcurrent. To prevent false detection, the first comparison circuit 62 can cooperate with the counter 54 to implement a mechanism that suppresses the increment of the counter 54 after the variable Ncounter assumes the maximum value NMAX after the reset caused by the pulse of receiving the second pulse signal RE_PLS, and this suppression lasts until the pulse of the first pulse signal FE_PLS after the pulse of receiving the second pulse signal RE_PLS, so that when receiving the pulse of the first pulse signal FE_PLS, the relationship Ncounter > TH_OV is applied; thus, overcurrent is not detected.

[0077] Regarding the second comparison circuit 64, it has inputs connected to the second register 59 and the counter 54 respectively to receive the second threshold TH_SW and the variable Ncounter; in addition, although not shown in detail, the first comparison circuit 62 is connected to the synchronous acquisition circuit 51 and the edge detection circuit 52 to receive the signal OV_COMP_D and the first pulse signal FE_PLS and the second pulse signal RE_PLS.

[0078] Nevertheless, the second comparator circuit 64 is configured to detect the corresponding duration T for each period of time when the converter 1 operates in low-power buck mode. switching Whether it is below the second limit duration Tth_sw. In fact, in the event of overcurrent during the period when converter 1 operates in low-power buck mode, the voltage V... OUT The voltage tends to rise slowly and may not reach the first voltage threshold TH_HIGH, although, as mentioned earlier, the reference voltage V... ref Equal to V* ref .

[0079] In practice, during each time period when the signal OV_COMP_D equals "0", the second comparison circuit 64 compares the variable Ncounter with the second threshold TH_SW at each pulse of the clock signal following the pulse of the first pulse signal FE_PLS caused by the falling edge of the signal OV_COMP_D, the falling edge of which has determined the start of the aforementioned time period when the signal OV_COMP_D equals "0". If the variable Ncounter has reached the second threshold TH_SW, the pulse of the clock signal corresponding to the aforementioned pulse of the first pulse signal FE_PLS is not compared to avoid reading the counter 54 before it is reset, which carries the risk of erroneous detection.

[0080] If the time period during which the signal OV_COMP_D equals "0" terminates before the variable Ncounter reaches the second threshold TH_SW, this means that... Figure 6 , Figure 8 , Figure 10 and Figure 11 As shown, no overcurrent occurred during the corresponding period when converter 1 operated in low-power buck mode.

[0081] On the contrary, such as Figure 12 and Figure 13 As shown, if the variable Ncounter reaches the second threshold TH_SW before the end of the time period when the signal OV_COMP_D is equal to "0", that is, before the next pulse of the second pulse signal RE_PLS, it means that an overcurrent has occurred.

[0082] Specifically, Figure 12 The diagram illustrates two time periods during which converter 1 operates in low-power buck mode, with overcurrent initiating in the second time period. Similarly, Figure 13 The diagram shows two time periods in which converter 1 operates in low-power buck mode, wherein an overcurrent occurs at the beginning of the second time period in which converter 1 operates in low-power buck mode.

[0083] In practice, by changing the value of the second threshold TH_SW, the current I when converter 1 operates in low-power buck mode can be changed. LOAD An assumed limit value can be set, and an overcurrent is detected when this limit value is exceeded.

[0084] As in Figure 12 As can be seen again, the second comparator circuit 64 can also generate a second comparator signal SS2 at the output terminal. The second comparator signal SS2 is initially equal to "0" and is set to "1" after the comparator operation that has generated Ncounter = TH_SW has been performed, that is, after an overcurrent is detected during the period when the converter 1 has been operating in low-power buck mode.

[0085] Without implying any general loss, the second comparator circuit 64 can reset the counter 54 after performing a comparator operation that has already generated Ncounter = TH_SW.

[0086] The monitoring circuit 49 can also be configured to apply a protection strategy to the converter 1 based on the comparison signals SS1 and SS2. For example, the monitoring circuit 49 can be configured to turn off all transistors of the converter 1 when one of the comparison signals SS1 and SS2 becomes equal to "1".

[0087] The description previously provided regarding the operation of converter 1 in low-power buck mode also applies to the case where converter 1 operates in low-power mode while simultaneously operating in boost mode, i.e., the case where converter 1 operates in the aforementioned low-power boost mode. In this case, control module 120 keeps both the second top transistor 4 and the first bottom transistor 6 off (during time interval T'). ON During and in the time interval T' OFF During this period, the first top transistor 2 and the second bottom transistor 8 are simultaneously driven in the same manner as described with reference to the aforementioned boost mode. Therefore, as Figure 14A As shown, in time interval T' ON During this period, current I L Both the first top transistor 2 and the second bottom transistor 8 remain on; because the body diode 24 is reverse biased, no current flows through it. During time interval T' OFFDuring this period, the first top transistor 2 remains on, while the second bottom transistor 8 is off, as... Figure 14B As shown, this makes the current I L The current will flow through body diode 24.

[0088] In practice, when converter 1 operates in low-power boost mode, its behavior is similar to that of an asynchronous boost converter. Furthermore, also in this case, the body diode 24 prevents the output capacitor C from... OUT Discharge occurs through the second top transistor 4, so the voltage V OUT In time interval T' ON and time interval T' OFF The voltage increases during this period. Therefore, in the same case, the control circuit 117 is configured to detect the voltage V. OUT When the first threshold TH_HIGH is reached, and used to control converter 1, so that at voltage V OUT After reaching the first threshold TH_HIGH, it will be compared with the reference. Figure 4C The same manner described operates in pulse frequency hopping mode, thereby causing current I... L The circuit recycles within the network formed by inductor 12 and the first bottom transistor 6 and the second bottom transistor 8 until voltage V... OUT It drops to the second threshold TH_LOW.

[0089] Therefore, overcurrent detection during the time period when converter 1 is operating in pulse frequency hopping mode or low power boost mode is performed in the same manner as described above.

[0090] The advantages offered by this control module are clearly evident from the preceding description.

[0091] Specifically, when converter 1 operates in low-power mode, this control module implements a new method for detecting overcurrent. Monitoring capacitor C OUT The discharge time is measured and compared to a threshold to detect whether the current absorbed by load 15 is higher than the expected current. This detection mechanism is accurate and far from expensive in terms of consumption.

[0092] Finally, it is clear that modifications and changes can be made to the control modules described and shown herein without departing from the scope of the invention as defined in the appended claims.

[0093] For example, control circuit 117 can implement different clock signals, which can control different parts of control circuit 117. For example, counter 54 can be timed based on clock signals other than synchronous acquisition circuit 51 and / or edge detection circuit 52; therefore, the duration of pulses such as the first pulse signal FE_PLS and the second pulse signal RE_PLS may be shorter than the update period of the value of variable Ncounter.

[0094] More generally, the control circuit 117 may employ a different mechanism than those already described to verify the relationship between the duration of the period during which the converter 1 operates in pulse hopping mode or low-power buck / boost mode and the corresponding limit duration. For example, two different counters may be implemented.

[0095] For low-power buck / boost modes, in addition to envisioning permanent suppression of the second top transistor 4, it is also conceivable to implement further functions to reduce power consumption.

[0096] In addition, the control module 120 can alternate between periods of operation in low-power buck mode and periods of operation in low-power boost mode.

[0097] Alternatively, transistors of a different type than those already described can be used. In this case, a parasitic diode exists instead of the body diode 24, depending on the type of transistor chosen to implement the second top transistor 4. It is possible, for example, that if the second top transistor 4 is replaced by a switch of a type other than a MOSFET, an external diode to the second top transistor 4 can be used instead of the body diode 24.

[0098] Finally, it is possible to present a lower performance embodiment in which overcurrent detection is limited to the time period during which converter 1 operates in pulse frequency hopping mode.

Claims

1. A control module for a switched buck-boost converter, the switched buck-boost converter comprising: The input node is configured to receive the input voltage. Output node, configured to be coupled to the load; inductor; Capacitor; First top switch; Second top switch; First bottom switch; The first top switch and the first bottom switch are connected in series to form a first internal node, and the second top switch and the second bottom switch are connected in series to form a second internal node. The inductor is coupled to the first internal node and the second internal node. The first top switch and the second top switch are respectively coupled to the input node and the output node. The capacitor is coupled to the output node. The switching buck-boost converter also includes a diode coupled to the on terminal of the second top switch and configured to prevent the capacitor from discharging through the second internal node when the second top switch is off. The control module includes: The controller is configured to operate in a low-power operating mode when coupled to the switching buck-boost converter, during which the controller causes the switching buck-boost converter to alternate between a first time period and a second time period, wherein... During the first time period, the controller is configured to disconnect the second top switch and to control the first top switch, the first bottom switch, and the second bottom switch to perform a charging and discharging cycle of the inductor, during which current flows through the inductor, wherein the current flows through the diode during each discharge cycle of the inductor and charges the capacitor in such a way that the voltage at the output node increases from a low threshold to a high threshold. During the second time period, the controller is configured to open the first top switch and the second top switch, and close the first bottom switch and the second bottom switch. During the closure of the first bottom switch and the second bottom switch, the current in the inductor is recirculated through the first bottom switch and the second bottom switch, and the capacitor is discharged by the current flowing in the load in a manner that reduces the voltage at the output node from the high threshold to the low threshold. The acquisition circuit is configured to generate a digital signal indicating the duration of the second time period; and An overcurrent detection circuit is configured to receive the digital signal and includes a first comparison circuit configured to compare the duration of each second time period with a first limit duration, and to indicate the occurrence of an overcurrent when the duration of the second time period is shorter than the first limit duration.

2. The control module according to claim 1, wherein: The digital signal also indicates the duration of the first time period; and The overcurrent detection circuit further includes a second comparison circuit configured to compare the duration of each first time period with a second limit duration, and to indicate the occurrence of the overcurrent when the duration of the first time period is at least equal to the second limit duration.

3. The control module according to claim 2, wherein: The overcurrent detection circuit further includes: The timing circuit is configured to generate a clock signal. An edge detection circuit is configured to generate, based on the digital signal, a second time period end signal indicating the end of each second time period and a first time period end signal indicating the end of each first time period, and... A counter is configured to store a value that is updated based on the clock signal and reset by the edge detection circuit at the end of each first time period and at the end of each second time period; and The first comparison circuit is configured to receive the second time period end signal and compare the value stored in the counter at the end of each second time period with a first numerical threshold, wherein the first limit duration is a function of the first numerical threshold and the clock signal.

4. The control module according to claim 3, wherein the second comparison circuit is configured as follows: Receive the second time period end signal and the first time period end signal, and The system detects whether the value stored in the counter reaches a second numerical threshold during each first time period.

5. The control module according to claim 1, wherein: During the first time period, the controller is also configured to: Disconnect the second bottom switch. The first top switch and the first bottom switch are respectively closed and opened during the first sub-interval of the first time period to charge the inductor. The first top switch and the first bottom switch are respectively opened and closed during the second sub-interval of the first time period to discharge the inductor, wherein the current flowing in the inductor passes through the diode during the first sub-interval and the second sub-interval; or During the first time period, the controller is further configured to: Disconnect the first bottom switch. The first top switch and the second bottom switch are closed respectively during the first sub-interval of the first time period to charge the inductor. The first top switch and the second bottom switch are closed and opened respectively during the second sub-interval of the first time period to discharge the inductor, wherein the current flowing in the inductor passes through the diode during the first sub-interval and the second sub-interval.

6. The control module according to claim 1, wherein: The controller is also configured to cause the switching buck-boost converter to alternate between operating in a low-power mode and operating in a high-power mode; During the high-power mode, the controller is configured to cause the switching buck-boost converter to operate selectively in either a high-power buck mode or a high-power boost mode; During the high-power buck mode, the controller is configured to: Keep the second top switch closed and the second bottom switch open, and The first top switch and the first bottom switch are controlled alternately. as well as During the high-power boost mode, the controller is configured to: Keep the first top switch closed and the first bottom switch open, and The second top switch and the second bottom switch are controlled alternately.

7. An electronic system comprising the control module and the switching buck-boost converter according to claim 1.

8. The electronic system according to claim 7, wherein: The first top switch, the second top switch, the first bottom switch, and the second bottom switch each include a MOSFET; and The diode is the body diode of the second top switch.

9. A method for controlling a switched buck-boost converter, the switched buck-boost converter comprising: The input node is configured to receive the input voltage. Output node, configured to be coupled to the load; inductor; Capacitor; First top switch; Second top switch; First bottom switch; The method includes a second bottom switch, wherein the first top switch and the first bottom switch are connected in series to form a first internal node, the second top switch and the second bottom switch are connected in series to form a second internal node, the inductor is coupled to the first internal node and the second internal node, the first top switch and the second top switch are respectively coupled to the input node and the output node, the capacitor is coupled to the output node, and the switching buck-boost converter further includes a diode coupled to the on terminal of the second top switch and configured to prevent the capacitor from discharging through the second internal node when the second top switch is off. The switching buck-boost converter operates in a low-power mode, including alternating first and second time periods. Operating the switching buck-boost converter in the low-power operating mode during the first time period includes: Disconnect the second top switch, and The first top switch, the first bottom switch, and the second bottom switch are controlled to perform a charging and discharging cycle of the inductor, during which current flows through the inductor, wherein the current flows through the diode during each discharge cycle of the inductor and charges the capacitor in such a way that the voltage at the output node increases from a low threshold to a high threshold. Operating the switching buck-boost converter in the low-power operating mode during the second time period includes: Disconnect the first top switch and the second top switch, and The first bottom switch and the second bottom switch are closed. During the closure of the first bottom switch and the second bottom switch, the current in the inductor is recirculated through the first bottom switch and the second bottom switch, and the capacitor is discharged by the current flowing in the load in such a way that the voltage at the output node is reduced from the high threshold to the low threshold. Generate a digital signal indicating the duration of the second time period; and Based on the digital signal, the duration of each second time period is compared with the first limit duration, and an overcurrent is indicated when the duration of the second time period is shorter than the first limit duration.

10. The method according to claim 9, wherein: The digital signal also indicates the duration of the first time period; and The method further includes comparing the duration of each first time period with a second limit duration based on the digital signal, and indicating the occurrence of the overcurrent when the duration of the first time period is at least equal to the second limit duration.

11. The method of claim 10, wherein comparing the duration of each second time period with the first limited duration comprises: Generate clock signal; Based on the digital signal, a second time period end signal indicating the end of each second time period and a first time period end signal indicating the end of each first time period are generated; Update the counter value based on the clock signal; The counter is reset at the end of each first time period and at the end of each second time period. as well as Based on the end signal of the second time period, the value of the counter at the end of each second time period is compared with a first numerical threshold, wherein the first limit duration is a function of the first numerical threshold and the clock signal.

12. The method of claim 11, wherein comparing the duration of each first time period to the second limit duration comprises: Based on the second time period end signal and the first time period end signal, it indicates whether the value stored in the counter reaches a second numerical threshold during each first time period.

13. The method of claim 9, wherein operating the switch buck-boost in the low-power operating mode further comprises: During the first time period: Disconnect the second bottom switch. The first top switch and the first bottom switch are respectively closed and opened during the first sub-interval of the first time period to charge the inductor. The first top switch and the first bottom switch are respectively opened and closed during the second sub-interval of the first time period to discharge the inductor, wherein the current flowing in the inductor passes through the diode during the first sub-interval and during the second sub-interval; or During the first time period: Disconnect the first bottom switch. The first top switch and the second bottom switch are closed respectively during the first sub-interval of the first time period to charge the inductor. The first top switch and the second bottom switch are closed and opened respectively during the second sub-interval of the first time period to discharge the inductor, wherein the current flowing in the inductor passes through the diode during the first sub-interval and the second sub-interval.

14. The method of claim 9, further comprising alternating between operating the switching buck-boost converter in a low-power mode and operating in a high-power mode, wherein: Operating in the high-power mode includes selectively operating the switching buck-boost converter in a high-power buck mode or in a high-power boost mode. Operating in the high-power buck mode includes: Keep the second top switch closed and the second bottom switch open, and Controlling the first top switch and the first bottom switch alternately; and Operating in the high-power boost mode includes: Keep the first top switch closed and the first bottom switch open, and The second top switch and the second bottom switch are controlled alternately.

15. A switch-mode power supply, comprising: A power controller is configured to be coupled to a power circuit including a plurality of switches coupled between a power input node and a power output node, and an inductor coupled to the plurality of switches. The power controller is configured to operate the power circuit in a low-power mode including alternating first and second time periods, wherein the power controller is configured to: When the output voltage of the power output node transitions from a first predetermined voltage threshold to a second predetermined voltage threshold, an active switching signal is applied to at least one of the plurality of switches during the first time period, and When the output voltage of the power output node changes from the second predetermined voltage threshold to the first predetermined voltage threshold, a static switching signal is applied to each of the plurality of switches during the second time period; A voltage measurement circuit is configured to be coupled to the power output node; as well as A first overcurrent measurement circuit, coupled to the voltage measurement circuit and configured to indicate a first overcurrent condition when the duration of the first time period is less than a first threshold, or when the duration of the second time period is greater than a second threshold.

16. The switch-mode power supply of claim 15, wherein the first overcurrent measurement circuit comprises: Digital counter; as well as At least one digital comparison circuit is coupled to the counter, the at least one digital comparison circuit being configured to compare the value of the digital counter with the first threshold or the second threshold.

17. The switch-mode power supply according to claim 15, wherein: The power controller further includes a second overcurrent measurement circuit configured to be coupled to a shunt resistor connected between the plurality of switches and the power output node; When the power supply circuit is operated in the low-power mode, the first overcurrent measurement circuit is activated; and The second overcurrent measurement circuit is activated when the power supply circuit is operated in low-power mode.

18. The switch-mode power supply of claim 17, wherein the first overcurrent measurement circuit is configured to detect an output current smaller than that of the second overcurrent measurement circuit.

19. The switch-mode power supply according to claim 17, further comprising the power supply circuit.

20. The switch-mode power supply according to claim 19, wherein: The plurality of switches includes: A first switch is coupled between the power input node and the first node; The second switch is coupled between the first node and the first reference node; The third switch is coupled between the power output node and the second node; A fourth switch is coupled between the second node and the reference node; and an inductor is coupled between the first node and the second node.

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