An automatic gain control compensation method

Abstract

This invention relates to an automatic gain control (AGC) compensation method that achieves synchronization of the AGC factor and I / Q data at the input of the AGC compensation module through hardware and software interaction. It can quickly track and detect the compensated saturated signal, rapidly attenuate signals exceeding a threshold, and generate a corresponding DVGA factor based on the attenuation amount. Without increasing storage resources, it achieves synchronous output of the compensated I / Q data and DVGA factor from the DFE to the baseband. This invention improves compensation performance while reducing hardware resource overhead.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and in particular to an automatic gain control compensation method. Background Technology

[0002] Automatic Gain Control (AGC) is a control method that automatically adjusts the gain to overcome input instability and maintain a relatively constant output. Currently, AGC is widely used in wireless communication and other fields. Typically, wireless communication chips are designed to convert the analog attenuation of the input signal power into digital AGC through an optical transceiver module, and then compensate in subsequent digital circuits to restore the original signal power. Many chip design manufacturers choose to perform carrier-level AGC compensation before CPRI and after DFE to reduce the impact of out-of-band interference.

[0003] AGC compensation requires alignment between the input AGC factor and I / Q data. Traditional solutions pipeline the AGC factor along with the data to the DFE stage, which consumes significant logic resources when link latency is high. Furthermore, large in-band interference can cause signal saturation after compensation. Directly transmitting this to the baseband would affect baseband-side FFT, channel estimation, and equalization. Therefore, large signals need to be attenuated, and the attenuation amount is used as the DVGA factor for further propagation. Traditional solutions store the compensated I / Q data and DVGA factor together in a large buffer, reading them sequentially when requested by the lowPHY and CPRI stages, ensuring data alignment with the DVGA factor. However, this approach significantly consumes chip storage resources and increases power consumption. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide an automatic gain control compensation method that can improve compensation performance while reducing hardware resource overhead.

[0005] The technical solution adopted by this invention to solve its technical problem is: to provide an automatic gain control compensation method, comprising the following steps:

[0006] Based on the business scenario, the latency of each carrier processed on the link is calculated in advance;

[0007] The software configures the routing relationship between the antenna and the carrier.

[0008] A pulse signal is generated at the location where the AGC factor changes, and several registers are opened for each antenna; each antenna performs a cyclic count based on its corresponding pulse signal, and when the count reaches a fixed value, the AGC factor and the pulse signal at this time are latched through the register respectively;

[0009] Based on the routing relationship from the antenna to the carrier, the antenna corresponding to each carrier is determined, thereby determining the AGC factor and pulse signal corresponding to each carrier;

[0010] Each carrier has several delay counters. Each delay counter starts counting when its corresponding pulse signal is valid. When the count value of the delay counter is equal to the delay of the corresponding carrier, the AGC factor of the carrier is obtained by reading the register of the corresponding antenna.

[0011] The AGC factor, which is aligned with the input carrier data, is obtained by selecting the carrier ID that accompanies the input carrier data.

[0012] There are three registers. Each antenna performs a cyclic count from 0 to 2 based on its corresponding pulse signal. When the counter equals 0, the first register latches the AGC factor and pulse signal at this time. When the counter equals 1, the second register latches the AGC factor and pulse signal at this time. When the counter equals 2, the third register latches the AGC factor and pulse signal at this time.

[0013] The number of delay counters is the same as the number of registers, and each delay counter corresponds to one of the registers.

[0014] The automatic gain control compensation method further includes:

[0015] The aligned AGC factor is converted to dB according to the resolution configured in the software, then converted to a ratio by looking up a table, and finally multiplied with the input carrier data to obtain the compensated carrier data.

[0016] Changes in the AGC factor are detected, and change pulses are generated at the locations where changes in the AGC factor occur.

[0017] Two changing pulses are used as one detection cycle, and the peak power of the compensated carrier data is continuously detected in each detection cycle.

[0018] After one detection cycle is completed, the most significant bit N corresponding to the peak power is calculated;

[0019] Determine whether the peak power exceeds the threshold value configured in the software based on the most significant bit N;

[0020] Carrier data with peak power exceeding a threshold is attenuated in the next detection period, and a DVGA factor is generated based on the attenuation amount.

[0021] The specific detection method for the peak power of the carrier data after compensation is as follows: In each clock cycle, first compare the maximum absolute values ​​of the I part and Q part of the same sample point, then compare the maximum value with the result of the previous clock cycle, save the larger one, and discard the smaller one.

[0022] The automatic gain control compensation method further includes:

[0023] The compensated carrier data is sequentially written into the RAM inside DFE_IF;

[0024] Based on the frame header and time slot configuration relationship output by the timing module, slot and symbol counts are generated to obtain the symbol index corresponding to the compensated carrier data, and the write address corresponding to the first sample point of each symbol is latched.

[0025] Latch the DVGA factor corresponding to the first sample point of each symbol, and at the same time detect whether the DVGA factor within each symbol changes. If there is a change, record the position information.

[0026] Inside DFE_IF, two registers are set up for each symbol to store the DVGA factor. The first register is used to store the DVGA factor corresponding to the first sample point, and the second register is used to store the DVGA factor of the changing position.

[0027] According to the read symbol index input by the subsequent module, find the write address of the first sample point of the current symbol, read the carrier data of the symbol from RAM, and update the DVGA factor at the positions where the symbol header and DVGA change.

[0028] The method of detecting whether the DVGA factor changes within each symbol also includes: determining whether the DVGA factor changes more than twice within each symbol; if so, reporting an anomaly.

[0029] Beneficial effects

[0030] By adopting the above-mentioned technical solution, this invention has the following advantages and positive effects compared with the prior art: This invention achieves the alignment of the compensation entry AGC factor and I / Q data through software and hardware interaction, greatly reducing logic resource overhead. The DFE_IF timestamp method designed in this invention does not require storing the DVGA factor and I / Q data together, and can align and output the DVGA factor and I / Q data when requesting a reading in the subsequent stage. Attached Figure Description

[0031] Figure 1 This is a block diagram of the intermediate frequency uplink processing link in an embodiment of the present invention;

[0032] Figure 2 This is a flowchart illustrating the AGC factor synchronization implementation in an embodiment of the present invention;

[0033] Figure 3 This is a schematic diagram of signal power detection after compensation in an embodiment of the present invention. Detailed Implementation

[0034] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0035] The embodiments of the present invention relate to an automatic gain control compensation method, which is based on, for example, Figure 1 The diagram illustrates the processing flow of the intermediate frequency (IF) uplink. This IF uplink processing flow includes subsystems such as Transceiver, JESD, UL_DFE / UL_DFE_IF, lowPHY, Compression, CPRI, and eCPRI. The automatic gain control compensation function in this embodiment mainly involves the JESD, UL_AGC_COMP, and UL_DFE_IF modules within the UL_DFE.

[0036] JESD receives I / Q data sent from the Transceiver, extracts the AGC factor, and directly passes it through to UL_AGC_COMP. The I / Q data is then pipelined to the next level module.

[0037] The main functions of UL_AGC_COMP include: a) mapping the received AGC factor from the antenna to the carrier and performing delay processing to align the input carrier I / Q data; b) compensating the I / Q data based on the AGC factor; c) detecting the compensated signal, and when the signal power exceeds the threshold, supporting signal attenuation and generating a DVGA factor corresponding to the attenuation amount to send to the subsequent stage.

[0038] UL_DFE_IF receives I / Q data and DVGA factor, timestamps the DVGA factor without adding extra storage resources, and aligns and outputs the DVGA factor and I / Q data after receiving a read request from the subsequent stage.

[0039] The compression module compresses the DVGA factor according to the granularity of BlcokSize. CPRI, based on the OTIC specification, sends data and the DVGA factor to the baseband. LowPHY compensates for the I / Q data based on the DVGA factor.

[0040] This implementation achieves AGC compensation input AGC factor alignment with carrier I / Q data through software and hardware interaction. Taking a single channel as an example, the AGC factor alignment I / Q data implementation process is roughly as follows: Figure 2 As shown.

[0041] 1. The software calculates the delay of each carrier of UL_DFE in advance according to the business scenario, then calculates the corresponding number of clock cycles according to the current working clock frequency of UL_AGC_COMP, and finally allocates the number of clock cycles to the hardware in the form of a register for each carrier.

[0042] 2. Configure the routing relationship from the antenna to the carrier in the software;

[0043] 3. It is agreed that when JESD outputs the AGC factor, a pulse signal agc_vld is generated at the position where it changes, and each antenna is independent;

[0044] 4. Three registers agc_lock0 to 2 are opened for each antenna; each antenna performs a cyclic count from 0 to 2 according to its corresponding pulse signal agc_vld. When the counter is equal to 0 / 1 / 2, the input AGC factor and pulse signal agc_vld are latched respectively.

[0045] 5. Based on the routing relationship from the antenna to the carrier, determine which antenna the AGC factor of each carrier originates from;

[0046] 6. Three delay counters are set up for each carrier. The three delay counters correspond to the AGC factor and pulse signal agc_vld latched in step 4, respectively. Each delay counter starts counting when its corresponding pulse signal agc_vld is valid. Each carrier is processed independently. When the count value of the delay counter is equal to the delay amount configured in the software, the corresponding register agc_lock is read to obtain the AGC factor of the carrier.

[0047] 7. After completing the above steps, the AGC factor of each carrier can be obtained in parallel. Then, the carrier ID of the accompanying path is selected every time, and finally the AGC factor aligned with the input I / Q data is obtained.

[0048] Taking a link latency of 20µs and an operating clock frequency of 491.52MHz as an example, the resource overhead of the traditional method is approximately 20*491.52*4*10 = 393216 gates, where 20*491.52 represents the number of pulses along the path, the AGC factor has a bit width of 4 bits, and each bit of register consumes 10 gates of resources. The resource overhead of this implementation can be roughly divided into the following parts: parameter configuration: (14*16+4*16)*10 = 2880 gates; counter and accumulation logic: 16*3*14*10+16*3*200 = 16320 gates; others: 5000 gates; total resource overhead = 2880+16320+5000 = 24200 gates, which is approximately 6.25% of the existing method. Here, 16 represents the number of carriers, and a 20µs link delay corresponds to approximately 9800 clock cycles, represented by a 14-bit register; the routing carrier ID is represented by a 4-bit register; each carrier corresponds to 3 14-bit counters, and each adder consumes 200 gates of resources.

[0049] This implementation also supports rapid tracking and detection of saturation signals at AGC factor change intervals, rapid attenuation of signals exceeding the threshold after compensation, and outputting the attenuation amount as a DVGA factor to the subsequent stage, specifically including:

[0050] 1. Based on the resolution configured in the software, the aligned AGC factor is converted to dB, then converted to a ratio by looking up a table, and finally multiplied with the input I / Q data to obtain the compensated I / Q data;

[0051] 2. Detect changes in the AGC factor and generate a change pulse (agc_change) at the location of the change; each carrier wave is processed independently.

[0052] 3. Take two changing pulses agc_change as one detection cycle. Continuously detect the peak power of the compensated I / Q data in each detection cycle. The specific detection method is as follows: In each detection cycle, first compare the maximum absolute values ​​of the I and Q parts of the same sample point, and then compare the maximum value with the detection result of the previous detection cycle. The larger value is saved and the smaller value is discarded.

[0053] 4. Once a detection cycle ends, the peak power peakPower within that detection cycle can be obtained, and the most significant bit N corresponding to peakPower can be calculated simultaneously.

[0054] 5. Determine whether the peak power (peakPower) exceeds the threshold value configured in the software based on the magnitude of the most significant bit (N).

[0055] 6. Carrier data whose peak power exceeds the threshold value is attenuated in the next detection period, and a DVGA factor is generated based on the attenuation amount;

[0056] 7. To ensure that the gain of each carrier in the same cell is the same for different antennas, the carriers in the same cell for different antennas must be subjected to the same attenuation treatment. To achieve this, the peak power of each carrier in the same cell for different antennas is first calculated, and then the maximum value is obtained by comparison. This maximum value is used to attenuate these carriers simultaneously in the next detection cycle. This function supports bypass, in which each carrier is detected and attenuated independently.

[0057] like Figure 3 As shown, when the compensated signal power exceeds the peak detection threshold, the DVGA module starts to control and rapidly attenuates the signal exceeding the threshold, so that the signal power is lower than the threshold, and outputs a DVGA factor corresponding to the attenuation amount. This method can improve the accuracy of baseband FFT, measurement results, and the performance of CE / EQ.

[0058] This implementation also designs a DFE_IF timestamp method, which does not add extra storage resources. When requesting readings in the subsequent stage, it completes the DVGA factor and I / Q data alignment output, specifically including:

[0059] 1. The input I / Q data is sequentially written into the RAM inside DFE_IF;

[0060] 2. Based on the 10ms frame header and time slot configuration relationship output by the timing module, generate slot and symbol counts, obtain the symbol index corresponding to the input I / Q data, and latch the write address corresponding to the first sample point of each symbol;

[0061] 3. Latch the DVGA factor corresponding to the first sample point of each symbol, and at the same time detect whether the DVGA factor within each symbol changes. If it changes, record the position information.

[0062] 4. Considering abnormal scenarios, the DVGA factor may change within a symbol. If the changed DVGA factor is not transmitted, it will cause the power before and after the symbol to be inconsistent. Therefore, two registers are opened inside DFE_IF to store the DVGA factor for each symbol. The first register is used to store the DVGA factor corresponding to the first sample point, and the second register is used to store the DVGA factor at the changed position.

[0063] 5. If the DVGA factor within the symbol changes more than twice, an anomaly should be reported;

[0064] 6. According to the read symbol index input by the subsequent lowPHY and CPRI, find the write address of the first sample point of the current symbol, read the I / Q data of the symbol from RAM, and update the DVGA factor at the symbol header and DVGA change positions.

[0065] Therefore, this method does not require storing DVGA factors at the sample point level, saving 4*N*2 storage resources, where N represents the depth of RAM, and each bit consumes 2 gates of resources, which is equivalent to saving 12.5% ​​of the original RAM.

Claims

1. An automatic gain control compensation method, characterized in that, Includes the following steps: Based on the business scenario, the latency of each carrier processed on the link is calculated in advance; The software configures the routing relationship between the antenna and the carrier. A pulse signal is generated at the location where the AGC factor changes, and several registers are opened for each antenna; each antenna performs a cyclic count based on its corresponding pulse signal, and when the count reaches a fixed value, the AGC factor and the pulse signal at this time are latched through the register respectively; Based on the routing relationship from the antenna to the carrier, the antenna corresponding to each carrier is determined, thereby determining the AGC factor and pulse signal corresponding to each carrier; Each carrier has several delay counters. Each delay counter starts counting when its corresponding pulse signal is valid. When the count value of the delay counter is equal to the delay of the corresponding carrier, the AGC factor of the carrier is obtained by reading the register of the corresponding antenna. The AGC factor, which is aligned with the input carrier data, is obtained by selecting the carrier ID that accompanies the input carrier data.

2. The automatic gain control compensation method according to claim 1, characterized in that, There are three registers. Each antenna performs a cyclic count from 0 to 2 based on its corresponding pulse signal. When the counter equals 0, the first register latches the AGC factor and pulse signal at this time. When the counter equals 1, the second register latches the AGC factor and pulse signal at this time. When the counter equals 2, the third register latches the AGC factor and pulse signal at this time.

3. The automatic gain control compensation method according to claim 1, characterized in that, The number of delay counters is the same as the number of registers, and each delay counter corresponds to one of the registers.

4. The automatic gain control compensation method according to claim 1, characterized in that, Also includes: The aligned AGC factor is converted to dB according to the resolution configured in the software, then converted to a ratio by looking up a table, and finally multiplied with the input carrier data to obtain the compensated carrier data. Changes in the AGC factor are detected, and change pulses are generated at the locations where changes in the AGC factor occur. Two changing pulses are used as one detection cycle, and the peak power of the compensated carrier data is continuously detected in each detection cycle. After one detection cycle is completed, the most significant bit N corresponding to the peak power is calculated; Determine whether the peak power exceeds the threshold value configured in the software based on the most significant bit N; Carrier data with peak power exceeding a threshold is attenuated in the next detection period, and a DVGA factor is generated based on the attenuation amount.

5. The automatic gain control compensation method according to claim 4, characterized in that, The specific detection method for the peak power of the carrier data after compensation is as follows: In each clock cycle, first compare the maximum absolute values ​​of the I part and Q part of the same sample point, then compare the maximum value with the result of the previous clock cycle, save the larger one, and discard the smaller one.

6. The automatic gain control compensation method according to claim 4, characterized in that, Also includes: The compensated carrier data is sequentially written into the RAM inside DFE_IF; Based on the frame header and time slot configuration relationship output by the timing module, slot and symbol counts are generated to obtain the symbol index corresponding to the compensated carrier data, and the write address corresponding to the first sample point of each symbol is latched. Latch the DVGA factor corresponding to the first sample point of each symbol, and simultaneously detect whether the DVGA factor changes within each symbol. If there are changes, record the location information; Inside DFE_IF, two registers are set up for each symbol to store the DVGA factor. The first register is used to store the DVGA factor corresponding to the first sample point, and the second register is used to store the DVGA factor of the changing position. According to the read symbol index input by the subsequent module, find the write address of the first sample point of the current symbol, read the carrier data of the symbol from RAM, and update the DVGA factor at the positions where the symbol header and DVGA change.

7. The automatic gain control compensation method according to claim 6, characterized in that, The method of detecting whether the DVGA factor changes within each symbol also includes: determining whether the DVGA factor changes more than twice within each symbol; if so, reporting an anomaly.

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