Air conditioner wire controller circuit and control method thereof

Abstract

The present application discloses an air conditioner wire controller circuit and a control method thereof. The circuit includes: a control processing chip provided with a first GPIO port and a second GPIO port; a touch button unit, a WIFI unit, an infrared remote control receiving circuit, an EEPROM storage unit, an indoor unit communication unit, a power-off detection unit, a power supply circuit unit, a clock management unit, and a power management unit electrically connected to the control processing chip. When the first GPIO port outputs a high level and the second GPIO port outputs a low level, i.e., when entering power-off mode, the control processing chip turns on the low-speed clock module of the clock management unit, controls the touch button unit and other functional modules to stop running, and maintains the input of the EEPROM storage unit unchanged. Based on the solution of the present application, when entering power-off mode, the interface input of the EEPROM storage unit remains unchanged, thereby reducing the power consumption of the EEPROM of the air conditioner wire controller and increasing the service life of the EEPROM of the air conditioner wire controller, thereby reducing the cost of the air conditioner wire controller.

Description

Technical Field

[0001] The present application relates to, but is not limited to, the field of electronic circuit technology, and in particular to an air conditioner wire controller circuit and a control method thereof. Background Art

[0002] Common air conditioner wired controllers are equipped with an EEPROM memory chip. Each time a user changes a parameter, the user's settings are memorized. This allows the air conditioner to continue operating after a power outage. However, this method cannot resolve the issue of resetting the system's 24-hour clock and calendar functions. Furthermore, frequent changes to air volume, direction, and set temperatures in large public spaces significantly shorten the lifespan of the EEPROM, necessitating frequent replacement of the EEPROM device, leading to higher costs for the air conditioner wired controller. Summary of the Invention

[0003] The embodiments of the present application provide an air conditioner wired controller circuit and a control method thereof, which can effectively reduce the power consumption of the EEPROM of the air conditioner wired controller, increase the service life of the EEPROM of the air conditioner wired controller, and thus reduce the cost of the air conditioner wired controller.

[0004] In a first aspect, an embodiment of the present application provides an air conditioner wired controller circuit, comprising:

[0005] A control processing chip is provided with a first GPIO port and a second GPIO port;

[0006] The touch button unit is electrically connected to the control processing chip via the T_SDA interface and the T_SCL interface;

[0007] An indicator light unit, electrically connected to the control processing chip via a preset interface;

[0008] The WIFI unit is electrically connected to the control processing chip through the W_RXD interface and the W_TXD interface;

[0009] An infrared remote control receiving circuit is electrically connected to the control processing chip via a REC interface;

[0010] An EEPROM storage unit is electrically connected to the control processing chip via an E_SDA interface and an E_SCL interface;

[0011] The indoor unit communication unit is electrically connected to the control processing chip via the RXD interface and the TXD interface;

[0012] a power-off detection unit, electrically connected to the first GPIO port and the second GPIO port;

[0013] a power supply circuit unit, the power supply circuit unit being electrically connected to the control processing chip and the power failure detection unit respectively;

[0014] A clock management unit, comprising a high-speed clock module and a low-speed clock module, wherein the control processing chip is electrically connected to the high-speed clock module and the low-speed clock module respectively;

[0015] a power management unit, the power management unit being electrically connected to the power supply circuit unit and the control processing chip respectively;

[0016] Among them, when the first GPIO port outputs a high level and the second GPIO port outputs a low level, the preset interface outputs a high level, the T_SDA interface, the T_SCL interface, the W_RXD interface, the W_TXD interface, the REC interface, the RXD interface, and the TXD interface all output a low level, the control processing chip turns on the low-speed clock module, and the E_SDA interface and the E_SCL interface maintain input unchanged.

[0017] In some embodiments, the power-off detection unit includes an isolation optocoupler, a first resistor and a second resistor, the first pin of the isolation optocoupler is electrically connected to the first resistor, the second pin and the fourth pin of the isolation optocoupler are grounded, and the second resistor is electrically connected to the third pin of the isolation optocoupler, the first VDD power supply voltage and the first GPIO port respectively.

[0018] In some embodiments, the power-off detection unit also includes a third resistor, a first capacitor and a reverse diode, the anode of the reverse diode is grounded, the cathode of the reverse diode is electrically connected to the first pin of the isolation optocoupler, one end of the first capacitor is grounded, the other end of the first capacitor is electrically connected to the first pin of the isolation optocoupler, one end of the third resistor is grounded, and the other end of the third resistor is electrically connected to the first pin of the isolation optocoupler.

[0019] In some embodiments, the power-off detection unit further includes a first Schottky diode and a fourth resistor, the anode of the first Schottky diode is electrically connected to the first resistor, and the fourth resistor is electrically connected to the cathode of the first Schottky diode and the second GPIO port, respectively, wherein when the first GPIO port outputs a high level, the second GPIO port outputs a low level.

[0020] In some embodiments, the power supply circuit unit includes a first power supply circuit and a second capacitor, the second VDD power supply voltage is electrically connected to the first power supply circuit and the second capacitor, respectively, the first power supply circuit includes a second Schottky diode and a fifth resistor, and the fifth resistor is electrically connected to the cathode of the second Schottky diode and the second VDD power supply voltage, respectively.

[0021] In some embodiments, the power supply circuit unit also includes a second power supply circuit, the second power supply circuit includes a third Schottky diode, a fourth Schottky diode, a sixth resistor and a third capacitor, the sixth resistor is electrically connected to the anode of the third Schottky diode, the negative electrode of the third capacitor is grounded, the positive electrode of the third capacitor is electrically connected to the cathode of the third Schottky diode and the anode of the fourth Schottky diode, respectively, and the cathode of the fourth Schottky diode is electrically connected to the second VDD power supply voltage.

[0022] In a second aspect, an embodiment of the present application provides a control method based on an air conditioner wired controller circuit, which is applied to the air conditioner wired controller circuit of the embodiment of the first aspect, wherein the power management unit includes a transistor, and the method includes:

[0023] When the first GPIO port outputs a high level and the second GPIO port outputs a low level, turning off the transistor;

[0024] Controlling the preset interface to output a high level;

[0025] Control the T_SDA interface, the T_SCL interface, the W_RXD interface, the W_TXD interface, the REC interface, the RXD interface and the TXD interface to output a low level;

[0026] Disconnect the high-speed clock module and connect the low-speed clock module;

[0027] The E_SDA interface and the E_SCL interface are controlled to keep input unchanged.

[0028] In some embodiments, the EEPROM storage unit includes a first data area, a second data area, and a third data area, the first data area stores first data, the second data area stores second data, and the third data area stores third data, wherein the first data area is an active data area, and the method includes:

[0029] When the first GPIO port outputs a high level and the second GPIO port outputs a low level, the second data and the third data are synchronized into the first data.

[0030] In some embodiments, after synchronizing the second data and the third data into the first data, the method further includes:

[0031] When the first GPIO port outputs a low level and the second GPIO port outputs a high level, target data is determined from the first data, the second data and the third data, the target data includes first target data and second target data with the same data, and the data area corresponding to the first target data or the data area corresponding to the second target data is determined as the current active data area.

[0032] In some embodiments, after synchronizing the second data and the third data into the first data, the method further includes:

[0033] Turning on the high-speed clock module and disconnecting the low-speed clock module;

[0034] Turning on the transistor to control the first GPIO port to output a low level, and controlling the second GPIO port to output a high level;

[0035] Controlling the preset interface to output a low level;

[0036] Control the T_SDA interface, the T_SCL interface, the W_RXD interface, the W_TXD interface, the REC interface, the RXD interface and the TXD interface to output a high level;

[0037] The E_SDA interface and the E_SCL interface are controlled to keep input unchanged.

[0038] The embodiment of the present application discloses an air conditioner wire controller circuit and a control method thereof, the air conditioner wire controller circuit includes: a control processing chip, provided with a first GPIO port and a second GPIO port; a touch button unit, electrically connected to the control processing chip through a T_SDA interface and a T_SCL interface; an indicator light unit, electrically connected to the control processing chip through a preset interface; a WIFI unit, electrically connected to the control processing chip through a W_RXD interface and a W_TXD interface; an infrared remote control receiving circuit, electrically connected to the control processing chip through a REC interface; an EEPROM storage unit, electrically connected to the control processing chip through an E_SDA interface and an E_SCL interface; an indoor unit communication unit, electrically connected to the control processing chip through an RXD interface and a TXD interface; a power-off detection unit, electrically connected to the first GPIO port and the second GPIO port connected; a power supply circuit unit, the power supply circuit unit is electrically connected to the control processing chip and the power-off detection unit respectively; a clock management unit, including a high-speed clock module and a low-speed clock module, the control processing chip is electrically connected to the high-speed clock module and the low-speed clock module respectively; a power management unit, the power management unit is electrically connected to the power supply circuit unit and the control processing chip respectively; wherein, when the first GPIO port outputs a high level and the second GPIO port outputs a low level, the preset interface outputs a high level, the T_SDA interface, the T_SCL interface, the W_RXD interface, the W_TXD interface, the REC interface, the RXD interface, and the TXD interface all output a low level, the control processing chip turns on the low-speed clock module, and the E_SDA interface and the E_SCL interface keep the input unchanged. The control processing chip of the present application combines the power-off detection unit and the power management unit to execute the corresponding power management strategy, so that when the first GPIO port outputs a high level and the second GPIO port outputs a low level, that is, when entering the power-off mode, the input of the EEPROM storage unit interface can be kept unchanged, thereby reducing the power consumption of the EEPROM of the air conditioner wired controller, increasing the service life of the EEPROM of the air conditioner wired controller, and thus reducing the cost of the air conditioner wired controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is a circuit diagram of an air conditioner wire controller circuit provided by one embodiment of the present application;

[0040] Figure 2 is a flowchart of the steps of a control method based on an air conditioner wire controller circuit provided by another embodiment of the present application;

[0041] Figure 3 is a flowchart of the steps of a data retention method provided by another embodiment of the present application;

[0042] Figure 4 is a flowchart of the steps of a data retention method provided by another embodiment of the present application;

[0043] Figure 5 This is a flowchart of the steps of a call reset method based on an air conditioner wired controller circuit provided in another embodiment of the present application. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0045] It is understood that although the device schematics illustrate functional module divisions and the flowcharts illustrate logical sequences, in certain circumstances, the steps shown or described may be performed in a sequence that differs from the module divisions in the device or the sequence in the flowcharts. The terms "first," "second," and the like in the specification, claims, or accompanying drawings are used to distinguish similar items and are not necessarily used to describe a specific sequence or precedence.

[0046] The present application provides an air conditioner wire controller circuit and a control method thereof, the air conditioner wire controller circuit comprising: a control processing chip, provided with a first GPIO port and a second GPIO port; a touch button unit, electrically connected to the control processing chip through a T_SDA interface and a T_SCL interface; an indicator light unit, electrically connected to the control processing chip through a preset interface; a WIFI unit, electrically connected to the control processing chip through a W_RXD interface and a W_TXD interface; an infrared remote control receiving circuit, electrically connected to the control processing chip through a REC interface; an EEPROM storage unit, electrically connected to the control processing chip through an E_SDA interface and an E_SCL interface; an indoor unit communication unit, electrically connected to the control processing chip through an RXD interface and a TXD interface; a power-off detection unit, electrically connected to the first GPIO port and the second GPIO port; A power supply circuit unit, the power supply circuit unit is electrically connected to the control processing chip and the power-off detection unit respectively; a clock management unit, including a high-speed clock module and a low-speed clock module, the control processing chip is electrically connected to the high-speed clock module and the low-speed clock module respectively; a power management unit, the power management unit is electrically connected to the power supply circuit unit and the control processing chip respectively; wherein, when the first GPIO port outputs a high level and the second GPIO port outputs a low level, the preset interface outputs a high level, the T_SDA interface, the T_SCL interface, the W_RXD interface, the W_TXD interface, the REC interface, the RXD interface, and the TXD interface all output a low level, the control processing chip turns on the low-speed clock module, and the E_SDA interface and the E_SCL interface keep the input unchanged. The control processing chip of the present application combines the power-off detection unit and the power management unit to execute the corresponding power management strategy, so that when the first GPIO port outputs a high level and the second GPIO port outputs a low level, that is, when entering the power-off mode, the input of the EEPROM storage unit interface can be kept unchanged, thereby reducing the power consumption of the EEPROM of the air conditioner wired controller, increasing the service life of the EEPROM of the air conditioner wired controller, and thus reducing the cost of the air conditioner wired controller.

[0047] The embodiments of the present application are further described below with reference to the accompanying drawings.

[0048] like Figure 1 As shown, Figure 1 This is a circuit structure diagram of an air conditioner wire controller circuit provided by an embodiment of the present application. This embodiment of the present application provides an air conditioner wire controller circuit, including:

[0049] The control processing chip 101 is provided with a first GPIO port and a second GPIO port;

[0050] The touch button unit 102 is electrically connected to the control processing chip 101 via the T_SDA interface and the T_SCL interface;

[0051] The indicator light unit 103 is electrically connected to the control processing chip 101 through a preset interface;

[0052] The WIFI unit 104 is electrically connected to the control processing chip 101 through the W_RXD interface and the W_TXD interface;

[0053] The infrared remote control receiving circuit 105 is electrically connected to the control processing chip 101 via the REC interface;

[0054] The EEPROM storage unit 106 is electrically connected to the control processing chip 101 via the E_SDA interface and the E_SCL interface;

[0055] The indoor unit communication unit 107 is electrically connected to the control processing chip 101 via the RXD interface and the TXD interface;

[0056] A power-off detection unit 108 is electrically connected to the first GPIO port and the second GPIO port;

[0057] The power supply circuit unit 109 is electrically connected to the control processing chip 101 and the power failure detection unit 108;

[0058] The clock management unit includes a high-speed clock module and a low-speed clock module, and the control processing chip 101 is electrically connected to the high-speed clock module and the low-speed clock module respectively;

[0059] The power management unit 110 is electrically connected to the power supply circuit unit 109 and the control processing chip 101 respectively;

[0060] Among them, when the first GPIO port outputs a high level and the second GPIO port outputs a low level, the preset interface outputs a high level, the T_SDA interface, T_SCL interface, W_RXD interface, W_TXD interface, REC interface, RXD interface, and TXD interface all output a low level, the control processing chip 101 turns on the low-speed clock module, and the E_SDA interface and E_SCL interface maintain input unchanged.

[0061] It can be understood that the air conditioner wire controller circuit of the embodiment of the present application includes a control processing chip 101 provided with a first GPIO port and a second GPIO port; a touch button unit 102, a WIFI unit 104, an infrared remote control receiving circuit 105, an EEPROM storage unit 106, an indoor unit communication unit 107, a power-off detection unit 108, a power supply circuit unit 109, a clock management unit and a power management unit 110 electrically connected to the control processing chip 101. When the first GPIO port outputs a high level and the second GPIO port outputs a low level, the control processing chip 101 turns on the low-speed clock module of the clock management unit, the preset interface outputs a high level, and the T_SDA interface, T_SCL interface, W_RXD interface, W_TXD interface, REC interface, RXD interface, and TXD interface all output a low level, that is, the touch button unit 102, the WIFI unit 104, the infrared remote control receiving circuit 105, the indoor unit communication unit 107 and other functional modules stop running, and the EEPROM storage unit 106 keeps the input unchanged. Based on the solution of the present application, when the air conditioner wired controller circuit enters the power-off mode, it can execute a corresponding power management strategy based on the control processing chip 101, in combination with the power-off detection unit 108 and the power management unit 110, to improve the communication between the various module units in the air conditioner wired controller circuit, and keep the interface input of the EEPROM storage unit 106 unchanged, so that the autonomous processing capability of the module unit can significantly save energy consumption, reduce the power consumption of the EEPROM of the air conditioner wired controller, and increase the service life of the EEPROM of the air conditioner wired controller, thereby reducing the cost of the air conditioner wired controller.

[0062] It should be noted that the air conditioner wire controller circuit of the embodiment of the present application may also include functional modules such as an LCD display management unit, a backlight unit 111, and a buzzer unit 112. Figure 1 The backlight unit 111 is electrically connected to the control processing chip 101 through the BL interface, and the buzzer unit 112 is electrically connected to the control processing chip 101 through the BUZZ interface.

[0063] In some embodiments, in order to further reduce energy consumption and maintain the power-down mode display, the LCD display management unit is based on the system secondary clock. When the air conditioner wire controller circuit is in normal mode, the LCD display management unit updates the system clock, calendar, weekly timer, air conditioner operating status and other information at intervals of 100ms, and displays the data refreshed by the dynamic video memory through the LCD display; when the air conditioner wire controller circuit is in power-down mode, the system clock, calendar, weekly clock flash and update every 0.5 seconds, and information such as the air conditioner operating status remains displayed.

[0064] In some embodiments, the clock management unit is based on the system secondary clock. When the air conditioner wire controller circuit is in power-off mode, the clock management unit continues to work. After waking up every 0.5s, it increments the seconds, minutes, hours, weeks, and years, months, and days.

[0065] In addition, in some embodiments, the power-off detection unit 108 includes an isolation optocoupler U102, a first resistor R103, and a second resistor R104. The first pin of the isolation optocoupler U102 is electrically connected to the first resistor R103, the second pin and the fourth pin of the isolation optocoupler U102 are grounded, and the second resistor R104 is electrically connected to the third pin of the isolation optocoupler U102, the first VDD power supply voltage, and the first GPIO port, respectively.

[0066] It can be understood that when the air conditioner is powered on and the power supply is stable, the air conditioner bus outputs power to provide a stable power supply for the 86-box wire controller (i.e., a wire controller corresponding to the air conditioner wire controller circuit of this embodiment). The first pin of the isolation optocoupler U102 in the power-off detection unit 108 of the air conditioner wire controller circuit is electrically connected to the first resistor R103, the second pin of the isolation optocoupler U102 is grounded, and the second resistor R104 is electrically connected to the third pin of the isolation optocoupler U102, the first VDD power supply voltage (i.e., the bus power supply voltage) and the first GPIO port respectively; when the bus power supply voltage VDD is +5V, it can be seen that its input operating current value is within the range of 25mA, the input voltage drop is 1V-1.3V at 10mA, and the resistance at the input end is about 10mA when it is turned on, which can achieve a relatively good working state, so the input The resistor, and the value of the first resistor R103 are: R103 = (5V-1.2V) / 10mA = 380Ω, one end of the second resistor R104 is connected to the power supply voltage VDD, and the other end of the second resistor R104 is connected to the first GPIO port; when the bus power is normal, the diode of the isolation optocoupler U102 is turned on, the diode emits light, the third pin and the fourth pin of the isolation optocoupler U102 are turned on, and current passes through the second resistor R104. At this time, the isolation optocoupler U102 reaches a saturation state; when the first GPIO port of the control processing chip 101 detects a low level, the current bus power is in a normal state; on the contrary, when the bus power is off or abnormal, the diode of the isolation optocoupler U102 cannot provide a normal conduction voltage, the diode does not emit light, and the output end is cut off, causing the first GPIO port to detect a high level.

[0067] In addition, in some embodiments, the power-off detection unit 108 also includes a third resistor R106, a first capacitor C103 and a reverse diode D105, the anode of the reverse diode D105 is grounded, the cathode of the reverse diode D105 is electrically connected to the first pin of the isolation optocoupler U102, one end of the first capacitor C103 is grounded, the other end of the first capacitor C103 is electrically connected to the first pin of the isolation optocoupler U102, one end of the third resistor R106 is grounded, and the other end of the third resistor R106 is electrically connected to the first pin of the isolation optocoupler U102.

[0068] It can be understood that in order to ensure the reliability of the wire controller when performing power-off detection, the power-off detection unit 108 adds a third resistor R106, a first capacitor C103 and a reverse diode D105 at the bus input end. The anode of the reverse diode D105 is grounded, and the cathode of the reverse diode D105 is electrically connected to the first pin of the isolation optocoupler U102. One end of the first capacitor C103 is grounded, and the other end of the first capacitor C103 is electrically connected to the first pin of the isolation optocoupler U102. One end of the third resistor R106 is grounded, and the other end of the third resistor R106 is electrically connected to the first pin of the isolation optocoupler U102. The reverse diode D105 is used to prevent the input signal from being connected in reverse, to avoid the input reverse withstand voltage exceeding 5V, and to damage the diode inside the isolation optocoupler U102. The reverse diode D105 is connected to realize reverse voltage input, and the reverse voltage is limited to within 1V to ensure the normal operation of the isolation circuit. The first capacitor C103 is used for filtering. If the input signal has high-frequency interference, the parallel capacitor and series current-limiting resistor form an RC low-pass filter, filtering out higher-frequency interference. The third resistor R106, on the one hand, can remove some interference from the bus outside the series connection, so that the low-voltage interference signal input will not cause the isolation optocoupler U102 to conduct, avoiding false detection of bus power restoration, reducing the frequent wake-up of the control processing chip 101, consuming backup power, and extending the use time of the wired controller. On the other hand, the third resistor R106 can accelerate the discharge time of the first capacitor C103, which can speed up the output end to make a judgment immediately after the bus power is lost and execute the preset power management strategy.

[0069] In addition, in some embodiments, the power-off detection unit 108 further includes a first Schottky diode D104 and a fourth resistor R105, the anode of the first Schottky diode D104 is electrically connected to the first resistor R103, and the fourth resistor R105 is electrically connected to the cathode of the first Schottky diode D104 and the second GPIO port, respectively, wherein when the first GPIO port outputs a high level, the second GPIO port outputs a low level.

[0070] It can be understood that in order to ensure correct environmental detection, the power-off detection unit 108 further adds a first Schottky diode D104 and a fourth resistor R105 at the bus input end, the anode of the first Schottky diode D104 is electrically connected to the first resistor R103, and the fourth resistor R105 is electrically connected to the cathode of the first Schottky diode D104 and the second GPIO port respectively, wherein, when the first GPIO port outputs a high level, the second GPIO port outputs a low level; since the first Schottky diode D104 is connected to the fourth resistor R105, the fourth resistor R105 can perform double detection with the second GPIO interface of the control processing chip 101, ensuring that the power-off detection signal detected by the second GPIO interface corresponds to a high level and is in a power-off state.

[0071] In addition, in some embodiments, the power supply circuit unit 109 includes a first power supply circuit and a second capacitor C102, the second VDD power supply voltage is electrically connected to the first power supply circuit and the second capacitor C102, respectively, the first power supply circuit includes a second Schottky diode D101 and a fifth resistor R102, and the fifth resistor R102 is electrically connected to the cathode of the second Schottky diode D101 and the second VDD power supply voltage, respectively.

[0072] It can be understood that, based on the structure of this embodiment, when the 86-box wired controller is working normally, the bus power supply voltage +5V passes through the second Schottky diode D101, the resistance of the fifth resistor R102 is set to 18 ohms, the fifth resistor R102 is electrically connected to the second capacitor C102, and the first power supply circuit supplies power to the control processing chip 101 and the LCD display management unit, the indoor unit communication unit 107, the WIFI unit 104 and other functional modules; the function of the second Schottky diode D101 is to prevent the first power supply circuit from back-supplying the bus circuit and external devices; the resistance of the fifth resistor R102 is set to 18 ohms, which implements current limiting protection for the bus output, effectively avoiding excessive current when the 86 and the wired controller's WIFI unit 104, touch button unit 102 and other functional modules are turned on at the same time, thereby damaging the three-terminal power supply voltage regulator.

[0073] In addition, in some embodiments, the power supply circuit unit 109 also includes a second power supply circuit, which includes a third Schottky diode D102, a fourth Schottky diode D103, a sixth resistor R101 and a third capacitor C101, the sixth resistor R101 is electrically connected to the anode of the third Schottky diode D102, the negative electrode of the third capacitor C101 is grounded, the positive electrode of the third capacitor C101 is electrically connected to the cathode of the third Schottky diode D102 and the anode of the fourth Schottky diode D103, respectively, and the cathode of the fourth Schottky diode D103 is electrically connected to the second VDD power supply voltage.

[0074] It's understood that, in addition to supplying power to the wired controller components, the bus power voltage also flows through the sixth resistor R101 and third Schottky diode D102 to the second power supply circuit, storing energy in the third capacitor C101. The third capacitor C101 then supplies power to the second VDD power supply voltage via the fourth Schottky diode D103. The third Schottky diode D102 prevents the second power supply circuit from back-powering the bus circuit and external devices. The fourth Schottky diode D103 prevents excessive current from flowing when the second power supply circuit stores energy unidirectionally, potentially borrowing power from the first power supply circuit and external devices, delaying the reset sequence and causing a misalignment. The sixth resistor R101 mitigates charging surges caused by the second power supply circuit storing energy unidirectionally in the third capacitor C101, which could cause secondary contamination of the bus power supply.

[0075] In addition, refer to Figure 2 and Figure 1 One embodiment of the present application further provides a control method based on an air conditioner wired controller circuit, which is applied to the air conditioner wired controller circuit described in the above embodiment. The power management unit 110 includes a transistor Q101. The control method includes but is not limited to the following steps:

[0076] Step S110, when the first GPIO port outputs a high level and the second GPIO port outputs a low level, turning off the transistor Q101;

[0077] Step S120, controlling the preset interface to output a high level;

[0078] Step S130, controlling the T_SDA interface, T_SCL interface, W_RXD interface, W_TXD interface, REC interface, RXD interface and TXD interface to output low level;

[0079] Step S140, disconnecting the high-speed clock module and connecting the low-speed clock module;

[0080] Step S150: Control the E_SDA interface and the E_SCL interface to keep input unchanged.

[0081] It can be understood that when the bus power supply is normal, the 86-box wired controller starts to work, and the transistor Q101 is turned on, thereby turning on the VCC power supply of functional modules such as the indoor unit communication unit 107, the WIFI unit 104, and the infrared wireless remote control receiving circuit. After initialization, each circuit component enters normal operation; when the first GPIO port outputs a high level and the second GPIO port outputs a low level, the air conditioner wired controller circuit enters the power-down mode, and the control processing chip 101 executes the power management strategy. The specific steps are as follows: turn off the transistor Q101. Since the emitter of the transistor Q101 is electrically connected to the VCC power supply voltage, turning off the transistor Q101 can cut off the VCC power supply voltage; control the preset interface to output a high level, control the T_SDA interface, T_SCL interface, and W_RXD interface , the W_TXD interface, the REC interface, the RXD interface and the TXD interface all output a low level, the high-speed clock module is disconnected, the low-speed clock module is turned on, and the E_SDA interface and the E_SCL interface are controlled to keep the input unchanged. That is to say, when the air-conditioning wire controller circuit enters the power-down mode, it can be based on the control processing chip 101, combined with the power-down detection unit 108 and the power management unit 110 to execute the corresponding power management strategy, improve the communication between the various module units in the air-conditioning wire controller circuit, and keep the EEPROM storage unit 106 interface input unchanged, so that the autonomous processing capability of the module unit can significantly save energy consumption, reduce the power consumption of the EEPROM of the air-conditioning wire controller, and improve the service life of the EEPROM of the air-conditioning wire controller, thereby reducing the cost of the air-conditioning wire controller.

[0082] In some embodiments, reference Figure 3 The EEPROM storage unit 106 includes a first data area, a second data area, and a third data area. The first data area stores first data, the second data area stores second data, and the third data area stores third data. The first data area is an active data area. The control method based on the air conditioner wire controller circuit in the embodiment of the present application further includes but is not limited to the following steps:

[0083] Step S210 : When the first GPIO port outputs a high level and the second GPIO port outputs a low level, the second data and the third data are synchronized into the first data.

[0084] Reference Figure 4 In some embodiments, when executing Figure 3 After step S210 in the illustrated embodiment, the control method based on the air conditioner wired controller circuit in the embodiment of the present application further includes but is not limited to the following steps:

[0085] Step S310, when the first GPIO port outputs a low level and the second GPIO port outputs a high level, the target data is determined from the first data, the second data and the third data, the target data includes the first target data and the second target data with the same data, and the data area corresponding to the first target data or the data area corresponding to the second target data is determined as the current active data area.

[0086] It can be understood that the EEPROM storage unit 106 of the wire controller may include a first data area, a second data area, and a third data area. When the wire controller circuit is powered on and operates normally, the first data area stores working data and is an active data area, and the second data area and the third data area are inactive data areas. When the wire controller circuit is powered off, that is, when the first GPIO port outputs a high level and the second GPIO port outputs a low level, the second data and the third data are synchronized with the first data. At this time, the second data area and the third data area serve as backup data areas for the first data area. Thereafter, when the first GPIO port changes from a high level to a low level, and the second GPIO port changes from a level to an output level, When a high level is output, that is, when the power is reset, data is read from the first data area, the second data area, and the third data area respectively, and the first data, the second data, and the third data are compared and processed. The target data is determined from the first data, the second data, and the third data. The target data includes the first target data and the second target data that are identical. The data area corresponding to the first target data or the data area corresponding to the second target data is determined as the current active data area, that is, two data areas storing the same data are screened as new candidate active data areas, and a new target active area is randomly determined from the two new candidate active data areas to implement data retention management based on the EEPROM storage unit 106. In some embodiments, when the first data, the second data, and the third data are different from each other, that is, in the initialization state, the initial value data is used as the target data. At this time, the first data area, the second data area, and the third data area are all inactive areas.

[0087] In addition, refer to Figure 5 In some embodiments, when executing Figure 3 After step S210 in the illustrated embodiment, the control method based on the air conditioner wired controller circuit in the embodiment of the present application further includes but is not limited to the following steps:

[0088] Step S410, turning on the high-speed clock module and turning off the low-speed clock module;

[0089] Step S420, turning on transistor Q101, controlling the first GPIO port to output a low level, and controlling the second GPIO port to output a high level;

[0090] Step S430, controlling the preset interface to output a low level;

[0091] Step S440, controlling the T_SDA interface, T_SCL interface, W_RXD interface, W_TXD interface, REC interface, RXD interface and TXD interface to output high level;

[0092] Step S450: Control the E_SDA interface and the E_SCL interface to keep input unchanged.

[0093] It can be understood that after the 86-box wired controller is in power-down mode, the bus power voltage detects that the first GPIO interface changes from outputting a high level to a low level, generates a falling edge signal interrupt, and the double detection interface, that is, the second GPIO interface detects a high level. The wired controller determines that the external bus is powered again, and at this time, the power management unit 110 performs a reset action. The specific steps are as follows: turning on the high-speed clock module, disconnecting the low-speed clock module, turning on the transistor Q101, controlling the first GPIO port to output a low level, controlling the second GPIO port to output a high level, controlling the preset interface to output a low level, controlling the T_SDA interface, T_SCL interface, W_RXD interface, W_TXD interface, REC interface, RXD interface and TXD interface to output a high level, and controlling the E_SDA interface and E_SCL interface to maintain input unchanged, thereby returning the wired controller from power-down mode to normal mode, so that functional modules such as the indoor unit communication unit 107, the WIFI unit 104, and the infrared wireless remote control receiving circuit continue to operate based on the working data before power failure.

Claims

1. An air conditioner wire controller circuit, characterized in that: include: A control processing chip is provided with a first GPIO port and a second GPIO port; The touch button unit is electrically connected to the control processing chip via the T_SDA interface and the T_SCL interface; An indicator light unit, electrically connected to the control processing chip via a preset interface; The WIFI unit is electrically connected to the control processing chip through the W_RXD interface and the W_TXD interface; An infrared remote control receiving circuit is electrically connected to the control processing chip via a REC interface; An EEPROM storage unit is electrically connected to the control processing chip via an E_SDA interface and an E_SCL interface; The indoor unit communication unit is electrically connected to the control processing chip via the RXD interface and the TXD interface; a power-off detection unit, electrically connected to the first GPIO port and the second GPIO port; a power supply circuit unit, the power supply circuit unit being electrically connected to the control processing chip and the power failure detection unit respectively; A clock management unit, comprising a high-speed clock module and a low-speed clock module, wherein the control processing chip is electrically connected to the high-speed clock module and the low-speed clock module respectively; a power management unit, the power management unit being electrically connected to the power supply circuit unit and the control processing chip respectively; Among them, when the first GPIO port outputs a high level and the second GPIO port outputs a low level, the preset interface outputs a high level, the T_SDA interface, the T_SCL interface, the W_RXD interface, the W_TXD interface, the REC interface, the RXD interface, and the TXD interface all output a low level, the control processing chip turns on the low-speed clock module, and the E_SDA interface and the E_SCL interface maintain input unchanged; Wherein, the power-off detection unit includes an isolation optocoupler, a first resistor and a second resistor, the first pin of the isolation optocoupler is electrically connected to the first resistor, the second pin and the fourth pin of the isolation optocoupler are grounded, and the second resistor is electrically connected to the third pin of the isolation optocoupler, the first VDD power supply voltage and the first GPIO port respectively; The power-off detection unit also includes a third resistor, a first capacitor and a reverse diode, the anode of the reverse diode is grounded, the cathode of the reverse diode is electrically connected to the first pin of the isolation optocoupler, one end of the first capacitor is grounded, the other end of the first capacitor is electrically connected to the first pin of the isolation optocoupler, one end of the third resistor is grounded, and the other end of the third resistor is electrically connected to the first pin of the isolation optocoupler.

2. The air conditioner wired controller circuit according to claim 1, characterized in that: The power-off detection unit also includes a first Schottky diode and a fourth resistor, the anode of the first Schottky diode is electrically connected to the first resistor, and the fourth resistor is electrically connected to the cathode of the first Schottky diode and the second GPIO port, respectively, wherein when the first GPIO port outputs a high level, the second GPIO port outputs a low level.

3. The air conditioner wired controller circuit according to claim 1, characterized in that: The power supply circuit unit includes a first power supply circuit and a second capacitor, the second VDD power supply voltage is electrically connected to the first power supply circuit and the second capacitor respectively, the first power supply circuit includes a second Schottky diode and a fifth resistor, and the fifth resistor is electrically connected to the cathode of the second Schottky diode and the second VDD power supply voltage respectively.

4. The air conditioner wired controller circuit according to claim 3, characterized in that: The power supply circuit unit also includes a second power supply circuit, which includes a third Schottky diode, a fourth Schottky diode, a sixth resistor and a third capacitor, the sixth resistor is electrically connected to the anode of the third Schottky diode, the negative electrode of the third capacitor is grounded, the positive electrode of the third capacitor is electrically connected to the cathode of the third Schottky diode and the anode of the fourth Schottky diode, respectively, and the cathode of the fourth Schottky diode is electrically connected to the second VDD power supply voltage.

5. A control method based on an air conditioner wire controller circuit, characterized in that: Applied to the air conditioner wire controller circuit according to any one of claims 1 to 4, the power management unit includes a transistor, and the method includes: When the first GPIO port outputs a high level and the second GPIO port outputs a low level, turning off the transistor; Controlling the preset interface to output a high level; Control the T_SDA interface, the T_SCL interface, the W_RXD interface, the W_TXD interface, the REC interface, the RXD interface and the TXD interface to output a low level; Disconnect the high-speed clock module and connect the low-speed clock module; The E_SDA interface and the E_SCL interface are controlled to keep input unchanged.

6. The control method based on the air conditioner wire controller circuit according to claim 5, characterized in that: The EEPROM storage unit includes a first data area, a second data area, and a third data area, wherein the first data area stores first data, the second data area stores second data, and the third data area stores third data, wherein the first data area is an active data area, and the method includes: When the first GPIO port outputs a high level and the second GPIO port outputs a low level, the second data and the third data are synchronized into the first data.

7. The control method based on the air conditioner wire controller circuit according to claim 6, characterized in that: After synchronizing the second data and the third data into the first data, the method further includes: When the first GPIO port outputs a low level and the second GPIO port outputs a high level, target data is determined from the first data, the second data and the third data, the target data includes first target data and second target data with the same data, and the data area corresponding to the first target data or the data area corresponding to the second target data is determined as the current active data area.

8. The control method based on the air conditioner wire controller circuit according to claim 6, characterized in that: After synchronizing the second data and the third data into the first data, the method further includes: Turning on the high-speed clock module and disconnecting the low-speed clock module; Turning on the transistor to control the first GPIO port to output a low level, and controlling the second GPIO port to output a high level; Controlling the preset interface to output a low level; Control the T_SDA interface, the T_SCL interface, the W_RXD interface, the W_TXD interface, the REC interface, the RXD interface and the TXD interface to output a high level; The E_SDA interface and the E_SCL interface are controlled to keep input unchanged.

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