Capacitance testing circuit and testing method thereof

Abstract

The application provides a capacitor test circuit and a test method thereof. The test circuit comprises a charging voltage generating circuit, a QVCM test circuit and a capacitor to be tested. The charging voltage generating circuit comprises a first transmission gate, a second transmission gate, a first source measurement unit and a second source measurement unit. The input ends of the first transmission gate and the second transmission gate are connected to the first source measurement unit and the second source measurement unit respectively. The output ends of the first transmission gate and the second transmission gate are connected to a first node. The QVCM test circuit comprises a third transmission gate, a fourth transmission gate, a third source measurement unit and a fourth source measurement unit. The output ends of the third transmission gate and the fourth transmission gate are connected to the third source measurement unit and the fourth source measurement unit respectively. The input ends of the third transmission gate and the fourth transmission gate are connected to a second node. The gate G end of the capacitor to be tested is connected to the second node, and the substrate B end, the source S end and the drain D end of the capacitor to be tested are connected to the first node.

Description

Technical Field

[0001] This invention belongs to the field of chip testing, and in particular relates to a capacitance testing circuit and its testing method. Background Technology

[0002] In the design and manufacturing process of integrated circuits, capacitors are indispensable and crucial components in the vast majority of integrated circuit chips. Correspondingly, capacitance testing is also a very important part, directly affecting the performance and quality of integrated circuit chips. Under the background of design for manufacturability, in order to improve the yield of integrated circuit products and shorten the yield maturity cycle, the industry generally adopts testing methods based on specially designed test chips. Testing these test chips obtains the data necessary for improving manufacturing processes and design yield. Integrating capacitance testing circuits into test chips to measure the capacitance of target structures is a common testing method.

[0003] The most common testing method is CBCM (Charge Based Capacitance Measurement), especially for measuring BEOL (back-end) or interconnect capacitance. When using CBCM to test capacitance, due to charge leakage within the capacitor, using the measured current as the charging current will introduce errors in the capacitance value measurement. Therefore, for femto farad level capacitors (such as FEOL capacitance), the traditional CBCM testing method cannot meet the accuracy requirements.

[0004] Related technologies also propose testing methods for QVCM (quadrature-clocked voltage-dependent capacitance measurement), such as... Figure 1As shown: Multiple devices under test (DUTs) are connected in parallel at one end. An ammeter Im is connected to a MOSFET controlled by clock T1 (CLK_Qm), and an ammeter Ip is connected to a MOSFET controlled by clock T2 (CLK_Qp). The MOSFETs controlled by clocks T1 and T2 must be identical. When a clock signal with frequency f, amplitude Vamp, and bias voltage Vbias is input to the input of DUT1, the inputs of the other DUTs are grounded. The current of DUT1 is measured in Im and Ip through clock circuits T1 and T2, respectively. Clock circuits T1 and T2 are inversely opposed to ensure that only one MOSFET is conducting at a time. CLK-I is a clock signal orthogonal to T1 and T2, used to charge and discharge the DUTs. The charging and discharging currents are measured in Im / Ip through different paths. The capacitance value measured under CLK-I input conditions is:

[0005]

[0006] Where Im0 and Ip0 are the values ​​of the ammeter Im and Ip when all dut are grounded.

[0007] The QVCM testing method described above overcomes the errors and shortcomings of CBCM, such as charge injection, and has become the main testing method for front-end capacitance measurement. However, it still has shortcomings such as a relatively simple measurement method and the need to improve measurement accuracy.

[0008] Therefore, optimizing capacitance testing circuits and methods to further enrich measurement methods and improve measurement accuracy is an urgent problem to be solved. Summary of the Invention

[0009] The present invention addresses all or part of the problems of the prior art by providing a capacitance testing circuit and testing method to further enrich measurement methods and improve measurement accuracy.

[0010] This invention provides a capacitance testing circuit, comprising:

[0011] The circuit includes a charging voltage generation circuit, a QVCM test circuit, and the capacitor under test; among which...

[0012] The charging voltage generation circuit includes a first transmission gate, a second transmission gate, a first source measurement unit, and a second source measurement unit; wherein, the input terminals of the first transmission gate and the second transmission gate are respectively connected to the first source measurement unit and the second source measurement unit, and the first source measurement unit and the second source measurement unit are respectively used to provide voltage; the output terminals of the first transmission gate and the second transmission gate are respectively connected to a first node, and the first node is used as the voltage output terminal of the charging voltage generation circuit; the first control terminal of the first transmission gate is connected to the second control terminal of the second transmission gate, and the second control terminal of the first transmission gate is connected to the first control terminal of the second transmission gate, and the first control terminal of the first transmission gate and the second control terminal of the second transmission gate are used to input a pair of opposite first clock signals;

[0013] The QVCM test circuit includes a third transmission gate, a fourth transmission gate, a third source measurement unit, and a fourth source measurement unit. The outputs of the third and fourth transmission gates are respectively connected to the third and fourth source measurement units, which are used to measure current. The inputs of the third and fourth transmission gates are respectively connected to a second node, which serves as the voltage input of the QVCM test circuit. The first control terminal of the third transmission gate is connected to the second control terminal of the fourth transmission gate, and the second control terminal of the third transmission gate is connected to the first control terminal of the fourth transmission gate. The first and second control terminals of the third and fourth transmission gates are used to input a pair of opposite second clock signals.

[0014] The gate G terminal of the capacitor under test is connected to the second node, and the substrate B terminal, source S terminal, and drain D terminal of the capacitor under test are connected to the first node.

[0015] The capacitance testing circuit also includes:

[0016] A different test item conversion circuit is provided, and the charging voltage generation circuit is connected to the capacitor under test through the different test item conversion circuit.

[0017] The different test item conversion circuit is configured to perform conversion tests on different test items, including the total gate capacitance, the gate capacitance to the substrate, and the gate capacitance to the source and drain under the substrate voltage.

[0018] The different test item conversion circuit includes:

[0019] The first multiplexer is connected to the substrate B terminal of each capacitor under test.

[0020] The second multiplexer is connected to the source (S) and drain (D) terminals of each capacitor under test; wherein,

[0021] The first multiplexer includes a fifth transmission gate and a sixth transmission gate. The input of the fifth transmission gate is connected to the first node, and the input of the sixth transmission gate is connected to the Bias voltage signal. The outputs of the fifth and sixth transmission gates are connected to the substrate B terminal of each capacitor under test. The first control terminal of the fifth transmission gate is connected to the second control terminal of the sixth transmission gate, and the second control terminal of the sixth transmission gate is connected to the first control terminal of the fifth transmission gate. The first and second control terminals of the fifth and sixth transmission gates are used to input a pair of opposite third control signals.

[0022] The second multiplexer includes a seventh transmission gate and an eighth transmission gate. The input of the seventh transmission gate is connected to the first node, and the input of the eighth transmission gate is connected to the Bias voltage signal. The outputs of the seventh and eighth transmission gates are connected to the source (S) and drain (D) terminals of each capacitor under test. The first control terminal of the seventh transmission gate is connected to the second control terminal of the eighth transmission gate, and the second control terminal of the eighth transmission gate is connected to the first control terminal of the seventh transmission gate. The first and second control terminals of the seventh and eighth transmission gates are used to input a pair of opposite fourth control signals.

[0023] The specific configuration of the different test item conversion circuit is as follows:

[0024] The seventh transmission gate is turned on and the eighth transmission gate is turned off; the fifth transmission gate is turned on and the sixth transmission gate is turned off; the source S terminal, drain D terminal and substrate B terminal of the capacitor under test are connected to the first node; the QVCM test circuit measures the total gate capacitance Cg-g at the G terminal.

[0025] The seventh transmission gate is turned on and the eighth transmission gate is turned off. The fifth transmission gate is turned off and the sixth transmission gate is turned on. The source S terminal and the drain D terminal of the capacitor under test are connected to the first node. The substrate B terminal of the capacitor under test is connected to the Bias voltage signal. The QVCM test circuit measures the gate-to-source and drain capacitance Cg-sd at the gate G terminal under the substrate voltage.

[0026] The seventh transmission gate is off and the eighth transmission gate is on; the fifth transmission gate is on and the sixth transmission gate is off. The source (S) and drain (D) terminals of the capacitor under test are connected to the Bias voltage signal, and the substrate (B) terminal of the capacitor under test is connected to the first node. The QVCM test circuit measures the gate-to-substrate capacitance Cg-b at the gate (G) terminal. This specific configuration of the different test item conversion circuit allows for the testing of three test items—total gate capacitance Cg-g, gate-to-substrate capacitance Cg-b, and gate-to-source and gate-to-drain capacitance Cg-sd under substrate voltage—without altering the internal chip structure. This optimizes the test system and improves test efficiency.

[0027] The capacitance testing circuit also includes:

[0028] The QVCM test circuit is connected to multiple capacitors under test via the addressing circuit. The addressing circuit is used to select the capacitors under test for connectivity testing.

[0029] The addressing circuit includes:

[0030] At least one decoder and multiple third multiplexers, the number of which is the same as the number of the capacitors under test and are connected in a one-to-one correspondence;

[0031] The output terminal of the third multiplexer is connected to the gate G terminal of the capacitor under test, and the two input terminals of each third multiplexer are respectively connected to the second node and the Disable signal;

[0032] The decoder has X digital signal input terminals, where X = log₂N. When log₂N is not an integer, X is an integer greater than log₂N with a difference less than 1. The decoder's output terminals are connected to the corresponding third multiplexer to output addressing signals for selecting the capacitor under test. Thus, the application of the addressing circuit not only saves on the number of pads in the test chip, significantly improving its area utilization, but also allows for parallel testing of capacitors under test in different QVCM circuit units through a unique circuit setup, improving testing efficiency.

[0033] The present invention also provides a capacitance testing method, which uses the above-described capacitance testing circuit to perform capacitance testing on the capacitor device under test.

[0034] The testing method includes:

[0035] The first source measurement unit and the second source measurement unit respectively provide the first voltage V. Low Second voltage V High A first clock signal with frequency f is provided to generate a first square wave voltage, the amplitude of which is V.amp The equivalent voltage is V m The frequency is f, where,

[0036] The third and fourth source measurement units respectively measure and obtain the first current I. 11 Second current I 21 ;

[0037] The first source measurement unit and the second source measurement unit respectively provide the second voltage V. High and the first voltage V Low A first clock signal with frequency f is provided to generate a second square wave voltage, the amplitude of which is V. amp The equivalent voltage is V m The frequency is f, where,

[0038] The third current I is obtained by measuring the third source measurement unit and the fourth source measurement unit respectively. 12 and the fourth current I 22 ;

[0039] The capacitance C of the capacitor under test is calculated using the following formula:

[0040]

[0041] In this way, by exchanging the voltages provided by the first source measurement unit and the second source measurement unit, the proportion of charging and discharging current in the measured current can be increased, thereby improving the measurement accuracy.

[0042] Before calculating the capacitance value C of the capacitor under test, the capacitance testing method further includes:

[0043] Within the bias range of the equivalent voltage Vm, the equivalent voltage Vm is divided equally by M voltage dividing points with an adjacent interval of ΔV, where M is an integer greater than 1;

[0044] Under the conditions of charging voltage amplitude Vamp=△V and Vm=-Vmin~Vmax at each voltage division point, calculate the capacitance value under the corresponding voltage bias at each voltage division point.

[0045] After calculating the capacitance value C of the capacitor under test, the capacitance testing method further includes:

[0046] A CV curve is plotted based on the voltage at each voltage division point and the capacitance value calculated under that voltage condition.

[0047] In some embodiments, the third source measurement unit and the fourth source measurement unit are respectively grounded; the first clock signal and the second clock signal have the same frequency and a phase difference of 90°.

[0048] Compared with the prior art, the main beneficial effects of the present invention are:

[0049] This invention provides a capacitance testing circuit that applies a square wave voltage to the substrate (B terminal), source (S terminal), and drain (D terminal) of the capacitor under test, and measures the charging and discharging current at the gate (G terminal) of the capacitor under test. This can expand the application scope and methods of existing QVCM testing circuits. Based on the capacitance testing circuit and the capacitance testing method adapted to it, the impact of process-induced mismatch between the first and second transmission gates on the measurement can be reduced, and the proportion of charging and discharging current in the measured current can be increased, thereby improving the measurement accuracy. Attached Figure Description

[0050] Figure 1 This is a schematic diagram of the QVCM testing method in related technologies.

[0051] Figure 2 This is a schematic diagram of the capacitance testing circuit provided in an embodiment of the present invention;

[0052] Figure 3 This is a schematic diagram of the capacitance testing circuit provided in another embodiment of the present invention;

[0053] Figure 4 The circuit structure diagram of the different test item conversion circuit provided in the embodiments of the present invention;

[0054] Figure 5 This invention provides simplified structural diagrams of the Cg-g, Cg-sd, and Cg-b phase capacitors for testing the device under test in embodiments of the invention.

[0055] Figure 6 A schematic diagram of the first clock signal, the second clock signal, the first square wave voltage, and the second square wave voltage in the test method provided in the embodiments of the present invention;

[0056] Figure 7 This is a schematic diagram of the CV curve in the test method provided by the present invention. Detailed Implementation

[0057] The technical solutions in specific embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0058] QVCM (quadrature-clocked voltage-dependent capacitance measurement) is an on-chip capacitance measurement method commonly used in advanced processes to obtain the CV curve of front-end capacitance. Due to its simple design and high measurement accuracy in principle, it is widely used.

[0059] The typical method for measuring QVCM capacitance is to apply a small square wave signal to the gate of the MOSFET, measure the charging and discharging current at the source, drain, and substrate, and calculate the capacitance under the bias voltage by means of charge conservation.

[0060] However, the above measurement methods are too simplistic, and the measurement accuracy still needs to be improved.

[0061] Based on this, see Appendix Figure 2 This application provides a capacitance testing circuit, including:

[0062] The circuit consists of a charging voltage generation circuit 10, a QVCM test circuit 20, and a capacitor under test 30; among which,

[0063] The charging voltage generation circuit 10 includes a first transmission gate 11, a second transmission gate 12, a first source measurement unit 13, and a second source measurement unit 14. The input terminals of the first transmission gate 11 and the second transmission gate 12 are respectively connected to the first source measurement unit 13 and the second source measurement unit 14, which are used to provide voltage. The output terminals of the first transmission gate 11 and the second transmission gate 12 are respectively connected to a first node 15, which serves as the voltage output terminal of the charging voltage generation circuit 10. The first control terminal of the first transmission gate 11 is connected to the second control terminal of the second transmission gate 12, and the second control terminal of the first transmission gate 11 is connected to the first control terminal of the second transmission gate 12. The first control terminal of the first transmission gate 11 and the second control terminal of the second transmission gate 12 are used to input a pair of opposite first clock signals.

[0064] The QVCM test circuit 20 includes a third transmission gate 21, a fourth transmission gate 22, a third source measurement unit 23, and a fourth source measurement unit 24. The outputs of the third transmission gate 21 and the fourth transmission gate 22 are connected to the third source measurement unit 23 and the fourth source measurement unit 24, respectively, and the third source measurement unit 23 and the fourth source measurement unit 24 are used to measure current. The inputs of the third transmission gate 21 and the fourth transmission gate 22 are connected to a second node 25, which serves as the voltage input of the QVCM test circuit 20. The first control terminal of the third transmission gate 21 is connected to the second control terminal of the fourth transmission gate 22, and the second control terminal of the third transmission gate 21 is connected to the first control terminal of the fourth transmission gate 22. The first control terminal of the third transmission gate 21 and the second control terminal of the fourth transmission gate 22 are used to input a pair of opposite second clock signals.

[0065] The gate G terminal of the capacitor under test 30 is connected to the second node 25, and the substrate B terminal, source S terminal and drain D terminal of the capacitor under test 30 are connected to the first node 15.

[0066] Here, the Source Measurement Unit (SMU), also known as a source meter, has both measurement and source functions, enabling simultaneous and accurate acquisition and measurement of voltage and / or current values. A source meter may include current and voltage sources, current and voltage measurements, and scanning capabilities.

[0067] See appendix Figure 2 CLKa1 and CLKa2 are a pair of opposite first clock signals, and CLKb1 and CLKb2 are a pair of opposite second clock signals. Here, the first clock signal can be a square wave controlling the switching of the first and second transmission gates; the second clock signal can be a square wave controlling the switching of the third and fourth transmission gates.

[0068] Specifically, the charging voltage generating circuit 10 includes a first transmission gate 11 and a second transmission gate 12. Each transmission gate has four ports: the first port is the connection point between the two transmission gates, the second port is the clock signal input, and the third port is the excitation signal input. At the excitation signal input, the first transmission gate 11 is directly connected to the first source measurement unit 13, which provides a fixed-point voltage to the first transmission gate 11. The second transmission gate 12 is directly connected to the second source measurement unit 14, which provides a fixed-point voltage to the second transmission gate 12. The clock signal input includes two NOT gates, and a wire connects the two NOT gates to the fourth port of the two transmission gates. The connection point between the two transmission gates serves as the voltage output of the charging voltage generating circuit 10.

[0069] The QVCM test circuit 20 includes two parallel third transmission gates 21 and fourth transmission gates 22. Each transmission gate has four ports, one of which is the connection point between the two transmission gates, and the other three ports are the clock signal input, the test input, and the voltage input, respectively. At the test input, the third transmission gate 21 is directly connected to the third source measurement unit 23, which measures the current. The fourth transmission gate 22 is directly connected to the fourth source measurement unit 24, which measures the current. The clock signal input includes two NOT gates, and a wire connects the two NOT gates to the connection point between the two transmission gates.

[0070] The gate (G) terminal of the capacitor under test is connected to the voltage input terminal of the QVCM test circuit, and the substrate (B), source (S), and drain (D) terminals of the capacitor under test are all connected to the voltage output terminal of the voltage generation circuit.

[0071] In some embodiments, see Appendix Figure 3 The capacitance test circuit also includes:

[0072] The different test item conversion circuit 40 and the charging voltage generation circuit 10 are connected to the capacitor under test 30 through the different test item conversion circuit 40.

[0073] The different test item conversion circuit 40 is configured to perform conversion tests on different test items, including the total gate capacitance Cg-g, the gate capacitance to the substrate Cg-b, and the gate capacitance to the source and drain under the substrate voltage Cg-sd.

[0074] Specifically, a different test item conversion circuit is set between the capacitor under test and the charging voltage generation circuit. Using the different test item conversion circuit, the three test items of the capacitor under test can be converted and tested: total gate capacitance Cg-g, gate-to-substrate capacitance Cg-b, and gate-to-source and drain capacitance Cg-sd under substrate voltage.

[0075] In some embodiments, see Appendix Figure 4 The different test item conversion circuit 40 includes:

[0076] The first multiplexer 41 is connected to the substrate B terminal of each capacitor under test 30.

[0077] The second multiplexer 42 is connected to the source (S) and drain (D) terminals of each capacitor under test 30; wherein...

[0078] The first multiplexer 41 includes a fifth transmission gate 411 and a sixth transmission gate 412. The input of the fifth transmission gate 411 is connected to the first node 15, and the input of the sixth transmission gate 412 is connected to the Bias voltage signal. The outputs of the fifth transmission gate 411 and the sixth transmission gate 412 are connected to the substrate B terminal of each capacitor under test. The first control terminal of the fifth transmission gate 411 is connected to the second control terminal of the sixth transmission gate 412, and the second control terminal of the sixth transmission gate 412 is connected to the first control terminal of the fifth transmission gate 411. The first control terminal of the fifth transmission gate 411 and the second control terminal of the sixth transmission gate 412 are used to input a pair of opposite third control signals.

[0079] The second multiplexer 42 includes a seventh transmission gate 421 and an eighth transmission gate 422. The input of the seventh transmission gate 421 is connected to the first node 15, and the input of the eighth transmission gate 422 is connected to the Bias voltage signal. The outputs of the seventh transmission gate 421 and the eighth transmission gate 422 are connected to the source (S) and drain (D) terminals of each capacitor under test 30. The first control terminal of the seventh transmission gate 421 is connected to the second control terminal of the eighth transmission gate 422, and the second control terminal of the eighth transmission gate 422 is connected to the first control terminal of the seventh transmission gate 421. The first control terminal of the seventh transmission gate 421 and the second control terminal of the eighth transmission gate 422 are used to input a pair of opposite fourth control signals.

[0080] Here, the multiplexer can be a 2-to-1 selector, such as the MUX21 selector. The third control signal can be used to control the switching of the fifth and sixth transmission gates; the fourth control signal is used to control the switching of the seventh and eighth transmission gates.

[0081] Specifically, the different test item conversion circuit includes two multiplexers. One multiplexer is connected to the substrate B terminal of all capacitors under test, and the other multiplexer is connected to the source S and drain D terminals of all capacitors under test. Each multiplexer consists of two transmission gates. The output terminals of the two transmission gates are connected to the capacitor under test. The input terminal of one transmission gate is connected to the Bias voltage signal, and the input terminal of the other transmission gate is connected to the voltage output terminal of the charging voltage generation circuit.

[0082] In some embodiments, see Appendix Figure 4 and attached Figure 5 The specific configuration of the different test item conversion circuit 40 is as follows:

[0083] In the second multiplexer 42, the seventh transmission gate 421 is turned on and the eighth transmission gate 422 is turned off. In the first multiplexer 41, the fifth transmission gate 411 is turned on and the sixth transmission gate 412 is turned off. The source S terminal, drain D terminal and substrate B terminal of the capacitor under test 30 are connected to the first node 15. The QVCM test circuit measures the total gate capacitance Cg-g at the G terminal.

[0084] In the second multiplexer 42, the seventh transmission gate 421 is turned on and the eighth transmission gate 422 is turned off. In the first multiplexer 41, the fifth transmission gate 411 is turned off and the sixth transmission gate 412 is turned on. The source S terminal and the drain D terminal of the capacitor under test 30 are connected to the first node 15. The substrate B terminal of the capacitor under test is connected to the Bias voltage signal. The QVCM test circuit measures the gate-to-source and drain capacitance Cg-sd under the substrate voltage at the gate G terminal.

[0085] In the second multiplexer 42, the seventh transmission gate 421 is off and the eighth transmission gate 422 is on. In the first multiplexer 41, the fifth transmission gate 411 is on and the sixth transmission gate 412 is off. The source S terminal and the drain D terminal of the capacitor under test 30 are connected to the Bias voltage signal. The substrate B terminal of the capacitor under test 30 is connected to the first node 15. The QVCM test circuit measures the capacitance Cg-b between the gate and the substrate at the gate G terminal.

[0086] It should be noted that in the capacitance Cg-sd between the gate, source, and drain at the substrate voltage, the substrate voltage is the Bias voltage signal connected to the B terminal of the substrate.

[0087] Specifically, when using different test item conversion circuits to switch between the total gate capacitance Cg-g, the gate-to-substrate capacitance Cg-b, and the gate-to-source and drain capacitance Cg-sd under substrate voltage, the conversion method for different test items is as follows:

[0088] Define the digital signals of the S and D terminal multiplexers as the first control signal; define the digital signal of the B terminal multiplexer as the second control signal Signal-5. When the logic state of the control signal is "1", the transmission gate is selected to connect to the first node 15 and connected to the capacitor charging and discharging circuit; when the logic state of the control signal is "0", the transmission gate is selected to connect to the Bias terminal. The voltage value of the pad connected to the Bias terminal is selected according to the specific test item. In the S-D multiplexer of the device under test (DUT), the transmission gate connected to the first node 15 is turned on, and the transmission gate connected to the Bias terminal is turned off. In the B-D multiplexer, the transmission gate connected to the first node 15 is turned on, and the transmission gate connected to the Bias terminal is turned off. At this time, the logic state of the first control signal is "1", and the logic state of the second control signal is "1". The D, S, and B terminals of the DUT are all connected to the first node 15, and Cg-g is measured at the G terminal. In the S-D multiplexer of the DUT, the transmission gate connected to the first node 15 is turned on, and the transmission gate connected to the Bias terminal is turned off. In the B-D multiplexer, the transmission gate connected to the Bias terminal is turned on, and the transmission gate connected to the first node 15 is turned off. At this time, the logic state of the first control signal is "1", and the logic state of the second control signal is "0". At this time, the D and S terminals of the DUT are connected to a test... The B terminal of the capacitor under test is connected to the Bias terminal. According to the voltage requirement of the B terminal during Cg-sd measurement, a voltage Vbias is applied to the Bias terminal, and Cg-sd is measured at the G terminal. In the multiplexer of the S and D terminals of the capacitor under test, the transmission gate connected to the Bias terminal is turned on, and the transmission gate connected to the VE terminal is turned off. In the multiplexer of the B terminal, the transmission gate connected to the first node 15 is turned on, and the transmission gate connected to the Bias terminal is turned off. At this time, the logic state of the first control signal is "0" and the logic state of the second control signal is "1". The D and S terminals of the capacitor under test are connected to the test point Bias. According to the voltage requirement of the S and D terminals during Cg-b measurement, a voltage Vbias is applied to the Bias terminal. The B terminal of the capacitor under test is connected to the first node 15. The generated charging and discharging voltage is applied to the B terminal, and Cg-b is measured at the test point at the G terminal.

[0089] In some embodiments, see Appendix Figure 3 The capacitance test circuit also includes:

[0090] The addressing circuit 50 and the QVCM test circuit 20 are connected to multiple capacitors under test 30 through the addressing circuit 50. The addressing circuit 50 is used to select the capacitors under test 30 for continuity testing.

[0091] Specifically, if there are multiple capacitors under test, an addressing circuit is also connected between the capacitors under test and the QVCM test circuit. The addressing circuit can be used to select the capacitors under test for connectivity testing.

[0092] Addressing circuit 50 includes:

[0093] At least one decoder (not shown in the figure) and multiple third multiplexers 51, the number of which is the same as the number of capacitors under test 30 and they are connected in a one-to-one correspondence.

[0094] The output of the third multiplexer 51 is connected to the gate G terminal of the capacitor under test 30, and the two input terminals of each third multiplexer 51 are respectively connected to the second node 25 and the Disable signal.

[0095] The decoder has X digital signal input terminals, where X = log2N. When log2N is not an integer, X is an integer greater than log2N and with a difference less than 1. The decoder's output terminals are connected to the corresponding third multiplexers to output address signals for selecting the capacitor under test.

[0096] For example, when the number of third multiplexers 51 is 8, the decoder has 3 digital signal inputs. See Appendix Figure 3 When the number of third multiplexers 51 is 4, the decoder has 2 digital signal input terminals. DUT1, DUT2, DUT3, and DUT4 are connected to the 4 third multiplexers respectively. When the decoder outputs an address signal, a unique capacitor under test is selected. This capacitor under test is tested in the equivalent voltage bias circuit. The other multiplexers are connected to the disable pad, where the voltage is the same as the voltage output of the charging voltage generation circuit. This ensures that the other capacitors under test have no voltage bias and do not form a complete circuit path, thus avoiding interference with the test of the selected capacitor under test and improving test accuracy. See Appendix. Figure 3 When the number of the third multiplexers 51 is 4, the address signals output by the decoder can be, for example, EN_0, EN_1, EN_2, and EN_3.

[0097] The present invention also provides a capacitance testing method, which uses the above-described capacitance testing circuit to perform capacitance testing on the capacitor device under test.

[0098] In some embodiments, see Appendix Figure 6 The testing methods include:

[0099] The first source measurement unit and the second source measurement unit respectively provide the first voltage V. Low Second voltage V High A first clock signal with frequency f is provided to generate a first square wave voltage, the amplitude of which is V. amp The equivalent voltage is V m The frequency is f, where,

[0100] The third and fourth source measurement units respectively measure and obtain the first current I. 11 Second current I 21 ;

[0101] The first source measurement unit and the second source measurement unit respectively provide the second voltage V. High and the first voltage V Low A first clock signal with frequency f is provided to generate a second square wave voltage, the amplitude of which is V. amp The equivalent voltage is V m The frequency is f, where,

[0102] The third current I is obtained by measuring the third source measurement unit and the fourth source measurement unit respectively. 12 and the fourth current I 22 ;

[0103] In the example case, the capacitance C of the capacitor under test can be calculated using the following formula:

[0104]

[0105] In this way, by exchanging the voltages provided by the first source measurement unit and the second source measurement unit, the proportion of charging and discharging current in the measured current can be increased, thereby improving the measurement accuracy.

[0106] Here, the frequency f can be, for example, 1 MHz, and the amplitude Vamp can range from, for example, 0.05 V to 1 V.

[0107] In some embodiments, before calculating the capacitance value C of the capacitor under test, the capacitance testing method further includes:

[0108] Within the bias range of the equivalent voltage Vm, the equivalent voltage Vm is divided equally using M voltage dividing points with an adjacent interval of ΔV, where M is an integer greater than 1;

[0109] Under the conditions of charging voltage amplitude Vamp=△V and Vm=-Vmin~Vmax at each voltage division point, calculate the capacitance value under the corresponding voltage bias at each voltage division point.

[0110] In some embodiments, see Appendix Figure 7 After calculating the capacitance value C of the capacitor under test, the capacitance test method also includes:

[0111] A CV curve is plotted based on the voltage at each voltage division point and the capacitance value calculated under that voltage condition.

[0112] It is worth noting that, theoretically, based on the principle of infinite division of the differential, the smaller the ΔV, the more accurate the CV curve. However, in actual measurement, the smaller the ΔV, the smaller the charging and discharging current under the condition that the charging voltage frequency remains constant. Since the QVCM itself has background noise current, if the charging and discharging current is less than the background noise current, the accuracy will decrease. Therefore, the selection of ΔV is an empirical value obtained based on the differential principle, the charging voltage frequency, and simulation results. Considering the above three factors, ΔV can be, for example, 0.1V. In some embodiments, ΔV can be adjusted according to requirements. The above-described capacitance testing method under different voltage biases, using the differential principle, can conveniently test and calculate the capacitance value of the device under test under different voltage biases, and can solve the technical problem of obtaining the CV curve of the front-end capacitor of integrated circuit chips under different voltage biases.

[0113] In some embodiments, the third source measurement unit and the fourth source measurement unit are respectively grounded; the first clock signal and the second clock signal have the same frequency and a phase difference of 90°.

[0114] In summary, this invention provides a capacitance testing circuit that applies a square wave voltage to the substrate (B terminal), source (S terminal), and drain (D terminal) of the capacitor under test, and measures the charging and discharging current at the gate (G terminal) of the capacitor under test. This expands the application scope and methods of existing QVCM testing circuits. Based on the capacitance testing circuit and the capacitance testing method adapted to it, the impact of process-induced mismatch between the first and second transmission gates on the measurement can be reduced, and the proportion of charging and discharging current in the measured current can be increased, thereby improving measurement accuracy.

[0115] The common English terms or letters used in this invention for clarity of description are for illustrative purposes only and are not limiting interpretations or specific uses. They should not be used to limit the scope of protection of this invention based on their possible Chinese translations or specific letters.

[0116] It should also be noted that in this article, relational terms such as “first” and “second” are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

Claims

1. A capacitance testing circuit, characterized in that, include: The circuit includes a charging voltage generation circuit, a QVCM test circuit, and the capacitor under test; among which... The charging voltage generation circuit includes a first transmission gate, a second transmission gate, a first source measurement unit, and a second source measurement unit; wherein, the input terminals of the first transmission gate and the second transmission gate are respectively connected to the first source measurement unit and the second source measurement unit, and the first source measurement unit and the second source measurement unit are respectively used to provide voltage; the output terminals of the first transmission gate and the second transmission gate are respectively connected to a first node, and the first node is used as the voltage output terminal of the charging voltage generation circuit; the first control terminal of the first transmission gate is connected to the second control terminal of the second transmission gate, and the second control terminal of the first transmission gate is connected to the first control terminal of the second transmission gate, and the first control terminal of the first transmission gate and the second control terminal of the second transmission gate are used to input a pair of opposite first clock signals; The QVCM test circuit includes a third transmission gate, a fourth transmission gate, a third source measurement unit, and a fourth source measurement unit. The outputs of the third and fourth transmission gates are respectively connected to the third and fourth source measurement units, which are used to measure current. The inputs of the third and fourth transmission gates are respectively connected to a second node, which serves as the voltage input of the QVCM test circuit. The first control terminal of the third transmission gate is connected to the second control terminal of the fourth transmission gate, and the second control terminal of the third transmission gate is connected to the first control terminal of the fourth transmission gate. The first and second control terminals of the third and fourth transmission gates are used to input a pair of opposite second clock signals. The gate G terminal of the capacitor under test is connected to the second node, and the substrate B terminal, source S terminal, and drain D terminal of the capacitor under test are connected to the first node.

2. The capacitance testing circuit according to claim 1, characterized in that, Also includes: A different test item conversion circuit is provided, and the charging voltage generation circuit is connected to the capacitor under test through the different test item conversion circuit. The different test item conversion circuit is configured to perform conversion tests on different test items, including the total gate capacitance, the gate capacitance to the substrate, and the gate capacitance to the source and drain under the substrate voltage.

3. The capacitance testing circuit according to claim 2, characterized in that, The different test item conversion circuit includes: The first multiplexer is connected to the substrate B terminal of each capacitor under test. The second multiplexer is connected to the source (S) and drain (D) terminals of each capacitor under test; wherein, The first multiplexer includes a fifth transmission gate and a sixth transmission gate. The input of the fifth transmission gate is connected to a first node, and the input of the sixth transmission gate is connected to a Bias voltage signal. The outputs of the fifth and sixth transmission gates are connected to the substrate B terminal of each capacitor under test. The first control terminal of the fifth transmission gate is connected to the second control terminal of the sixth transmission gate, and the second control terminal of the sixth transmission gate is connected to the first control terminal of the fifth transmission gate. The first and second control terminals of the fifth and sixth transmission gates are used to input a pair of opposite third control signals. The second multiplexer includes a seventh transmission gate and an eighth transmission gate. The input of the seventh transmission gate is connected to the first node, and the input of the eighth transmission gate is connected to the Bias voltage signal. The outputs of the seventh and eighth transmission gates are connected to the source (S) and drain (D) terminals of each capacitor under test. The first control terminal of the seventh transmission gate is connected to the second control terminal of the eighth transmission gate, and the second control terminal of the eighth transmission gate is connected to the first control terminal of the seventh transmission gate. The first and second control terminals of the seventh and eighth transmission gates are used to input a pair of opposite fourth control signals.

4. The capacitance testing circuit according to claim 3, characterized in that, The specific configuration of the different test item conversion circuit is as follows: In the second multiplexer, the seventh transmission gate is turned on and the eighth transmission gate is turned off. In the first multiplexer, the fifth transmission gate is turned on and the sixth transmission gate is turned off. The source S terminal, drain D terminal, and substrate B terminal of the capacitor under test are all connected to the first node. The QVCM test circuit measures the total gate capacitance at the G terminal. In the second multiplexer, the seventh transmission gate is turned on and the eighth transmission gate is turned off. In the first multiplexer, the fifth transmission gate is turned off and the sixth transmission gate is turned on. The source S terminal and the drain D terminal of the capacitor under test are connected to the first node. The substrate B terminal of the capacitor under test is connected to the Bias voltage signal. The QVCM test circuit measures the gate-to-source and drain capacitances at the gate G terminal under the substrate voltage. In the second multiplexer, the seventh transmission gate is off and the eighth transmission gate is on. In the first multiplexer, the fifth transmission gate is on and the sixth transmission gate is off. The source (S) and drain (D) terminals of the capacitor under test are connected to the Bias voltage signal. The substrate (B) terminal of the capacitor under test is connected to the first node. The QVCM test circuit measures the capacitance between the gate and the substrate at the gate (G) terminal.

5. The capacitance testing circuit according to claim 1, characterized in that, Also includes: The QVCM test circuit is connected to multiple capacitors under test via the addressing circuit. The addressing circuit is used to select the capacitors under test for connectivity testing.

6. The capacitance testing circuit according to claim 5, characterized in that, The addressing circuit includes: At least one decoder and multiple third multiplexers, the number of which is the same as the number of the capacitors under test and are connected in a one-to-one correspondence; The output of the third multiplexer is connected to the gate G terminal of the capacitor under test, and the two inputs of each multiplexer are respectively connected to the second node and the Disable signal; The decoder has X digital signal input terminals, where X = log2N. When log2N is not an integer, X is an integer greater than log2N and with a difference less than 1. The output terminals of the decoder are respectively connected to the corresponding third multiplexer to output the addressing signal for selecting the capacitor under test.

7. A capacitance testing method, characterized in that, The capacitance test circuit described in any one of claims 1-6 is used to perform capacitance testing on the capacitor device under test.

8. The capacitance testing method according to claim 7, characterized in that, include: The first source measurement unit and the second source measurement unit respectively provide the first voltage V. Low Second voltage V High A first clock signal with frequency f is provided to generate a first square wave voltage, the amplitude of which is V. amp The equivalent voltage is V m The frequency is f, where, The third and fourth source measurement units respectively measure and obtain the first current I. 11 Second current I 21 ; The first source measurement unit and the second source measurement unit respectively provide the second voltage V. High and the first voltage V Low A first clock signal with frequency f is provided to generate a second square wave voltage, the amplitude of which is V. amp The equivalent voltage is V m The frequency is f, where, The third current I is obtained by measuring the third source measurement unit and the fourth source measurement unit respectively. 12 and the fourth current I 22 ; The capacitance C of the capacitor under test is calculated using the following formula:

9. The capacitance testing method according to claim 8, characterized in that, Before calculating the capacitance value C of the capacitor under test, the capacitance testing method further includes: Within the bias range of the equivalent voltage Vm, the equivalent voltage Vm is divided equally by M voltage dividing points with an adjacent interval of ΔV, where M is an integer greater than 1; Under the condition that the charging voltage amplitude Vamp=△V and Vm=-Vmin~Vmax at each voltage division point, calculate the capacitance value under the corresponding voltage bias at each voltage division point. After calculating the capacitance value C of the capacitor under test, the capacitance testing method further includes: A CV curve is plotted based on the voltage at each voltage division point and the capacitance value calculated under that voltage condition.

10. The capacitance testing method according to claim 8, characterized in that, The third source measurement unit and the fourth source measurement unit are respectively grounded; The first clock signal and the second clock signal have the same frequency and a phase difference of 90°.

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