A Verification Strategy for DMA Access in Digital IC Verification

Abstract

The present invention provides a verification strategy for DMA access in digital IC verification. First, both the main memory address spaces of the terminal and the device side are set as static variables; at least one of the device side and the terminal is selected as the verification side, and data layout of a data sequence is performed on the verification side; after writing device-side data into the terminal main memory through a DMA write request and reading back the terminal data to the device side through a DMA read request, the data of the verification side is compared with the data finally received by the device side to complete the data verification of the DMA write and read requests. By setting both RC and EP as static variables, the present invention ensures that the data layout of either party will not interfere with the other party.

Description

Technical Field

[0001] The present invention belongs to the field of digital IC verification, and particularly relates to a verification strategy for DMA access in digital IC verification. Background Art

[0002] DMA (Direct Memory Access) is an important feature of all modern computers. DMA access is direct memory access. DMA transfer copies data from one address space to another address space. It allows hardware devices with different speeds to communicate. For example, moving a block of external memory to a faster memory area inside the chip. Otherwise, the CPU needs to copy each segment of data from the source to the register and then write them back to the new place again. During this process, the CPU generates a large amount of interrupt load.

[0003] Since DMA allows hardware devices with different speeds to communicate, it is very important to perform DMA data verification to ensure the correctness of DMA data transfer.

[0004] Currently, the method for performing DMA data verification is to set the shadow main memory as a static variable, which serves as a medium for data verification between the terminal (RC) main memory address space and the device - side (EP) data address space. When setting data at the terminal and the device - side, the same data is set in the shadow main memory as a backup of the data transfer starting party. The purpose is to ensure the integrity of the data at the starting party after the data is transferred back to the starting party. The data can be verified with the data in the shadow after the data sending and receiving are completed to ensure the correctness of the data transfer.

[0005] As Figure 1 shown, the above - mentioned method first performs data layout of the same data sequence on the device - side (EP) and the shadow main memory. After writing the device - side data into the terminal (RC) main memory through a DMA write request and reading the terminal data back to the device - side through a DMA read request, the data transported from the starting address in the shadow is verified with the data finally received at the device - side at the device - side to complete the data verification of the DMA write and read requests. The main purpose of introducing the shadow is to prevent the data read by the DMA read request from overwriting the original data and causing the original data sequence to be overwritten.

[0006] The disadvantage of the above - mentioned method is that the shadow main memory is a static variable, and it can only maintain consistent data layout with RC or EP at the same time. When the verification strategy requires both RC and EP ends to perform data layout on the address space data simultaneously, conflicts will occur. Summary of the Invention

[0007] The present invention provides a verification strategy for DMA access in digital IC verification. By setting both RC and EP as static variables, data distribution control on either side will not interfere with the other side.

[0008] For a verification strategy of DMA access in digital IC verification according to the present invention, first, the main memory address spaces of both the terminal and the device end are set as static variables;

[0009] Select at least one of the device end and the terminal as the verification end, and perform data distribution control on the data sequence of the verification end;

[0010] After writing the device end data into the terminal main memory through a DMA write request and reading the terminal data back to the device end through a DMA read request, verify the data of the verification end against the data finally received by the device end to complete the data verification of the DMA write and read requests.

[0011] In one embodiment, the method of data verification is: accurately locate the target data by means of a mask and data address offset.

[0012] In one embodiment, the method of data verification is to verify 128B of data each time. When the starting address is not 128B aligned, take 256B of data from the 128B aligned address before the starting address, offset according to the starting address, and only verify 128B of data starting from the starting address; verifying 128B of data each time is because the virtual main memory can only fetch 128B of data starting from a 128B aligned address each time.

[0013] A verification strategy of DMA access in digital IC verification according to the present invention has the following improvements compared with the existing verification strategy:

[0014] 1. Abandon the use of the shadow main memory, reduce the use of one virtual main memory, and increase the simplicity of the verification environment;

[0015] 2. When setting data, data distribution control can be performed on either one or both of the two parties (terminal, device end), increasing the diversity and flexibility of the verification strategy; when performing partial operations on the main memories of the two parties, the test intensity of the verification strategy is increased; this method will not affect the shared shadow main memory due to misoperations. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Schematic diagram of an existing verification strategy for DMA access in digital IC verification

[0017] Figure 2 Schematic diagram of an embodiment of the verification strategy for DMA access in digital IC verification according to the present invention

[0018] Figure 3Schematic diagram of another embodiment of the verification strategy for DMA access in the digital IC verification of the present invention

[0019] Figure 4 Schematic diagram of another embodiment of the verification strategy for DMA access in the digital IC verification of the present invention Detailed implementation manner

[0020] To clearly describe the present invention, it will be further described below in conjunction with the accompanying drawings.

[0021] As Figure 2 shown, for a verification strategy for DMA access in digital IC verification, first, the main memory address spaces of both the terminal and the device end are set as static variables, so that either the terminal or the device end can access the local main memory and the main memory of the other party.

[0022] Select the device end as the verification end, perform data layout control on the data sequence of the verification end, and the system statically allocates a storage address for data sequence 0, that is, the allocation situation will not change during operation;

[0023] After writing the device - end data into the terminal main memory through a DMA write request to form data sequence 1 and reading the terminal data back to the device end through a DMA read request to form data sequence 2, compare the last - received data sequence 2 at the device end with the data sequence 0 stored at the statically - allocated address at the device end. That is, the data verification of the DMA write - read request is completed. The verification accurately locates the target data through the method of mask and data - address offset.

[0024] As Figure 3 shown, for a verification strategy for DMA access in digital IC verification, first, the main memory address spaces of both the terminal and the device end are set as static variables, so that either the terminal or the device end can access the local main memory and the main memory of the other party.

[0025] Select the terminal as the verification end, perform data layout control on the data sequence of the verification end, and the system statically allocates a storage address for data sequence 0, that is, the allocation situation will not change during operation;

[0026] After writing the device - end data into the terminal main memory through a DMA write request to form data sequence 1 and reading the terminal data back to the device end through a DMA read request to form data sequence 2, compare the last - received data sequence 2 at the device end with the data sequence 0 stored at the statically - allocated address at the terminal. That is, the data verification of the DMA write - read request is completed. The verification accurately locates the target data through the method of mask and data - address offset.

[0027] As Figure 4A verification strategy for DMA access in digital IC verification is shown as follows. First, the main memory address spaces of the terminal and the device are both set as static variables, enabling either the terminal or the device to access the local main memory and the main memory of the other party.

[0028] At the same time, select either the device or the terminal as the verification end, and perform data layout control on the data sequences of both the device and the terminal. The system statically allocates storage addresses for the data sequence 0 on both the device and the terminal, that is, the allocation situation will not change during runtime.

[0029] After writing the device data into the terminal main memory through a DMA write request to form data sequence 1, and reading the terminal data back to the device through a DMA read request to form data sequence 2, the last received data sequence 2 on the device is compared with the data sequence 0 stored at the statically allocated address on the device or the terminal, thus completing the data verification of the DMA write and read requests. During verification, the virtual main memory is implemented as an array with a width of 128B, and 128B of data is verified each time (each time 128B of data is verified because the virtual main memory can only fetch 128B of data starting from a 128B aligned address), that is: each time data is fetched, it can only start from a 128B aligned address, such as 0B, 128B, 256B... The length of the fetched data is a multiple of 128B; when the starting address of the data to be fetched (such as 1B) is not 128B aligned, an offset needs to be made according to the starting address, and the fetch starts from the first 128B aligned address smaller than this address (such as 0B); and to fetch more than 128B of data to obtain all the required data, that is, 256B (2 times of 128B) of data needs to be fetched starting from the first 128B aligned address before the starting address, but only the required 128B of data is operated on (for example, for the data corresponding to the addresses 1 - 128B, only the 128B of data starting from the starting address is verified).

[0030] In the above example, the operation initiator can also be changed. The terminal (initiator) initiates DMA read and write operations on the terminal main memory by the device (target), and the verification is performed on the terminal; or, after a single read or write operation, the data verification is directly performed on the target.

[0031] A verification strategy for DMA access in digital IC verification of the present invention has the following improvements compared with the existing verification strategy:

[0032] 1. Abandon the use of shadow main memory, reduce the use of one virtual main memory, and increase the simplicity of the verification environment.

[0033] 2. When setting data, data control can be performed on either one or both of the two parties (the terminal and the device side), which increases the diversity and flexibility of the verification strategy; when performing partial operations on the main memories of the two parties, the test intensity of the verification strategy is increased; this method will not affect the shared shadow main memory due to misoperations.

Claims

1. A verification strategy for DMA access in digital IC verification, characterized in that: First, set the main memory address spaces of both the terminal and the device side as static variables; Select at least one of the device side and the terminal as the verification side, and perform data layout of the data sequence on the verification side; After writing the device-side data into the terminal main memory through a DMA write request and reading the terminal data back to the device side through a DMA read request, verify the data of the verification side against the data finally received by the device side to complete the data verification of the DMA write / read request.

2. The verification strategy for DMA access in digital IC verification as described in claim 1, wherein, The method of data verification is: accurately locate the target data by means of a mask and data address offset.

3. The verification strategy for DMA access in digital IC verification according to claim 1, wherein The method of data verification is to verify 128B of data each time. When the starting address is not aligned to 128B, take 256B of data from the first 128B-aligned address before the starting address, offset according to the starting address, and only verify 128B of data starting from the starting address; verifying 128B of data each time is because the virtual main memory can only fetch 128B of data starting from a 128B-aligned address each time.

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