Display control system, electronic device, and display method

Abstract

The application discloses a display control system, an electronic device and a display method. The system comprises a display screen and a DPU; the display screen comprises a DDIC, a control circuit, N display areas and N driving circuits; the DPU comprises a first processing module; the DDIC is connected between the first processing module and the N driving circuits; the N driving circuits correspond to the N display areas one by one; the control circuit is connected with the N driving circuits respectively; the first processing module determines a first image according to layer information and sends the first image to the DDIC, the first image comprises N sub-areas, the N sub-areas correspond to the N display areas one by one, and the frame rate of a sub-area is the same as that of a corresponding display area; the DDIC drives the N driving circuits to refresh the respective corresponding sub-areas in the first image to the corresponding display areas; and the control circuit is used for controlling a target driving circuit to perform a first operation, and the first operation comprises: refreshing a target display area at a first frame rate, and the first frame rate is the frame rate of the target display area.

Description

Technical Field

[0001] This application belongs to the field of display screen control technology, specifically relating to a display control system, electronic device, and display method. Background Technology

[0002] In related technologies, an electronic device can display two image contents with different frame rates. For example, image content A, refreshed at 120Hz, is displayed on the left side of the same screen, while image content B, refreshed at 30Hz, is displayed on the right side. However, since the content displayed on the same screen is refreshed as a whole—that is, both image content A and image content B are refreshed at 120Hz—image content B will have a duplicate frame rate, leading to increased power consumption of the electronic device. Summary of the Invention

[0003] The purpose of this application is to provide a display control system, electronic device, and display method that can refresh different display areas on the display screen according to their respective corresponding frame rates, thereby reducing the power consumption of the electronic device.

[0004] In a first aspect, embodiments of this application provide a display control system, which includes: a display screen and a display processing unit (DPU), wherein the display screen is connected to the DPU;

[0005] The display screen includes: a display driver chip DDIC, a control circuit, N display areas, and N driving circuits, where N is an integer greater than 1;

[0006] The DPU includes a first processing module;

[0007] The DDIC is connected between the first processing module and the N driving circuits;

[0008] Each of the N driving circuits corresponds one-to-one with one of the N display areas;

[0009] The control circuit is connected to each of the N drive circuits;

[0010] The first processing module is used to determine a first image based on layer information and send the first image to the DDIC. The first image includes N sub-regions, and the N sub-regions correspond one-to-one with the N display regions. The frame rate of the sub-regions and the corresponding display regions is the same.

[0011] The DDIC is used to drive N driving circuits to refresh their respective sub-regions in the first image to their corresponding display areas. The control circuit is used to control the target driving circuit to perform a first operation, which includes: refreshing the target display area according to a first frame rate, where the first frame rate is the frame rate of the target display area. The N driving circuits include the target driving circuit, the N display areas include the target display area, and the target driving circuit corresponds to the target display area.

[0012] Secondly, embodiments of this application provide a display control system, which includes: a display screen and a display processing unit (DPU), wherein the display screen is connected to the DPU;

[0013] The display screen includes: a display driver chip DDIC, a control circuit, N display areas, and N driving circuits, where N is an integer greater than 1;

[0014] The DPU includes M processing paths, where M is a positive integer;

[0015] The DDIC is connected between the processing path and the N driving circuits;

[0016] Each of the N driving circuits corresponds one-to-one with one of the N display areas;

[0017] The control circuit is connected to each of the N drive circuits;

[0018] Among them, M processing paths are used to acquire layer information, process the layer information in parallel to obtain N second images, and send the N second images to the DDIC;

[0019] The DDIC is used to send the target second image to the target driving circuit, and the control circuit is used to control the target driving circuit to perform a first operation. The first operation includes: refreshing the target display area according to a first frame rate, where the first frame rate is the frame rate of the target display area, wherein the frame rate of the target second image is the same as the frame rate of the target display area, N second images include the target second image, N driving circuits include the target driving circuit, the N display areas include the target display area, and the target driving circuit corresponds to the target display area.

[0020] Thirdly, embodiments of this application provide a display control system, which includes: a display screen and a display processing unit (DPU), wherein the display screen is connected to the DPU;

[0021] The display screen includes: a display driver chip DDIC, a control circuit, N display areas, and N driving circuits, where N is an integer greater than 1;

[0022] The DPU includes M processing paths and a first processing module, wherein the M processing paths are connected to the first processing module, and M is a positive integer;

[0023] The DDIC is connected between the first processing module and the N driving circuits;

[0024] Each of the N driving circuits corresponds one-to-one with one of the N display areas;

[0025] The control circuit is connected to each of the N drive circuits;

[0026] M processing paths are used to acquire layer information and perform parallel or serial processing on the layer information. The first processing module is used to perform a first processing on the output information of the M processing paths to obtain a first image and send the first image to the DDIC.

[0027] The DDIC is used to drive N driving circuits to refresh their respective sub-regions in the first image to their corresponding display areas. The control circuit is used to control the target driving circuit to perform a first operation, which includes: refreshing the target display area according to a first frame rate, where the first frame rate is the frame rate of the target display area. The N driving circuits include the target driving circuit, the N display areas include the target display area, and the target driving circuit corresponds to the target display area.

[0028] Fourthly, embodiments of this application provide an electronic device that includes a display control system as described in the first, second, or third aspect.

[0029] Fifthly, embodiments of this application provide a display method applied to a display control system as described in the first, second, or third aspect, the method comprising:

[0030] Obtain the frame rate corresponding to at least two display areas on the screen;

[0031] The image content is refreshed in each of the at least two display areas according to its corresponding frame rate.

[0032] In a sixth aspect, embodiments of this application provide an electronic device including a processor and a memory, the memory storing programs or instructions executable on the processor, the programs or instructions, when executed by the processor, implementing the steps of the method described in the fifth aspect.

[0033] In a seventh aspect, embodiments of this application provide a readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the method described in the fifth aspect.

[0034] Eighthly, embodiments of this application provide a chip, the chip including a processor and a communication interface, the communication interface being coupled to the processor, the processor being used to run programs or instructions to implement the method as described in the fifth aspect.

[0035] Ninthly, embodiments of this application provide a computer program product stored in a storage medium, which is executed by at least one processor to implement the method described in the fifth aspect.

[0036] In this embodiment, the display area on the screen is divided into N regions, and each display area is driven by its own driving circuit. The refresh rate of each driving circuit is controlled by a control circuit, allowing different display areas on the screen to refresh at different frame rates, thus reducing energy consumption caused by refresh displays. Furthermore, second images with different frame rates can be processed through a processing path and then sent to the corresponding display area via DDIC for display. Alternatively, a first image can be synthesized by a first processing module, and the refresh rate of different sub-regions in this first image can be different. In this way, each sub-region of the first image is refreshed to the corresponding display area via DDIC. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of the structure of a display control system in related technologies;

[0038] Figure 2 This refers to the DPU's intention in synchronously acquiring refresh frames based on the tearing effect (TE) signal in related technologies.

[0039] Figure 3 This is a schematic diagram illustrating the process of refreshing display areas at different frame rates in related technologies;

[0040] Figure 4a This is one of the intended processing steps for refreshing display areas at different frame rates in the embodiments of this application;

[0041] Figure 4b This is the second intention of the processing procedure for refreshing display areas with different frame rates in the embodiments of this application;

[0042] Figure 4c This is one of the structural schematic diagrams of the display control system in the embodiments of this application;

[0043] Figure 4d This is the third intention of the processing procedure for refreshing display areas with different frame rates in the embodiments of this application;

[0044] Figure 4e This is the second schematic diagram of the display control system in the embodiments of this application;

[0045] Figure 5a This is the fourth intention of the processing procedure for refreshing display areas with different frame rates in the embodiments of this application;

[0046] Figure 5b This is the fifth intention of the processing procedure for refreshing display areas with different frame rates in the embodiments of this application;

[0047] Figure 5c This is the third schematic diagram of the display control system in the embodiments of this application;

[0048] Figure 5d This is the fourth schematic diagram of the display control system in the embodiments of this application;

[0049] Figure 5e This is the fifth schematic diagram of the display control system in the embodiments of this application;

[0050] Figure 6 This is the sixth intention of the processing procedure for refreshing display areas with different frame rates in the embodiments of this application;

[0051] Figure 7a This is the seventh intention of the processing procedure for refreshing display areas with different frame rates in the embodiments of this application;

[0052] Figure 7b This is the eighth intention of the processing procedure for refreshing display areas with different frame rates in the embodiments of this application;

[0053] Figure 7c This is the sixth schematic diagram of the display control system in the embodiments of this application;

[0054] Figure 8 This is the ninth intention of the processing procedure for refreshing display areas with different frame rates in the embodiments of this application;

[0055] Figure 9 This is a schematic diagram of the TE signal in an embodiment of this application;

[0056] Figure 10 This is a schematic diagram of the display method provided in an embodiment of this application;

[0057] Figure 11 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0058] Figure 12This is a schematic diagram of the hardware structure of another electronic device provided in an embodiment of this application. Detailed Implementation

[0059] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0060] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0061] Mobile phone display technology has advanced rapidly, with screen refresh rates evolving from 60Hz to 120Hz, 144Hz, and now dynamic frame rate refresh. This means the screen can refresh at many different frame rates; for example, a static image might refresh at 10Hz, a 24fps movie at 24Hz, a 60fps game at 60Hz, and scrolling at 120Hz or 144Hz.

[0062] In some embodiments, for scenarios such as foldable screens, large screens, and split-screen applications, at least two windows can be displayed on the screen, and the refresh rate of the different windows can be different. For ease of explanation, this application embodiment uses an application to a foldable screen phone as an example for illustration, and does not limit the type of display screen in the display control system provided in this application embodiment.

[0063] For foldable screen phones, such as Figure 1 As shown, it may include two screens, where screen 1 is the main screen and screen 2 is the secondary screen. Of course, a foldable screen phone may also include only one foldable screen 1. For ease of explanation, in this embodiment, a foldable screen phone including screen 1 and screen 2 is usually used as an example for illustration.

[0064] The Application Processor (AP) in a foldable phone is the main control chip. This AP includes a Display Processing Unit (DPU), which processes the content to be displayed and then sends the image content to screens 1 and 2 for display. The DPU mainly consists of display content processing paths, which may include modules such as color enhancement, image quality processing, rotation, and screenshotting. The specific structure and function of these display content processing paths can be found in related technologies on the display content processing paths within the DPU, and will not be elaborated upon here.

[0065] like Figure 1 As shown, the process of DPU processing a frame of content to be displayed is as follows: DPU's display content processing path 1 retrieves the layers to be composited from the buffer, such as layer 1, layer 2, layer 3, and layer 4. After processing by display content processing path 1, a frame of content to be displayed is composited and stored in the frame buffer. The content in the frame buffer is sent to screen 1 for display through the Mobile Industry Processor Interface (MIPI) DSI port 1.

[0066] Based on the same principle, the content to be displayed on screen 2 is processed by display content processing path 0. Specifically, the display content processing path 0 of the DPU retrieves the layer from the cache, processes it, and then synthesizes it into a frame of content to be displayed. This frame is stored in its corresponding frame cache position and then sent to screen 2 for display via the MIPI DSI port 0 interface.

[0067] As can be seen from the above, in the relevant technologies, although the two screens can refresh the image at different frame rates, two independent display content processing paths are required. The two independent display content processing paths are connected to the two screens one-to-one through their respective DSI ports. In this way, the two independent display content processing paths can process the image content of their respective frame rates and send it to their respective screens.

[0068] Taking the content processing path 1 as an example of processing the content to be displayed on screen 1, when a mobile phone opens an application, such as an application (APP), or takes a photo or video, or watches a video, the content drawn by the graphics processing unit (GPU) or the network content is downloaded, decoded, and stored in the cache as layers, such as... Figure 1Layer 1, Layer 2, ... In the image, after the DPU obtains the layers, it performs overlay processing to form the final content to be displayed and stores it in the frame buffer. The content of the frame buffer is sent to screen 1 for display through the Display Serial Interface (DSI).

[0069] Specifically, such as Figure 2 As shown, a frame of content is composed of multiple layers stacked together. The framebuffer stores the content to be displayed. One image in the framebuffer represents a frame of content to be displayed. It is composed by the DPU retrieving relevant layers from the cache. The cache type of the framebuffer is generally DDR memory, namely Double Data Rate (DDR) Synchronous Dynamic Random-Access Memory (SDRAM).

[0070] The specific screen refresh process is as follows:

[0071] The image sent to the screen by the DPU consists of lines of content. For example, a Full High-Definition (FHD) screen has a resolution of 2520*1080, meaning it has 2520 lines of data. After processing, the DPU sends the data to the DDIC, which drives the screen's Gate Driver On Array (GOA) circuit to display the image line by line on the screen.

[0072] For example, in a single frame of content, the first line is the top of the screen. Under the driving timing and driving circuit, the screen opens the first line, and the DDIC refreshes the first line at the top of the screen, then refreshes the second line, and so on until the last line, thus completing the display refresh of one frame of content.

[0073] For example, suppose we need to display 60Hz content, which means refreshing the image content 60 times per second. The AP DPU extracts the content to be displayed frame by frame from the frame buffer according to the synchronization of the tearing effect (TE) synchronization signal, processes it frame by frame, and finally transmits it to the DDIC frame by frame through the DSI interface, so that the screen can refresh and display it frame by frame.

[0074] It's important to note that related technologies also allow for the display of different image content on different areas of the same screen. For example, on a foldable phone, a webpage might be displayed on the left, while a chat interface from a social media application is displayed on the right. In this case, the refresh rate of the different displayed content can be different. Alternatively, a user can interact with a portion of the same screen, in which case the refresh rate of that portion is higher than that of the uninterrupted portion.

[0075] However, in related technologies, one screen corresponds to one display content processing path, and the refresh rate of the image content processed by this display content processing path is the same, which will cause the content displayed on the same screen to be refreshed at the same frame rate.

[0076] For example, suppose a foldable screen displays a social media application interface, which includes a first display area on the left and a second display area on the right. If the user touches the first display area and the second display area displays a video chat interface, the refresh rate of the first display area can be 120Hz, and the refresh rate of the second display area can be 30Hz. However, since the entire image displayed on the foldable screen is refreshed as a single large image, everything needs to be refreshed at 120Hz. This would result in many duplicate frames in the video in the second display area, leading to a waste of phone battery power.

[0077] In other words, in foldable phones or other traditional candybar phones, especially those with foldable screens and split-screen applications, when there are two pieces of content with different refresh rates, the DPU (Data Processing Unit) stitches the two parts together to output a complete large image, and then refreshes that complete large image onto the screen using the highest refresh rate. For example: Figure 3 As shown, assuming content A has a refresh rate of 60Hz and content B has a refresh rate of 24Hz, the 24Hz content B will be repeated to make up the 60Hz refresh rate. Thus, content A and content B will be refreshed together at a 60Hz refresh rate, meaning the entire screen content will be refreshed at 60Hz. This causes the low-frame-rate content B to be repeatedly refreshed under the high-frame-rate drive, wasting power.

[0078] In this embodiment, by updating the display control system, the system can differentiate and process screen content with different frame rates, and deliver it to the display screen according to the actual frame rate of each content, so that the screen can be refreshed according to the actual frame rate of the content. For example, assuming that the refresh rate of content A is 60Hz and the refresh rate of content B is 24Hz, in this embodiment, content A will be refreshed on the display screen at 60Hz, and content B will be refreshed on the display screen at 24Hz.

[0079] The display control system, electronic device, and display method provided in this application will be described in detail below with reference to the accompanying drawings and through specific embodiments and application scenarios.

[0080] Implementation Method 1

[0081] Please see Figure 4a The display control system provided in this application embodiment includes: a display screen 1 and a DPU 2;

[0082] The display screen 1 includes: a control circuit 11, N display areas 12, N driving circuits 13 and a DDIC 14, where N is an integer greater than 1;

[0083] DPU 2 includes a first processing module 22;

[0084] DDIC 14 is connected between the first processing module 22 and the N drive circuits 13;

[0085] N driving circuits 13 correspond one-to-one with N display areas 12;

[0086] The control circuit 11 is connected to N drive circuits 13 respectively;

[0087] The first processing module 22 is used to determine a first image based on layer information and send the first image to the DDIC 14. The first image includes N sub-regions, and the N sub-regions correspond one-to-one with the N display areas 12. The frame rate of the sub-regions and the corresponding display areas 12 is the same.

[0088] The DDIC 14 is used to drive N driving circuits 13 to refresh their respective sub-regions in the first image to their corresponding display areas 12. The control circuit 11 is used to control the target driving circuit to perform a first operation, which includes: refreshing the target display area according to a first frame rate, where the first frame rate is the frame rate of the target display area. The N driving circuits 13 include the target driving circuit, the N display areas 12 include the target display area, and the target driving circuit corresponds to the target display area.

[0089] For ease of explanation, in this embodiment, display screen 1 is a folding screen, and the folding screen is divided into two display areas, i.e., N=2, as an example. In other embodiments, display screen 1 can be any screen, and the display areas on the screen can be divided into 3, 4 or even more, which does not constitute a specific limitation.

[0090] Optionally, the driving circuit 13 can be a GOA circuit. For example: Figure 4aAs shown, display area A corresponds to GOA and display area B corresponds to GOA 1. At this time, GOA is used to refresh the image in display area A, and GOA 1 is used to refresh the image in display area B.

[0091] N GOA circuits are arranged in parallel, and the DDIC controls the refresh of the N GOA circuits through signals on control lines, with at least one control signal line. The frequency of the TE signal can be determined according to the refresh frame rate corresponding to the N display areas 12. For example, the AP notifies the DDIC of the refresh frame rate, and the timing module of the DDIC outputs the TE signal according to the refresh frame rate. Under the synchronization of the TE signal, the DDIC control line signal can be transmitted from the first GOA circuit to the Nth GOA circuit. During this process, the control circuit 11 can control the opening of each GOA circuit or the cutting off of some GOA circuits. At this time, the cut-off GOA circuit will not refresh the corresponding display area. In this way, by controlling each GOA circuit to be in the open or cut-off state by the control circuit 11, the refresh frame rate of each GOA circuit can be adjusted.

[0092] In one embodiment, the TE signal corresponds one-to-one with the frame rate of the display area. At this time, the DDIC drives the control circuit 11 through the control line to adjust each GOA circuit to be in a cut-off or open state, so as to control the GOA circuit to refresh according to the frame rate of the corresponding display area.

[0093] Optionally, the display control system further includes:

[0094] The synchronization signal line, also known as the TE line, is connected between the DPU 2 and the DDIC 14. The DDIC 14 is used to send N types of synchronization signals to the DPU 2 through the synchronization signal line.

[0095] Among them, the N types of synchronization signals correspond one-to-one with the frame rates of the N display areas 12, and the DPU 2 is used to synchronize the corresponding frame rate image to the DDIC 14 according to the N types of synchronization signals.

[0096] In practice, the N synchronization signals can be N different shapes of synchronization signals, for example: one synchronization signal is 111, another synchronization signal is 011, etc.

[0097] For example: Figure 9As shown, assuming N equals 2, two waveforms of TE signals can be set. When DPU 2 detects the first waveform of TE signal at a specific frame time, it determines to synchronize the image content of the display area 12 corresponding to the first waveform of TE signal to DDIC 14; when DPU 2 detects the second waveform of TE signal at a specific frame time, it determines to synchronize the image content of the display area 12 corresponding to the second waveform of TE signal to DDIC 14.

[0098] Optionally, at a specific frame time, when at least two TE signals are transmitted on the synchronization signal line, the at least two TE signals can be superimposed to generate a new shape of TE signal. At this time, DPU 2 can determine to simultaneously synchronize the image content of the display area 12 corresponding to the two TE signals to DDIC 14 based on receiving the new shape of TE signal.

[0099] In this embodiment, at least two synchronization signals can be transmitted using a single synchronization signal line, which reduces the number of synchronization signal lines and DDIC 14, and simplifies the structure of the display control system.

[0100] Of course, in another implementation, N synchronization signal lines can be set up to correspond one-to-one with the frame rates of the N display areas 12, so that each synchronization signal line only needs to transmit the TE signal of one frame rate.

[0101] For example: Figure 4e or Figure 5e As shown, assuming N=2, and there are two display areas 12, two DDICs 14, and two TE lines, one DDIC 14 can be connected to DPU 2 via the synchronization signal line TE 1, so that DPU 2, under the synchronization of the TE1 signal, synchronously sends the image content of the first frame rate to the DDIC 14. Then, the DDIC 14 drives the received image content to be synchronized to the display area 12 of the first frame rate. The other DDIC 14 can be connected to DPU 2 via the synchronization signal line TE 2, so that DPU 2, under the synchronization of the TE2 signal, synchronously sends the image content of the second frame rate to the DDIC 14. Then, the DDIC 14 drives the received image content to be synchronized to the display area 12 of the second frame rate.

[0102] In another implementation, with only one TE signal, the control circuit 11 can cut off the GOA circuit corresponding to the low frame rate display area 12 so that the low frame rate display area 12 does not refresh repeatedly. For example, assuming that the frame rate of display area A is 120Hz, the frame rate of display area B is 30Hz, and the frequency of the TE signal is 120Hz, the control circuit 11 can periodically cut off the GOA circuit of display area B so that the GOA circuit corresponding to display area B will only refresh display area B at a frame rate of 30Hz, and will not refresh display area B repeatedly.

[0103] The first image mentioned above can be understood as the integration of image content that needs to be refreshed in N display areas.

[0104] It should be noted that in addition to the first processing module 22, DPU 2 may also have other processing modules for compositing, adjusting brightness, chroma, resolution, etc. of layer information. For ease of explanation, this embodiment of the application takes DPU 2 including processing path 21 for compositing, adjusting brightness, chroma, resolution, etc. of layer information as an example for illustration.

[0105] In one embodiment, the DPU 2 may include a processing path 21 for serial processing of layer information at different frame rates, i.e., time-division processing of layer information at different frame rates, and then sending the processed image data to the first processing module 22 so that the first processing module 22 can fuse the image data or the third image at different frame rates to obtain a first image.

[0106] In another embodiment, the DPU 2 may include at least two processing paths 21, which are used to process layer information at different frame rates in parallel. Each processing path 21 sends the processed image data to the first processing module 22, so that the first processing module 22 can fuse the image data or the third image at different frame rates to obtain a first image.

[0107] In one embodiment, the DPU 2 can obtain layer information from a cache. The content stored in the cache may be downloaded from the network by an electronic device with the display control system, or it may be captured by the camera of the electronic device. The AP encodes and decodes these contents from different sources and stores them in the DDR buffer storage area of ​​the mobile phone. After obtaining the contents from the cache storage area, the DPU 2 performs synthesis, brightness, color, resolution and other adjustments. Then, the first processing module 22 fuses the image content of each frame rate to obtain the image frame that needs to be refreshed. Finally, the image frame is sent to the DDIC 14 of the display screen 1, and the DDIC 14 controls the driving circuit 13 to refresh each sub-region in the image frame onto its corresponding display area 12.

[0108] It should be noted that when the refresh rates of the N display areas 12 are different, at a specific frame moment, at least a portion of the display content of the display areas 12 can be refreshed. In this case, some sub-regions in the first image may not have image content. For sub-regions without image content, it is not necessary to drive the corresponding display area to refresh the display content through the driving circuit 13.

[0109] For example: Suppose that the refresh rate of display area A is 60Hz and the refresh rate of display area B is 24Hz, then... Figure 5a In the first frame of the image shown, both display area A and display area B contain image content in their respective sub-regions; while Figure 5b In the second frame of the first image shown, only the sub-region corresponding to the display area A with a high refresh rate has image content, while the sub-region corresponding to the display area B with a low refresh rate has no image content. Thus, in the driving circuit 13... Figure 5b When the first frame of the image shown is refreshed and displayed on the screen, the driving circuit 13 corresponding to display area A drives display area A to refresh, while the driving circuit 13 corresponding to display area B does not drive display area B to refresh.

[0110] In one implementation, the DDIC 14 can store the first image in different storage spaces on the DDIC 14 according to the distribution of the sub-regions with display content. In this way, the driving circuit 13 can determine whether the corresponding display area 12 needs to be refreshed based on the storage space where the first image is stored in the DDIC 14.

[0111] For example: Assuming N equals 2, the refresh rate of display area A is 60Hz, and the refresh rate of display area B is 24Hz, then... Figure 5a In the first frame of the image shown, both display area A and display area B contain image content in their respective sub-regions. At this time, DDIC 14 stores the first image in storage space A; while Figure 5b In the second frame of the first image shown, only the sub-region corresponding to display area A with a high refresh rate has image content, while the sub-region corresponding to display area B with a low refresh rate has no image content. In this case, DDIC 14 stores the first image in storage space B. Subsequently, DDIC 14 can drive the driving circuits 13 corresponding to display areas A and B to refresh the first image in storage space A; or, DDIC 14 can drive the driving circuit 13 corresponding to display area A to refresh the first image in storage space B.

[0112] It should be noted that the number of storage spaces in the aforementioned DDIC 14 can be adjusted according to the number of display areas 12 and the combination of sub-regions containing image content in the first image, etc., and no specific limitation is made here.

[0113] Of course, in other embodiments, DDIC 14 can also use other methods to drive the driving circuit 13 corresponding to the sub-region with image content to refresh the display area, which is not specifically limited here. For example, the control circuit can determine the sub-region with image content, thereby controlling the driving circuit 13 corresponding to the sub-region with image content to drive the display area to refresh.

[0114] In this embodiment, the content of a single frame of image displayed on the entire display screen 1 is treated as a whole, which facilitates the management of the first image.

[0115] As an optional implementation, the first processing module 22 includes:

[0116] The compositing module is used to synthesize image data streams of N frame rates to obtain the first image, wherein the image data stream is the data stream output from the processing path in the DPU; or,

[0117] The jigsaw puzzle module is used to perform jigsaw puzzle processing on a third image with N frame rates to obtain the first image. The third image is the image processed by the processing path in the DPU.

[0118] In one embodiment, when the first processing module 22 includes a synthesis module, the first processing module 22 directly acquires the image data stream output by the processing path 21 and performs synthesis processing on the image data stream to obtain image data of a first frame of image.

[0119] In another embodiment, when the first processing module 22 includes a jigsaw puzzle module, the processing path 21 first outputs a third image, which may be an intermediate image that corresponds one-to-one with the display area 12. Then, the jigsaw puzzle module performs jigsaw puzzle processing on the third images output by each processing path 21 to obtain the first image.

[0120] Optionally, if the first processing module includes the jigsaw puzzle module, the display control system further includes:

[0121] There are N second storage spaces, each corresponding to one of the N display areas. The N second storage spaces are used to iteratively store at least one row of image data to be transmitted to the puzzle module from the third image. The refresh rate of the third image stored in each of the N second storage spaces is the same as the frame rate of the display area corresponding to each of the N second storage spaces.

[0122] The puzzle module is used to obtain image data of the third image from N second storage spaces.

[0123] The second storage space can be a cache space of a specified size, such as DDR or SRAM. The size of this storage space can be greater than, equal to, or less than the image data size of a frame of the third image. When the second storage space is smaller than the image data size of a frame of the third image, a portion of the image data in the third image can be stored each time. When the image data of a certain row is sent to the puzzle module, the image data of that row is deleted from the second storage space so that the next row of image data in the third image after being processed by the storage processing path 21 can be added to the second storage space. In this way, the smaller size of the second storage space can be used to iteratively store each row of data in the third image until all the image data of a frame of the third image to be refreshed is sent to the puzzle module to complete the puzzle.

[0124] For ease of explanation, in the embodiments of this application, the example is usually taken as the size of the second storage space being equal to the data size of one frame of the third image. In this case, the second storage space can be called a frame buffer, that is, it can store one complete frame of the third image at a time.

[0125] For example: Figure 5e As shown, the second storage space includes frame buffer A' and frame buffer B'. Frame buffer A' is used to store the 60Hz third image output by processing path A, and frame buffer B' is used to store the 24Hz third image output by processing path B.

[0126] It should be noted that at a specific frame moment, the N second storage spaces may only partially store the third image of the refresh frame, while the other part of the second storage space may not store the third image. For example, at a certain frame moment, only processing path A generates a 60Hz third image, while processing path B does not generate a 24Hz third image. In this case, the mosaic module only reads the third image from the second storage space containing the third image and leaves the sub-regions where the third image does not exist empty. That is, the first image is formed by mosaicking only the third image with the refresh frame.

[0127] In this embodiment, the third image output by the processing path 21 is stored in the corresponding second storage space according to the refresh frame rate, so that the puzzle module can obtain the third image to be puzzled from the second storage space.

[0128] It should be noted that when there are at least two processing paths 21, for example, M processing paths 21, the synthesis module is used to synthesize the data streams output by the M processing paths 21 to obtain the first image; or, the mosaic module is used to mosaic the M third images processed by the M processing paths 21 to obtain the first image.

[0129] Furthermore, in the case where the DPU 2 includes M processing paths 21, in order to enable the jigsaw puzzle module to know which processing paths 21 have newly generated third images, the jigsaw puzzle module can actively detect whether each processing path 21 has a newly generated third image, or a first unit can be set in the jigsaw puzzle module, the first unit being used to determine whether each processing path 21 has the processed third image, or the first unit being used to receive first information from each processing path 21.

[0130] Optionally, the jigsaw puzzle module includes a first unit, which is used to determine whether the M processing paths have the processed third image, or the first unit is used to receive first information from the M processing paths;

[0131] Specifically, when the first unit receives the first information from the target processing path or determines that the target processing path has the processed third image, the puzzle module reads the image data of the processed third image from the second storage space corresponding to the target processing path.

[0132] Among them, the processing path 21 in DPU 2 includes the aforementioned target processing path.

[0133] In some implementations, the first information is used to indicate to the processing path 21 that a new third image has been generated. The processing path 21 may send the first information to the first unit when generating the third image or during the process of generating the third image.

[0134] In this embodiment, the jigsaw puzzle module can determine which processing paths 21 have newly generated third images based on the judgment result of the first unit or the reception of the first information, and thus obtain the newly generated third images for jigsaw puzzle processing.

[0135] It is worth noting that, given that the display area 12 that needs to be refreshed differs at a specific frame moment—that is, the distribution of sub-regions in the first image processed by DPU 2 differs—DPU 2 can store the processed first image in different frame buffers based on the different display areas 12 that need to be refreshed. In other words, the reference frame rate in different frame buffers can be different.

[0136] As an optional implementation, the display control system further includes:

[0137] The first cache 3 and the first storage space 4 are used to cache layer information, and the first storage space 4 is used to iteratively store at least one row of image data in the first image processed by the DPU 2 to be transmitted to the DDIC 14.

[0138] The number of the first cache 3 is N, and the N first cache 3 correspond one-to-one with the frame rate of the N display areas 12. The N first cache 3 are used to cache the layer information of their respective frame rates.

[0139] The number of the first storage spaces 4 is Y. The Y first storage spaces 4 are respectively used to store the image data of the first image with their respective reference frame rates. The reference frame rate is related to the frame rate of the sub-region containing image content in the corresponding first image.

[0140] The first cache 3 can be a cache in the AP used to cache layer information for various frame rates. The first storage space 4 can be a storage space of a specified size, such as DDR or SRAM. The size of the storage space can be greater than, equal to or less than the image data size of a frame of the first image. When the first storage space 4 is smaller than the image data size of a frame of the first image, a portion of the image data in the first image can be stored each time. When the image data of a certain row is sent to DDIC 14, the image data of that row is deleted from the first storage space 4 so that the next row of image data in the first image after being processed by DPU 2 can be added to the first storage space 4. In this way, the smaller size of the first storage space 4 can be used to iteratively store each row of data in the first image until all the image data of a frame of the first image to be refreshed is sent to DDIC 14.

[0141] For ease of explanation, in the embodiments of this application, the size of the first storage space 4 is usually taken as an example where the size of the first storage space 4 is equal to the data size of a frame of the first image. In this case, the first storage space 4 can be called a frame buffer, that is, it can store a complete frame of the first image at a time.

[0142] For example, the first storage space 4 can be a frame buffer for storing a frame of image content to be refreshed after processing by DPU 2. When refreshing the frame of image is completed, or when transmitting the frame of image content to DDIC 14 is completed, the frame of image content can be deleted from the first storage space 4.

[0143] In this embodiment, image content with different reference frame rates obtained after DPU 2 processing can be distinguished by at least two first storage spaces 4. In this way, when transmitting image content with a specified reference frame rate to DDIC 14, the image content to be transmitted can be obtained from the first storage space 4 corresponding to the reference frame rate.

[0144] For example: Figure 5c and Figure 5d As shown, display content processing path A is used to process images with a frame rate of 60Hz. Display content processing path A obtains the 60Hz layer information from the first buffer 3, performs overlay and other processing on the 60Hz layer information, and outputs the data stream of the 60Hz image. Display content processing path B is used to process images with a frame rate of 24Hz. Display content processing path B obtains the 24Hz layer information from the first buffer 3, performs overlay and other processing on the 24Hz layer information, and outputs the data stream of the 24Hz image. After that, the data streams processed by display content processing path A and display content processing path B are combined by the first processing module 22 (i.e., the compositing module) to obtain a first image. For a specific frame moment, there may be a first image where only the sub-region corresponding to 60Hz has image content, or both the sub-region corresponding to 60Hz and the sub-region corresponding to 24Hz have image content. Based on this, the first storage space 4 is divided into two: frame buffer A and frame buffer B. Frame buffer B is used to store the first image where only the sub-region corresponding to 60Hz has image content, and frame buffer A is used to store the first image where both the sub-region corresponding to 60Hz and the sub-region corresponding to 24Hz have image content.

[0145] Of course, in practice, there may be situations where only the sub-region corresponding to 24Hz has image content at a specific frame time. In this case, the amount of the first storage space can be increased to store the first image that has image content in the sub-region corresponding to only 24Hz.

[0146] For example: Figure 5eAs shown, display content processing path A is used to process images with a frame rate of 60Hz. Display content processing path A obtains the 60Hz layer information from the first cache 3 and performs overlay and other processing on the 60Hz layer information to obtain a 60Hz third image. Display content processing path B is used to process images with a frame rate of 24Hz. Display content processing path B obtains the 24Hz layer information from the first cache 3 and performs overlay and other processing on the 24Hz layer information to obtain a 24Hz third image. After that, the first processing module 22 (i.e., the mosaic module) performs mosaic processing on the third images processed by display content processing path A and display content processing path B to obtain a first image. In this process, the first storage space 4 includes frame buffer C and frame buffer D, and the second storage space includes frame buffer A' and frame buffer B'. Frame buffer A' is used to store the third image at a frame rate of 60Hz after processing by the display content processing path A, and frame buffer B' is used to store the third image at a frame rate of 24Hz after processing by the display content processing path B. The first processing module 22 obtains the third image to be pieced together from frame buffer A' and frame buffer B' respectively. For a specific frame moment, there may be only a 60Hz third image, in which case only the sub-region corresponding to 60Hz in the synthesized first image has image content; or, there may be a 60Hz third image and a 24Hz third image, in which case both the sub-region corresponding to 60Hz and the sub-region corresponding to 24Hz in the synthesized first image have image content. Based on this, frame buffer C and frame buffer D can also be set, where frame buffer C is used to store the first image where only the sub-region corresponding to 60Hz has image content, and frame buffer D is used to store the first image where both the sub-region corresponding to 60Hz and the sub-region corresponding to 24Hz have image content.

[0147] It should be noted that, in one embodiment, the size of the first storage space 4 can be smaller than the size of a first image frame, and the size of the second storage space can be smaller than the size of a third image frame. In this case, the first storage space 4 is used to iteratively store U rows of data in a first image frame to be refreshed, where U is an integer greater than or equal to 1, and the second storage space is used to iteratively store V rows of data in a third image frame to be pieced together, where V is an integer greater than or equal to 1.

[0148] Specifically, processing path 21 iteratively stores V rows of data from the processed third image into the second storage space. The jigsaw puzzle module sequentially reads each row of data from N third images from the second storage space. When a row of data in a third image is read by the jigsaw puzzle module, that row of data is deleted from the second storage space so that the next row of data in the third image can be added to the second storage space, until the jigsaw puzzle module reads a complete frame of the third image to be jigsaw from the second storage space. Similarly, the jigsaw puzzle module can iteratively store at least one row of data after the jigsaw puzzle processing is completed into the first storage space 4 so that DDIC 14 can obtain each row of data of the first image from the first storage space 4. After sending a row of data in the first image to DDIC 14, the row of data is deleted from the first storage space 4 so that the next row of data in the first image can be added to the first storage space 4, until DDIC 14 reads a complete frame of the first image to be refreshed from the first storage space 4.

[0149] For example: Figure 7c As shown, the display content processing path B is used to serially process images at a frame rate of 60Hz and images at a frame rate of 24Hz. At a specific frame moment, the display content processing path B can obtain the layer information of the 60Hz frame rate from the first buffer 3, and perform overlay and other processing on the 60Hz layer information to obtain the first image. In this first image, only the sub-region corresponding to 60Hz has image content, and this first image is stored in the frame buffer A. At another specific frame moment, the display content processing path B can obtain the layer information of the 60Hz frame rate and the 24Hz frame rate from the first buffer 3, and perform overlay and other processing on the 60Hz and 24Hz layer information respectively to obtain the first image. In this first image, both the sub-region corresponding to 60Hz and the sub-region corresponding to 24Hz have image content, and this first image is stored in the frame buffer B.

[0150] It is worth noting that in implementation, DDIC 14 can also have at least two different cache spaces, such as Figure 4a As shown, DDIC 14 includes SRAM 1 and SRAM 2. In this way, DDIC 14 can associate SRAM 1 with the display area corresponding to the image content that needs to be refreshed. For example, SRAM 1 stores the image content corresponding to display area A, and SRAM 2 stores the image content corresponding to display area B; or SRAM 1 stores the image content corresponding to display areas A and B, and SRAM 2 stores the image content corresponding to display area A, etc.

[0151] As an optional implementation method, such as Figure 4e , Figure 5e , Figure 6 and Figure 8As shown in any one of the following, the DPU 2 further includes:

[0152] X first interfaces 23, where X is a positive integer, the DPU 2 sends the first image to the DDIC 14 through the X first interfaces 23.

[0153] The first interface 23 can be a Display Serial Interface (DSI). For example, DPU 2 and DDIC 14 are connected via a Display Serial Interface (DSI), as follows: Figure 4c As shown, the two processing paths 21 of DPU 2 are connected to DDIC 14 through two Mobile Industry Processor Interface (MIPI) DSI interfaces.

[0154] Optionally, such as Figure 4c As shown, the MIPI DSI interface typically uses the MIPI D physical layer (Dphy) interface, consisting of four data lines and one set of clock signal lines. CLK_P + CLK_N form one set of differential clock signal lines, where P represents positive and N represents negative. The data lines are also differential signals. D0_P and D0_N represent the first set of data lines, where D0 represents data0, P represents positive, and N represents negative. The other three sets of data lines follow the same pattern.

[0155] Of course, the first interface 23 can also be other image data transmission interfaces. For ease of explanation, this embodiment of the application uses the first interface 23 as a DSI interface as an example for illustration, which does not constitute a specific limitation.

[0156] In this embodiment, the first image processed by DPU 2 is sent to DDIC 14 via the DSI interface.

[0157] It should be noted that during the display control process, the image content output by DPU 2 can be sent to the storage space of DDIC 14 via the MIPI DSI interface under TE signal synchronization, such as Static Random-Access Memory (SRAM) or line buffer. Then, under the drive of circuits such as the DDIC 14 controlling the display screen GOA, the content in the storage space of DDIC 14 is refreshed line by line onto display screen 1.

[0158] The aforementioned line-by-line refresh can be performed from the top to the bottom of the display screen 1, or from the bottom to the top of the display screen 1; no specific limitation is made here.

[0159] Implementation Method 2

[0160] like Figure 4a and Figure 4b As shown in the embodiment of this application, another display control system includes:

[0161] Display screen 1 and DPU 2, with display screen 1 connected to DPU 2;

[0162] The display screen 1 includes: DDIC 14, control circuit 11, N display areas 12, and N driving circuits 13, where N is an integer greater than 1;

[0163] DPU 2 includes M processing paths 21, where M is a positive integer;

[0164] DDIC 14 is connected between the processing path 21 and the N drive circuits 13;

[0165] N driving circuits 13 correspond one-to-one with N display areas 12;

[0166] The control circuit 11 is connected to N drive circuits 13 respectively;

[0167] Among them, M processing paths 21 are used to acquire layer information and process the layer information in parallel to obtain N second images, and send the N second images to DDIC 14;

[0168] DDIC 14 is used to send the target second image to the target driving circuit, and control circuit 11 is used to control the target driving circuit to perform a first operation. The first operation includes: refreshing the target display area according to a first frame rate, where the first frame rate is the frame rate of the target display area, wherein the frame rate of the target second image is the same as the frame rate of the target display area, N second images include the target second image, N driving circuits 13 include the target driving circuit, N display areas 12 include the target display area, and the target driving circuit corresponds to the target display area.

[0169] The differences between this second embodiment and the first embodiment are as follows: In this embodiment, the frame image refreshed by each display area 12 is treated as an independent second image, while in the previous embodiment, the frame images refreshed by all display areas 12 were treated as a whole first image. Furthermore, in this embodiment, M processing paths 21 are used to process image content at different frame rates in parallel, which improves image processing efficiency. In this embodiment, the DDIC 14 only needs to drive the display areas 12 to refresh their respective second images via the driving circuit 13.

[0170] It should be noted that when the refresh rates of the N display areas 12 are different, at a specific frame moment, at least a portion of the display content of the display areas 12 can be refreshed. In this case, some of the N second images may not have any image content. For second images without image content, it is not necessary to drive the corresponding display area to refresh the display content through the driving circuit 13.

[0171] For example, assuming that the refresh rate of display area A is 60Hz and the refresh rate of display area B is 24Hz, then at a certain frame, both display area A and display area B have image content in their respective sub-regions; while at another frame, only the second image corresponding to display area A with the higher refresh rate is generated, and the second image corresponding to display area B with the lower refresh rate is not generated. Thus, when the driving circuit 13 refreshes the second image of the other frame to the display screen, the driving circuit 13 corresponding to display area A drives display area A to refresh, while the driving circuit 13 corresponding to display area B does not drive display area B to refresh.

[0172] It should be noted that M can be less than or equal to N.

[0173] The processing path 21 in this embodiment can also be called the display content processing path. The display content processing path can obtain the layer information of the specified frame rate in the first cache 3, and perform overlay and other processing on these layer information to obtain a frame image.

[0174] In one implementation, at least two processing paths 21 in the DPU 2 can be used to process refresh frame images of different display areas 12 in parallel, for example: Figure 5a and Figure 5b As shown, the refreshed image content of display area A is processed using processing path A (hereinafter referred to as "path A") in DPU 2, and the refreshed image content of display area B is processed using processing path B (hereinafter referred to as "path B") in DPU 2.

[0175] In this embodiment, M can be equal to N.

[0176] As an optional implementation method, such as Figure 4e , Figure 5e , Figure 6 and Figure 8 As shown in any one of the following, the DPU 2 further includes:

[0177] X first interfaces 23, where X is a positive integer, the DPU 2 sends N second images to the DDIC 14 through the X first interfaces 23.

[0178] The first interface 23 can be a Display Serial Interface (DSI). For example, DPU 2 and DDIC 14 are connected via a Display Serial Interface (DSI), as follows: Figure 4c As shown, the two processing paths 21 of DPU 2 are connected to DDIC 14 through two Mobile Industry Processor Interface (MIPI) DSI interfaces.

[0179] Optionally, such as Figure 6 As shown, when the DPU 2 includes M processing paths 21, X equals M, and X of the first interfaces 23 are connected to the M processing paths 21 in a one-to-one correspondence.

[0180] The images processed by the M processing paths 21 are sent to the DDIC 14 through their respective first interfaces 23.

[0181] Of course, when the DPU 2 includes M processing paths 21, X can be less than M or greater than M.

[0182] For example, when X is less than M, at least two processing paths 21 can use the same first interface 23 to send the processed image content to the DDIC 14 in a time-division manner.

[0183] For example, when X is greater than M, the same processing path 21 can send the processed image content to the DDIC 14 in parallel using at least two first interfaces 23. Alternatively, if there are at least two displays 1, the first interfaces 23 correspond one-to-one with the displays 1, and the M processing paths 21 are connected to the X first interfaces through the switching module 24. The switching module 24 can switch the conduction state between the two processing paths 21 of the DPU 2 and the two DSI interfaces.

[0184] Optionally, X equals N, and X of the first interfaces 23 correspond one-to-one with N of the display areas 12;

[0185] Each of the first interfaces 23 is used to transmit the second image of its respective display area 12.

[0186] In this embodiment, DDIC 14 can determine the display area 12 corresponding to the second image based on the first interface 23 for transmitting the second image, and then drive the driving circuit 13 corresponding to the display area 12 to refresh the second image to the display area 12.

[0187] Optionally, such as Figure 4cAs shown, the MIPI DSI interface typically uses the MIPI D physical layer (Dphy) interface, consisting of four data lines and one set of clock signal lines. CLK_P + CLK_N form one set of differential clock signal lines, where P represents positive and N represents negative. The data lines are also differential signals. D0_P and D0_N represent the first set of data lines, where D0 represents data0, P represents positive, and N represents negative. The other three sets of data lines follow the same pattern.

[0188] Of course, the first interface 23 can also be other image data transmission interfaces. For ease of explanation, this embodiment of the application uses the first interface 23 as a DSI interface as an example for illustration, which does not constitute a specific limitation.

[0189] In this embodiment, the first or second image processed by DPU 2 is sent to DDIC14 via the DSI interface.

[0190] It should be noted that during the display control process, the image content output by DPU 2 can be sent to the storage space of DDIC 14 via the MIPI DSI interface under TE signal synchronization, such as Static Random-Access Memory (SRAM) or line buffer. Then, under the drive of circuits such as the DDIC 14 controlling the display screen GOA, the content in the storage space of DDIC 14 is refreshed line by line onto display screen 1.

[0191] The aforementioned line-by-line refresh can be performed from the top to the bottom of the display screen 1, or from the bottom to the top of the display screen 1; no specific limitation is made here.

[0192] Optionally, such as Figure 4c As shown, a switching module 24 can be provided between at least two processing paths 21 and DDIC 14. The switching module 24 can switch the conduction state between the two processing paths 21 of DPU 2 and the two DSI interfaces.

[0193] For example, if the DPU 2 includes M processing paths 21, where M is greater than 1 and X is less than M, the DPU 2 further includes:

[0194] The switching module 24 includes M first terminals and X second terminals. The M first terminals are connected to the M processing paths 21 in a one-to-one correspondence, and the X second terminals are connected to the X first interfaces 23 in a one-to-one correspondence.

[0195] The switching module 24 is used to switch the conduction relationship between X second terminals and M first terminals. When the target first terminal and the target second terminal are connected, the second image processed by the processing path 21 connected to the target first terminal is sent to the DDIC 14 through the first interface 23 connected to the target second terminal. The M first terminals include the target first terminal, and the X second terminals include the target second terminal.

[0196] In this embodiment, the switching module 24 can switch the conduction state between the processing path 21 and the first interface 23. For example, the processing path 21 that generates refreshed image content can be changed at different frame times. The switching module 24 can connect the processing path 21 that generates the second image to the first interface 23, so that the processing path 21 that generates refreshed image frames can send refreshed image content to DDIC 14 through the first interface 23.

[0197] It is worth noting that, given that the display area 12 that needs to be refreshed is different at a specific frame moment—that is, the display area 12 corresponding to the second image is different—DPU 2 can store the processed second image in different frame buffers according to the different display areas 12 that need to be refreshed. In other words, the reference frame rate in different frame buffers can be different.

[0198] As an optional implementation, the display control system further includes:

[0199] The first cache 3 and the first storage space 4 are used to cache layer information, and the first storage space 4 is used to iteratively store at least one row of image data to be transmitted to the DDIC in the second image processed by the DPU 2.

[0200] The number of the first cache 3 is N, and the N first cache 3 correspond one-to-one with the frame rate of the N display areas 12. The N first cache 3 are used to cache the layer information of their respective frame rates.

[0201] The number of the first storage spaces 4 is Y, and the Y first storage spaces 4 are respectively used to store image data in the second image with their respective reference frame rates, wherein the reference frame rate is related to the frame rate of the corresponding second image.

[0202] The first cache 3 can be a cache in the AP used to cache layer information for various frame rates. The first storage space 4 can be a storage space of a specified size, such as DDR or SRAM. The size of the storage space can be greater than, equal to or less than the image data size of a frame of the second image. When the first storage space 4 is smaller than the image data size of a frame of the second image, a portion of the image data in the second image can be stored each time. When the image data of a certain row is sent to DDIC 14, the image data of that row is deleted from the first storage space 4 so that the next row of image data in the second image after being processed by DPU 2 can be added to the first storage space 4. In this way, the smaller size of the first storage space 4 can be used to iteratively store each row of data in the second image until all the image data of a frame of the second image to be refreshed is sent to DDIC 14.

[0203] For ease of explanation, in the embodiments of this application, the size of the first storage space 4 is usually taken as an example where the data size of one frame of the second image is equal to that of the first storage space 4. In this case, the first storage space 4 can be called a frame buffer, that is, it can store one complete frame of the second image at a time.

[0204] For example, the first storage space 4 can be a frame buffer for storing a frame of image content to be refreshed after processing by DPU 2. When refreshing the frame of image is completed, or when transmitting the frame of image content to DDIC 14 is completed, the frame of image content can be deleted from the first storage space 4.

[0205] In this embodiment, image content with different reference frame rates obtained after DPU 2 processing can be distinguished by at least two first storage spaces 4. In this way, when transmitting image content with a specified reference frame rate to DDIC 14, the image content to be transmitted can be obtained from the first storage space 4 corresponding to the reference frame rate.

[0206] For example: Figure 4c , Figure 4eAs shown, assuming the first storage space 4 includes frame buffer 3A and frame buffer 3B, and display content processing path A is used to process images at a frame rate of 60Hz, then display content processing path A obtains the 60Hz layer information from the first buffer 3, performs overlay processing on the 60Hz layer information to obtain a 60Hz second image, and stores the 60Hz second image in frame buffer 3A. Subsequently, DDIC 14 can obtain the 60Hz second image from frame buffer 3A through the first interface 23 and drive GOA to refresh the 60Hz second image to the display area 12 refreshed at 60Hz. Similarly, display content processing path B is used to process images at a frame rate of 24Hz, then display content processing path B obtains the 24Hz layer information from the first buffer 3, performs overlay processing on the 24Hz layer information to obtain a 24Hz second image, and stores the 24Hz second image in frame buffer 3B. Subsequently, DDIC 14 can obtain the 24Hz second image from frame buffer 3B through the first interface 23, and drive GOA 1 to refresh the 24Hz second image to the display area 12 which is refreshed at 24Hz.

[0207] It is worth noting that in implementation, DDIC 14 can also have at least two different cache spaces, such as Figure 4a As shown, DDIC 14 includes SRAM 1 and SRAM 2. In this way, DDIC 14 can associate SRAM 1 with the display area corresponding to the image content that needs to be refreshed. For example, SRAM 1 stores the image content corresponding to display area A, and SRAM 2 stores the image content corresponding to display area B; or SRAM 1 stores the image content corresponding to display areas A and B, and SRAM 2 stores the image content corresponding to display area A, etc.

[0208] Implementation Method 3

[0209] The third display control system provided in this application embodiment may include:

[0210] Display screen 1 and DPU 2, with display screen 1 connected to DPU 2;

[0211] The display screen 1 includes: DDIC 14, control circuit 11, N display areas 12, and N driving circuits 13, where N is an integer greater than 1;

[0212] DPU 2 includes M processing paths 21 and a first processing module 22. The M processing paths 21 are connected to the first processing module 22, and M is a positive integer.

[0213] DDIC 14 is connected between the first processing module 22 and N drive circuits 13;

[0214] N driving circuits 13 correspond one-to-one with N display areas 12;

[0215] The control circuit 11 is connected to N drive circuits 13 respectively;

[0216] Among them, M processing paths 21 are used to acquire layer information and perform parallel or serial processing on the layer information. The first processing module 22 is used to perform a first processing on the output information of the M processing paths 21 to obtain a first image and send the first image to the DDIC 14.

[0217] DDIC 14 is used to drive N driving circuits 13 to refresh the corresponding sub-regions in the first image to the corresponding display area 12. Control circuit 11 is used to control the target driving circuit to perform a first operation, the first operation including: refreshing the target display area according to a first frame rate, the first frame rate being the frame rate of the target display area, wherein the N driving circuits 13 include the target driving circuit, the N display areas 12 include the target display area, and the target driving circuit corresponds to the target display area.

[0218] This third embodiment can be a combination of the first and second embodiments described above.

[0219] In one implementation, M equals 1. In this case, a processing path 21 in DPU 2 can be used to serially process the refresh frame images of different display areas 12, for example: Figure 7a and Figure 7b As shown, the same processing path 21 can be used to process the refreshed image content of display area A and display area B in a time-division manner.

[0220] In another implementation, M can be any integer greater than 1 and less than N. In this case, the same processing path 21 can serially process the refreshed image content of at least two display areas 12, and at least two processing paths 21 can process the refreshed image content in parallel.

[0221] In another implementation, M can be equal to N. In this case, M processing paths 21 are used to process the image content corresponding to their respective refresh rates in parallel.

[0222] In one implementation, such as Figure 5c As shown, the first processing module 22 includes a synthesis module, which is used to synthesize the data streams output from the M processing paths 21 to obtain the first image.

[0223] In this embodiment, the processing path 21 transmits data streams to the compositing module, which then combines the received data streams to obtain a data stream of a first image. At this time, the first processing can be the compositing processing of the data streams.

[0224] In another implementation, such as Figure 5d and Figure 5e As shown, the first processing module 22 includes a jigsaw puzzle module, which is used to perform jigsaw puzzle processing on the M third images processed by the M processing paths to obtain the first image.

[0225] In this embodiment, the processing path 21 transmits the third image to the jigsaw puzzle module, and the synthesis module combines the M third images into a first image. At this time, the first processing module is used to perform image synthesis processing.

[0226] In another implementation, such as Figure 7a , Figure 7b and Figure 7c As shown, when a processing path 21 serially processes image content of at least two different frame rates, the first processing module 22 can integrate the image content of N display areas 12 after processing by the processing path 21 into a first image.

[0227] It is worth noting that at a specific frame moment, a portion of the image in display area 12 may not be refreshed, such as... Figure 7b As shown, the sub-region corresponding to the non-refreshed display area 12 in the first image synthesized by the first processing module 22 has no image content.

[0228] The display control system provided in this application allows for separate processing of content at different frame rates during data processing by the DPU 2 of the AP. For example, for 60Hz content, refresh image frames are generated at a 60Hz frame rate, and for 24Hz content, refresh image frames are generated at a 24Hz frame rate. This ensures that the actual frame rate of different screen content is sent to the DDIC 14, thereby enabling the display screen 1 to refresh at the actual different display frame rates. This avoids the need, as in related technologies, to repeatedly pad the 24Hz content to 60Hz and then refresh the 24Hz content on the display screen at a 60Hz frame rate when refreshing display content at 60Hz and 24Hz in different display areas.

[0229] To facilitate understanding of the display control system in this application embodiment, it is assumed that N equals 2, and the display control system provided in this application embodiment is illustrated using the following scenario:

[0230] Scenario 1: The processing path 21 corresponds one-to-one with the frame rate. Each processing path 21 is used to independently process the image content of its corresponding frame rate.

[0231] like Figure 4b As shown, DPU 2 retrieves content A and content B at different frame rates from different first buffers. Under the synchronization of the same synchronization signal TE, content A is processed through independent path A of DPU 2, and content B is processed through independent path B of DPU 2. Then, the processed content B is first sent to SRAM 2 and refreshed to the 24-frame display area of ​​the screen for display. The processed content A is then sent to the corresponding SRAM 1 and refreshed to the 60-frame display area of ​​the screen for display.

[0232] During the refresh process of display screen 1, control circuit 11 can divide display screen 1 into two display areas 12 that refresh at 60 frames and 24 frames respectively, so that the GOA circuit of the 24-frame refresh display area 12 refreshes at a driving clock of 24 Hz, while the GOA circuit of the 60-frame refresh display area 12 refreshes at a driving clock of 60 Hz.

[0233] Optionally, such as Figure 4c As shown, high frame rate (60 frames per second) content is processed by display content processing path A and then sent to MIPI DSI port B for display on DDIC 14. Low frame rate (24 frames per second) content is sent to DDIC 14 for display via MIPI DSI port B through display content processing path B. Since both display content processing path A and display content processing path B are connected to MIPI DSI port B, a switching module 24 can be set up. This switching module 24 includes a switching switch and an arbitration module. Under the control of the arbitration module, the switching switch is adjusted to ensure that display content processing path A and display content processing path B are sequentially and orderly sent to display screen 1 via MIPI DSI port B.

[0234] Optionally, for better synchronization, two or more TE synchronization signals can be set. For example: Figure 4d As shown, data from channel B is sent to SRAM 2 of DDIC 14 under the synchronization of TE 2, and then sent to the 24-frame display area of ​​display screen 1 for refresh display; data from channel A is sent to SRAM 1 of DDIC 14 under the synchronization of TE1, and then sent to the 60-frame display area of ​​display screen 1 for refresh display.

[0235] Furthermore, two DDICs 14 can also be set on display screen 1, with different DDICs 14 responsible for controlling display areas with different frame rates on display screen 1. For example: Figure 4eAs shown, the 24Hz display content processed by path A is sent to the 24-frame display area 12 via a DDIC 14 for display; the 60Hz display content processed by path B is sent to the 60-frame display area 12 via another DDIC 14 for display. Path A and path B are controlled by different TE synchronization signals.

[0236] Scenario 2: Add a first processing module 22 (which can also be called a post-processing module, compositing module, jigsaw puzzle module, etc.).

[0237] like Figure 5a and Figure 5b As shown, in DPU 2, the 60Hz content of display area A is processed through path A, and the 24Hz content of display area B is processed through path B. Then, a first processing module 22 is added. The content processed by path A and path B is combined into a large image (the first image), which is then sent to the storage space of DDIC 14. After that, DDIC 14 refreshes the first image onto the display screen 1. During this process, DPU 2 can obtain the frame rate information and other metadata from the first cache 3, and after reference, assist path A, path B, and the first processing module 22 in coordinating according to the frame rate content.

[0238] Specifically, because content displayed at a lower frame rate has fewer frames than content displayed at a higher frame rate, for example: Figure 5b As shown, in some cases, when the 60Hz content of display area A is finished being processed, the 24Hz content of display area B is empty at this time. In this case, the first processing module 22 can refer to the frame rate information and other metadata to update only the 60Hz part of the display content to be refreshed to DDIC 14, and then DDIC 14 refreshes this updated display content to the corresponding display area A of display screen 1.

[0239] Optionally, path A processes 60 frames of display content, and path B processes 24 frames of display content. The compositing module then uses the content processed by these two paths as layers to composite the display frames (i.e., the first image) in the frame buffer. Figure 5c As shown, when both 60 frames and 24 frames are present, the composite first frame is stored in frame buffer B and refreshed onto display screen 1 via DDIC 14. When the content of 24 frames is missing, another frame buffer A is allocated, at which point the first image contains only the content of 60 frames, and it is refreshed onto the corresponding display area 12 on display screen 1 via DDIC 14. In this way, different frame rates are refreshed by storing different content in two frame buffers.

[0240] Optionally, the first processing module 22 can be a jigsaw puzzle module, for example: Figure 5d or Figure 5e As shown, the images processed by display content processing path A and display content processing path B and stored in the frame buffer are retrieved and re-stitched. The stitching module may include a judgment module or a receiving information module. For example, it can receive data information from display content processing path A and display content processing path B. This data information can be used to inform the stitching module whether new content will be delivered next. If content is delivered from both display content processing paths, the processed image content of the two display content processing paths is extracted from frame buffer A' and frame buffer B' respectively, and stitched into a large image and stored in frame buffer D. If only display content processing path A has processed high frame rate content, the processed image content of display content processing path A extracted from frame buffer A' is stored in frame buffer C, or the high frame rate display content in frame buffer A' is directly sent to DDIC 14.

[0241] Of course, in addition to sending data information to the puzzle module through the display content processing path to inform the puzzle module whether there is new content to be delivered, the puzzle module can also use other methods to find out whether there is new content to be delivered through the display content processing path. For example, the puzzle module can detect whether there is new content to be delivered through the display content processing path itself.

[0242] In addition, for such Figure 5e In the illustrated embodiment, frame buffers A' and B' can be omitted. Instead, the image content processed by the display content processing path can be directly stitched together by the stitching module and stored in frame buffer D or frame buffer C.

[0243] Scenario 3: Transmit the image content processed by DPU 2 to DDIC 14 through at least two first interfaces 23.

[0244] In one implementation, at least two first interfaces 23 can be interfaces obtained by forking the MIPI interface, for example: Figure 6 As shown, the MIPI interface of DPU 2 is forked into two DSI interfaces, namely DSI_1 and DSI_2. The content of path A is sent to DDIC 14 via DSI_1 and can be stored in a designated memory space of DDIC 14, such as SRAM1, for improved system reliability. The content of path B is sent to DDIC 14 via DSI_2 and can be stored in another designated memory space of DDIC 14, such as SRAM 2, for further system reliability. Then, DDIC 14 can refresh the content stored in SRAM 1 and SRAM 2 onto the corresponding display area 12.

[0245] Through at least two first interfaces 23, image content refreshed at different frame rates can be synchronously transmitted to DDIC 14, thereby enabling DDIC 14 to synchronously drive at least two display areas 12 to refresh the display content according to their respective frame rates, which helps to improve the smoothness of at least two display areas 12 refreshing according to their respective frame rates.

[0246] Scenario 4: The same processing path 21 serially processes image content at least two frame rates.

[0247] like Figure 7a As shown, DPU 2 can have only one processing path 21. DPU 2 retrieves the 60Hz content corresponding to display area A and the 24Hz content corresponding to display area B from the first cache, and processes them on the processing path 21 of DPU 2. Then, they are combined in the first processing module 22 to obtain a first image including the display content of display area A and display area B, and then sent to display screen 1 for display through the DSI interface.

[0248] like Figure 7b As shown, because the number of content frames at 24Hz is less than that at 60Hz, sometimes the first buffer only contains 60Hz content. After receiving it, DPU 2 only processes the 60Hz content and sends the processed image content to the first processing module 22. The first processing module 22 performs data alignment and other processing on the data to be sent before sending it to the display screen 1. The data alignment processing may include adjusting the sending position, data sending timing, etc., to avoid display errors.

[0249] Optionally, in order to improve data reliability, the first processing module 22 may partition and store data based on the frame rate of the image.

[0250] For example: Figure 7c As shown, only the display content processing path B is used for serial processing. When both high frame rate (60Hz) and low frame rate (24Hz) content are available, a frame of content is synthesized and stored in frame buffer B. The image content in frame buffer B is then sent to DDIC 14 to refresh the display screen 1. When low frame rate content is missing, another frame buffer A is opened. The image stored in frame buffer A is only high frame rate content. After that, the image content in frame buffer A is sent to DDIC 14 to refresh the corresponding display area 12 on display screen 1.

[0251] In this way, different content is stored in two frame buffers to achieve refresh when displaying content at different frame rates. Of course, only one frame buffer can be set up, or the first processing module 22 can determine the size of the image content processed by the display content processing path B, and decide whether to store the display content in frame buffer A or frame buffer B accordingly.

[0252] In this scenario, one processing path 21 can process image content at different frame rates, which can reduce the number of processing paths 21 and reduce the structural complexity of the display control system.

[0253] Scenario 5: The same processing path 21 serially processes image content at least two frame rates, and transmits the image content processed by DPU 2 to DDIC 14 through at least two first interfaces 23.

[0254] This scenario combines scenarios three and four above. One processing path 21 can process image content at different frame rates, and the processed data at different frame rates can be transmitted separately to display screen 1. In this way, display screen 1 can distinguish the display area 12 corresponding to the image content transmitted by a data interface based on the source of the data interface, and thus refresh the image frame received from a certain data interface onto the corresponding display area 12.

[0255] This application also provides an electronic device, which may include, for example, Figures 4a to 9 Any of the display control systems shown in the embodiments.

[0256] For example, electronic devices can be mobile phones, tablets, laptops, handheld computers, in-vehicle electronic devices, mobile internet devices (MID), augmented reality (AR) / virtual reality (VR) devices, robots, wearable devices, ultra-mobile personal computers (UMPCs), netbooks, or personal digital assistants (PDAs), etc. They can also be servers, network attached storage (NAS), personal computers (PCs), televisions (TVs), ATMs, or self-service machines, etc. The embodiments of this application do not impose specific limitations.

[0257] The electronic device provided in this application embodiment, based on a display control system, can refresh the display screen at its respective frame rate on different display areas, thereby saving energy consumption of the electronic device.

[0258] This application also provides a display method, which can be applied to, for example... Figures 4a to 9 Any of the display control systems in the illustrated embodiments, such as Figure 10 As shown, the method includes:

[0259] Step 1001: Obtain the frame rate corresponding to at least two display areas on the display screen.

[0260] Step 1002: Refresh the image content in the at least two display areas according to their respective frame rates.

[0261] The frame rate corresponding to each of the at least two display areas on the screen can be obtained based on at least one of the following: user settings, application scenario, system configuration, user operation trigger, etc. For example, when power saving mode is enabled, the refresh rate of the screen is lower.

[0262] For example, the refresh rate can be different when different applications are opened. For instance, the refresh rate of the chat interface is lower than that of the game interface.

[0263] For example, the refresh rate of the display area operated by the user is higher than the refresh rate of the display area not operated by the user.

[0264] The at least two display areas can be the display areas corresponding to the interfaces of at least two applications, or the at least two display areas can be the display areas of different windows in the same application, without being specifically limited here.

[0265] In this embodiment, the GOA circuits corresponding to each of the at least two display areas can be controlled by a control circuit to refresh the display areas according to their respective frame rates. Furthermore, this embodiment can achieve the same results as... Figures 4a to 9 The same technical effects are achieved by any of the display control systems in the illustrated embodiments, and will not be repeated here to avoid repetition.

[0266] Optionally, such as Figure 11 As shown, this application embodiment also provides an electronic device 1100, including a processor 1101 and a memory 1102. The memory 1102 stores a program or instructions that can run on the processor 1101. When the program or instructions are executed by the processor 1101, they implement the various steps of the above-described display method embodiment and can achieve the same technical effect. To avoid repetition, they will not be described again here.

[0267] It should be noted that the electronic devices in the embodiments of this application include the mobile electronic devices and non-mobile electronic devices described above.

[0268] Figure 12 A schematic diagram of the hardware structure of an electronic device to implement an embodiment of this application.

[0269] The electronic device 1200 includes, but is not limited to, components such as: radio frequency unit 1201, network module 1202, audio output unit 1203, input unit 1204, sensor 1205, display unit 1206, user input unit 1207, interface unit 1208, memory 1209, and processor 1210.

[0270] Those skilled in the art will understand that the electronic device 1200 may also include a power supply (such as a battery) for supplying power to various components. The power supply may be logically connected to the processor 1210 through a power management system, thereby enabling functions such as managing charging, discharging, and power consumption through the power management system. Figure 12 The electronic device structure shown does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements, which will not be elaborated here.

[0271] The processor 1210 is used to obtain the frame rate corresponding to at least two display areas on the display screen.

[0272] The processor 1210 is also configured to control the display unit 1206 to refresh image content in the at least two display areas according to their respective corresponding frame rates.

[0273] The electronic device provided in this application embodiment can achieve the following: Figure 10 The various processes of the method embodiments shown are all capable of achieving the same beneficial effects, and will not be described again here to avoid repetition.

[0274] It should be understood that, in this embodiment, the input unit 1204 may include a graphics processing unit (GPU) 12041 and a microphone 12042. The GPU 12041 processes image data of still images or videos obtained by an image capture device (such as a camera) in video capture mode or image capture mode. The display unit 1206 may include a display panel 12061, which may be configured in the form of a liquid crystal display, an organic light-emitting diode, or the like. The user input unit 1207 includes a touch panel 12071 and at least one of other input devices 12072. The touch panel 12071 is also called a touch screen. The touch panel 12071 may include a touch detection device and a touch controller. Other input devices 12072 may include, but are not limited to, physical keyboards, function keys (such as volume control buttons, power buttons, etc.), trackballs, mice, and joysticks, which will not be described in detail here.

[0275] The memory 1209 can be used to store software programs and various data. The memory 1209 may primarily include a first storage area for storing programs or instructions and a second storage area for storing data. The first storage area may store the operating system, application programs or instructions required for at least one function (such as sound playback, image playback, etc.). Furthermore, the memory 1209 may include volatile memory or non-volatile memory, or both. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus RAM (DRRAM). The memory 1209 in this embodiment includes, but is not limited to, these and any other suitable types of memory.

[0276] Processor 1210 may include one or more processing units; optionally, processor 1210 integrates an application processor and a modem processor, wherein the application processor mainly handles operations involving the operating system, user interface, and applications, and the modem processor mainly handles wireless communication signals, such as a baseband processor. It is understood that the aforementioned modem processor may also not be integrated into processor 1210.

[0277] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the above-described display method embodiments and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0278] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0279] This application embodiment also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the above-described display method embodiments and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0280] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0281] This application provides a computer program product that is stored in a storage medium and executed by at least one processor to implement the various processes shown in the above-described method embodiments, and can achieve the same technical effects. To avoid repetition, it will not be described again here.

[0282] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0283] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0284] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A display control system, characterized in that, include: A display screen and a display processing unit (DPU), wherein the display screen is connected to the DPU; The display screen includes: a display driver chip DDIC, a control circuit, N display areas, and N driving circuits, where N is an integer greater than 1; The DPU includes a first processing module; The DDIC is connected between the first processing module and the N driving circuits; Each of the N driving circuits corresponds one-to-one with one of the N display areas; The control circuit is connected to each of the N drive circuits; The first processing module is used to determine a first image based on layer information and send the first image to the DDIC. The first image includes N sub-regions, and the N sub-regions correspond one-to-one with the N display regions. The frame rate of the sub-regions and the corresponding display regions is the same. The DDIC is used to drive N driving circuits to refresh their respective sub-regions in the first image to their corresponding display areas. The control circuit is used to control the target driving circuit to perform a first operation, which includes: refreshing the target display area according to a first frame rate, where the first frame rate is the frame rate of the target display area. The N driving circuits include the target driving circuit, the N display areas include the target display area, and the target driving circuit corresponds to the target display area. The display control system further includes: A first cache and a first storage space, wherein the first cache is used to cache layer information, and the first storage space is used to iteratively store at least one row of image data in the first image processed by the DPU that is to be transmitted to the DDIC; The number of first caches is N, and each of the N first caches corresponds one-to-one with the frame rate of the N display areas. Each of the N first caches is used to cache the layer information of its corresponding frame rate. The number of the first storage spaces is Y, and each of the Y first storage spaces is used to store image data in the first image with its corresponding reference frame rate. The reference frame rate is related to the frame rate of the sub-region containing image content in the corresponding first image.

2. The system according to claim 1, characterized in that, The first processing module includes: The compositing module is used to synthesize image data streams of N frame rates to obtain the first image, wherein the image data stream is the data stream output from the processing path in the DPU; or, The jigsaw puzzle module is used to perform jigsaw puzzle processing on a third image with N frame rates to obtain the first image. The third image is the image processed by the processing path in the DPU.

3. A display control system, characterized in that, include: A display screen and a display processing unit (DPU), wherein the display screen is connected to the DPU; The display screen includes: a display driver chip DDIC, a control circuit, N display areas, and N driving circuits, where N is an integer greater than 1; The DPU includes M processing paths, where M is a positive integer; The DDIC is connected between the processing path and the N driving circuits; Each of the N driving circuits corresponds one-to-one with one of the N display areas; The control circuit is connected to each of the N drive circuits; Among them, M processing paths are used to acquire layer information, process the layer information in parallel to obtain N second images, and send the N second images to the DDIC; The DDIC is used to send the target second image to the target driving circuit, and the control circuit is used to control the target driving circuit to perform a first operation. The first operation includes: refreshing the target display area according to a first frame rate, where the first frame rate is the frame rate of the target display area, wherein the frame rate of the target second image is the same as the frame rate of the target display area, N second images include the target second image, N driving circuits include the target driving circuit, the N display areas include the target display area, and the target driving circuit corresponds to the target display area. The display control system further includes: A first cache and a first storage space, wherein the first cache is used to cache layer information, and the first storage space is used to iteratively store at least one row of image data in the second image processed by the DPU that is to be transmitted to the DDIC; The number of first caches is N, and each of the N first caches corresponds one-to-one with the frame rate of the N display areas. Each of the N first caches is used to cache the layer information of its corresponding frame rate. The number of the first storage spaces is Y, and each of the Y first storage spaces is used to store image data in the second image at its corresponding reference frame rate, wherein the reference frame rate is related to the frame rate of the corresponding second image.

4. The system according to claim 3, characterized in that, The DPU also includes: X first interfaces, where X is a positive integer, and the DPU sends N second images to the DDIC through the X first interfaces.

5. The system according to claim 4, characterized in that, When M is greater than 1 and X is less than M, the DPU further includes: The switching module includes M first terminals and X second terminals, wherein the M first terminals are connected one-to-one with the M processing paths, and the X second terminals are connected one-to-one with the X first interfaces. The switching module is used to switch the conduction relationship between X second terminals and M first terminals. When the target first terminal and the target second terminal are connected, the second image processed by the processing path connected to the target first terminal is sent to the DDIC through the first interface connected to the target second terminal. The M first terminals include the target first terminal, and the X second terminals include the target second terminal.

6. The system according to any one of claims 3 to 5, characterized in that, The display control system further includes: A synchronization signal line is provided, which is connected between the DPU and the DDIC. The DDIC is used to send N kinds of synchronization signals to the DPU through the synchronization signal line. Among them, the N types of synchronization signals correspond one-to-one with the frame rates of the N display areas, and the DPU is used to synchronize the second image with the corresponding frame rate to the DDIC according to the N types of synchronization signals.

7. The system according to claim 6, characterized in that, The number of DDICs is N, the number of synchronization signal lines is N, the N synchronization signal lines correspond one-to-one with the N types of synchronization signals, and the N DDICs correspond one-to-one with the N synchronization signal lines. The target DDIC is used to send a target synchronization signal to the DPU through the target synchronization signal line. The N DDICs include the target DDIC, the N synchronization signal lines include the target synchronization signal lines, the N types of synchronization signals include the target synchronization signal, and the target DDIC corresponds to the target synchronization signal line.

8. A display control system, characterized in that, include: A display screen and a display processing unit (DPU), wherein the display screen is connected to the DPU; The display screen includes: a display driver chip DDIC, a control circuit, N display areas, and N driving circuits, where N is an integer greater than 1; The DPU includes M processing paths and a first processing module, wherein the M processing paths are connected to the first processing module, and M is a positive integer; The DDIC is connected between the first processing module and the N driving circuits; Each of the N driving circuits corresponds one-to-one with one of the N display areas; The control circuit is connected to each of the N drive circuits; M processing paths are used to acquire layer information and perform parallel or serial processing on the layer information. The first processing module is used to perform a first processing on the output information of the M processing paths to obtain a first image and send the first image to the DDIC. The DDIC is used to drive N driving circuits to refresh their respective sub-regions in the first image to their corresponding display areas. The control circuit is used to control the target driving circuit to perform a first operation, which includes: refreshing the target display area according to a first frame rate, where the first frame rate is the frame rate of the target display area. The N driving circuits include the target driving circuit, the N display areas include the target display area, and the target driving circuit corresponds to the target display area. The display control system further includes: A first cache and a first storage space, wherein the first cache is used to cache layer information, and the first storage space is used to iteratively store at least one row of image data in the first image processed by the DPU that is to be transmitted to the DDIC; The number of first caches is N, and each of the N first caches corresponds one-to-one with the frame rate of the N display areas. Each of the N first caches is used to cache the layer information of its corresponding frame rate. The number of the first storage spaces is Y, and each of the Y first storage spaces is used to store image data in the first image at its corresponding reference frame rate, wherein the reference frame rate is related to the frame rate of the sub-region containing image content in the corresponding first image.

9. The system according to claim 8, characterized in that, The first processing module includes: The compositing module is used to compose the data streams output from the M processing paths to obtain the first image; or, The jigsaw puzzle module is used to perform jigsaw puzzle processing on the M third images processed by the M processing paths to obtain the first image.

10. The system according to claim 9, characterized in that, When the first processing module includes the puzzle module, the display control system further includes: There are N second storage spaces, each corresponding to one of the N display areas. The N second storage spaces are used to iteratively store at least one row of image data to be transmitted to the puzzle module from the third image. The refresh rate of the third image stored in each of the N second storage spaces is the same as the frame rate of the display area corresponding to each of the N second storage spaces. The puzzle module is used to obtain image data of the third image from N second storage spaces.

11. The system according to claim 10, characterized in that, The puzzle module includes a first unit, which is used to determine whether the M processing paths have the processed third image, or the first unit is used to receive first information from the M processing paths. Specifically, when the first unit receives the first information from the target processing path or determines that the target processing path has the processed third image, the puzzle module reads the image data of the processed third image from the second storage space corresponding to the target processing path.

12. The system according to any one of claims 9 to 11, characterized in that, M is less than N, and at least some of the M processing paths are used to serially process the layer information at at least two different frame rates.

13. The system according to any one of claims 9 to 11, characterized in that, The DPU also includes: The first processing module sends the first image to the DDIC through X first interfaces, where X is a positive integer.

14. An electronic device, characterized in that, Includes the display control system as described in any one of claims 1 to 13.

15. A display method, characterized in that, The method, applied to a display control system as described in any one of claims 1 to 13, comprises: Obtain the frame rate corresponding to at least two display areas on the screen; The image content is refreshed in each of the at least two display areas according to its corresponding frame rate.

16. An electronic device, characterized in that, It includes a processor and a memory, the memory storing a program or instructions that can run on the processor, the program or instructions being executed by the processor to implement the steps of the display method as described in claim 15.

17. A readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, implement the steps of the display method as described in claim 15.

Images