NMOS-based ladder type nuclear radiation total dose indication and compensation circuit

Abstract

A kind of NMOS-based stepped nuclear radiation total dose indication and compensation circuit, comprising: bias circuit provides stepped bias voltage for NMOS tube gate;Stepped bias switching circuit receives NMOS transistor sensing signal, and switches bias voltage to NMOS transistor radiation sensing array circuit;Sensing array circuit is damaged by nuclear radiation source to itself NMOS transistor, and the influence of NMOS transistor threshold voltage to indication circuit board ionizing radiation total dose level;FPGA compensation control circuit receives the level change signal output from sensing array circuit, and the corresponding size of nuclear radiation total dose is output, and the compensation control signal of digital potentiometer is output, and the resistance of radiation damage electric signal output is compensated by modifying digital potentiometer.It is evaluated that the present circuit board is received by the threshold voltage radiation damage effect of NMOS transistor in nuclear radiation environment total dose of fixed point size, and the indication signal is provided for FPGA radiation compensation circuit, with the advantages of low power consumption, strong robustness etc..

Description

Technical Field

[0001] This invention relates to the field of nuclear radiation safety monitoring technology, and in particular to a step-type total nuclear radiation dose indication and compensation circuit based on NMOS. Background Technology

[0002] As nuclear power gradually becomes one of the main methods of power generation, the safety of radioactive nuclear power plants has begun to receive much attention. Nuclear emergency rescue equipment and methods have become a research hotspot, and the demand for nuclear emergency response robots is growing. Robots operating in nuclear environments can effectively reduce the harm to operators caused by nuclear radiation. The most critical aspect of robot systems operating in nuclear radiation environments is overcoming the radiation damage effects on the circuitry. Circuitry systems in nuclear radiation environments are susceptible to the total ionization dose effect, which can cause them to malfunction, leading to the paralysis of the entire robot system.

[0003] Existing methods for handling the total dose effect of ionizing radiation in circuit systems can be broadly categorized into three types: The first type focuses on radiation hardening of semiconductor materials, using process modifications to reduce radiation impact by addressing oxide impurities, oxide layer defects, and oxide layer structure. The second type involves radiation-hardened circuit and layout designs for integrated circuits. Since radiation-induced trap charges accumulate in the oxide layer, causing threshold voltage drift and edge leakage current, potential leakage current paths are cut off by modifying the circuit and device layout. Both of these types of radiation hardening designs require significant research resources and are extremely costly. The third type, modifying the circuit system structure, is typically used to improve radiation resistance. This method generally improves the robustness of the circuit system and requires an assessment of the current radiation dose to enhance its adaptability. Furthermore, typical radiation dose indicator circuits are complex, necessitating additional radiation hardening for weak signal amplification modules.

[0004] Therefore, a highly efficient total dose indication circuit for ionizing radiation is needed to effectively compensate for the electrical signals of radiation damage. Summary of the Invention

[0005] This invention designs a step-type total nuclear radiation dose indication and compensation circuit based on NMOS, comprising:

[0006] Bias voltage circuit, stepped bias switching circuit, NMOS transistor radiation sensing array circuit, and FPGA compensation control circuit.

[0007] The bias circuit consists of multiple resistors connected in series. Each resistor divides the voltage to provide a stepped bias voltage to the gate of the NMOS transistor in the NMOS transistor radiation sensing array circuit. The bias voltage is switched by a stepped bias switching circuit, and the magnitude of the bias voltage is controlled by adjusting the size of the resistors.

[0008] The stepped bias switching circuit receives the NMOS transistor sensing signal from the NMOS transistor radiation sensing array circuit and switches the bias voltage to the NMOS transistor radiation sensing array circuit.

[0009] The NMOS transistor radiation sensing array circuit indicates the total dose level of ionizing radiation on the circuit board by measuring the radiation damage to its own NMOS transistors from the nuclear radiation source and the effect on the threshold voltage of the NMOS transistors.

[0010] The FPGA compensation control circuit consists of an FPGA basic unit and a digital potentiometer. The FPGA basic unit receives the level change signal output from the NMOS transistor radiation sensing array circuit and outputs the corresponding total nuclear radiation dose according to the different IO ports of the level change. At the same time, the FPGA basic unit outputs a compensation control signal to the digital potentiometer to compensate for the output resistance value of the radiation damage electrical signal by modifying the digital potentiometer.

[0011] Furthermore, the series resistance value of the bias voltage circuit is determined by the measured voltage. The gate of the first NMOS transistor in the NMOS transistor radiation sensing array circuit is connected to the start-up bias voltage provided by two voltage divider resistors. The voltage divider voltage is lower than the threshold voltage of a normal NMOS transistor. The remaining resistors are pull-up resistors connected to the drains of the remaining NMOS transistor array.

[0012] Furthermore, the stepped bias switching circuit is composed of multiple two-to-one analog switch circuits. The first data port is connected to the gate of the corresponding NMOS transistor in the NMOS transistor radiation sensing array circuit, the second data port B0 is connected to the voltage divider calibration voltage provided by the bias voltage circuit, the third data port is connected to ground, and the control selection port is connected to the drain of the corresponding NMOS transistor in the NMOS transistor radiation sensing array circuit. When the control selection port is low, the first data port is connected to the second data port; when the data selection port is high, the first data port is connected to the third data port.

[0013] Furthermore, the NMOS transistor radiation sensing array circuit is composed of multiple NMOS transistors connected in parallel. The gate is connected to the calibration voltage of the bias resistor voltage divider or directly grounded, and the switching logic is controlled by a stepped bias switching circuit. The drain is connected to the control selection port of the stepped bias switching circuit and is stabilized at a high level by a pull-up resistor. The source is directly grounded. The gate of the first NMOS transistor among the multiple NMOS transistors is directly connected to the set start-up voltage. The drain of the NMOS transistor radiation sensing array circuit changes level due to nuclear radiation and is connected in parallel to the IO port of the FPGA compensation control circuit.

[0014] Furthermore, after receiving the potential change signal from the NMOS transistor radiation sensing array circuit, the FPGA basic unit calculates the corresponding total nuclear radiation dose through a lookup table unit and outputs it as a digital signal. Simultaneously, the FPGA basic unit inputs the total nuclear radiation dose value into the internal BP network forward calculation unit and outputs the corresponding radiation damage electrical signal parameter offset value. The output resistance of the radiation damage electrical signal is controlled by a digital potentiometer. The offset value that needs to be compensated is output as a digital signal through the FPGA basic unit to control the resistance value of the digital potentiometer to compensate for the radiation damage signal.

[0015] Furthermore, the BP network forward computation unit uses the total nuclear radiation dose and the electrical parameter offset value of the radiation damage signal as training data to build and train the BP neural network. The electrical parameter offset value is the amplitude difference between the radiation damage signal and the normal signal from the sensor. The output value of the BP neural network is the modified value of the digital potentiometer. The weights obtained from training the BP neural network are transcoded and stored in the on-chip RAM of the FPGA basic unit. The total nuclear radiation dose obtained from the lookup table unit is input into the BP neural network. After obtaining the output of the electrical parameter offset value of the radiation damage signal, the digital potentiometer is controlled to compensate for the amplitude of the radiation damage signal.

[0016] This invention utilizes the negative threshold voltage drift characteristic of NMOS transistors in nuclear radiation environments. A calibrated bias voltage is provided to the gate to indicate the degree of this negative drift. This degree effectively represents the total dose level of ionizing radiation in a nuclear radiation environment, providing information for subsequent radiation hardening redundancy or compensation circuits. Existing technologies generally require AD sampling or other complex analog devices, necessitating consideration of the radiation hardening issues of these electronic components. This invention avoids AD conversion and other complex analog devices, employing simple components whose performance is unaffected by radiation. Furthermore, the intelligent BP network forward calculation algorithm within the FPGA program obtains the corresponding radiation damage offset value of the electronic components, converting it into a control signal for a digital potentiometer, achieving intelligent real-time compensation for electrical signals in the radiation environment. Compared to existing technologies, this invention offers advantages such as low cost, simple structure, strong robustness and real-time performance, low power consumption, and no need for additional indicating instrument circuits or radiation hardening designs for electronic components. Attached Figure Description

[0017] Figure 1 A block diagram of the circuit connection logic structure of the present invention is shown;

[0018] Figure 2 The NMOS transistor radiation sensing array circuit of the present invention is shown;

[0019] Figure 3 The bias voltage circuit and stepped bias switching circuit of the present invention are shown.

[0020] Figure 4 The connection diagram of the FPGA compensation control circuit of the present invention is shown; Detailed Implementation

[0021] The technical solution of the present invention will be specifically described below with reference to the embodiments.

[0022] Figure 1 As shown, it mainly consists of a bias voltage circuit, a stepped bias switching circuit, an NMOS transistor radiation sensing array circuit, and an FPGA compensation control circuit.

[0023] The bias voltage circuit consists of multiple resistors connected in series. Each resistor divides the voltage to provide a stepped bias voltage to the gate of the NMOS transistor in the NMOS transistor radiation induction array circuit. The bias voltage is switched by a stepped bias switching circuit, and the magnitude of the bias voltage is controlled by adjusting the size of the resistors.

[0024] The series resistor value of the bias voltage circuit is determined by the measurement voltage to be calibrated, and the required resistor value can be obtained using the series voltage divider formula. The gate of the first NMOS transistor in the NMOS transistor radiation sensing array circuit needs to be connected to a start-up bias voltage provided by two voltage divider resistors; the resistor divider voltage needs to be lower than the normal NMOS transistor threshold voltage. The remaining resistors are pull-up resistors connected to the drains of the remaining NMOS transistor array.

[0025] The stepped bias switching circuit receives the NMOS transistor sensing signal from the NMOS transistor radiation sensing array circuit and switches the bias voltage to the NMOS transistor radiation sensing array circuit.

[0026] The stepped bias switching circuit consists of multiple 2-to-1 analog switch circuits. Data port A is connected to the gate of the corresponding NMOS transistor in the NMOS transistor radiation sensing array circuit. Data port B0 is connected to the voltage divider calibration voltage provided by the bias voltage circuit. Data port B1 is connected to ground. The control selection port is connected to the drain of the corresponding NMOS transistor in the NMOS transistor radiation sensing array circuit. When the control selection port is low, data port A is connected to data port B0; when the control selection port is high, data port A is connected to data port B1.

[0027] The NMOS transistor radiation sensing array circuit indicates the total dose level of ionizing radiation on the circuit board by measuring the effect of radiation damage to the NMOS transistors from nuclear radiation sources on the threshold voltage of the NMOS transistors.

[0028] The NMOS transistor radiation sensing array circuit consists of multiple NMOS transistors connected in parallel. The gate is connected to the calibration voltage of the bias resistor divider or directly to ground, and the switching logic is controlled by a stepped bias switching circuit. The drain is connected to the control selection port of the stepped bias switching circuit and stabilized at a high level by a pull-up resistor. The source is directly grounded. The gate of the first NMOS transistor is directly connected to the set startup voltage and does not require switching circuit control. The drain of the NMOS transistor radiation sensing array circuit changes level due to nuclear radiation and is connected in parallel to the I / O port of the FPGA compensation control circuit.

[0029] Utilizing the radiation damage characteristics of NMOS transistors in a radiation sensing array circuit, the threshold voltage of the NMOS transistors drifts due to interface trap charges and oxide traps generated under nuclear radiation. By applying different threshold voltages to the gate of the NMOS transistors, the transistors are turned on to determine which radiation dose calibration point has been reached. In reality, the NMOS threshold voltage generally drifts negatively under the damage of radiation. By applying a bias voltage to the gate that has not yet reached the threshold voltage, when the NMOS turns on due to the decrease in threshold voltage caused by radiation effects, the corresponding total nuclear radiation dose calibration point can be determined.

[0030] In a nuclear radiation environment, the threshold voltage of an NMOS transistor decreases as the total ionizing radiation dose decreases. The original gate voltage falls below the normal threshold voltage, and the NMOS transistor remains off. For example, the gate of the first NMOS transistor is connected to a startup bias voltage, which is slightly lower than the normal threshold voltage, ensuring it is initially in a non-conducting state. When radiation damage causes the threshold voltage of this NMOS transistor to decrease, the transistor turns on, and the gate signal changes from high to low. This signal serves as an indicator to determine whether the total ionizing radiation dose calibration point has been reached. Simultaneously, this signal also serves as a control logic input to an analog switch. When the previous NMOS transistor turns on, it controls the analog switch to connect the gate of the next-stage NMOS transistor from ground to its bias voltage. The next-stage NMOS transistor then enters a radiation-prone state. When the total ionizing radiation dose causes a greater shift in the threshold voltage of the next-stage NMOS transistor, it turns on again, and this process repeats.

[0031] Those skilled in the art can select the NMOS model, prioritizing models with good radiation tolerance test data for rapid development and verification. By modifying the voltage divider resistance value, the total ionizing radiation dose level corresponding to the bias voltage can be easily controlled.

[0032] The FPGA compensation control circuit processes signals received from the NMOS transistors in the NMOS transistor radiation sensing array circuit via intelligent software algorithms. Specifically, the NMOS drain signal changes from high to low. The radiation damage electrical signal is a simulated signal of interference to electronic components in a radiation environment, primarily considering amplitude damage. The FPGA receives the level change signal from the NMOS transistor radiation sensing array circuit and outputs a corresponding total nuclear radiation dose (radiation dose indication signal) through different I / O ports based on the level change. Simultaneously, the FPGA outputs a compensation control signal to the digital potentiometer, modifying the potentiometer to compensate for the output resistance of the radiation damage electrical signal and correct it back to normal.

[0033] The FPGA compensation control circuit consists of FPGA basic units and digital potentiometers. The signal output of the NMOS transistor radiation sensing array circuit is input as a parallel signal to the FPGA's I / O port. A LUT (Look-Up Table) unit maps the parallel signal to the total nuclear radiation dose, outputting it as a digital signal from the FPGA. Simultaneously, the total radiation dose is input to the internal BP network forward calculation program. For example... Figure 4 As shown, the total nuclear radiation dose and the electrical parameter offset of the radiation damage signal are used as training data on the host computer. The electrical parameter offset is the amplitude difference between the radiation damage signal and the normal signal from the sensor. A BP neural network is built and trained. Considering FPGA performance and storage capacity, a small BP network is constructed with 3×10×5 neurons in the input, hidden, and output layers. The network output is the modified value of the digital potentiometer. The obtained weights are transcoded and stored in the on-chip RAM of the FPGA. During actual operation, the total nuclear radiation dose obtained from the LUT lookup unit is input into the network. After obtaining the electrical parameter offset of the radiation damage signal, the output signal controls the digital potentiometer to compensate for the amplitude of the radiation damage signal, realizing intelligent compensation control. The corresponding electrical parameter offset values ​​of the radiation-damaged electronic components are obtained, and the offset values ​​to be compensated are converted into the resistance values ​​of the digital potentiometer, effectively improving the robustness of the circuit system and providing stronger radiation resistance.

[0034] After the FPGA receives the parallel data output from the NMOS transistor radiation sensing array circuit, i.e., the received potential change signal from the NMOS transistor radiation sensing array circuit, the FPGA obtains the corresponding total nuclear radiation dose, i.e., the nuclear radiation dose indication signal, through the LUT lookup table unit and outputs it as a digital signal. Simultaneously, the FPGA inputs the total nuclear radiation dose value into the internal BP network forward calculation program, which outputs the corresponding radiation damage electrical signal parameter offset value, i.e., the compensation signal. The output resistance of the radiation damage electrical signal is a digital potentiometer. The offset value to be compensated is controlled by the FPGA's output digital signal to compensate the radiation damage signal, effectively improving the robustness of the circuit system and providing stronger radiation resistance.

[0035] like Figure 2 As shown, taking a five-NMOS transistor array as an example, the NMOS transistor radiation sensing array circuit provided by this invention includes the following structure:

[0036] Resistors R6 and R7 provide the initial bias voltage for the first NMOS transistor. This value is determined by the unaffected threshold voltage of the MOS transistor and needs to be ensured to be below the bias threshold voltage.

[0037] Resistors R9 to R12 are used as pull-up resistors connected to the drain of the MOSFET to ensure signal stability. Generally, a "weak pull-up" is sufficient.

[0038] Five NMOS transistors Q1, Q2, Q3, Q4, and Q5 are used to sense radiation damage;

[0039] All five NMOS transistors have the same function, and their models can be changed according to the specific nuclear radiation environment. The gate of the first NMOS transistor is connected to the start-up bias voltage provided by a resistor divider. The remaining NMOS transistors are all connected to port A of the logic switch, waiting for switching. The drains of all NMOS transistors are connected to the control port of the next-stage logic switch, controlling whether the gate of the next-stage NMOS transistor is connected to the bias voltage. At the same time, the drain signal is output as the final indication signal, which can be used to determine the level of total ionizing radiation dose.

[0040] like Figure 3 As shown, taking a voltage divider with five resistors as an example, the bias voltage circuit and stepped bias switching circuit of the present invention include the following structure:

[0041] The switching logic switches U1, U2, U3, and U4, used to switch the NMOS gate bias voltage, form a stepped bias switching circuit.

[0042] Since the gate of the first NMOS transistor is directly connected to the bias startup voltage, only one less logic switch than the NMOS transistor is needed. Port A is connected to the gate of the NMOS transistor, and the switching of the connection port is controlled by the switch of the MOS transistor. Port B0 is connected to the bias voltage of the marked point, and port B1 is connected to ground.

[0043] Resistors R1 to R5 form a bias voltage circuit, providing a series bias voltage, thus providing four calibration detection voltages V1, V2, V3, and V4. The resistance values ​​are determined by the radiation damage degradation performance of the NMOS transistor.

[0044] like Figure 4 As shown, the FPGA compensation control circuit of the present invention includes the following structure:

[0045] The FPGA compensation control circuit consists of a minimum FPGA circuit system including a power supply and clock module and an external digital potentiometer. It is connected to the drain signal of the NMOS transistor and the control signal port of the digital potentiometer through I / O ports. The digital potentiometer is connected to the radiation damage signal and serves as its output resistor.

[0046] This invention utilizes the characteristic that NMOS transistors have a low total dose effect from nuclear radiation in their off-state, allowing NMOS transistors to withstand a higher total ionizing radiation dose. By keeping the NMOS array in the same off-state, a stepped bias voltage is applied to the gate to indicate the current total ionizing radiation dose level. During this process, only the gates of the NMOS transistors to be damaged by radiation are connected to the calibrated bias voltage; the rest are grounded. The conduction of NMOS transistors at different steps indicates whether the total ionizing radiation dose exceeds a certain value. This utilizes the radiation damage mechanism of NMOS transistors, and the other devices are simple logic devices with strong radiation resistance in nuclear radiation environments, requiring no additional radiation hardening. It can provide both total ionizing radiation dose indication and compensation signals.

[0047] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A step-type total nuclear radiation dose indication and compensation circuit based on NMOS, comprising: Bias voltage circuit, stepped bias switching circuit, NMOS transistor radiation sensing array circuit, and FPGA compensation control circuit. The bias circuit consists of multiple resistors connected in series. Each resistor divides the voltage to provide a stepped bias voltage to the gate of the NMOS transistor in the NMOS transistor radiation sensing array circuit. The bias voltage is switched by a stepped bias switching circuit, and the magnitude of the bias voltage is controlled by adjusting the size of the resistors. The stepped bias switching circuit receives the NMOS transistor sensing signal from the NMOS transistor radiation sensing array circuit and switches the bias voltage to the NMOS transistor radiation sensing array circuit. The NMOS transistor radiation sensing array circuit indicates the total dose level of ionizing radiation on the circuit board by measuring the radiation damage to its own NMOS transistors from the nuclear radiation source and the effect on the threshold voltage of the NMOS transistors. The FPGA compensation control circuit consists of an FPGA basic unit and a digital potentiometer. The FPGA basic unit receives the level change signal output from the NMOS transistor radiation sensing array circuit and outputs the corresponding total nuclear radiation dose according to the different I / O ports of the level change. At the same time, the FPGA basic unit outputs a compensation control signal to the digital potentiometer to compensate for the output resistance value of the radiation damage electrical signal by modifying the digital potentiometer. The NMOS transistor radiation sensing array circuit is composed of multiple NMOS transistors connected in parallel. The gate is connected to the calibration voltage of the bias resistor voltage divider or directly grounded, and the switching logic is controlled by a stepped bias switching circuit. The drain is connected to the control selection port of the stepped bias switching circuit and is stabilized at a high level by a pull-up resistor. The source is directly grounded. The gate of the first NMOS transistor among the multiple NMOS transistors is directly connected to the set start-up voltage. The drain of the NMOS transistor radiation sensing array circuit changes level due to nuclear radiation and is connected in parallel to the IO port of the FPGA compensation control circuit.

2. The circuit as claimed in claim 1, wherein the series resistance value of the bias voltage circuit is determined by the measured voltage, the gate of the first NMOS transistor in the NMOS transistor radiation sensing array circuit is connected to the start-up bias voltage provided by two voltage divider resistors, the voltage divider voltage is lower than the normal NMOS transistor threshold voltage, and the remaining resistors are pull-up resistors connected to the drains of the remaining NMOS transistor array.

3. The circuit as described in claim 1, wherein the stepped bias switching circuit is composed of multiple two-to-one analog switch circuits, the first data port is connected to the gate of the corresponding NMOS transistor in the NMOS transistor radiation sensing array circuit, the second data port B0 is connected to the voltage divider calibration voltage provided by the bias voltage circuit, the third data port is connected to ground, and the control selection port is connected to the drain of the corresponding NMOS transistor in the NMOS transistor radiation sensing array circuit; when the control selection port is low, the first data port is connected to the second data port; when the data selection port is high, the first data port is connected to the third data port.

4. The circuit as described in claim 1, wherein after the FPGA basic unit receives the potential change signal from the NMOS transistor radiation sensing array circuit, the FPGA basic unit calculates the corresponding total nuclear radiation dose through a lookup table unit and outputs it as a digital signal. Simultaneously, the FPGA basic unit inputs the total nuclear radiation dose value into the internal BP network forward calculation unit and outputs the corresponding radiation damage electrical signal parameter offset value. The output resistance of the radiation damage electrical signal is controlled by a digital potentiometer. The offset value that needs to be compensated is output as a digital signal through the FPGA basic unit to control the resistance value of the digital potentiometer to compensate for the radiation damage signal.

5. The circuit of claim 4, wherein the BP network forward calculation unit constructs and trains a BP neural network using the total nuclear radiation dose and the electrical parameter offset value of the radiation damage signal as training data, wherein the electrical parameter offset value is the amplitude difference between the sensor radiation damage signal and the normal signal, and the output value of the BP neural network is the modified value of the digital potentiometer; the weights obtained by training the BP neural network are transcoded and stored in the on-chip RAM of the FPGA basic unit, the total nuclear radiation dose obtained by the lookup table unit is input into the BP neural network, and after obtaining the output of the electrical parameter offset value of the radiation damage signal, the digital potentiometer is controlled to compensate for the amplitude of the radiation damage signal.

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