Method and apparatus for eliminating current mirror mismatch

Abstract

The application discloses a method and device for eliminating current mirror mismatch, wherein the drain of MOS tube Q1 and the drain of MOS tube Q2 in a current mirror to be adjusted are connected with a first operational amplifier circuit and a second operational amplifier circuit respectively, and the two operational amplifier circuits respectively comprise n parallel reference current sources; a switch is arranged between each reference current source and the MOS tube Q1 in the first operational amplifier circuit, and a switch is arranged between each reference current source and the MOS tube Q2 in the second operational amplifier circuit; the method comprises the following steps: controlling the switch corresponding to each reference current source, and simultaneously selecting one reference current source from the two operational amplifier circuits under each time sequence of a bias current control time sequence cycle; alternately connecting the selected two reference current sources to a reference current source, and adjusting the drain voltage of the reference current source to be equal to a reference voltage by using a differential amplifier circuit; and within the bias current control time sequence cycle, all the reference current sources are adjusted, the mismatch of the current mirror to be adjusted is eliminated, and ripple noise is not caused.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and more specifically to a method and apparatus for eliminating current mirror mismatch. Background Technology

[0002] In practical circuits, many current sources are needed. Typically, device matching is used, employing a single "reference current source" as input to provide bias voltages for multiple current sources, or in other words, to directly provide multiple constant currents. The structure composed of these matched devices is called a current mirror. A current mirror is one of the fundamental circuit units in analog integrated circuit design. It not only provides bias current and current copying but also functions as an active load. Its controlled current is equal to the input reference current, meaning the input-output current transfer ratio is 1. Its characteristic is that the output current is a proportional "copy" of the input current, and the "copied" current can and often is a changing signal current.

[0003] like Figure 1 As shown, the basic structure of a current mirror consists of two MOS field-effect transistors (MOSFETs). The gate and drain of one transistor are connected, and the gates of the two transistors are connected together. Its working principle is based on the principle that the gate voltages (relative to the source) of the two transistors are equal, thus equalizing the current and achieving current amplification or inversion. Specifically, when the gate voltage of one transistor increases, its source current also increases, and the gate voltage of the other transistor also increases, resulting in an increase in its drain current, thereby amplifying the current in the entire circuit. Conversely, when the gate voltage of one transistor decreases, its source current decreases, and the gate voltage of the other transistor also decreases, resulting in a decrease in its drain current, thus inverting the current in the entire circuit.

[0004] In integrated circuits, the simplest way to generate a mirrored current is to make the VGS voltage (gate-to-source voltage) of two identical MOSFETs in the saturation region equal. Then, the ID current of both MOSFETs will be the saturation current, and their magnitudes will naturally be equal. However, in actual manufacturing, identical MOSFETs always exhibit slight differences. To adjust these differences, the formula for drain saturation current needs to be applied: Among them, W / L, V gs V ds For design parameters, Cox, V th λ and λ are process-related parameters. During the production process, the concentration of dopants in each MOSFET, the process temperature, etc. will affect the changes in the values ​​of these parameters, which will lead to current mirror mismatch, affect the mirror error, reduce the circuit performance, and prevent it from working properly.

[0005] To address the mismatch issue in current mirrors, existing solutions mainly include the following two types:

[0006] (1) Trimming Current Method

[0007] like Figure 2 As shown, current source A1 and adjustable current source A2 are added between MOSFETs Q1 and Q3, and Q2 and Q4, respectively. If there is a mismatch current ΔI (ΔI = I1-I2) between Q1 and Q2, the bias currents I1 and I2 are adjusted to reduce the mismatch and improve the image accuracy. However, this method requires many small-scale current source inputs to correct the mismatch current, and a calibration is required at the factory, which increases the cost. In addition, since this calibration method is a one-time adjustment under fixed conditions, it cannot effectively eliminate the current mismatch caused by subsequent temperature drift and 1 / f noise. 1 / f noise is a low-frequency noise whose noise power is inversely proportional to its frequency.

[0008] (2) Chopper Current Method

[0009] like Figure 3 As shown, switches S1 and S2 are added between MOSFETs Q1 and Q3, and Q2 and Q4, respectively. The current flow is adjusted by timing control of these switches, switching Q1 and Q2 as input and output transistors, respectively. The a and b terminals of the switches are clock signals. By switching the a and b terminals of the switches to control the current flow, if there is a mismatch current of ΔI between Q1 and Q2, the output current will have a ripple of amplitude ΔI, with the ripple frequency matching the clock signal frequency. From a time-domain perspective, switching the mirror transistors is equivalent to averaging and eliminating the mismatch. Compared to the Trimming Current method, this method can dynamically eliminate mismatch errors in real time, but it requires clock coordination and timing requirements, and it generates ripple.

[0010] In related technologies, patent application CN114696833A addresses the problem of multi-channel mismatch caused by differences in the manufacturing processes of integrators across channels. However, this solution compensates for the mismatch caused by capacitor mismatch in the multi-channel integrator circuit by adjusting the reference voltage of the analog-to-digital conversion module, rather than addressing the mismatch of the bias current source in the current mirror. Patent application CN111769831A proposes a charge pump solution to eliminate current mismatch, utilizing an operational amplifier to reduce current mismatch; however, using an operational amplifier introduces additional noise. Summary of the Invention

[0011] The technical problem to be solved by this invention is how to eliminate current mismatch error in real time without generating ripple noise.

[0012] The present invention solves the above-mentioned technical problems through the following technical means:

[0013] On one hand, this invention proposes a method for eliminating current mirror mismatch. In the current mirror to be adjusted, the drains of MOSFETs Q1 and Q2 are respectively connected to a first operational amplifier circuit and a second operational amplifier circuit. The first and second operational amplifier circuits each include n parallel reference current sources, where n is a constant and greater than 1. A switch is provided between each reference current source in the first operational amplifier circuit and MOSFET Q1, and a switch is provided between each reference current source in the second operational amplifier circuit and MOSFET Q2. The method includes:

[0014] Control the switches corresponding to each of the reference current sources, and simultaneously select one reference current source from the first operational amplifier circuit and the second operational amplifier circuit in each timing sequence of the bias current control timing cycle;

[0015] Two selected reference current sources are alternately connected to the reference current source, and the drain voltage of the reference current source is adjusted to be equal to the reference voltage using a differential amplifier circuit.

[0016] During the bias current control timing period, all reference current sources in the first and second operational amplifier circuits are adjusted to eliminate the mismatch of the current mirror to be adjusted.

[0017] Furthermore, the reference current source includes a reference MOSFET and a combined capacitor. The combined capacitor is connected to the gate of the reference MOSFET. A first switch is connected to the connection point between the gate of each reference MOSFET and the corresponding combined capacitor. A second switch is connected to the drain of the reference MOSFET. The second switch is a single-pole double-throw switch. The second stationary terminal of the second switch is connected to the drain of the MOSFET Q1 or the MOSFET Q2 via a third switch. The first stationary terminal of the second switch is connected to the first stationary terminal of the second switch corresponding to the other reference MOSFETs.

[0018] Furthermore, the reference current source includes a PMOS transistor Q3, and the gate of the PMOS transistor Q3 is connected to a bias voltage signal P. bias The source of PMOS transistor Q3 is connected to the reference current I. ref The drain of PMOS transistor Q3 is switched to each reference current source via the second switch corresponding to each reference current source.

[0019] Furthermore, the differential amplifier circuit includes MOSFETs Q4 and Q5. The sources of MOSFETs Q4 and Q5 are connected to the reference current source. The drains of MOSFETs Q4 and Q5 are connected to resistors R1 and R2, respectively. The first switch corresponding to each reference current source is connected between the drain of MOSFET Q5 and resistor R2. The gate of MOSFET Q4 is connected to the first stationary terminal of the second switch corresponding to each reference current source.

[0020] Further, the step of controlling the switches corresponding to each of the reference current sources, simultaneously selecting one reference current source from the first operational amplifier circuit and the second operational amplifier circuit respectively in each timing sequence of the bias current control timing cycle, includes:

[0021] In each timing cycle of the bias current control timing period, a reference current source selected from the first operational amplifier circuit is determined as the first target current source, and a reference current source selected from the second operational amplifier circuit is determined as the second target current source.

[0022] Disconnect the third switch corresponding to the first target current source and the third switch corresponding to the second target current source.

[0023] Further, the two selected reference current sources are respectively used as the first target current source and the second target current source. The step of alternately connecting the two selected reference current sources to the reference current source and adjusting the drain voltage of the reference current source to be equal to the reference voltage using a differential amplifier circuit includes:

[0024] The first switch corresponding to the first target current source is closed and connected to the differential amplifier circuit via the first switch. The moving terminal of the second switch corresponding to the first target current source is connected to its first stationary terminal, and the first stationary terminal is connected to the reference current source. Correspondingly, the first switch corresponding to the second target current source is opened and the moving terminal of the second switch corresponding to the second target current source is connected to its second stationary terminal.

[0025] The voltage value of the combined capacitor in the first target current source is adjusted using the differential amplifier circuit so that the drain voltage of the first target current source is equal to the reference voltage, and the gate voltage value of the combined capacitor is saved at this time.

[0026] Disconnect the first switch corresponding to the first target current source and connect the moving end of the second switch corresponding to the first target current source to its second stationary end. Then, close the first switch corresponding to the second target current source and connect it to the differential amplifier circuit through the first switch. Connect the moving end of the second switch corresponding to the second target current source to its first stationary end, and connect the first stationary end to the reference current source.

[0027] The voltage value of the combined capacitor in the second target current source is adjusted using the differential amplifier circuit so that the drain voltage of the second target current source is equal to the reference voltage, and the gate voltage value of the combined capacitor is saved at this time.

[0028] Furthermore, adjusting the drain voltage of the reference current source to be equal to the reference voltage using a differential amplifier circuit includes:

[0029] The drain voltage of the reference current source is fed back to the differential amplifier circuit through the inverting input terminal of the differential amplifier circuit.

[0030] The drain voltage of the reference current source is adjusted to the reference voltage by adjusting the output voltage of the differential amplifier circuit according to the drain voltage.

[0031] Secondly, the present invention also proposes a device for eliminating current mirror mismatch. The drains of MOSFETs Q1 and Q2 in the current mirror to be adjusted are respectively connected to a first operational amplifier circuit and a second operational amplifier circuit. The first and second operational amplifier circuits each include n parallel reference current sources, where n is a constant and greater than 1. A switch is provided between each reference current source in the first operational amplifier circuit and MOSFET Q1, and a switch is provided between each reference current source in the second operational amplifier circuit and MOSFET Q2. The switch corresponding to each reference current source is connected to a switching unit, which includes:

[0032] The switch control module is used to control the switches corresponding to each of the reference current sources, and simultaneously select one reference current source from the first operational amplifier circuit and the second operational amplifier circuit in each timing of the bias current control timing cycle.

[0033] The access control module is used to alternately connect the two selected reference current sources to the reference current source, and use a differential amplifier circuit to adjust the drain voltage of the reference current source to be equal to the reference voltage.

[0034] The timing control module is used to adjust all the reference current sources in the first operational amplifier circuit and the second operational amplifier circuit within the bias current control timing period, thereby eliminating the mismatch of the current mirror to be adjusted.

[0035] Furthermore, the reference current source includes a reference MOSFET and a combined capacitor. The combined capacitor is connected to the gate of the reference MOSFET. A first switch is connected to the connection point between the gate of each reference MOSFET and the corresponding combined capacitor. A second switch is connected to the drain of the reference MOSFET. The second switch is a single-pole double-throw switch. The second stationary terminal of the second switch is connected to the drain of the MOSFET Q1 or the MOSFET Q2 via a third switch. The first stationary terminal of the second switch is connected to the first stationary terminal of the second switch corresponding to the other reference MOSFETs.

[0036] Furthermore, the differential amplifier circuit includes MOSFETs Q4 and Q5. The sources of MOSFETs Q4 and Q5 are connected to the reference current source. The drains of MOSFETs Q4 and Q5 are connected to resistors R1 and R2, respectively. A first switch corresponding to each reference current source is connected between the drain of MOSFET Q5 and resistor R2. The gate of MOSFET Q4 is connected to the first stationary terminal of the second switch corresponding to each reference current source. The first stationary terminal of the second switch corresponding to each reference current source is connected to the reference current source.

[0037] The advantages of this invention are:

[0038] (1) In this invention, the drains of MOS transistors Q1 and Q2 in the current mirror are connected to the first operational amplifier circuit and the second operational amplifier circuit respectively. Each operational amplifier circuit is equipped with n parallel reference current sources to divide the overall power source into many small reference current sources and perform adaptive calibration step by step to ensure that the two bias currents are equal. Since the two bias currents I1=I2≠0 are always maintained in the timing of each pair of reference current source adjustment, no ripple noise will be introduced. Moreover, the adjustment method can eliminate the low frequency noise caused by 1 / f by dynamically adjusting the current at a fixed period and can offset the current mismatch caused by temperature drift.

[0039] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0040] Figure 1 This is a basic structural diagram of the current mirror mentioned in the background section of this invention;

[0041] Figure 2 This is a circuit diagram of the Trimming Current method mentioned in the background section of this invention;

[0042] Figure 3 This is a circuit schematic diagram of the Chopper Current method mentioned in the background section of this invention;

[0043] Figure 4 This is a flowchart illustrating a method for eliminating current mirror mismatch according to an embodiment of the present invention;

[0044] Figure 5 This is a circuit diagram corresponding to the current mirror mismatch elimination in an embodiment of the present invention;

[0045] Figure 6 This is a circuit diagram of a reference current source and an adjusted reference current source in an embodiment of the present invention.

[0046] Figure 7 This is a circuit diagram of a current mirror mismatch elimination circuit composed of three sets of reference current sources in an embodiment of the present invention;

[0047] Figure 8 This is a control timing cycle diagram corresponding to the three sets of reference MOS transistors in this embodiment of the invention;

[0048] Figure 9 This is a schematic diagram of the reference MOS switch state at timing 1 in an embodiment of the present invention;

[0049] Figure 10 This is a schematic diagram of the reference MOS switch state during timing 2 in this embodiment of the invention;

[0050] Figure 11 This is a schematic diagram of the reference MOS switch state at timing 3 in an embodiment of the present invention;

[0051] Figure 12 This is a schematic diagram of the reference MOS switch state at timing 4 in this embodiment of the invention;

[0052] Figure 13 This is a schematic diagram of the reference MOS switch state at timing 5 in an embodiment of the present invention;

[0053] Figure 14 This is a schematic diagram of the reference MOS switch state at timing 6 in an embodiment of the present invention;

[0054] Figure 15 This is a schematic diagram of the switching unit in a device for eliminating current mirror mismatch according to an embodiment of the present invention. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0056] like Figure 4 As shown, the first embodiment of the present invention proposes a method for eliminating current mirror mismatch. The drains of MOSFETs Q1 and Q2 in the current mirror to be adjusted are respectively connected to a first operational amplifier circuit and a second operational amplifier circuit. The first and second operational amplifier circuits each include n parallel reference current sources, where n is a constant and greater than 1. A switch is provided between each reference current source in the first operational amplifier circuit and MOSFET Q1, and a switch is provided between each reference current source in the second operational amplifier circuit and MOSFET Q2. The method includes the following steps:

[0057] S10. Control the switches corresponding to each of the reference current sources, and simultaneously select one reference current source from the first operational amplifier circuit and the second operational amplifier circuit in each timing of the bias current control timing cycle.

[0058] S20. The two selected reference current sources are alternately connected to the reference current source, and the drain voltage of the reference current source is adjusted to be equal to the reference voltage using a differential amplifier circuit.

[0059] S30. During the bias current control timing period, adjust all reference current sources in the first operational amplifier circuit and the second operational amplifier circuit to eliminate the mismatch of the current mirror to be adjusted.

[0060] In this embodiment, the drains of MOSFETs Q1 and Q2 in the current mirror are connected to the first operational amplifier circuit and the second operational amplifier circuit, respectively. Each operational amplifier circuit has n parallel reference current sources. The current I1 through MOSFET Q1 is the sum of the currents of the n reference current sources in the first operational amplifier circuit, and the current I2 through MOSFET Q2 is the sum of the currents of the n reference current sources in the second operational amplifier circuit. In this way, the overall power supply is divided into many small reference current sources, and adaptive calibration is performed step by step. As long as the current of each reference current source is equal, their sum will be equal, thus ensuring that I1=I2, achieving the effect of matching the two bias currents. Since the two bias currents are kept equal in the timing of each pair of reference current source adjustments, no ripple noise is introduced. Moreover, this adjustment method can eliminate the low-frequency noise caused by 1 / f by dynamically adjusting the current at a fixed period. In addition, this circuit can offset the current mismatch caused by temperature drift by dynamically correcting ΔI=I1-I2.

[0061] In one embodiment, such as Figure 5 As shown, the reference current source includes a reference MOSFET and a combined capacitor. The combined capacitor is connected to the gate of the reference MOSFET. A first switch is connected to the connection point between the gate of each reference MOSFET and the corresponding combined capacitor. A second switch is connected to the drain of the reference MOSFET. The second switch is a single-pole double-throw switch. The second stationary terminal of the second switch is connected to the drain of the MOSFET Q1 or the MOSFET Q2 via a third switch. The first stationary terminal of the second switch is connected to the first stationary terminal of the second switch corresponding to the other reference MOSFETs.

[0062] Specifically, with Figure 5 The reference MOSFET M in L1 For example, refer to MOSFET M L1 The gate and the corresponding combined capacitor C L1 Connection, refer to MOSFET M L1 The gate and combined capacitor C L1The connection point is connected to the first switch S L1（1） Reference MOSFET M L1 The drain is connected to the second switch S. L1（2） The moving end, the second switch S L1（2） The second stationary end is connected to the third switch S 1（3） It is connected to the drain of MOSFET Q1.

[0063] By controlling the switch corresponding to the reference current source, a specific reference current source can be selected and switched to the reference current source and differential amplifier circuit to adjust the drain voltage of the reference current source.

[0064] In one embodiment, such as Figure 6 As shown, the reference current source includes a PMOS transistor Q3, and the gate of the PMOS transistor Q3 is connected to a bias voltage signal P. bias The source of PMOS transistor Q3 is connected to the reference current I. ref The drain of PMOS transistor Q3 is switched to each reference current source via a second switch corresponding to each reference current source, with a current magnitude I. ref By P bias Voltage is used for control.

[0065] In one embodiment, the differential amplifier circuit includes MOSFETs Q4 and Q5. The sources of MOSFETs Q4 and Q5 are connected to the reference current source. The drains of MOSFETs Q4 and Q5 are connected to resistors R1 and R2, respectively. A first switch corresponding to each reference current source is connected between the drain of MOSFET Q5 and resistor R2. The gate of MOSFET Q4 is connected to the first stationary terminal of a second switch corresponding to each reference current source. The values ​​of resistors R1 and R2 are used to control the gain of the differential amplifier circuit.

[0066] It should be noted that when adjusting the current, one of the reference current sources from the first operational amplifier circuit and the second operational amplifier circuit is selected simultaneously each time to form a set of current sources for current adjustment. For example, disconnecting S... 1(3) And control S according to the timing sequence L1(1) ,S L1(2) ,S R1(1) and S R1(2) The four switches can activate the MOSFET M in the first operational amplifier circuit. L1 and capacitor C L1 The current source and the MOS transistor M in the second operational amplifier circuit R1 and capacitor C R1 The current source alternately switches to Figure 6 The dashed box section connects the switched reference current source to the reference current source and the differential amplifier circuit, and compares it with the reference current source to adjust the bias current.

[0067] It should be noted that the reference current source in the first and second op-amp circuits can be controlled by S. 1(3) At the same time from Figure 4 The circuit is disconnected, and other switches are controlled according to the timing sequence to achieve sequential operation. Figure 6 The bias current is adjusted in the circuit. The reference current source that wasn't switched to adjust the bias current will continue to operate within the circuit. Figure 5 In the circuit operation, since the reference current sources in the first and second operational amplifier circuits are disconnected simultaneously during the adjustment of the bias current, although the absolute values ​​of the currents I1 and I2 will differ by the size of one current source during the calibration process, it is still possible to ensure that I1 = I2.

[0068] In one embodiment, step S10: controlling the switches corresponding to each of the reference current sources, and simultaneously selecting one reference current source from the first operational amplifier circuit and the second operational amplifier circuit in each timing sequence of the bias current control timing cycle, includes the following steps:

[0069] S11. In each timing sequence of the bias current control timing cycle, a reference current source selected from the first operational amplifier circuit is determined as the first target current source, and a reference current source selected from the second operational amplifier circuit is determined as the second target current source.

[0070] S12. Disconnect the third switch corresponding to the first target current source and the third switch corresponding to the second target current source.

[0071] In one embodiment, two selected reference current sources are used as the first target current source and the second target current source, respectively. Step S20: The two selected reference current sources are alternately connected to the reference current source, and the drain voltage of the reference current source is adjusted to be equal to the reference voltage using a differential amplifier circuit, including the following steps:

[0072] S21. The first switch corresponding to the first target current source is turned off and connected to the differential amplifier circuit through the first switch. The moving end of the second switch corresponding to the first target current source is connected to its first stationary end, and the first stationary end is connected to the reference current source. Correspondingly, the first switch corresponding to the second target current source is turned off and the moving end of the second switch corresponding to the second target current source is connected to its second stationary end.

[0073] S22. Adjust the voltage value of the combined capacitor in the first target current source using the differential amplifier circuit so that the drain voltage of the first target current source is equal to the reference voltage, and save the gate voltage value of the combined capacitor at this time.

[0074] S23. Disconnect the first switch corresponding to the first target current source and connect the moving end of the second switch corresponding to the first target current source to its second stationary end. Then, close the first switch corresponding to the second target current source and connect it to the differential amplifier circuit through the first switch. Connect the moving end of the second switch corresponding to the second target current source to its first stationary end, and connect the first stationary end to the reference current source.

[0075] S24. Adjust the voltage value of the combined capacitor in the second target current source using the differential amplifier circuit so that the drain voltage of the second target current source is equal to the reference voltage, and save the gate voltage value of the combined capacitor at this time.

[0076] In one embodiment, in step S20, adjusting the drain voltage of the reference current source to be equal to the reference voltage using a differential amplifier circuit specifically includes:

[0077] The drain voltage of the reference current source is fed back to the differential amplifier circuit through the inverting input terminal of the differential amplifier circuit.

[0078] The drain voltage of the reference current source is adjusted to the reference voltage by adjusting the output voltage of the differential amplifier circuit according to the drain voltage.

[0079] It should be noted that the basic logic of a differential amplifier circuit is to adjust the voltage of Node A to be equal to V. ref During current regulation, the voltage of Node A is fed back to the differential amplifier circuit through the inverting input. The output of the differential amplifier circuit adjusts M based on the voltage value of Node B at the output of Node A. (L / R)n The voltage at the drain is also the voltage at Node A until Node A = V. ref .

[0080] pass Figure 5 S in (L / R)n(1) and S (L / R)n(2) The switch can be selected from the corresponding MOSFET M (L / R)n Capacitor C (L / R)n Switch to Figure 6 The MOSFET M corresponding to the dashed box in the circuit (L / R)n and C (L / R)n The bias current is adjusted at the position. This is to eliminate current mirror misalignment and ensure proper current flow through the MOSFET M. (L / R)n The current and the reference current I ref If they are equal, then the MOS transistors M must be set one by one. n Combined capacitor C n Voltage value V n V is adjusted through the negative feedback of the differential amplifier circuit. nVoltage, such that Node A = V ref .

[0081] The specific bias current adjustment principle is described below, assuming... When the voltage of Node A is greater than V ref At this time, the current flowing through Q4 decreases, and the current flowing through Q5 increases. Simultaneously, the voltage at Node B of the differential amplifier circuit increases, while the voltage at Node A decreases. The negative feedback of the differential amplifier circuit begins to take effect until it adjusts to Node A = V. ref Capacitor C (L / R)n It will save the Node B voltage value under the current conditions as M. (L / R)n The gate voltage value; when the voltage of Node A is less than V ref At this time, the current flowing through Q4 increases, the current flowing through Q5 decreases, and the voltage at Node B of the differential amplifier circuit decreases simultaneously. Meanwhile, the voltage at Node A also increases, and the negative feedback of the differential amplifier circuit begins to take effect until it adjusts to Node A = V. ref Capacitor C (L / R)n It will save the Node B voltage value under the current conditions as M. (L / R)n The gate voltage value; when the voltage of Node A deviates from V ref Adjust until Node A equals V ref The value of is such that the current flowing through Q3 is equal to I. ref Then the current flows through the MOSFET M (L / R)n The current is also equal to I ref At this point, the bias current adjustment for a single current source is complete.

[0082] The following is through, for example Figure 7 Taking the mismatch elimination process of the current mirror circuit shown as an example, Figure 7 The first and second operational amplifier circuits in the current mirror circuit shown are both composed of three reference current sources connected in parallel. Figure 8 The timing diagram for the corresponding bias current adjustment is shown. A complete bias current adjustment cycle T consists of 3 clock cycles 1 / f, according to... Figure 8 The cycle T shown can be decomposed into six timing segments, which also correspond to six steps in the bias current adjustment process. The following uses a complete bias current adjustment cycle as an example to illustrate the bias current adjustment process. The two switching states of the second switch corresponding to each reference current source are D1 or D2. D1 indicates that the moving end of the second switch is connected to the first stationary end, and D2 indicates that the moving end of the second switch is connected to the second stationary end.

[0083] (1) such as Figure 9 As shown, by controlling the on / off state of the switches corresponding to each reference current source, the reference MOSFET M is...L1 and its combined capacitor C L1 Switch to Figure 6 Within the dashed box, the on / off state of the switch is as follows:

[0084] S L1(1) =Closed; S L2(1) =Disconnect; S L3(1) =Disconnect; S R1(1) =Disconnect; S R2(1) =Disconnect; S R3(1) =Disconnect

[0085] S L1(2) =D1; S L2(1) =D2; S L3(1) =D2; S R1(1) =D2; S R2(1) =D2; S R3(1) =D2

[0086] S 1(3) =Disconnect; S 2(3) =Closed; S 3(3) =Closed

[0087] (2) For example Figure 10 As shown, by controlling the on / off state of the switches corresponding to each reference current source, the reference MOSFET M is... R1 and its combined capacitor C R1 Switch to Figure 6 Within the dashed box, the on / off state of the switch is as follows:

[0088] S L1(1) =Disconnect; S L2(1) =Disconnect; S L3(1) =Disconnect; S R1(1) =Closed; S R2(1) =Disconnect; S R3(1) =Disconnect

[0089] S L1(2) =D2; S L2(1) =D2; S L3(1) =D2; S R1(1) =D1; S R2(1) =D2; S R3(1) =D2

[0090] S 1(3) =Disconnect; S 2(3) =Closed; S 3(3) =Closed

[0091] (3) such as Figure 11 As shown, by controlling the on / off state of the switches corresponding to each reference current source, the reference MOSFET M is...L2 and its combined capacitor C L2 Switch to Figure 6 Within the dashed box, the on / off state of the switch is as follows:

[0092] S L1(1) =Disconnect; S L2(1) =Closed; S L3(1) =Disconnect; S R1(1) =Disconnect; S R2(1) =Disconnect; S R3(1) =Disconnect

[0093] S L1(2) =D2; S L2(1) =D1; S L3(1) =D2; S R1(1) =D2; S R2(1) =D2; S R3(1) =D2

[0094] S 1(3) =Closed; S 2(3) =Disconnect; S 3(3) =Closed

[0095] (4) such as Figure 12 As shown, by controlling the on / off state of the switches corresponding to each reference current source, the reference MOSFET M is... R2 and its combined capacitor C R2 Switch to Figure 6 Within the dashed box, the on / off state of the switch is as follows:

[0096] S L1(1) =Disconnect; S L2(1) =Disconnect; S L3(1) =Disconnect; S R1(1) =Disconnect; S R2(1) =Closed; S R3(1) =Disconnect

[0097] S L1(2) =D2; S L2(1) =D2; S L3(1) =D2; S R1(1) =D2; S R2(1) =D1; S R3(1) =D2

[0098] S 1(3) =Closed; S 2(3) =Disconnect; S 3(3) =Closed

[0099] (5) such as Figure 13 As shown, by controlling the on / off state of the switches corresponding to each reference current source, the reference MOSFET M is...L3 and its combined capacitor C L3 Switch to Figure 6 Within the dashed box, the on / off state of the switch is as follows:

[0100] S L1(1) =Disconnect; S L2(1) =Disconnect; S L3(1) =Closed; S R1(1) =Disconnect; S R2(1) =Disconnect; S R3(1) =Disconnect

[0101] S L1(2) =D2; S L2(1) =D2; S L3(1) =D1; S R1(1) =D2; S R2(1) =D2; S R3(1) =D2

[0102] S 1(3) =Closed; S 2(3) =Closed; S 3(3) =Disconnect

[0103] (6) For example Figure 14 As shown, by controlling the on / off state of the switches corresponding to each reference current source, the reference MOSFET M is... R3 and its combined capacitor C R3 Switch to Figure 6 Within the dashed box, the on / off state of the switch is as follows:

[0104] S L1(1) =Disconnect; S L2(1) =Disconnect; S L3(1) =Disconnect; S R1(1) =Disconnect; S R2(1) =Disconnect; S R3(1) =Closed

[0105] S L1(2) =D2; S L2(1) =D2; S L3(1) =D2; S R1(1) =D2; S R2(1) =D2; S R3(1) =D1

[0106] S 1(3) =Closed; S 2(3) =Closed; S 3(3) =Disconnect

[0107] In addition, such as Figure 15As shown, the second embodiment of the present invention also proposes a device for eliminating current mirror mismatch. The drains of MOS transistors Q1 and Q2 in the current mirror to be adjusted are respectively connected to a first operational amplifier circuit and a second operational amplifier circuit. The first operational amplifier circuit and the second operational amplifier circuit each include n parallel reference current sources, where n is a constant and greater than 1. A switch is provided between each reference current source in the first operational amplifier circuit and MOS transistor Q1, and a switch is provided between each reference current source in the second operational amplifier circuit and MOS transistor Q2. The switch corresponding to each reference current source is connected to a switching unit, which includes:

[0108] The switch control module 10 is used to control the switches corresponding to each of the reference current sources, and simultaneously select one reference current source from the first operational amplifier circuit and the second operational amplifier circuit in each timing of the bias current control timing cycle.

[0109] The access control module 20 is used to alternately connect the two selected reference current sources to the reference current source, and use a differential amplifier circuit to adjust the drain voltage of the reference current source to be equal to the reference voltage.

[0110] The timing control module 30 is used to adjust all the reference current sources in the first operational amplifier circuit and the second operational amplifier circuit within the bias current control timing period, thereby eliminating the mismatch of the current mirror to be adjusted.

[0111] In one embodiment, the reference current source includes a reference MOSFET and a combined capacitor. The combined capacitor is connected to the gate of the reference MOSFET. A first switch is connected to the connection point between the gate of each reference MOSFET and the corresponding combined capacitor. A second switch is connected to the drain of the reference MOSFET. The second switch is a single-pole double-throw switch. The second stationary terminal of the second switch is connected to the drain of the MOSFET Q1 or the MOSFET Q2 via a third switch. The first stationary terminal of the second switch is connected to the first stationary terminal of the second switch corresponding to the other reference MOSFETs.

[0112] In one embodiment, the differential amplifier circuit includes MOSFETs Q4 and Q5. The sources of MOSFETs Q4 and Q5 are connected to the reference current source. The drains of MOSFETs Q4 and Q5 are connected to resistors R1 and R2, respectively. A first switch corresponding to each reference current source is connected between the drain of MOSFET Q5 and resistor R2. The gate of MOSFET Q4 is connected to the first stationary terminal of the second switch corresponding to each reference current source. The first stationary terminal of the second switch corresponding to each reference current source is connected to the reference current source.

[0113] In one embodiment, the switch control module 10 is specifically used for:

[0114] In each timing cycle of the bias current control timing period, a reference current source selected from the first operational amplifier circuit is determined as the first target current source, and a reference current source selected from the second operational amplifier circuit is determined as the second target current source.

[0115] Disconnect the third switch corresponding to the first target current source and the third switch corresponding to the second target current source.

[0116] In one embodiment, the access control module 20 is specifically used for:

[0117] The first switch corresponding to the first target current source is closed and connected to the differential amplifier circuit via the first switch. The moving terminal of the second switch corresponding to the first target current source is connected to its first stationary terminal, and the first stationary terminal is connected to the reference current source. Correspondingly, the first switch corresponding to the second target current source is opened and the moving terminal of the second switch corresponding to the second target current source is connected to its second stationary terminal.

[0118] The voltage value of the combined capacitor in the first target current source is adjusted using the differential amplifier circuit so that the drain voltage of the first target current source is equal to the reference voltage, and the gate voltage value of the combined capacitor is saved at this time.

[0119] Disconnect the first switch corresponding to the first target current source and connect the moving end of the second switch corresponding to the first target current source to its second stationary end. Then, close the first switch corresponding to the second target current source and connect it to the differential amplifier circuit through the first switch. Connect the moving end of the second switch corresponding to the second target current source to its first stationary end, and connect the first stationary end to the reference current source.

[0120] The voltage value of the combined capacitor in the second target current source is adjusted using the differential amplifier circuit so that the drain voltage of the second target current source is equal to the reference voltage, and the gate voltage value of the combined capacitor is saved at this time.

[0121] It should be noted that other embodiments or implementation methods of the device for eliminating current mirror mismatch described in this invention can refer to the above-described method embodiments, and will not be repeated here.

[0122] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0123] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0124] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A method of eliminating current mirror mismatch, comprising: The drains of MOS tubes Q1 and Q2 in the current mirror to be adjusted are connected to a first operational amplifier circuit and a second operational amplifier circuit respectively, the first operational amplifier circuit and the second operational amplifier circuit each include n reference current sources connected in parallel, n is a constant and greater than 1; a switch is arranged between each reference current source and the MOS tube Q1 in the first operational amplifier circuit, and a switch is arranged between each reference current source and the MOS tube Q2 in the second operational amplifier circuit, and the method comprises: controlling the switches corresponding to each reference current source to simultaneously select one reference current source from the first operational amplifier circuit and the second operational amplifier circuit at each timing of a bias current control timing period; alternately connecting the selected two reference current sources to a reference current source, and adjusting the drain voltage of the reference current source to be equal to a reference voltage by using a differential amplification circuit; in the bias current control timing period, adjusting all reference current sources in the first operational amplifier circuit and the second operational amplifier circuit to eliminate the mismatch of the current mirror to be adjusted; the reference current source includes a reference MOS tube and a combination capacitor, the combination capacitor is connected to the gate of the reference MOS tube, the connection point of the gate of each reference MOS tube and the corresponding combination capacitor is connected to a first switch, the drain of the reference MOS tube is connected to a second switch, the second switch is a single-pole double-throw switch, the second stationary end of the second switch is connected to the drain of the MOS tube Q1 or the MOS tube Q2 through a third switch, and the first stationary end of the second switch is connected to the first stationary end of the second switch corresponding to the other reference MOS tube; The reference current source comprises a PMOS tube Q3, a gate of the PMOS tube Q3 is connected with a bias voltage signal P bias , a source of the PMOS tube Q3 is connected with a reference current I ref , and a drain of the PMOS tube Q3 is connected with each reference current source through a second switch corresponding to each reference current source. the differential amplification circuit includes MOS tubes Q4 and Q5, the sources of the MOS tubes Q4 and Q5 are connected and connected to the reference current source, the drains of the MOS tubes Q4 and Q5 are respectively connected to a resistor R1 and a resistor R2, the first switch corresponding to each reference current source is connected between the drain of the MOS tube Q5 and the resistor R2, and the gate of the MOS tube Q4 is connected to the first stationary end of the second switch corresponding to each reference current source.

2. The method of canceling current mirror mismatch of claim 1, wherein, the controlling the switches corresponding to each reference current source to simultaneously select one reference current source from the first operational amplifier circuit and the second operational amplifier circuit at each timing of a bias current control timing period comprises: at each timing of the bias current control timing period, determining that the selected reference current source from the first operational amplifier circuit is a first target current source, and determining that the selected reference current source from the second operational amplifier circuit is a second target current source; disconnecting the third switch corresponding to the first target current source and the third switch corresponding to the second target current source.

3. The method of canceling current mirror mismatch of claim 1, wherein, the alternately connecting the selected two reference current sources to a reference current source, and adjusting the drain voltage of the reference current source to be equal to a reference voltage by using a differential amplification circuit, when the selected two reference current sources are used as a first target current source and a second target current source, comprises: The first switch corresponding to the first target current source is closed and the first switch is connected to the differential amplification circuit, the movable terminal of the second switch corresponding to the first target current source is connected to the first fixed terminal, and the first fixed terminal is connected to the reference current source; correspondingly, the first switch corresponding to the second target current source is opened, and the movable terminal of the second switch corresponding to the second target current source is connected to the second fixed terminal; The voltage value of the combined capacitor in the first target current source is adjusted by using the differential amplification circuit, so that the drain voltage of the first target current source is equal to the reference voltage, and the gate voltage value of the combined capacitor at this time is saved; The first switch corresponding to the first target current source is opened, the movable terminal of the second switch corresponding to the first target current source is connected to the second fixed terminal, and then the first switch corresponding to the second target current source is closed and connected to the differential amplification circuit, the movable terminal of the second switch corresponding to the second target current source is connected to the first fixed terminal, and the first fixed terminal is connected to the reference current source; The voltage value of the combined capacitor in the second target current source is adjusted by using the differential amplification circuit, so that the drain voltage of the second target current source is equal to the reference voltage, and the gate voltage value of the combined capacitor at this time is saved.

4. The method of canceling current mirror mismatch of claim 1, wherein, The drain voltage of the reference current source is equal to the reference voltage by using the differential amplification circuit, which comprises: The drain voltage of the reference current source is fed back to the differential amplification circuit through the inverting input terminal of the differential amplification circuit; The drain voltage of the reference current source is adjusted to the reference voltage by adjusting the output voltage value of the differential amplification circuit according to the drain voltage.

5. An apparatus for eliminating current mirror mismatch, comprising: The drains of MOS transistor Q1 and MOS transistor Q2 in the current mirror to be adjusted are respectively connected to a first operational amplifier circuit and a second operational amplifier circuit, the first operational amplifier circuit and the second operational amplifier circuit respectively comprise n parallel reference current sources, n is a constant and greater than 1; switches are arranged between each reference current source and MOS transistor Q1 in the first operational amplifier circuit, switches are arranged between each reference current source and MOS transistor Q2 in the second operational amplifier circuit, and the switches corresponding to each reference current source are connected to a switching unit, the switching unit comprises: A switch control module is used for controlling the switches corresponding to each reference current source, and simultaneously selecting one reference current source from the first operational amplifier circuit and the second operational amplifier circuit at each timing of a bias current control timing period; An access control module is used for alternately connecting the selected two reference current sources to a reference current source, and adjusting the drain voltage of the reference current source to be equal to the reference voltage by using a differential amplification circuit; A timing control module is used for adjusting all reference current sources in the first operational amplifier circuit and the second operational amplifier circuit in the bias current control timing period, and eliminating the mismatch amount of the current mirror to be adjusted. The reference current source comprises reference MOS tubes and combined capacitors connected to the gates of the reference MOS tubes, the connection points of each of the reference MOS tubes and the corresponding combined capacitors are connected to a first switch, the drains of the reference MOS tubes are connected to a second switch, the second switch is a single-pole double-throw switch, the second stationary end of the second switch is connected to the drain of the MOS tube Q1 or the MOS tube Q2 through a third switch, and the first stationary end of the second switch is connected to the first stationary end of the second switch corresponding to the other reference MOS tube; The reference current source comprises a PMOS tube Q3, a gate of the PMOS tube Q3 is connected with a bias voltage signal P bias , a source of the PMOS tube Q3 is connected with a reference current I ref , and a drain of the PMOS tube Q3 is connected with each reference current source through a second switch corresponding to each reference current source. The differential amplification circuit comprises MOS tubes Q4 and Q5, the sources of the MOS tubes Q4 and Q5 are connected and then connected to the reference current source, the drains of the MOS tubes Q4 and Q5 are respectively connected to a resistor R1 and a resistor R2, the first switch corresponding to each of the reference current sources is connected between the drain of the MOS tube Q5 and the resistor R2, and the gate of the MOS tube Q4 is connected to the first stationary end of the second switch corresponding to each of the reference current sources; and the first stationary end of the second switch corresponding to each of the reference current sources is connected to the reference current source.

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