Error detection method, detection system, terminal and medium for synchronous serial communication
By receiving and processing synchronous serial data bit by bit, and constructing frame header data to identify error types, the problem of not being able to identify the cause of errors in synchronous serial communication is solved, thus improving the reliability of data transmission.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TIANJIN JINHANG COMP TECH RES INST
- Filing Date
- 2023-06-27
- Publication Date
- 2026-06-02
AI Technical Summary
In existing synchronous serial communication, the receiving end cannot identify the cause of the error, making it impossible to take corresponding measures and affecting the reliability of data transmission.
The system receives synchronous serial data bit by bit, stores it in a shift register to form the first data, extracts valid data and stores it in a buffer module, constructs frame header data, determines the data error type and sends it to the receiving end, and the receiving end takes corresponding measures according to the error type identifier.
This technology enables the identification of error frames and the acquisition of error types, thereby improving the reliability of data transmission at the receiving end.
Smart Images
Figure CN116756076B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer bus communication technology, specifically to an error detection method, detection system, terminal, and medium for synchronous serial communication. Background Technology
[0002] Serial communication buses are the most commonly used interfaces in computer application systems. Serial communication generally refers to the transmission of data between peripherals and a computer via data lines. Serial communication includes synchronous serial communication and asynchronous serial communication. In synchronous serial communication, both the peripheral and the computer agree on a fixed communication rate, ensuring that the clock signal frequency and phase at the transmitting and receiving ends remain consistent. Data can be acquired at either the rising or falling edge of the clock. Asynchronous serial communication, on the other hand, transmits characters one by one. A start bit is used to synchronize the receiver and transmitter after each character is transmitted. Asynchronous serial communication typically begins with a start bit and ends with a stop bit.
[0003] High Level Data Link Control (HDLC) is a bit-oriented synchronous data link layer protocol developed by an international standards organization. For this synchronous serial port HDLC, data integrity is typically determined solely by CRC checksum. When the receiver receives erroneous data, it simply discards the frame without being able to determine the cause of the error, thus preventing appropriate corrective action. Summary of the Invention
[0004] In view of the above-mentioned defects or deficiencies in the prior art, this application aims to provide an error detection method, detection system, terminal and medium for synchronous serial communication.
[0005] Firstly, this application provides an error detection method for synchronous serial communication, comprising the following steps:
[0006] The synchronous serial data sent by the transmitter is received bit by bit and stored in the shift register to obtain the first data.
[0007] Extract the first data to obtain at least the valid data;
[0008] The valid data is stored in the cache module;
[0009] Construct the original frame header content, which includes at least a plurality of error type identifiers, each error type identifier corresponding to a type of data error, and each error type identifier having a first state and a second state. The first state represents that the first data does not have a data error corresponding to the error type identifier, and the second state represents that the first data has a data error corresponding to the error type identifier.
[0010] When it is determined that the first data has at least one type of data error, the error type identifier corresponding to the data error is switched from the first state to the second state to obtain the first frame header data;
[0011] The first frame header data is sent to the receiving end, and the valid data in the cache module is discarded.
[0012] According to the technical solution provided in the embodiments of this application, the data error includes frame data error. The method for determining that the first data has the frame data error is: if the first data is high for seven consecutive clock cycles, then the first data has the frame data error.
[0013] According to the technical solution provided in the embodiments of this application, the data error also includes a CRC error. The method for determining that the first data has the CRC error is: if the first data cannot correctly complete the CRC check, then the first data has the CRC error.
[0014] According to the technical solution provided in the embodiments of this application, the data parsing module has a data receiving state and a data receiving exit state; the data error also includes a disconnection error, and the method for determining that the first data has the disconnection error includes the following steps:
[0015] Set the preset reception duration;
[0016] When the data parsing module is in the data receiving state, the initial time is obtained;
[0017] If, starting from the initial moment, the data parsing module remains in the data receiving state throughout the preset receiving time, then the first data has the disconnection error.
[0018] According to the technical solution provided in the embodiments of this application, after extracting the first data, at least an address field and a control field are obtained; the first frame header data also includes the address field and the control field.
[0019] According to the technical solution provided in the embodiments of this application, the first frame header data also includes a number of valid bytes preceding the address field, and the number of valid bytes is obtained by counting the number of bytes of the valid data.
[0020] According to the technical solution provided in the embodiments of this application, the first frame header data also includes a channel number located between the control domain and the error type identification.
[0021] Secondly, this application provides a detection system with the above-described synchronous serial communication error detection method, comprising:
[0022] The data parsing module has at least one output channel. The data parsing module is configured to receive synchronous serial data corresponding to each output channel sent by the transmitting end in bits, obtain first data, and parse the first data to obtain valid data.
[0023] A fault monitoring module is provided in the data parsing module. The fault monitoring module is configured to determine whether the first data has data errors and generate the first frame header data.
[0024] At least one buffer module corresponding to each of the output channels, the buffer module being connected to the data parsing module, is used to store the valid data and send the valid data or the first frame header data to the receiving end corresponding to each of the output channels.
[0025] Thirdly, this application provides a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the error detection method for synchronous serial communication as described above.
[0026] Fourthly, this application provides a computer-readable storage medium having a computer program that, when executed by a processor, implements the steps of the error detection method for synchronous serial communication described above.
[0027] In summary, this application proposes an error detection method for synchronous serial communication. The method involves storing received synchronous serial data in bits within a shift register to form first data; extracting valid data from the first data and storing it in a buffer module; and, when the first data is found to have errors, switching the state of the error type identifier corresponding to various data errors in the original frame header content from a first state to a second state to obtain the first frame header data, which is then sent to the receiving end. Upon receiving a data frame, the receiving end can determine the error type of the erroneous data frame by identifying which error type identifier is in the second state, allowing the receiving end to take appropriate measures based on this error type. Compared to existing technologies, the method of this application enables the receiving end to obtain the error type while identifying erroneous data frames, thus improving the reliability of the receiving end. Attached Figure Description
[0028] Figure 1 A schematic diagram of a detection system structure for an error detection method with synchronous serial communication provided in an embodiment of this application;
[0029] Figure 2 A flowchart illustrating an error detection method for synchronous serial communication provided in this application embodiment;
[0030] Figure 3 This is a schematic diagram of the structure of the first frame header data provided in an embodiment of this application;
[0031] Figure 4 This is a schematic diagram of the data error handling process provided in an embodiment of this application;
[0032] Figure 5 This is a schematic diagram of the computer system structure of the terminal device or server in an embodiment of this application.
[0033] 1. Data parsing module; 2. Transmitter; 3. Buffer module; 4. Receiver; 700. Computer system; 701. CPU; 702. ROM; 703. RAM; 704. Bus; 705. I / O interface; 706. Input section; 707. Output section; 708. Storage section; 709. Communication section; 710. Driver; 711. Removable media. Detailed Implementation
[0034] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.
[0035] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.
[0036] Example 1
[0037] As mentioned in the background section, this application proposes a detection system with an error detection method for synchronous serial communication, comprising:
[0038] The data parsing module 1 has at least one output channel. The data parsing module 1 is configured to receive the synchronous serial data corresponding to each output channel sent by the transmitting end 2 in bits, obtain first data, and parse the first data to obtain valid data.
[0039] A fault monitoring module is provided in the data parsing module 1. The fault monitoring module is configured to determine whether the first data has data errors and generate the first frame header data.
[0040] At least one buffer module 3 corresponding to each of the output channels, the buffer module 3 being connected to the data parsing module 1, for storing the valid data, and sending the valid data or the first frame header data to the receiving end 4 corresponding to the output channel.
[0041] Among them, such as Figure 1 As shown, the data parsing module 1 is designed based on the Field-Programmable Gate Array (FPGA) platform. The input end of the data parsing module 1 is connected to the transmitting end 2. The two are connected through the transmitting clock line, transmitting data line, receiving clock line, and receiving data line of the serial bus, and the protocol is HDLC protocol.
[0042] The cache module 3 corresponding to each of the output channels is a first-in-first-out (FIFO) data storage device, and the FIFO is connected to the output terminal of the data parsing module 1 through a FIFO data protocol line.
[0043] The format of the HDLC protocol is shown in Table-1:
[0044] Table 1
[0045]
[0046] The HDLC protocol uses a fixed flag field "01111110" as the frame boundary. When receiving an HDLC data frame, the reception begins upon detecting an "F" flag; if another "F" flag is detected during reception, the frame is considered to have ended. To distinguish the transmitted data segment from the flag field, every five "1"s are padded with a "0". For the receiving party, the zeros are removed to restore the original data.
[0047] The data parsing module 1 receives the synchronous serial data bit by bit, samples the synchronous serial data according to the rising edge of the clock line, and places each bit into the least significant bit of the shift register to form the first data. The entire data packet header is determined by judging whether the value of the shift register is the F flag. After judging the packet header, the address field, control field and data of the data segment can be extracted in sequence, that is, the valid data.
[0048] The buffer module 3 includes a receive buffer FIFO, which has a valid data byte counter and a byte count register. When the valid data is stored in the receive buffer FIFO, the receive buffer FIFO is pulled high once to enable write when the shift register is full for each byte, and the valid data corresponding to that byte is written into the receive buffer FIFO. The valid data byte counter is incremented by 1 each time the write enable of the receive buffer FIFO is pulled high. When the frame data ends, the number of bytes of valid data is obtained by counting the valid data byte counter and transmitted to the byte count register.
[0049] The data parsing module 1 further includes a mechanism for monitoring whether the first data contains data errors. When a data error is detected, a first frame header is generated, which includes the type of data error. This first frame header is then sent to the buffer module 3. If the first data does not contain the data error, the buffer module 3 sends valid data to the receiving end 4. If a data error is detected, the buffer module 3 sends the first frame header to the receiving end 4 and deletes the valid data from the buffer module 3. This application can identify erroneous data frames and obtain the error type within the data error, allowing the receiving end 4 to take appropriate measures based on the error type, thus improving the reliability of the receiving end 4.
[0050] Example 2
[0051] Based on Embodiment 1, this application provides an error detection method for synchronous serial communication, such as... Figure 2 As shown, it includes the following steps:
[0052] S1. Receive the synchronous serial data sent by the transmitter 2 bit by bit and store it in the shift register to obtain the first data; receive the synchronous serial data sent by the transmitter 2 through the data parsing module 1. The synchronous serial data follows the HDLC protocol.
[0053] S2. Extract the first data to obtain at least valid data; the first data includes a flag field, an address field, a control field, a data segment, and a flag field, and extract the data segment as the valid data.
[0054] S3. The valid data is stored in the cache module 3; the cache module 3 is a FIFO, and the valid data is stored in the receiving cache FIFO of the FIFO.
[0055] S4. Construct the original frame header content, which includes at least a plurality of error type identifiers. Each error type identifier corresponds to a type of data error. Each error type identifier has a first state and a second state. The first state indicates that the first data does not have a data error corresponding to the error type identifier. The second state indicates that the first data has a data error corresponding to the error type identifier. When there is no data error, the error type identifier corresponding to this type of data error is in the first state, and the value of this bit is "0". When there is a data error, the error type identifier corresponding to this type of data error is in the second state, and the error type identifier is set high, with a value of "1".
[0056] S5. When it is determined that the first data has at least one type of data error, the error type identifier corresponding to the data error is switched from the first state to the second state to obtain the first frame header data; the fault monitoring module determines whether the data error exists. If the data error exists, the first frame header data is formed and transmitted to the receiving buffer FIFO.
[0057] S6. The first frame header data is sent to the receiving end 4, and the valid data in the buffer module 3 is discarded. Before each data transmission from the receiving buffer FIFO to the receiving end 4, the first frame header data is sent first. When the state of any error type identifier in the first frame header data is the second state, the valid data received by the receiving buffer FIFO is discarded. When the state of all error type identifiers in the first frame header data is the first state, the receiving end 4 receives the valid data.
[0058] After receiving a data frame, the receiving end 4 of this application can determine the error type of the erroneous data frame by judging which error type identifier is in the second state, so that the receiving end 4 can take corresponding measures according to the error type. Compared with the prior art, the method of this application enables the receiving end 4 to obtain the error type at the same time as identifying the erroneous data frame, thereby improving the reliability of the receiving end 4.
[0059] In a preferred embodiment, the data error includes a frame data error. The method for determining that the first data has the whole data error is as follows: if the first data is high for seven consecutive clock cycles, then the first data has the frame data error.
[0060] Please refer to Figure 3As shown, the error type identifier includes a frame error identifier, and the corresponding data error is the frame data error. When the frame data error identifier is in the second state, it indicates that the first data contains the frame data error. The frame data error is when there are more than 7 consecutive "1" bits on the data line of the frame data. According to the format of the HDLC protocol, the frame header and frame tail are "01111110". For the data transmission of the data segment, every 5 consecutive "1" bits are padded with "0". Therefore, there is no situation where there are 7 consecutive "1" bits on the data line of the frame data. When this situation occurs, it means that the data has the frame data error.
[0061] When the fault monitoring module detects that the data in the shift register is 0xfe or 0xff, the state machine exits the receiving state and pulls the frame error flag high to notify the receiving end 4. It also resets the byte count register in the buffer module 3 and invalidates the received valid data in order to wait for new data to be received.
[0062] In a preferred embodiment, the data error further includes a CRC error. The method for determining that the first data has the CRC error is as follows: if the first data cannot correctly complete the CRC check, then the first data has the CRC error.
[0063] Please refer to Figure 3 As shown, the error type identifier also includes a CRC check error identifier, and the corresponding error is the CRC error. When the CRC check error identifier is in the second state, it indicates that a CRC error exists. The CRC error occurs when a frame of data is transmitted, and a CRC check is performed on each byte transmitted until the CRC check value of the last two bytes is calculated. If the result does not match the CRC check result, the CRC check cannot be completed correctly. The CRC check is existing technology and will not be described in detail here. When the CRC error occurs, that is, when the CRC check result data is not equal to the preset value, the state machine of the shift register exits the receiving state, pulls the CRC check error identifier high and notifies the receiving end 4, resets all registers, and invalidates the valid data of the received frame, waiting to receive new data.
[0064] In a preferred embodiment, the data parsing module 1 has a data receiving state and a data receiving exit state; the data error further includes a disconnection error, and the method for determining that the first data has the disconnection error includes the following steps:
[0065] Set a preset reception duration; optionally, the preset reception duration is 2ms;
[0066] When the data parsing module 1 is in the data receiving state, the initial time is obtained;
[0067] If, starting from the initial moment, the data parsing module 1 remains in the data receiving state throughout the preset receiving time, then the first data has the disconnection error.
[0068] Please refer to Figure 3 As shown, the error type identifier also includes a disconnection identifier. The data error corresponding to the disconnection identifier is the disconnection error. When the disconnection identifier is in the second state, it indicates that the disconnection error has occurred. The disconnection error is caused by a wire break or other interruption during data transmission. The data parsing module 1 also has a timer. The initial moment is when the state machine of the shift register starts receiving data. The timer starts counting. When the countdown reaches 2ms, if the state machine has not exited the data receiving state, it is considered that the state machine is stuck or an abnormal disconnection has occurred, i.e., the disconnection error has occurred. The registers are reset, the received valid data is invalidated, and the error type identifier is pulled high to notify the receiving end 4, and wait to receive new data. When the error type identifier includes the frame error identifier, the CRC check error identifier, and the disconnection identifier, the processing flow is as follows: Figure 4 As shown.
[0069] In a preferred embodiment, after extracting the first data, at least an address field and a control field are obtained; the first frame header data also includes the address field and the control field; it also includes a number of valid bytes preceding the address, the number of valid bytes being obtained by counting the number of bytes in the valid data. The first frame header data also includes a channel number located between the control field and the error type identification.
[0070] Please refer to Figure 3As shown, the first frame header data sequentially includes: valid data number (valid_data_num), address field (addr), control field (control), channel number field (channel), frame error flag (frame_error), CRC check error flag (crc_error), and disconnection flag (disconnect_error). Except for the valid data number, which occupies 1-2 bytes, the others are all 1 byte each. Data transmission between the receiving end 4 and the data parsing module 1 follows the HDLC protocol. The address field and control field are located after the flag field of the HDLC protocol data frame. The valid data number is obtained through the byte count register of the FIFO corresponding to each output channel. The data parsing module 1 includes at least one output channel, and each output channel has a channel number. The channel number corresponding to the output channel from which valid data is transmitted to the FIFO is written into the channel number field.
[0071] Example 3
[0072] A terminal device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the above-described error detection method for synchronous serial communication.
[0073] The following is for reference. Figure 5 It shows a schematic diagram of the structure of a computer system 700 suitable for implementing terminal devices or servers in the embodiments of this application.
[0074] like Figure 5 As shown, the computer system 700 includes a central processing unit (CPU) 701, which can perform various appropriate actions and processes based on programs stored in read-only memory (ROM) 702 or programs loaded from storage section 708 into random access memory (RAM) 703. The RAM 703 also stores various programs and data required for the operation of the system 700. The CPU 701, ROM 702, and RAM 703 are interconnected via a bus 704. An input / output (I / O) interface 705 is also connected to the bus 704.
[0075] The following components are connected to the I / O interface 705: an input section 706 including a keyboard, mouse, etc.; an output section 707 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 708 including a hard disk, etc.; and a communication section 709 including a network interface card such as a LAN card, modem, etc. The communication section 709 performs communication processing via a network such as the Internet. A drive 710 is also connected to the I / O interface 705 as needed. A removable medium 711, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 710 as needed so that computer programs read from it can be installed into the storage section 708 as needed.
[0076] Specifically, according to embodiments of this application, the above references Figure 2 The described process can be implemented as a computer software program. For example, embodiments of this application include a computer program product comprising a computer program tangibly embodied on a machine-readable medium, the computer program containing instructions for performing... Figure 2 The program code for the method. In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 709, and / or installed from the removable medium 711.
[0077] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.
[0078] Example 4
[0079] A fourth embodiment of this application also provides a computer-readable storage medium, which may be a computer-readable storage medium included in the apparatus described in the above embodiments; or it may be a standalone computer-readable storage medium not assembled into the device. The computer-readable storage medium stores one or more programs, which are used by one or more processors to execute the steps of the error detection method for synchronous serial communication described in Embodiment 2.
[0080] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.
Claims
1. A method for error detection in synchronous serial communication, characterized in that, Includes the following steps: The synchronous serial data sent by the transmitter is received bit by bit and stored in the shift register to obtain the first data. Extract the first data to obtain at least the valid data; The valid data is stored in the cache module (3); Construct the original frame header content, which includes at least a plurality of error type identifiers, each error type identifier corresponding to a type of data error, and each error type identifier having a first state and a second state. The first state represents that the first data does not have a data error corresponding to the error type identifier, and the second state represents that the first data has a data error corresponding to the error type identifier. When it is determined that the first data has at least one type of data error, the error type identifier corresponding to the data error is switched from the first state to the second state to obtain the first frame header data; The first frame header data is sent to the receiving end (4), and the valid data in the cache module (3) is discarded.
2. The error detection method for synchronous serial communication according to claim 1, characterized in that, The data error includes frame data error. The method for determining that the first data has the frame data error is: if the first data is high for seven consecutive clock cycles, then the first data has the frame data error.
3. The error detection method for synchronous serial communication according to claim 2, characterized in that, The data error also includes CRC error. The method for determining that the first data has the CRC error is: if the first data cannot complete the CRC check correctly, then the first data has the CRC error.
4. The error detection method for synchronous serial communication according to claim 3, characterized in that, The data parsing module (1) has a data receiving state and a data receiving exit state; the data error also includes a disconnection error, and the method for determining that the first data has the disconnection error includes the following steps: Set the preset reception duration; When the data parsing module (1) is in the data receiving state, the initial time is obtained; If the data parsing module (1) remains in the data receiving state throughout the preset receiving time starting from the initial time, then the first data has the disconnection error.
5. The error detection method for synchronous serial communication according to claim 1, characterized in that, After extracting the first data, at least the address field and the control field are also obtained; the first frame header data also includes the address field and the control field.
6. The error detection method for synchronous serial communication according to claim 5, characterized in that, The first frame header data also includes the number of valid bytes preceding the address field, which is obtained by counting the number of bytes in the valid data.
7. The error detection method for synchronous serial communication according to claim 6, characterized in that, The first frame header data also includes a channel number located between the control field and the error type identification.
8. A detection system having an error detection method for synchronous serial communication as described in any one of claims 1-7, characterized in that, include: The data parsing module (1) has at least one output channel. The data parsing module (1) is configured to receive the synchronous serial data corresponding to each output channel sent by the transmitting end in bits, obtain first data, and parse the first data to obtain valid data. The fault monitoring module is located in the data parsing module (1). The fault monitoring module is configured to determine whether the first data has data errors and generate the first frame header data. At least one buffer module (3) corresponding to each of the output channels, the buffer module (3) being connected to the data parsing module (1), for storing the valid data and sending the valid data or the first frame header data to the receiving end (4) corresponding to each of the output channels.
9. A terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the error detection method for synchronous serial communication as described in any one of claims 1 to 7.
10. A computer-readable storage medium having a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the error detection method for synchronous serial communication as described in any one of claims 1 to 7.