A wafer edge detection method and device, electronic equipment and storage medium

Abstract

The embodiment of the application belongs to the technical field of semiconductors, and provides a wafer edge detection method and device, an electronic device and a storage medium. The edge detection method obtains a wafer image by optical imaging of the wafer, extracts edge features according to the wafer image to obtain a plurality of wafer edge data, acquires a design drawing file of the wafer, acquires a plurality of edge design data of the wafer according to the design drawing file, maps all the edge design data to the wafer image to obtain a plurality of wafer edge reference data, and performs edge detection on the wafer according to all the wafer edge reference data and all the wafer edge data to obtain a detection result. The method provided in the application maps the edge of the wafer on the design drawing file to the wafer image, compares the mapped edge with the actual edge of the wafer, provides an accurate detection reference, reduces the difficulty of edge detection, and improves the detection accuracy of the wafer edge.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and particularly relates to a wafer edge detection method and device, an electronic device and a storage medium. BACKGROUND

[0002] At present, with the development of the wafer industry, in order to improve production efficiency, wafer production gradually introduces automatic equipment and improves the degree of automation. As an important part of wafer production, quality inspection affects the quality of wafers and also affects the subsequent production of semiconductor circuits.

[0003] Wafer edge detection is one part of quality inspection. The currently used method is to compare the wafer image with a standard template image. However, for some wafers, the standard template is difficult to extract, and such wafers need to be compared with a design drawing.

[0004] Using a design drawing for comparison requires aligning the wafer image. However, due to the difference between the actual wafer edge and the theoretical edge on the design drawing during production, it is difficult to accurately align the two edges, which may cause system errors and affect the accuracy of edge detection. SUMMARY

[0005] The main purpose of the embodiments of the present application is to provide a wafer edge detection method, device, electronic device and storage medium, aiming at the accuracy of wafer edge detection.

[0006] To achieve the above purpose, the first aspect of the embodiments of the present application provides a wafer edge detection method, which comprises the following steps:

[0007] Optically imaging the wafer to obtain a wafer image;

[0008] Extracting edge features from the wafer image to obtain a plurality of wafer edge data;

[0009] Obtaining a design drawing file of the wafer, and obtaining a plurality of edge design data of the wafer according to the design drawing file;

[0010] Mapping all the edge design data to the wafer image to obtain a plurality of wafer edge reference data;

[0011] Performing edge detection on the wafer according to all the wafer edge reference data and all the wafer edge data to obtain a detection result.

[0012] In some possible embodiments of the present application, the edge feature extraction from the wafer image to obtain a plurality of wafer edge data comprises:

[0013] edge recognition is performed on the wafer image to obtain a plurality of edge recognition data;

[0014] image element enhancement is performed according to all the edge recognition data to obtain a plurality of edge enhancement data;

[0015] data updating is performed on all the edge recognition data according to all the edge enhancement data to obtain all the wafer edge data.

[0016] In some possible embodiments of the present application, the mapping of the edge design data to the wafer image to obtain a plurality of wafer edge reference data comprises:

[0017] function fitting is performed on all the wafer edge data and all the edge design data to obtain a mapping function;

[0018] all the edge design data is mapped to the wafer image according to the mapping function to obtain a plurality of the wafer edge reference data.

[0019] In some possible embodiments of the present application, the function fitting on all the wafer edge data and all the edge design data to obtain a mapping function comprises:

[0020] data pair construction is performed on all the wafer edge data and all the edge design data to obtain a plurality of control point pairs;

[0021] quality inspection is performed on the control point pair according to a preset quality inspection rule to obtain a quality inspection result;

[0022] when the quality inspection result indicates that the control point pair is abnormal, the control point pair is corrected according to a preset correction rule, and a control point pair set is constructed according to all the current control point pairs to obtain a target control point pair set;

[0023] the mapping function is obtained by function fitting on the control point pair set.

[0024] In some possible embodiments of the present application, before the function fitting on the control point pair set to obtain the mapping function, the method further comprises:

[0025] quantity detection is performed on all the control point pairs in the control point pair set to obtain a quantity detection result;

[0026] when the quantity detection result indicates that the number of control point pairs in the control point pair set is insufficient, an updated control point pair is obtained according to a preset supplement rule, all the wafer edge data and all the edge design data, the updated control point pair is added to the control point pair set to obtain a target control point pair set;

[0027] The mapping function is obtained by function fitting according to the set of control point pairs.

[0028] The mapping function is obtained by function fitting according to the set of target control point pairs.

[0029] In some possible embodiments of the present application, the mapping function is obtained by function fitting according to the set of control point pairs, including:

[0030] The set of control point pairs is divided according to a preset data set division rule to obtain a set of verification operation control point pairs and a set of mapping operation control point pairs.

[0031] An initial mapping function is obtained by function fitting according to the set of mapping operation control point pairs.

[0032] A verification result is obtained by function verification of the initial mapping function according to the set of verification operation control point pairs.

[0033] When the verification result indicates that the initial mapping function fails to pass the verification, the mapping function is obtained by re-performing data pair construction according to all the wafer edge data and all the edge design data.

[0034] In some possible embodiments of the present application, the edge detection of the wafer according to all the wafer edge reference data and all the wafer edge data to obtain a detection result, includes:

[0035] Error range information is obtained by error range expansion according to all the wafer edge reference data.

[0036] The detection result is obtained by detection of each wafer edge data according to the error range information.

[0037] To achieve the above object, a second aspect of the embodiments of the present application provides an edge detection device of a wafer. The edge detection device includes:

[0038] A wafer image acquisition module is configured to perform optical imaging on the wafer to obtain a wafer image.

[0039] A wafer edge data acquisition module is configured to perform edge feature extraction according to the wafer image to obtain a plurality of wafer edge data.

[0040] An edge design data acquisition module is configured to acquire a design drawing file of the wafer, and acquire a plurality of edge design data of the wafer according to the design drawing file.

[0041] An edge reference data acquisition module is configured to map all the edge design data to the wafer image to obtain a plurality of wafer edge reference data.

[0042] The detection result acquisition module is used to perform edge detection on the wafer based on all the wafer edge reference data and all the edge design data, and obtain the detection result.

[0043] To achieve the aforementioned objectives, a third aspect of this application provides an electronic device comprising a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the method described in the first aspect.

[0044] To achieve the above objectives, a fourth aspect of the present application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method described in the first aspect.

[0045] This application proposes a wafer edge detection method, apparatus, electronic device, and storage medium. It performs optical imaging on the wafer to obtain a wafer image, extracts edge features from the wafer image to obtain multiple wafer edge data, acquires the wafer's design drawing file, obtains multiple edge design data from the design drawing file, maps all edge design data onto the wafer image to obtain multiple wafer edge reference data, and performs edge detection on the wafer based on all wafer edge reference data and all wafer edge data to obtain a detection result. The method proposed in this application maps the wafer edges on the design drawing file to the wafer image, and compares the mapped edges with the actual wafer edges, providing an accurate detection benchmark, reducing the difficulty of edge detection, and improving the accuracy of wafer edge detection. Attached Figure Description

[0046] Figure 1 This is a schematic diagram illustrating the steps of a wafer edge detection method provided in an embodiment of this application;

[0047] Figure 2 yes Figure 1 A schematic diagram of the sub-steps of step S102;

[0048] Figure 3 This is a schematic diagram of the Hough transform process for edge recognition data;

[0049] Figure 4 yes Figure 1 A schematic diagram of the sub-steps of step S104;

[0050] Figure 5 yes Figure 4 A schematic diagram of the sub-steps of step S301;

[0051] Figure 6 yes Figure 4Another embodiment of the step S301 is shown in the following step diagram.

[0052] Figure 7 is Figure 5 Another embodiment of the step S404 is shown in the following step diagram.

[0053] Figure 8 is Figure 1 Another embodiment of the step S105 is shown in the following step diagram.

[0054] Figure 9 is Figure 8 An embodiment of the step S701 is shown in the following diagram.

[0055] Figure 10 is a structural diagram of a wafer edge detection device provided by an embodiment of the present application.

[0056] Figure 11 A structural diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0057] In order to make the objects, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0058] It should be noted that although the functional modules are divided in the device diagram, and the logical order is shown in the flowchart, in some cases, the steps shown or described can be performed in a manner different from the module division in the device or the order in the flowchart. The terms "first", "second", etc. in the specification and claims and the above-described drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence.

[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0060] At present, with the development of the wafer industry, in order to improve production efficiency, wafer production gradually introduces automatic equipment and improves the degree of automation. As an important part of wafer production, quality inspection affects the quality of wafers and also affects the subsequent production of semiconductor circuits.

[0061] As one part of quality inspection, the current method for wafer edge detection is to compare the image of a wafer with the image of a standard template of a non-defective sample. However, for some wafers, the standard template is difficult to extract and there are few of them, and such wafers need to be compared with a design drawing.

[0062] Using the setting drawing to compare needs to align the image of the wafer, due to the difference between the actual wafer edge and the theoretical edge on the design drawing in the production process, it is difficult to accurately align the two edges, at this time, system error will occur, which affects the accuracy of edge detection.

[0063] Therefore, the embodiment of the present application provides a wafer edge detection method and device, electronic equipment and storage medium, aiming at the accuracy of wafer edge detection.

[0064] The wafer edge detection method and device, electronic equipment and storage medium provided by the embodiment of the present application are specifically described by the following embodiment, first, the recommended method in the embodiment of the present application is described.

[0065] The wafer edge detection method provided by the embodiment of the present application can be applied to a terminal, can also be applied to a server side, and can also be software running in the terminal or the server side. In some embodiments, the terminal can be a smart phone, a tablet computer, a notebook computer, a desktop computer, etc.; the server side can be configured as a separate physical server, can also be configured as a server cluster or a distributed system composed of multiple physical servers, can also be configured as a cloud server providing basic cloud computing services such as cloud service, cloud database, cloud computing, cloud function, cloud storage, network service, cloud communication, middleware service, domain name service, security service, CDN and big data and artificial intelligence platform; the software can be an application that implements the wafer edge detection method, etc., but is not limited to the above forms.

[0066] The present application can be used in many general or special computer system environments or configurations. For example: personal computer, server computer, handheld device or portable device, tablet device, multi-processor system, microprocessor-based system, set-top box, programmable consumer electronics, network PC, small computer, large computer, distributed computing environment including any of the above systems or devices, etc. The present application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The present application can also be practiced in a distributed computing environment, in which tasks are performed by remote processing devices connected by a communication network. In a distributed computing environment, program modules can be located in local and remote computer storage media, including storage devices.

[0067] Please see Figure 1 , Figure 1 is a step schematic diagram of a wafer edge detection method provided by the embodiment of the present application, Figure 1The method in the method can include but is not limited to steps S101-S105.

[0068] Step S101, optical imaging of the wafer to obtain a wafer image.

[0069] It should be understood that the wafer image here refers to the final image, and the optical imaging here refers to the imaging step including preprocessing. Specifically, first, a pre-image is obtained by photographing the wafer through an optical system, and the wafer image is obtained by preprocessing the pre-image.

[0070] It should be understood that the optical system here is diverse, for example, an optical processing system, a photographing and preprocessing integrated system, an external optical lens and an image processing system, etc. Those skilled in the art can select appropriate equipment as the optical system according to actual needs, and the present application does not limit it.

[0071] It should be understood that the preprocessing here is diverse, for example, grayscale of the image, binarization of the image, noise filtering of the image, etc. Those skilled in the art can select appropriate methods as preprocessing means to improve the accuracy of the wafer image according to actual needs, and the present application does not limit it.

[0072] Step S102, edge feature extraction according to the wafer image to obtain a plurality of wafer edge data.

[0073] It should be understood that the specific way of edge feature extraction here is diverse, for example, identifying the external contour of the wafer on the wafer image through edge detection, extracting position information according to the identified external contour to obtain a plurality of wafer edge data; again, mapping the wafer image to a feature space through a deep learning neural network, performing edge calculation through an internal network structure to identify the external contour of the wafer, and then extracting position information through the external contour to obtain a plurality of wafer edge data.

[0074] It should be understood that the specific number of the plurality here is diverse, for example, in order to complete the data, the position information of the external contour is extracted to obtain all wafer edge data, for example, in order to improve the detection efficiency, a plurality of wafer edge data is extracted, etc. Those skilled in the art can determine the number of wafer edge data to be obtained according to actual needs, and the present application does not limit it.

[0075] Step S103, obtaining a design drawing file of the wafer, and obtaining a plurality of edge design data of the wafer according to the design drawing file.

[0076] It should be understood that the edge design data here is the data of the theoretical profile of the wafer when the wafer is designed. Due to the consideration of the damage caused by the sharp corners to the device installer, device producer, engineer, etc. in the actual application scene, chamfering needs to be performed, and the actual obtained wafer is not the same size as the wafer design originally, and the data of the theoretical profile needs to be compared.

[0077] It should be understood that the design drawing file here refers to a file containing information about the wafer design drawing, which is an electronic file.

[0078] It should be understood that the way of obtaining the design drawing file of the wafer here is various, depending on the carrier of the design drawing information. For example, when the design drawing information of the wafer is stored in a paper design drawing, it is converted into an electronic image through scanning or shooting from the paper design drawing, and then the electronic image is executed as the "edge feature extraction" in step 102 to obtain the theoretical edge information of the wafer, and the plurality of edge design data is obtained according to the theoretical edge information of the wafer. For example, the design drawing file is an electronic design drawing, and the edge design data is obtained by data extraction, etc. Those skilled in the art can select a suitable way to obtain the edge design data from the design drawing file according to the actual situation, and the present application does not limit it.

[0079] Step S104, mapping all edge design data to the wafer image to obtain a plurality of wafer edge reference data.

[0080] Affected by factors such as shooting angle and magnification, the edge design data and the wafer edge data are not in the same reference system. Taking coordinates as data forms for example, assuming that the wafer as a whole is in the upper right of the wafer image, assuming that the specific type of the design drawing file is an electronic picture, the wafer as a whole is in the center of the electronic picture and occupies most of the position of the electronic picture, and there is an edge point with a coordinate (10, 20) in the wafer edge data on the wafer image. The position of this edge point on the electronic picture is (-15, 70). Even if both data represent the same edge point, they will not be considered the same edge point in data comparison. If mapping is not performed, serious detection errors will occur.

[0081] It should be understood that the mapping of all edge design data to the wafer image here refers to the mapping of all edge design data to the reference system on the wafer image, removing the influence of magnification and shooting angle. Taking the above example, "mapping all edge design data to the wafer image" means that the edge of the wafer on the electronic picture is reduced and shifted to the upper right of the wafer image for comparison.

[0082] Specifically, all edge design data is mapped from a reference system in which all edge design data is located to a reference system in which wafer edge data is located by a mapping function, and after all edge design data is mapped to the reference system in which wafer edge data is located, the data is converted to wafer edge reference data by the mapping function.

[0083] It should be understood that the mapping function herein is various, for example, a linear transformation, the position of the wafer in the design drawing file is fixed, the position of the wafer in the wafer image is fixed, the wafer edge reference data is obtained by linear transformation, and the like, and a person skilled in the art can map all edge design data to the wafer image according to actual conditions to obtain a plurality of wafer edge reference data, and the present application does not limit this.

[0084] In step S105, the wafer is detected according to all wafer edge reference data and all wafer edge data to obtain a detection result.

[0085] Specifically, by comparing the wafer edge reference data and the wafer edge data detection, the error between the actual edge of the wafer represented by the wafer edge data and the theoretical edge represented by the wafer edge reference data is detected, and whether the error is within the error allowable range, thereby obtaining the detection result.

[0086] It should be understood that the specific form of detecting the wafer according to all wafer edge reference data and all wafer edge data herein is various, for example, the distance between each wafer edge data and its corresponding wafer reference edge data is calculated, and the calculation result is compared with the edge threshold to obtain the detection result; for example, the intersection over union (IOU) of the reference area surrounded by all wafer edge reference data and the actual area surrounded by all wafer edge data is calculated, and the intersection over union is compared with a preset intersection over union threshold to obtain the detection result, and the like, and a person skilled in the art can select a suitable detection method to detect the wafer according to all wafer edge reference data and all wafer edge data according to actual needs, and the present application does not limit this.

[0087] The application provides a wafer edge detection method and device, electronic equipment and a storage medium. The wafer is optically imaged to obtain a wafer image, edge feature extraction is performed according to the wafer image to obtain a plurality of wafer edge data, a design drawing file of the wafer is acquired, a plurality of edge design data of the wafer is acquired according to the design drawing file, all the edge design data is mapped to the wafer image to obtain a plurality of wafer edge reference data, and edge detection is performed on the wafer according to all the wafer edge reference data and all the wafer edge data to obtain a detection result. The edge of the wafer on the design drawing file is mapped to the wafer image by the method, the mapped edge is compared with the actual edge of the wafer, an accurate detection reference is provided, the difficulty of edge detection is reduced, and the detection accuracy of the wafer edge is improved.

[0088] See Figure 2 , Figure 2 for Figure 1 the sub-steps of step S102. In some possible embodiments of the application, step S102 includes but is not limited to the following sub-steps.

[0089] In step S201, edge recognition is performed on the wafer image to obtain a plurality of edge recognition data.

[0090] It should be understood that the edge recognition herein is various, for example, the outer contour of the wafer on the wafer image is recognized by an edge detection method to obtain a plurality of edge recognition data; for another example, the wafer image is mapped to a feature space by a deep learning neural network, and edge calculation is performed by an internal network structure to obtain a plurality of edge recognition data. Those skilled in the art can select a suitable method to continue edge recognition on the wafer image according to actual conditions, and the application does not limit this.

[0091] In step S202, image element enhancement is performed according to all the edge recognition data to obtain a plurality of edge enhancement data.

[0092] It should be understood that the image element enhancement herein refers to restoring the chamfered part in actual production of the wafer to improve the accuracy of mapping the edge design data to the wafer image.

[0093] It should be understood that the specific method of image element enhancement herein is various, for example, a least square method is used to fit an intersection line segment, and a plurality of edge enhancement data are obtained in the intersection line segment; for another example, a neural network model is used to map the edge enhancement data to a feature space to obtain edge design features, convolution calculation is performed on the edge design features to predict an intersection line segment, and a plurality of edge enhancement data are obtained in the intersection line segment. Those skilled in the art can select a suitable method for image element enhancement according to actual needs, and the application does not limit this.

[0094] In some possible embodiments of the present application, the image element enhancement herein is implemented through Hough transformation. Please refer to Figure 3 , Figure 3 A process diagram for Hough transformation of edge recognition data, Figure 3 The solid dots in the diagram are edge recognition data, and the hollow dots are edge enhancement data. Hough transformation is performed on each wafer edge data to obtain a plurality of straight lines passing through each wafer edge data, and there is a straight line passing through another wafer edge data. Through this principle, two straight lines passing through most of the image edge data are detected, and the two straight lines intersect at a point. The two straight lines are the theoretical edge of the wafer, and a plurality of edge enhancement data are obtained on the two straight lines.

[0095] In step S203, all edge recognition data is updated according to all edge enhancement data to obtain all wafer edge data.

[0096] It should be understood that the data update herein refers to adding all edge enhancement data to all edge recognition data to form wafer edge data.

[0097] It should be understood that the wafer edge data herein includes both the original edge recognition data and the relevant edge enhancement data of the missing part of the theoretical edge that is chamfered.

[0098] The embodiments of the present application perform image element enhancement on the wafer on the wafer image, supplement data on the original edge data, restore the chamfered part of the wafer, and enable the theoretical edge to be mapped and referenced to the restored part for positioning, thereby improving the accuracy of mapping the edge design data to the wafer image and improving the accuracy of the detection result.

[0099] Please refer to Figure 4 , Figure 4 is Figure 1 A step diagram of the sub-step of step S104 in

[0100] In step S301, function fitting is performed on all wafer edge data and all edge design data to obtain a mapping function.

[0101] It should be understood that the function fitting herein refers to fitting a function through which all edge design data is mapped to the wafer image.

[0102] It should be understood that the function fitting here refers to function fitting of taking the wafer edge data as the dependent variable and the edge design data as the variable, to obtain a mapping function representing mapping of the reference system of the edge design data to the reference system of the wafer edge data, so that both the edge design data and the wafer edge data are represented in the reference system of the wafer edge data.

[0103] It should be understood that the specific way of function fitting here is various, for example, linear fitting, polynomial fitting, exponential fitting, etc., and for example, fitting of a high-dimensional function through a neural network to make the mapping function more accurate, etc., and a person skilled in the art can select a suitable way for function fitting according to the actual situation, and the present application does not limit this.

[0104] Step S302, mapping all edge design data to the wafer image according to the mapping function to obtain a plurality of wafer edge reference data.

[0105] Specifically, all edge design data are mapped according to the mapping function obtained in step S301, and each edge design data is mapped to a wafer edge reference data through the mapping function.

[0106] It should be understood that the theoretical edge formed by the wafer edge reference data does not necessarily completely coincide with the edge of the wafer on the wafer image, and the degree of coincidence depends on the fitting accuracy of the mapping function.

[0107] See Figure 5 , Figure 5 for Figure 4 the steps of the sub-steps of step S301. In some possible embodiments of the present application, step S301 includes but is not limited to the following sub-steps.

[0108] Step S401, constructing a data pair according to all wafer edge data and all edge design data to obtain a plurality of control point pairs.

[0109] It should be understood that the data pair construction method herein is diverse, and exemplary, such as a corner point pairing method, a two-dimensional feature point matching algorithm in a traditional three-dimensional reconstruction algorithm (Structure from motion, SFM), a key point matching part in a visual simultaneous localization and mapping algorithm (Visual Simultaneous Localization and Mapping, V SLAM), and the like; or a scale invariant feature transform algorithm (Scale Invariant Feature Transform, SIFT), a feature extraction algorithm (Speeded Up Robust Features, SURF), and the like. Those skilled in the art can select a suitable method to construct a plurality of control point pairs according to actual conditions, and the present application does not limit this.

[0110] It should be understood that each control point pair herein includes a wafer edge data and an edge design data.

[0111] In step S402, for each control point pair, the control point pair is inspected according to a preset inspection rule to obtain an inspection result.

[0112] It should be understood that the preset inspection rule herein is used to inspect the quality of the control point pair obtained in step S401 to improve the accuracy of the mapping function. The specific content of the preset inspection rule is diverse, and exemplary, such as using a spatial distance to perform inspection, mapping all control point pairs to a feature space, calculating the spatial distance between the wafer edge data and the edge design data in each control point pair in the feature space, calculating the average spatial distance between all wafer edge data and edge design data, comparing the spatial distance of each control point pair with the average spatial distance to achieve inspection, and the like. Those skilled in the art can select and define a suitable preset inspection rule according to actual needs, and the present application does not limit this.

[0113] In step S403, when the inspection result indicates that the control point pair is abnormal, the control point pair is corrected according to a preset correction rule, and a data set is constructed according to all current control point pairs to obtain a control point pair set.

[0114] It should be understood that the preset correction rules here are diverse and exemplary, such as deleting an abnormal control point pair, replacing one of the wafer edge data and the edge design data in the control point pair when the control point pair is generally abnormal, and deleting the control point pair when the control point pair is severely abnormal. Those skilled in the art can define the preset correction rules according to actual conditions, and the present application does not limit this.

[0115] It should be understood that the current all control point pairs here refer to the control point pairs that have been inspected and whose inspection results indicate normality. The data set construction according to the current all control point pairs includes two cases. One is that the first control point pair that has been inspected and is normal is added to a data set to start data set construction. The other is that the control point pairs are successively added to the aforementioned data set to continue data set construction until the last control point pair is added to the data set, the data set construction is completed, and the control point pair set is obtained.

[0116] In step S404, a function fitting is performed according to the control point pair set to obtain a mapping function.

[0117] The embodiments of the present application improve the accuracy of the mapping function by forming control point pairs and inspecting all control point pairs, improve the accuracy of the theoretical edge mapping to the wafer image, and thus improve the accuracy of the edge detection.

[0118] Please refer to Figure 6 , Figure 6 for Figure 4 another embodiment of step S301. In some possible embodiments of the present application, step S301 further includes but is not limited to the following substeps before step S404.

[0119] In step S501, quantity detection is performed on all control point pairs in the control point pair set to obtain a quantity detection result.

[0120] Specifically, the number information of the control point pair set is obtained by traversing the control point pair set obtained in step S403, and the number information of the control point pair set is compared with a preset control point pair number threshold to obtain the quantity detection result.

[0121] It should be understood that the preset control point pair number threshold is diverse, and those skilled in the art can set the specific value of the preset control point pair number threshold according to the fitting accuracy, operation speed, and other requirements, and the present application does not limit this.

[0122] Step S502, when the number detection result indicates that the number of control point pairs in the control point pair set is insufficient, the updated control point pairs are obtained according to the preset supplement rule, all wafer edge data and all edge design data, the updated control point pairs are added to the control point pair set to obtain a target control point pair set.

[0123] Specifically, when the number of control point pairs in the control point pair set is less than the preset control point pair number threshold, it indicates that the number of control point pairs is insufficient, and the new control point pairs, i.e., the updated control point pairs, are constructed again according to the preset supplement rule and the manner of step S401, and the newly constructed updated control point pairs are added to the control point pair set to obtain the target control point pair set.

[0124] It should be understood that the preset supplement rule herein is various, and examples include increasing the number of control point pairs to the number equivalent to the preset control point pair number threshold, or increasing the number of control point pairs to 20% of the number of the current control point pair set, and the like. Those skilled in the art can define the preset supplement rule according to actual conditions, which is not limited in the present application.

[0125] Step S404 includes but is not limited to the following sub-steps:

[0126] Step S503, function fitting is performed according to the target control point pair set to obtain a mapping function.

[0127] The embodiments of the present application ensure that there is sufficient data for function fitting by detecting the number of the control point pair set and increasing the control point pair set, ensure the effectiveness and quality of the mapping function, and improve the accuracy of edge detection.

[0128] Please refer to Figure 7 , Figure 7 for Figure 5 the step diagram of the sub-steps of step S404. In some possible embodiments of the present application, step S404 includes but is not limited to the following sub-steps.

[0129] Step S601, the control point pair set is divided according to a preset data set division rule to obtain a verification task control point pair set and a mapping task control point pair set.

[0130] It should be understood that the preset data set division rule here is various, and exemplary, such as randomly extracting 80% of the control point pairs in the control point pair set to form a mapping operation control point pair set, and the remaining 20% of the control point pairs form a verification operation control point pair set; such as mapping each control point pair into a feature space, calculating the spatial distance of the wafer edge data and the wafer edge reference data in each control point pair, and sorting according to the spatial distance, the first 20% of the control point pairs with the smallest spatial distance form a verification operation control point pair set, and the remaining control point pairs form a mapping operation control point pair set, etc. Those skilled in the art can define the preset data set division rule according to the actual situation, and the present application does not limit it.

[0131] Step S602, function fitting is performed according to the mapping operation control point pair set to obtain an initial mapping function.

[0132] Specifically, according to the fitting of all control point pairs in the mapping control point pair set, the wafer edge data of all control point pairs in the mapping control point pair set is taken as the dependent variable, and the wafer edge reference data of all control point pairs in the mapping control point pair set is taken as the variable for data fitting to obtain the initial mapping function.

[0133] Step S603, function verification is performed on the initial mapping function according to the verification operation control point pair set to obtain a verification result.

[0134] Specifically, the wafer edge reference data of all control point pairs in the verification operation control point pair set is taken as a variable to substitute into the initial mapping function for mapping operation to obtain a plurality of dependent variables. Each dependent variable is compared with the corresponding wafer edge data to obtain a verification result.

[0135] It should be understood that the specific form of comparing the dependent variable with the corresponding wafer edge data to obtain the verification result here is various, and exemplary, such as calculating the distance between each dependent variable and the corresponding wafer edge data and comparing it with the related preset threshold value, calculating the number of dependent variables whose distance exceeds the related threshold value, comparing the number of dependent variables with the preset detection threshold value to obtain the verification result; such as calculating the proportion of the number of dependent variables whose distance exceeds the related threshold value relative to the number of control point pairs in the verification operation control point pair set to obtain the verification result, etc. Those skilled in the art can select an appropriate way to compare the dependent variable with the corresponding wafer edge data to obtain the verification result according to the actual need, and the present application does not limit it.

[0136] Step S604, when the verification result indicates that the initial mapping function fails to verify, data pairs are re-constructed according to all wafer edge data and all edge design data to obtain a mapping function.

[0137] Specifically, when the verification result indicates that the initial mapping function verification fails, data pairs are re-constructed according to all wafer edge data and all edge design data, so as to re-execute step S301.

[0138] The embodiment of the application improves the accuracy of the mapping function and reduces the influence of mapping errors caused by control point pair correction errors by setting the verification job control point pair set and the mapping job control point pair set to detect the accuracy of the mapping function, and re-fitting the mapping function when the verification fails.

[0139] Please refer to Figure 8 , Figure 8 for Figure 1 the steps of the sub-steps of step S105. In some possible examples of the application, step S105 includes but is not limited to the following sub-steps.

[0140] Step S701, according to all wafer edge reference data, error range expansion is performed to obtain error range information.

[0141] It should be understood that the error range here refers to the allowable error range of the wafer edge and the theoretical edge, and the error range expansion here refers to obtaining error range reference data representing the allowable error range through wafer edge reference data, and the specific way of obtaining error range information through error range expansion is various, for example, setting an expansion function, generating a plurality of error range reference data according to all wafer edge reference data and the expansion function to obtain the error range information; for example, generating a plurality of error range reference data according to a preset offset distance according to all wafer edge reference data to obtain the error range information, and the like. Those skilled in the art can select a suitable way to expand the error range according to actual needs, and the application does not limit this.

[0142] Please refer to Figure 9 , Figure 9 for Figure 8 the implementation schematic diagram of step S701 in the embodiment. Step S701 specifically represents that the theoretical edge represented by all wafer edge reference data is expanded to an allowable error range, for example, Figure 9 (a), when the actual edge represented by the wafer edge data is located within the range, it indicates that the wafer meets the requirements; for example, Figure 9 (b), when the actual edge represented by the wafer edge data is located within the range, it indicates that the wafer has defects.

[0143] Step S702, according to the error range information, each wafer edge data is detected to obtain a detection result.

[0144] It should be understood that the detection here refers to detecting whether each wafer edge data is within the error range according to the error range information, and the specific form is various, for example, calculating the shortest distance between each wafer edge data and the error range reference data, comparing the shortest distance with a preset error distance to obtain a detection result; for example, calculating the intersection-over-union of the error region surrounded by the error range reference data and the actual region surrounded by the wafer edge data, and comparing the intersection-over-union with a preset intersection-over-union threshold to obtain a detection result, and the like. Those skilled in the art can select a suitable comparison method to obtain a detection result according to actual needs, and the present application does not limit this.

[0145] The embodiments of the present application detect the wafer edge by expanding the error range according to all wafer edge reference data, reduce the need to obtain a defect sample for comparison with the wafer edge, reduce the difficulty of edge detection, and expand the error range based on the theoretical edge for edge detection, improve the accuracy of detection, and reduce the system error caused by sample matching.

[0146] Please refer to Figure 10 , Figure 10 A structure schematic diagram of a wafer edge detection device provided by the embodiments of the present application can implement the above edge detection method. The device 800 comprises:

[0147] A wafer image acquisition module 801 is configured to perform optical imaging on the wafer to obtain a wafer image.

[0148] A wafer edge data acquisition module 802 is configured to extract edge features from the wafer image to obtain a plurality of wafer edge data.

[0149] An edge design data acquisition module 803 is configured to obtain a design drawing file of the wafer, and obtain a plurality of edge design data of the wafer according to the design drawing file.

[0150] A wafer edge reference data acquisition module 804 is configured to map all the edge design data to the wafer image to obtain a plurality of wafer edge reference data.

[0151] A detection result acquisition module 805 is configured to perform edge detection on the wafer according to all the wafer edge reference data and all the edge design data to obtain a detection result.

[0152] The specific embodiments of the edge detection device are basically the same as the specific embodiments of the above edge detection method, and will not be repeated here.

[0153] The embodiment of the present application further provides an electronic device, which comprises a memory and a processor, the memory stores a computer program, and the processor implements the wafer edge detection method when executing the computer program. The electronic device can be any intelligent terminal, such as a tablet computer or a vehicle-mounted computer.

[0154] Please refer to Figure 11 , Figure 11 FIG. 9 is a structural schematic diagram of an electronic device according to an embodiment of the present application. The electronic device 900 comprises:

[0155] The processor 901 can be implemented in a general-purpose CPU (Central Processing Unit), a microprocessor, an ASIC (Application Specific Integrated Circuit), or one or more integrated circuits, and is used to execute related programs to implement the technical solutions provided by the embodiments of the present application.

[0156] The memory 902 can be implemented in the form of a ROM (ReadOnly Memory), a static storage device, a dynamic storage device, or a RAM (Random Access Memory). The memory 902 can store an operating system and other application programs. When the technical solutions provided by the embodiments of the present application are implemented by software or firmware, the related program codes are stored in the memory 902 and are called and executed by the processor 901 to implement the wafer edge detection method of the embodiments of the present application.

[0157] The input / output interface 903 is used to realize information input and output.

[0158] The communication interface 904 is used to realize the communication interaction between the device and other devices. The communication can be realized by a wired manner (for example, a USB, a network cable, etc.) or a wireless manner (for example, a mobile network, WIFI, Bluetooth, etc.).

[0159] The bus 905 is used to transmit information between various components (for example, the processor 901, the memory 902, the input / output interface 903, and the communication interface 904) of the device.

[0160] The processor 901, the memory 902, the input / output interface 903, and the communication interface 904 are connected to each other through the bus 905 to realize the communication connection between them in the device.

[0161] The embodiment of the present application further provides a computer readable storage medium, which stores a computer program. The computer program is executed by a processor to implement the wafer edge detection method.

[0162] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. In addition, the memory can include a high-speed random access memory and can also include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state memory device. In some embodiments, the memory can optionally include a memory that is remotely arranged with respect to the processor, and these remote memories can be connected to the processor through a network. Examples of the above network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0163] The application provides a wafer edge detection method and device, electronic equipment and storage medium. The wafer is optically imaged to obtain a wafer image. Edge feature extraction is performed according to the wafer image to obtain a plurality of wafer edge data. A design drawing file of the wafer is obtained. A plurality of edge design data of the wafer is obtained according to the design drawing file. All edge design data is mapped to the wafer image to obtain a plurality of wafer edge reference data. Edge detection is performed on the wafer according to all wafer edge reference data and all wafer edge data to obtain a detection result. The edge of the wafer on the design drawing file is mapped to the wafer image by the method, the mapped edge is compared with the actual edge of the wafer, an accurate detection reference is provided, the difficulty of edge detection is reduced, and the detection accuracy of the wafer edge is improved.

[0164] The embodiments described in the embodiments of the application are used to more clearly illustrate the technical solutions of the embodiments of the application, and do not constitute a limitation on the technical solutions provided by the embodiments of the application. Those skilled in the art can know that, with the evolution of technology and the appearance of new application scenarios, the technical solutions provided by the embodiments of the application are also applicable to similar technical problems.

[0165] Those skilled in the art can understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the application, and can include more or fewer steps than shown in the figures, or combine certain steps or different steps.

[0166] The device embodiments described above are only schematic, and the units described as separate components can or can not be physically separate, that is, they can be located in one place or distributed on multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the embodiments.

[0167] Those skilled in the art can understand that all or some of the steps in the above disclosed method, the function modules / units in the system and the device can be implemented as software, firmware, hardware and their appropriate combinations.

[0168] The terms "first", "second", "third", "fourth", and the like in the description and in the claims of this application, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the use of the terms so termed is interchangeable under appropriate circumstances such that the embodiments of the application described herein are, for example, capable of orderly or chronological mundane operation, reverse order operation, based on circuitry availability, based on stated preference or the like, and that "default" or other orderings are thus permissible. Further, the terms "comprise", "comprising", "include", "including", and the like, are specifically intended to be open-ended. That is, references to individual steps and the like do not suhstantially exclude the presence of two or more of a recited step or its integral sub-steps or additional steps whether or not readily ascertainable from the description or the like. Further, the words "a" or "an", as used herein in the disclosure and elsewhere, are used indiscriminately and are to be interpreted in the same way, i.e. as meaning "one or more".

[0169] It should be understood that, in the application, "at least one" means one or more, and "multiple" means two or more. "And / or" is used to describe the relationship between associated objects, which means that there can be three relationships, for example, "A and / or B" can mean that there are only A, only B, and A and B at the same time, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects. "At least one of the following" or the like means any combination of these items, including single or multiple combinations. For example, at least one of a, b or c can mean a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0170] In several embodiments provided in the application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the above units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be omitted or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed objects can be indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0171] The units described above as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e. they can be located in one place or distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0172] In addition, each function unit in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software function unit.

[0173] When the integrated unit is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application, essentially or in part, or all or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes multiple instructions used to cause a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods in the embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various other media that can store programs.

[0174] The preferred embodiments of the embodiments of the present application are described above with reference to the accompanying drawings, and are not intended to limit the scope of the embodiments of the present application. Any modifications, equivalent replacements and improvements made by those skilled in the art without departing from the scope and essence of the embodiments of the present application shall be within the scope of the embodiments of the present application.

Claims

1. A method for edge detection of a wafer, characterized in that, The edge detection method includes the following steps: Optical imaging is performed on the wafer to obtain a wafer image; Edge features are extracted from the wafer image to obtain multiple wafer edge data; Obtain the design drawing file of the wafer, and obtain multiple edge design data of the wafer based on the design drawing file; A mapping function is obtained by fitting a function to all the wafer edge data and all the edge design data; Based on the mapping function, all the edge design data are mapped to the wafer image to obtain multiple wafer edge reference data; Edge detection is performed on the wafer based on all the wafer edge reference data and all the wafer edge data to obtain the detection results.

2. The edge detection method according to claim 1, characterized in that, The step of extracting edge features from the wafer image to obtain multiple wafer edge data includes: Edge recognition is performed on the wafer image to obtain multiple edge recognition data; Image element enhancement is performed based on all the edge recognition data to obtain multiple edge enhancement data; All edge recognition data are updated based on all the edge enhancement data to obtain all the wafer edge data.

3. The edge detection method according to claim 1, characterized in that, The step of fitting a function to all the wafer edge data and all the edge design data to obtain a mapping function includes: Data pairs are constructed based on all the wafer edge data and all the edge design data to obtain multiple control point pairs; For each control point pair, a quality inspection is performed on the control point pair according to a preset quality inspection rule to obtain the quality inspection result; When the quality inspection result indicates that the control point pair is abnormal, the control point pair is corrected according to the preset correction rules, and a dataset is constructed based on all the current control point pairs to obtain a control point pair set; The mapping function is obtained by fitting a function to the set of control points.

4. The edge detection method according to claim 3, characterized in that, Before performing function fitting on the control point set to obtain the mapping function, the edge detection method further includes: The number of all control point pairs in the control point pair set is detected to obtain the number detection result; When the quantity detection result indicates that the number of control point pairs in the control point pair set is insufficient, an updated control point pair is obtained according to a preset supplementation rule, all wafer edge data and all edge design data, and the updated control point pair is added to the control point pair set to obtain the target control point pair set. The step of fitting a function to the control point set to obtain the mapping function includes: The mapping function is obtained by fitting a function to the set of target control points.

5. The edge detection method according to claim 3, characterized in that, The step of fitting a function to the control point set to obtain the mapping function includes: According to the preset dataset partitioning rules, the control point pair set is partitioned to obtain the verification operation control point pair set and the mapping operation control point pair set; The initial mapping function is obtained by fitting a function to the set of control points of the mapped operation. The initial mapping function is validated based on the set of validation operation control points to obtain the validation result. If the verification result indicates that the initial mapping function verification failed, the data pairs are reconstructed based on all the wafer edge data and all the edge design data to obtain the mapping function.

6. The edge detection method according to claim 1, characterized in that, The step of performing edge detection on the wafer based on all the wafer edge reference data and all the wafer edge data to obtain detection results includes: Error range information is obtained by expanding the error range based on all the aforementioned wafer edge reference data; The edge data of each wafer is detected based on the error range information to obtain the detection result.

7. A wafer edge detection device, characterized in that, The edge detection device includes: A wafer image acquisition module is used to perform optical imaging on the wafer to obtain a wafer image; The wafer edge data acquisition module is used to extract edge features based on the wafer image to obtain multiple wafer edge data. An edge design data acquisition module is used to acquire the design drawing file of the wafer and acquire multiple edge design data of the wafer based on the design drawing file; The edge reference data acquisition module is used to perform function fitting on all the wafer edge data and all the edge design data to obtain a mapping function; and to map all the edge design data to the wafer image according to the mapping function to obtain multiple wafer edge reference data. The detection result acquisition module is used to perform edge detection on the wafer based on all the wafer edge reference data and all the edge design data, and obtain the detection result.

8. An electronic device, characterized in that, The electronic device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the edge detection method of any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, characterized in that, when the computer program is executed by a processor, it implements the edge detection method of any one of claims 1 to 6.

Images